adw_pci.c revision 241588
1/*- 2 * Device probe and attach routines for the following 3 * Advanced Systems Inc. SCSI controllers: 4 * 5 * ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB) 6 * ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel) 7 * ABP970UW - Bus-Master PCI Ultra-Wide (253 CDB) 8 * ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB) 9 * ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB) 10 * 11 * Copyright (c) 1998, 1999, 2000 Justin Gibbs. 12 * All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions, and the following disclaimer, 19 * without modification. 20 * 2. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36#include <sys/cdefs.h> 37__FBSDID("$FreeBSD: head/sys/dev/advansys/adw_pci.c 241588 2012-10-15 15:26:00Z jhb $"); 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/kernel.h> 42#include <sys/module.h> 43#include <sys/lock.h> 44#include <sys/mutex.h> 45#include <sys/bus.h> 46 47#include <machine/bus.h> 48#include <machine/resource.h> 49 50#include <sys/rman.h> 51 52#include <dev/pci/pcireg.h> 53#include <dev/pci/pcivar.h> 54 55#include <cam/cam.h> 56#include <cam/scsi/scsi_all.h> 57 58#include <dev/advansys/adwvar.h> 59#include <dev/advansys/adwlib.h> 60#include <dev/advansys/adwmcode.h> 61 62#define ADW_PCI_IOBASE PCIR_BAR(0) /* I/O Address */ 63#define ADW_PCI_MEMBASE PCIR_BAR(1) /* Mem I/O Address */ 64 65#define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull 66#define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull 67#define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull 68#define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 69#define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 70 71struct adw_pci_identity; 72typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *, 73 struct adw_softc *adw); 74 75struct adw_pci_identity { 76 u_int64_t full_id; 77 u_int64_t id_mask; 78 char *name; 79 adw_device_setup_t *setup; 80 const struct adw_mcode *mcode_data; 81 const struct adw_eeprom *default_eeprom; 82}; 83 84static adw_device_setup_t adw_asc3550_setup; 85static adw_device_setup_t adw_asc38C0800_setup; 86#ifdef NOTYET 87static adw_device_setup_t adw_asc38C1600_setup; 88#endif 89 90struct adw_pci_identity adw_pci_ident_table[] = 91{ 92 /* asc3550 based controllers */ 93 { 94 PCI_ID_ADVANSYS_3550, 95 PCI_ID_DEV_VENDOR_MASK, 96 "AdvanSys 3550 Ultra SCSI Adapter", 97 adw_asc3550_setup, 98 &adw_asc3550_mcode_data, 99 &adw_asc3550_default_eeprom 100 }, 101 /* asc38C0800 based controllers */ 102 { 103 PCI_ID_ADVANSYS_38C0800_REV1, 104 PCI_ID_DEV_VENDOR_MASK, 105 "AdvanSys 38C0800 Ultra2 SCSI Adapter", 106 adw_asc38C0800_setup, 107 &adw_asc38C0800_mcode_data, 108 &adw_asc38C0800_default_eeprom 109 }, 110#ifdef NOTYET 111 /* XXX Disabled until I have hardware to test with */ 112 /* asc38C1600 based controllers */ 113 { 114 PCI_ID_ADVANSYS_38C1600_REV1, 115 PCI_ID_DEV_VENDOR_MASK, 116 "AdvanSys 38C1600 Ultra160 SCSI Adapter", 117 adw_asc38C1600_setup, 118 NULL, /* None provided by vendor thus far */ 119 NULL /* None provided by vendor thus far */ 120 } 121#endif 122}; 123 124static const int adw_num_pci_devs = 125 sizeof(adw_pci_ident_table) / sizeof(*adw_pci_ident_table); 126 127#define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL) 128#define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL) 129 130static int adw_pci_probe(device_t dev); 131static int adw_pci_attach(device_t dev); 132 133static device_method_t adw_pci_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, adw_pci_probe), 136 DEVMETHOD(device_attach, adw_pci_attach), 137 { 0, 0 } 138}; 139 140static driver_t adw_pci_driver = { 141 "adw", 142 adw_pci_methods, 143 sizeof(struct adw_softc) 144}; 145 146static devclass_t adw_devclass; 147 148DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, 0, 0); 149MODULE_DEPEND(adw, pci, 1, 1, 1); 150 151static __inline u_int64_t 152adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 153{ 154 u_int64_t id; 155 156 id = subvendor 157 | (subdevice << 16) 158 | ((u_int64_t)vendor << 32) 159 | ((u_int64_t)device << 48); 160 161 return (id); 162} 163 164static struct adw_pci_identity * 165adw_find_pci_device(device_t dev) 166{ 167 u_int64_t full_id; 168 struct adw_pci_identity *entry; 169 u_int i; 170 171 full_id = adw_compose_id(pci_get_device(dev), 172 pci_get_vendor(dev), 173 pci_get_subdevice(dev), 174 pci_get_subvendor(dev)); 175 176 for (i = 0; i < adw_num_pci_devs; i++) { 177 entry = &adw_pci_ident_table[i]; 178 if (entry->full_id == (full_id & entry->id_mask)) 179 return (entry); 180 } 181 return (NULL); 182} 183 184static int 185adw_pci_probe(device_t dev) 186{ 187 struct adw_pci_identity *entry; 188 189 entry = adw_find_pci_device(dev); 190 if (entry != NULL) { 191 device_set_desc(dev, entry->name); 192 return (BUS_PROBE_DEFAULT); 193 } 194 return (ENXIO); 195} 196 197static int 198adw_pci_attach(device_t dev) 199{ 200 struct adw_softc *adw; 201 struct adw_pci_identity *entry; 202 u_int32_t command; 203 struct resource *regs; 204 int regs_type; 205 int regs_id; 206 int error; 207 int zero; 208 209 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 210 entry = adw_find_pci_device(dev); 211 if (entry == NULL) 212 return (ENXIO); 213 regs = NULL; 214 regs_type = 0; 215 regs_id = 0; 216#ifdef ADW_ALLOW_MEMIO 217 if ((command & PCIM_CMD_MEMEN) != 0) { 218 regs_type = SYS_RES_MEMORY; 219 regs_id = ADW_PCI_MEMBASE; 220 regs = bus_alloc_resource_any(dev, regs_type, 221 ®s_id, RF_ACTIVE); 222 } 223#endif 224 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) { 225 regs_type = SYS_RES_IOPORT; 226 regs_id = ADW_PCI_IOBASE; 227 regs = bus_alloc_resource_any(dev, regs_type, 228 ®s_id, RF_ACTIVE); 229 } 230 231 if (regs == NULL) { 232 device_printf(dev, "can't allocate register resources\n"); 233 return (ENOMEM); 234 } 235 236 adw = adw_alloc(dev, regs, regs_type, regs_id); 237 if (adw == NULL) 238 return(ENOMEM); 239 240 /* 241 * Now that we have access to our registers, just verify that 242 * this really is an AdvanSys device. 243 */ 244 if (adw_find_signature(adw) == 0) { 245 adw_free(adw); 246 return (ENXIO); 247 } 248 249 adw_reset_chip(adw); 250 251 error = entry->setup(dev, entry, adw); 252 253 if (error != 0) 254 return (error); 255 256 /* Ensure busmastering is enabled */ 257 pci_enable_busmaster(dev); 258 259 /* Allocate a dmatag for our transfer DMA maps */ 260 error = bus_dma_tag_create( 261 /* parent */ bus_get_dma_tag(dev), 262 /* alignment */ 1, 263 /* boundary */ 0, 264 /* lowaddr */ ADW_PCI_MAX_DMA_ADDR, 265 /* highaddr */ BUS_SPACE_MAXADDR, 266 /* filter */ NULL, 267 /* filterarg */ NULL, 268 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT, 269 /* nsegments */ ~0, 270 /* maxsegsz */ ADW_PCI_MAX_DMA_COUNT, 271 /* flags */ 0, 272 /* lockfunc */ NULL, 273 /* lockarg */ NULL, 274 &adw->parent_dmat); 275 276 adw->init_level++; 277 278 if (error != 0) { 279 device_printf(dev, "Could not allocate DMA tag - error %d\n", 280 error); 281 adw_free(adw); 282 return (error); 283 } 284 285 adw->init_level++; 286 287 error = adw_init(adw); 288 if (error != 0) { 289 adw_free(adw); 290 return (error); 291 } 292 293 /* 294 * If the PCI Configuration Command Register "Parity Error Response 295 * Control" Bit was clear (0), then set the microcode variable 296 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 297 * to ignore DMA parity errors. 298 */ 299 if ((command & PCIM_CMD_PERRESPEN) == 0) 300 adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG, 301 adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG) 302 | ADW_MC_CONTROL_IGN_PERR); 303 304 zero = 0; 305 adw->irq_res_type = SYS_RES_IRQ; 306 adw->irq = bus_alloc_resource_any(dev, adw->irq_res_type, &zero, 307 RF_ACTIVE | RF_SHAREABLE); 308 if (adw->irq == NULL) { 309 adw_free(adw); 310 return (ENOMEM); 311 } 312 313 error = adw_attach(adw); 314 if (error != 0) 315 adw_free(adw); 316 return (error); 317} 318 319static int 320adw_generic_setup(device_t dev, struct adw_pci_identity *entry, 321 struct adw_softc *adw) 322{ 323 adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 324 adw->chip = ADW_CHIP_NONE; 325 adw->features = ADW_FENONE; 326 adw->flags = ADW_FNONE; 327 adw->mcode_data = entry->mcode_data; 328 adw->default_eeprom = entry->default_eeprom; 329 return (0); 330} 331 332static int 333adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry, 334 struct adw_softc *adw) 335{ 336 int error; 337 338 error = adw_generic_setup(dev, entry, adw); 339 if (error != 0) 340 return (error); 341 adw->chip = ADW_CHIP_ASC3550; 342 adw->features = ADW_ASC3550_FE; 343 adw->memsize = ADW_3550_MEMSIZE; 344 /* 345 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits 346 * sets a FIFO threshold of 128 bytes. This register is 347 * only accessible to the host. 348 */ 349 adw_outb(adw, ADW_DMA_CFG0, 350 ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM); 351 adw_outb(adw, ADW_MEM_CFG, 352 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB); 353 return (0); 354} 355 356static int 357adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry, 358 struct adw_softc *adw) 359{ 360 int error; 361 362 error = adw_generic_setup(dev, entry, adw); 363 if (error != 0) 364 return (error); 365 /* 366 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 367 * START_CTL_TH [3:2] bits for the default FIFO threshold. 368 * 369 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 370 * 371 * For DMA Errata #4 set the BC_THRESH_ENB bit. 372 */ 373 adw_outb(adw, ADW_DMA_CFG0, 374 ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B 375 |ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM); 376 adw_outb(adw, ADW_MEM_CFG, 377 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB); 378 adw->chip = ADW_CHIP_ASC38C0800; 379 adw->features = ADW_ASC38C0800_FE; 380 adw->memsize = ADW_38C0800_MEMSIZE; 381 return (error); 382} 383 384#ifdef NOTYET 385static int 386adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry, 387 struct adw_softc *adw) 388{ 389 int error; 390 391 error = adw_generic_setup(dev, entry, adw); 392 if (error != 0) 393 return (error); 394 adw->chip = ADW_CHIP_ASC38C1600; 395 adw->features = ADW_ASC38C1600_FE; 396 adw->memsize = ADW_38C1600_MEMSIZE; 397 return (error); 398} 399#endif 400