advlib.h revision 50477
118781Sgibbs/* 218781Sgibbs * Definitions for low level routines and data structures 318781Sgibbs * for the Advanced Systems Inc. SCSI controllers chips. 418781Sgibbs * 539217Sgibbs * Copyright (c) 1996-1997 Justin T. Gibbs. 618781Sgibbs * All rights reserved. 718781Sgibbs * 818781Sgibbs * Redistribution and use in source and binary forms, with or without 918781Sgibbs * modification, are permitted provided that the following conditions 1018781Sgibbs * are met: 1118781Sgibbs * 1. Redistributions of source code must retain the above copyright 1239217Sgibbs * notice, this list of conditions, and the following disclaimer, 1339217Sgibbs * without modification, immediately at the beginning of the file. 1418781Sgibbs * 2. Redistributions in binary form must reproduce the above copyright 1518781Sgibbs * notice, this list of conditions and the following disclaimer in the 1618781Sgibbs * documentation and/or other materials provided with the distribution. 1718781Sgibbs * 3. The name of the author may not be used to endorse or promote products 1818781Sgibbs * derived from this software without specific prior written permission. 1918781Sgibbs * 2018781Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2118781Sgibbs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2218781Sgibbs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2318781Sgibbs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2418781Sgibbs * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2518781Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2618781Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2718781Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2818781Sgibbs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2918781Sgibbs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3018781Sgibbs * SUCH DAMAGE. 3118781Sgibbs * 3250477Speter * $FreeBSD: head/sys/dev/advansys/advlib.h 50477 1999-08-28 01:08:13Z peter $ 3318781Sgibbs */ 3418781Sgibbs/* 3518781Sgibbs * Ported from: 3618781Sgibbs * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 3718781Sgibbs * 3818781Sgibbs * Copyright (c) 1995-1996 Advanced System Products, Inc. 3918781Sgibbs * All Rights Reserved. 4018781Sgibbs * 4118781Sgibbs * Redistribution and use in source and binary forms, with or without 4218781Sgibbs * modification, are permitted provided that redistributions of source 4318781Sgibbs * code retain the above copyright notice and this comment without 4418781Sgibbs * modification. 4518781Sgibbs */ 4618781Sgibbs 4739217Sgibbs#ifndef _ADVLIB_H_ 4839217Sgibbs#define _ADVLIB_H_ 4939217Sgibbs 5039217Sgibbs#include <sys/queue.h> 5139217Sgibbs 5239217Sgibbsstruct cam_path; 5339217Sgibbs 5418781Sgibbstypedef u_int8_t target_bit_vector; 5518781Sgibbs#define TARGET_BIT_VECTOR_SET -1 5639217Sgibbs#define ADV_SCSI_ID_BITS 3 5739217Sgibbs#define ADV_MAX_TID 7 5839217Sgibbs#define ADV_MAX_LUN 7 5918781Sgibbs 6018781Sgibbs/* Enumeration of board types */ 6118781Sgibbstypedef enum { 6218781Sgibbs ADV_NONE = 0x000, 6339217Sgibbs ADV_ISA = 0x001, 6439217Sgibbs ADV_ISAPNP = 0x003, 6539217Sgibbs ADV_VL = 0x004, 6639217Sgibbs ADV_EISA = 0x008, 6739217Sgibbs ADV_PCI = 0x010, 6839217Sgibbs ADV_MCA = 0x020, 6939217Sgibbs ADV_PCMCIA = 0x040, 7039217Sgibbs ADV_ULTRA = 0x100, 7139217Sgibbs ADV_WIDE = 0x200, 7239217Sgibbs ADV_WIDE32 = 0x400 7339217Sgibbs} adv_btype; 7418781Sgibbs 7518781Sgibbstypedef enum { 7639217Sgibbs ADV_STATE_NONE = 0x00 7739217Sgibbs} adv_state; 7818781Sgibbs 7939217Sgibbstypedef enum { 8039217Sgibbs ACCB_FREE = 0x00, 8139217Sgibbs ACCB_ACTIVE = 0x01, 8239217Sgibbs ACCB_ABORT_QUEUED = 0x02, 8339217Sgibbs ACCB_RECOVERY_CCB = 0x04, 8439217Sgibbs ACCB_RELEASE_SIMQ = 0x08 8539217Sgibbs} adv_ccb_state; 8639217Sgibbs 8739217Sgibbsstruct adv_ccb_info { 8839217Sgibbs adv_ccb_state state; 8939217Sgibbs bus_dmamap_t dmamap; 9039217Sgibbs SLIST_ENTRY(adv_ccb_info) links; 9139217Sgibbs}; 9239217Sgibbs 9339217Sgibbs#define ccb_cinfo_ptr spriv_ptr0 9439217Sgibbs 9518781Sgibbs#define ADV_SYN_XFER_NO 8 9618781Sgibbs#define ADV_SYN_MAX_OFFSET 0x0F 9718781Sgibbs#define ADV_DEF_SDTR_OFFSET 0x0F 9818781Sgibbs#define ADV_DEF_SDTR_INDEX 0x00 9939217Sgibbs#define ADV_OVERRUN_BSIZE 0x00000040 10018781Sgibbs#define ADV_MAX_CDB_LEN 12 10118781Sgibbs#define ADV_MAX_SENSE_LEN 32 10218781Sgibbs#define ADV_MIN_SENSE_LEN 14 10318781Sgibbs 10418781Sgibbs#define ADV_TIDLUN_TO_IX(tid, lun) ((tid) | ((lun) << ADV_SCSI_ID_BITS) ) 10539217Sgibbs#define ADV_TID_TO_TARGET_MASK(tid) (0x01 << (tid)) 10639217Sgibbs#define ADV_TIX_TO_TARGET_MASK(tix) (0x01 << ((tix) & ADV_MAX_TID)) 10718781Sgibbs#define ADV_TIX_TO_TID(tix) ((tix) & ADV_MAX_TID) 10818781Sgibbs#define ADV_TID_TO_TIX(tid) ((tid) & ADV_MAX_TID) 10918781Sgibbs#define ADV_TIX_TO_LUN(tix) (((tix) >> ADV_SCSI_ID_BITS) & ADV_MAX_LUN ) 11018781Sgibbs 11118781Sgibbs 11218781Sgibbs/* 11318781Sgibbs * XXX 11418781Sgibbs * PnP port addresses 11518781Sgibbs * I believe that these are standard PnP address and should be replaced 11618781Sgibbs * by the values in a central ISA PnP header file when we get one. 11718781Sgibbs */ 11818781Sgibbs#define ADV_ISA_PNP_PORT_ADDR (0x279) 11918781Sgibbs#define ADV_ISA_PNP_PORT_WRITE (ADV_ISA_PNP_PORT_ADDR+0x800) 12039217Sgibbs 12118781Sgibbs/* 12218781Sgibbs * Board Signatures 12318781Sgibbs */ 12439217Sgibbs#define ADV_SIGNATURE_WORD 0x0000 12539217Sgibbs#define ADV_1000_ID0W 0x04C1 12639217Sgibbs#define ADV_1000_ID0W_FIX 0x00C1 12718781Sgibbs 12839217Sgibbs#define ADV_SIGNATURE_BYTE 0x0001 12939217Sgibbs#define ADV_1000_ID1B 0x25 13018781Sgibbs 13139217Sgibbs#define ADV_REG_IH 0x0002 13239217Sgibbs#define ADV_INS_HALTINT 0x6281 13339217Sgibbs#define ADV_INS_HALT 0x6280 13439217Sgibbs#define ADV_INS_SINT 0x6200 13539217Sgibbs#define ADV_INS_RFLAG_WTM 0x7380 13639217Sgibbs 13739217Sgibbs#define ADV_CONFIG_LSW 0x0002 13839217Sgibbs#define ADV_CFG_LSW_ISA_DMA_CHANNEL 0x0003 13939217Sgibbs#define ADV_CFG_LSW_HOST_INT_ON 0x0020 14039217Sgibbs#define ADV_CFG_LSW_BIOS_ON 0x0040 14139217Sgibbs#define ADV_CFG_LSW_VERA_BURST_ON 0x0080 14239217Sgibbs#define ADV_CFG_LSW_SCSI_PARITY_ON 0x0800 14339217Sgibbs#define ADV_CFG_LSW_SCSIID 0x0700 14439217Sgibbs#define ADV_CFG_LSW_SCSIID_SHIFT 8 14539217Sgibbs#define ADV_CONFIG_SCSIID(cfg) ((cfg >> ADV_CFG_LSW_SCSIID_SHIFT) & ADV_MAX_TID) 14639217Sgibbs 14718781Sgibbs/* 14818781Sgibbs * Chip Revision Number 14918781Sgibbs */ 15018781Sgibbs#define ADV_NONEISA_CHIP_REVISION 0x0003 15118781Sgibbs#define ADV_CHIP_MIN_VER_VL 0x01 15218781Sgibbs#define ADV_CHIP_MAX_VER_VL 0x07 15318781Sgibbs#define ADV_CHIP_MIN_VER_PCI 0x09 15418781Sgibbs#define ADV_CHIP_MAX_VER_PCI 0x0F 15518781Sgibbs#define ADV_CHIP_VER_PCI_BIT 0x08 15639217Sgibbs#define ADV_CHIP_VER_PCI_ULTRA_3150 (ADV_CHIP_VER_PCI_BIT | 0x02) 15739217Sgibbs#define ADV_CHIP_VER_PCI_ULTRA_3050 (ADV_CHIP_VER_PCI_BIT | 0x03) 15818781Sgibbs#define ADV_CHIP_MIN_VER_ISA 0x11 15918781Sgibbs#define ADV_CHIP_MIN_VER_ISA_PNP 0x21 16018781Sgibbs#define ADV_CHIP_MAX_VER_ISA 0x27 16118781Sgibbs#define ADV_CHIP_VER_ISA_BIT 0x30 16218781Sgibbs#define ADV_CHIP_VER_ISAPNP_BIT 0x20 16318781Sgibbs#define ADV_CHIP_VER_ASYN_BUG 0x21 16418781Sgibbs#define ADV_CHIP_MIN_VER_EISA 0x41 16518781Sgibbs#define ADV_CHIP_MAX_VER_EISA 0x47 16618781Sgibbs#define ADV_CHIP_VER_EISA_BIT 0x40 16718781Sgibbs 16839217Sgibbs#define ADV_CONFIG_MSW 0x0004 16939217Sgibbs#define ADV_CFG_MSW_SCSI_TARGET_ON 0x0080 17039217Sgibbs#define ADV_CFG_MSW_LRAM_8BITS_ON 0x0800 17139217Sgibbs#define ADV_CFG_MSW_CLR_MASK 0x30C0 17218781Sgibbs 17339217Sgibbs#define ADV_EEPROM_DATA 0x0006 17439217Sgibbs 17539217Sgibbs#define ADV_EEPROM_CMD 0x0007 17639217Sgibbs#define ADV_EEPROM_CMD_READ 0x80 17739217Sgibbs#define ADV_EEPROM_CMD_WRITE 0x40 17839217Sgibbs#define ADV_EEPROM_CMD_WRITE_ENABLE 0x30 17939217Sgibbs#define ADV_EEPROM_CMD_WRITE_DISABLE 0x00 18039217Sgibbs 18139217Sgibbs#define ADV_DMA_SPEED 0x0007 18239217Sgibbs#define ADV_DEF_ISA_DMA_SPEED 4 18339217Sgibbs#define ADV_REG_FLAG 0x0007 18439217Sgibbs 18539217Sgibbs#define ADV_LRAM_DATA 0x0008 18639217Sgibbs 18739217Sgibbs#define ADV_LRAM_ADDR 0x000A 18839217Sgibbs 18939217Sgibbs#define ADV_SYN_OFFSET 0x000B 19039217Sgibbs 19139217Sgibbs#define ADV_REG_PROG_COUNTER 0x000C 19239217Sgibbs#define ADV_MCODE_START_ADDR 0x0080 19339217Sgibbs 19439217Sgibbs#define ADV_REG_IFC 0x000D 19539217Sgibbs#define ADV_IFC_REG_LOCK 0x00 19639217Sgibbs#define ADV_IFC_REG_UNLOCK 0x09 19739217Sgibbs#define ADV_IFC_WR_EN_FILTER 0x10 19839217Sgibbs#define ADV_IFC_RD_NO_EEPROM 0x10 19939217Sgibbs#define ADV_IFC_SLEW_RATE 0x20 20039217Sgibbs#define ADV_IFC_ACT_NEG 0x40 20139217Sgibbs#define ADV_IFC_INP_FILTER 0x80 20239217Sgibbs#define ADV_IFC_INIT_DEFAULT (ADV_IFC_ACT_NEG | ADV_IFC_REG_UNLOCK) 20318781Sgibbs 20418781Sgibbs#define ADV_CHIP_STATUS 0x000E 20518781Sgibbs#define ADV_CSW_TEST1 0x8000 20618781Sgibbs#define ADV_CSW_AUTO_CONFIG 0x4000 20718781Sgibbs#define ADV_CSW_RESERVED1 0x2000 20818781Sgibbs#define ADV_CSW_IRQ_WRITTEN 0x1000 20918781Sgibbs#define ADV_CSW_33MHZ_SELECTED 0x0800 21018781Sgibbs#define ADV_CSW_TEST2 0x0400 21118781Sgibbs#define ADV_CSW_TEST3 0x0200 21218781Sgibbs#define ADV_CSW_RESERVED2 0x0100 21318781Sgibbs#define ADV_CSW_DMA_DONE 0x0080 21418781Sgibbs#define ADV_CSW_FIFO_RDY 0x0040 21518781Sgibbs#define ADV_CSW_EEP_READ_DONE 0x0020 21618781Sgibbs#define ADV_CSW_HALTED 0x0010 21718781Sgibbs#define ADV_CSW_SCSI_RESET_ACTIVE 0x0008 21818781Sgibbs#define ADV_CSW_PARITY_ERR 0x0004 21918781Sgibbs#define ADV_CSW_SCSI_RESET_LATCH 0x0002 22018781Sgibbs#define ADV_CSW_INT_PENDING 0x0001 22118781Sgibbs/* 22218781Sgibbs * XXX I don't understand the relevence of the naming 22318781Sgibbs * convention change here. What does CIW stand for? 22418781Sgibbs * Perhaps this is to differentiate read and write 22518781Sgibbs * values? 22618781Sgibbs */ 22718781Sgibbs#define ADV_CIW_INT_ACK 0x0100 22818781Sgibbs#define ADV_CIW_TEST1 0x0200 22918781Sgibbs#define ADV_CIW_TEST2 0x0400 23018781Sgibbs#define ADV_CIW_SEL_33MHZ 0x0800 23118781Sgibbs#define ADV_CIW_IRQ_ACT 0x1000 23239217Sgibbs#define ADV_CIW_CLR_SCSI_RESET_INT 0x1000 23318781Sgibbs 23439217Sgibbs#define ADV_CHIP_CTRL 0x000F 23539217Sgibbs#define ADV_CC_CHIP_RESET 0x80 23639217Sgibbs#define ADV_CC_SCSI_RESET 0x40 23739217Sgibbs#define ADV_CC_HALT 0x20 23839217Sgibbs#define ADV_CC_SINGLE_STEP 0x10 23939217Sgibbs#define ADV_CC_DMA_ENABLE 0x08 24039217Sgibbs#define ADV_CC_TEST 0x04 24139217Sgibbs#define ADV_CC_BANK_ONE 0x02 24239217Sgibbs#define ADV_CC_DIAG 0x01 24318781Sgibbs 24439217Sgibbs#define ADV_HALTCODE_W 0x0040 24539217Sgibbs#define ADV_STOP_CODE_B 0x0034 24639217Sgibbs#define ADV_STOP_REQ_RISC_STOP 0x01 24739217Sgibbs#define ADV_STOP_ACK_RISC_STOP 0x03 24839217Sgibbs#define ADV_STOP_CLEAN_UP_BUSY_Q 0x10 24939217Sgibbs#define ADV_STOP_CLEAN_UP_DISC_Q 0x20 25039217Sgibbs#define ADV_STOP_HOST_REQ_RISC_HALT 0x40 25118781Sgibbs 25218781Sgibbs/* 25318781Sgibbs * EEPROM routine constants 25418781Sgibbs * XXX What about wide controllers? 25518781Sgibbs * Surely they have space for 8 more targets. 25618781Sgibbs */ 25718781Sgibbs#define ADV_EEPROM_CFG_BEG_VL 2 25818781Sgibbs#define ADV_EEPROM_MAX_ADDR_VL 15 25918781Sgibbs#define ADV_EEPROM_CFG_BEG 32 26018781Sgibbs#define ADV_EEPROM_MAX_ADDR 45 26118781Sgibbs#define ADV_EEPROM_MAX_RETRY 20 26218781Sgibbs 26318781Sgibbsstruct adv_eeprom_config { 26418781Sgibbs u_int16_t cfg_lsw; 26518781Sgibbs 26618781Sgibbs u_int16_t cfg_msw; 26718781Sgibbs 26818781Sgibbs u_int8_t init_sdtr; 26918781Sgibbs u_int8_t disc_enable; 27018781Sgibbs 27118781Sgibbs u_int8_t use_cmd_qng; 27218781Sgibbs u_int8_t start_motor; 27318781Sgibbs 27418781Sgibbs u_int8_t max_total_qng; 27518781Sgibbs u_int8_t max_tag_qng; 27618781Sgibbs 27718781Sgibbs u_int8_t bios_scan; 27818781Sgibbs u_int8_t power_up_wait; 27918781Sgibbs 28018781Sgibbs u_int8_t no_scam; 28118781Sgibbs u_int8_t scsi_id_dma_speed; 28218781Sgibbs#define EEPROM_SCSI_ID_MASK 0x0F 28318781Sgibbs#define EEPROM_DMA_SPEED_MASK 0xF0 28439217Sgibbs#define EEPROM_DMA_SPEED(ep) \ 28539217Sgibbs (((ep).scsi_id_dma_speed & EEPROM_DMA_SPEED_MASK) >> 4) 28639217Sgibbs#define EEPROM_SET_DMA_SPEED(ep, speed) \ 28739217Sgibbs (ep).scsi_id_dma_speed &= ~EEPROM_DMA_SPEED_MASK; \ 28839217Sgibbs (ep).scsi_id_dma_speed |= \ 28939217Sgibbs (((speed) << 4) & EEPROM_DMA_SPEED_MASK) 29018781Sgibbs#define EEPROM_SCSIID(ep) ((ep).scsi_id_dma_speed & EEPROM_SCSI_ID_MASK) 29139217Sgibbs#define EEPROM_SET_SCSIID(ep, id) \ 29239217Sgibbs (ep).scsi_id_dma_speed &= ~EEPROM_SCSI_ID_MASK; \ 29339217Sgibbs (ep).scsi_id_dma_speed |= ((id) & EEPROM_SCSI_ID_MASK) 29418781Sgibbs /* XXX What about wide controllers??? */ 29518781Sgibbs u_int8_t sdtr_data[8]; 29618781Sgibbs u_int8_t adapter_info[6]; 29718781Sgibbs 29818781Sgibbs u_int16_t cntl; 29918781Sgibbs 30018781Sgibbs u_int16_t chksum; 30118781Sgibbs}; 30218781Sgibbs 30339217Sgibbs/* Bank 1 */ 30439217Sgibbs#define ADV_SEQ_ACCUM 0x0000 30539217Sgibbs#define ADV_QUEUE_ELEMENT_INDEX 0x0001 30639217Sgibbs#define ADV_SEQ_INSTRUCTION_HOLD 0x0002 30739217Sgibbs#define ADV_QUEUE_ELEMENT_POINTER 0x0003 30839217Sgibbs#define ADV_HOST_DATA_FIFO_L 0x0004 30939217Sgibbs#define ADV_HOST_SCSIID 0x0005 31039217Sgibbs#define ADV_HOST_DATA_FIFO_H 0x0006 31139217Sgibbs#define ADV_SCSI_CONTROL 0x0009 31239217Sgibbs#define SC_SEL 0x80 31339217Sgibbs#define SC_BSY 0x40 31439217Sgibbs#define SC_ACK 0x20 31539217Sgibbs#define SC_REQ 0x10 31639217Sgibbs#define SC_ATN 0x08 31739217Sgibbs#define SC_IO 0x04 31839217Sgibbs#define SC_CD 0x02 31939217Sgibbs#define SC_MSG 0x01 32039217Sgibbs#define ADV_SCSIDATL 0x000B 32139217Sgibbs#define ADV_DMA_TRANSFER_CNT 0x000C 32239217Sgibbs#define ADV_DMA_TRANSFER_CNT1 0x000E 32339217Sgibbs 32418781Sgibbs/* 32518781Sgibbs * Instruction data and code segment addresses, 32618781Sgibbs * and transaction address translation (queues). 32718781Sgibbs * All addresses refer to on board LRAM. 32818781Sgibbs */ 32918781Sgibbs#define ADV_DATA_SEC_BEG 0x0080 33018781Sgibbs#define ADV_DATA_SEC_END 0x0080 33118781Sgibbs#define ADV_CODE_SEC_BEG 0x0080 33218781Sgibbs#define ADV_CODE_SEC_END 0x0080 33318781Sgibbs#define ADV_QADR_BEG 0x4000 33418781Sgibbs#define ADV_QADR_END 0x7FFF 33518781Sgibbs#define ADV_QLAST_ADR 0x7FC0 33618781Sgibbs#define ADV_QBLK_SIZE 0x40 33718781Sgibbs#define ADV_BIOS_DATA_QBEG 0xF8 33818781Sgibbs#define ADV_MAX_QNO 0xF8 33918781Sgibbs#define ADV_QADR_USED (ADV_MAX_QNO * 64) 34018781Sgibbs#define ADV_QNO_TO_QADDR(q_no) ((ADV_QADR_BEG) + ((u_int16_t)(q_no) << 6)) 34118781Sgibbs 34218781Sgibbs#define ADV_MIN_ACTIVE_QNO 0x01 34318781Sgibbs#define ADV_QLINK_END 0xFF 34418781Sgibbs 34518781Sgibbs#define ADV_MAX_SG_QUEUE 5 34618781Sgibbs#define ADV_SG_LIST_PER_Q 7 34718781Sgibbs#define ADV_MAX_SG_LIST (1 + ((ADV_SG_LIST_PER_Q) * (ADV_MAX_SG_QUEUE))) 34818781Sgibbs 34918781Sgibbs#define ADV_MIN_REMAIN_Q 0x02 35039217Sgibbs#define ADV_DEF_MAX_TOTAL_QNG 0xF0 35118781Sgibbs#define ADV_MIN_TAG_Q_PER_DVC 0x04 35218781Sgibbs#define ADV_DEF_TAG_Q_PER_DVC 0x04 35318781Sgibbs#define ADV_MIN_FREE_Q ADV_MIN_REMAIN_Q 35418781Sgibbs#define ADV_MIN_TOTAL_QNG ((ADV_MAX_SG_QUEUE)+(ADV_MIN_FREE_Q)) 35518781Sgibbs#define ADV_MAX_TOTAL_QNG 240 35618781Sgibbs#define ADV_MAX_INRAM_TAG_QNG 16 35718781Sgibbs#define ADV_MAX_PCI_INRAM_TOTAL_QNG 20 35839217Sgibbs#define ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 35939217Sgibbs#define ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 36018781Sgibbs 36118781Sgibbs#define ADV_DEF_IRQ_NO 10 36218781Sgibbs#define ADV_MAX_IRQ_NO 15 36318781Sgibbs#define ADV_MIN_IRQ_NO 10 36418781Sgibbs 36518781Sgibbs#define ADV_SCSIQ_CPY_BEG 4 36618781Sgibbs#define ADV_SCSIQ_SGHD_CPY_BEG 2 36718781Sgibbs 36839217Sgibbs/* SCSIQ Microcode representation offsets */ 36918781Sgibbs#define ADV_SCSIQ_B_FWD 0 37018781Sgibbs#define ADV_SCSIQ_B_BWD 1 37118781Sgibbs#define ADV_SCSIQ_B_STATUS 2 37218781Sgibbs#define ADV_SCSIQ_B_QNO 3 37318781Sgibbs#define ADV_SCSIQ_B_CNTL 4 37418781Sgibbs#define ADV_SCSIQ_B_SG_QUEUE_CNT 5 37539217Sgibbs#define ADV_SCSIQ_B_LIST_CNT 6 37639217Sgibbs#define ADV_SCSIQ_B_CUR_LIST_CNT 7 37739217Sgibbs#define ADV_SCSIQ_D_DATA_ADDR 8 37839217Sgibbs#define ADV_SCSIQ_D_DATA_CNT 12 37939217Sgibbs#define ADV_SCSIQ_B_SENSE_LEN 20 38039217Sgibbs#define ADV_SCSIQ_DONE_INFO_BEG 22 38139217Sgibbs#define ADV_SCSIQ_D_CCBPTR 22 38239217Sgibbs#define ADV_SCSIQ_B_TARGET_IX 26 38339217Sgibbs#define ADV_SCSIQ_B_CDB_LEN 28 38439217Sgibbs#define ADV_SCSIQ_B_TAG_CODE 29 38539217Sgibbs#define ADV_SCSIQ_W_VM_ID 30 38639217Sgibbs#define ADV_SCSIQ_DONE_STATUS 32 38739217Sgibbs#define ADV_SCSIQ_HOST_STATUS 33 38839217Sgibbs#define ADV_SCSIQ_SCSI_STATUS 34 38939217Sgibbs#define ADV_SCSIQ_CDB_BEG 36 39039217Sgibbs#define ADV_SCSIQ_B_SG_WK_QP 49 39139217Sgibbs#define ADV_SCSIQ_B_SG_WK_IX 50 39239217Sgibbs#define ADV_SCSIQ_W_REQ_COUNT 52 39339217Sgibbs#define ADV_SCSIQ_DW_REMAIN_XFER_ADDR 56 39439217Sgibbs#define ADV_SCSIQ_DW_REMAIN_XFER_CNT 60 39518781Sgibbs 39618781Sgibbs/* LRAM Offsets */ 39718781Sgibbs#define ADVV_MSGOUT_BEG 0x0000 39818781Sgibbs#define ADVV_MSGOUT_SDTR_PERIOD (ADVV_MSGOUT_BEG+3) 39918781Sgibbs#define ADVV_MSGOUT_SDTR_OFFSET (ADVV_MSGOUT_BEG+4) 40018781Sgibbs 40139217Sgibbs#define ADVV_BREAK_SAVED_CODE 0x0006 40239217Sgibbs 40318781Sgibbs#define ADVV_MSGIN_BEG (ADVV_MSGOUT_BEG+8) 40418781Sgibbs#define ADVV_MSGIN_SDTR_PERIOD (ADVV_MSGIN_BEG+3) 40518781Sgibbs#define ADVV_MSGIN_SDTR_OFFSET (ADVV_MSGIN_BEG+4) 40618781Sgibbs 40718781Sgibbs#define ADVV_SDTR_DATA_BEG (ADVV_MSGIN_BEG+8) 40818781Sgibbs#define ADVV_SDTR_DONE_BEG (ADVV_SDTR_DATA_BEG+8) 40918781Sgibbs#define ADVV_MAX_DVC_QNG_BEG 0x0020 41018781Sgibbs 41139217Sgibbs#define ADVV_BREAK_ADDR 0x0028 41239217Sgibbs#define ADVV_BREAK_NOTIFY_COUNT 0x002A 41339217Sgibbs#define ADVV_BREAK_CONTROL 0x002C 41439217Sgibbs#define ADVV_BREAK_HIT_COUNT 0x002E 41539217Sgibbs 41618781Sgibbs#define ADVV_ASCDVC_ERR_CODE_W 0x0030 41718781Sgibbs#define ADVV_MCODE_CHKSUM_W 0x0032 41818781Sgibbs#define ADVV_MCODE_SIZE_W 0x0034 41918781Sgibbs#define ADVV_STOP_CODE_B 0x0036 42018781Sgibbs#define ADVV_DVC_ERR_CODE_B 0x0037 42118781Sgibbs 42218781Sgibbs#define ADVV_OVERRUN_PADDR_D 0x0038 42318781Sgibbs#define ADVV_OVERRUN_BSIZE_D 0x003C 42418781Sgibbs 42518781Sgibbs#define ADVV_HALTCODE_W 0x0040 42639217Sgibbs#define ADV_HALT_EXTMSG_IN 0x8000 42739217Sgibbs#define ADV_HALT_CHK_CONDITION 0x8100 42839217Sgibbs#define ADV_HALT_SS_QUEUE_FULL 0x8200 42939217Sgibbs#define ADV_HALT_DISABLE_ASYN_USE_SYN_FIX 0x8300 43039217Sgibbs#define ADV_HALT_ENABLE_ASYN_USE_SYN_FIX 0x8400 43139217Sgibbs#define ADV_HALT_SDTR_REJECTED 0x4000 43218781Sgibbs 43318781Sgibbs#define ADVV_CHKSUM_W 0x0042 43418781Sgibbs#define ADVV_MC_DATE_W 0x0044 43518781Sgibbs#define ADVV_MC_VER_W 0x0046 43618781Sgibbs#define ADVV_NEXTRDY_B 0x0048 43718781Sgibbs#define ADVV_DONENEXT_B 0x0049 43818781Sgibbs#define ADVV_USE_TAGGED_QNG_B 0x004A 43918781Sgibbs#define ADVV_SCSIBUSY_B 0x004B 44039217Sgibbs#define ADVV_Q_DONE_IN_PROGRESS_B 0x004C 44118781Sgibbs#define ADVV_CURCDB_B 0x004D 44218781Sgibbs#define ADVV_RCLUN_B 0x004E 44318781Sgibbs#define ADVV_BUSY_QHEAD_B 0x004F 44418781Sgibbs#define ADVV_DISC1_QHEAD_B 0x0050 44518781Sgibbs 44618781Sgibbs#define ADVV_DISC_ENABLE_B 0x0052 44718781Sgibbs#define ADVV_CAN_TAGGED_QNG_B 0x0053 44818781Sgibbs#define ADVV_HOSTSCSI_ID_B 0x0055 44918781Sgibbs#define ADVV_MCODE_CNTL_B 0x0056 45018781Sgibbs#define ADVV_NULL_TARGET_B 0x0057 45118781Sgibbs 45218781Sgibbs#define ADVV_FREE_Q_HEAD_W 0x0058 45318781Sgibbs#define ADVV_DONE_Q_TAIL_W 0x005A 45418781Sgibbs#define ADVV_FREE_Q_HEAD_B (ADVV_FREE_Q_HEAD_W+1) 45518781Sgibbs#define ADVV_DONE_Q_TAIL_B (ADVV_DONE_Q_TAIL_W+1) 45618781Sgibbs 45718781Sgibbs#define ADVV_HOST_FLAG_B 0x005D 45818781Sgibbs#define ADV_HOST_FLAG_IN_ISR 0x01 45918781Sgibbs#define ADV_HOST_FLAG_ACK_INT 0x02 46018781Sgibbs 46118781Sgibbs 46218781Sgibbs#define ADVV_TOTAL_READY_Q_B 0x0064 46318781Sgibbs#define ADVV_VER_SERIAL_B 0x0065 46418781Sgibbs#define ADVV_HALTCODE_SAVED_W 0x0066 46518781Sgibbs#define ADVV_WTM_FLAG_B 0x0068 46618781Sgibbs#define ADVV_RISC_FLAG_B 0x006A 46718781Sgibbs#define ADV_RISC_FLAG_GEN_INT 0x01 46818781Sgibbs#define ADV_RISC_FLAG_REQ_SG_LIST 0x02 46918781Sgibbs 47018781Sgibbs#define ADVV_REQ_SG_LIST_QP 0x006B 47139217Sgibbs 47239217Sgibbs#define ADV_TRANS_CUR 0x01 /* Modify current neogtiation status */ 47339217Sgibbs#define ADV_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 47439217Sgibbs#define ADV_TRANS_GOAL 0x04 /* Modify negotiation goal */ 47539217Sgibbs#define ADV_TRANS_USER 0x08 /* Modify user negotiation settings */ 47639217Sgibbs 47739217Sgibbsstruct adv_transinfo { 47839217Sgibbs u_int8_t period; 47939217Sgibbs u_int8_t offset; 48039217Sgibbs}; 48139217Sgibbs 48239217Sgibbsstruct adv_target_transinfo { 48339217Sgibbs struct adv_transinfo current; 48439217Sgibbs struct adv_transinfo goal; 48539217Sgibbs struct adv_transinfo user; 48639217Sgibbs}; 48739217Sgibbs 48818781Sgibbsstruct adv_softc 48918781Sgibbs{ 49039217Sgibbs bus_space_tag_t tag; 49139217Sgibbs bus_space_handle_t bsh; 49239217Sgibbs bus_dma_tag_t parent_dmat; 49339217Sgibbs bus_dma_tag_t buffer_dmat; 49439217Sgibbs bus_dma_tag_t sense_dmat; 49539217Sgibbs bus_dmamap_t sense_dmamap; 49639217Sgibbs struct scsi_sense_data *sense_buffers; 49739217Sgibbs bus_addr_t sense_physbase; 49839217Sgibbs bus_addr_t overrun_physbase; 49918781Sgibbs adv_btype type; 50039217Sgibbs struct adv_target_transinfo tinfo[8]; 50139217Sgibbs target_bit_vector fix_asyn_xfer; 50239217Sgibbs target_bit_vector fix_asyn_xfer_always; 50339217Sgibbs target_bit_vector disc_enable; 50439217Sgibbs target_bit_vector user_disc_enable; 50518781Sgibbs target_bit_vector cmd_qng_enabled; 50639217Sgibbs target_bit_vector user_cmd_qng_enabled; 50718781Sgibbs u_int16_t control; 50818781Sgibbs#define ADV_CNTL_INITIATOR 0x0001 50918781Sgibbs#define ADV_CNTL_BIOS_GT_1GB 0x0002 51018781Sgibbs#define ADV_CNTL_BIOS_GT_2_DISK 0x0004 51118781Sgibbs#define ADV_CNTL_BIOS_REMOVABLE 0x0008 51218781Sgibbs#define ADV_CNTL_NO_SCAM 0x0010 51318781Sgibbs#define ADV_CNTL_INT_MULTI_Q 0x0080 51418781Sgibbs#define ADV_CNTL_NO_LUN_SUPPORT 0x0040 51518781Sgibbs#define ADV_CNTL_NO_VERIFY_COPY 0x0100 51618781Sgibbs#define ADV_CNTL_RESET_SCSI 0x0200 51718781Sgibbs#define ADV_CNTL_INIT_INQUIRY 0x0400 51818781Sgibbs#define ADV_CNTL_INIT_VERBOSE 0x0800 51918781Sgibbs#define ADV_CNTL_SCSI_PARITY 0x1000 52018781Sgibbs#define ADV_CNTL_BURST_MODE 0x2000 52139217Sgibbs#define ADV_CNTL_SDTR_ENABLE_ULTRA 0x4000 52218781Sgibbs 52318781Sgibbs u_int16_t bug_fix_control; 52439217Sgibbs#define ADV_BUG_FIX_IF_NOT_DWB 0x0001 52539217Sgibbs#define ADV_BUG_FIX_ASYN_USE_SYN 0x0002 52618781Sgibbs 52718781Sgibbs adv_state state; 52839217Sgibbs struct cam_path *path; 52939217Sgibbs int unit; 53039217Sgibbs int init_level; 53139217Sgibbs u_int32_t max_dma_addr; 53218781Sgibbs u_int32_t max_dma_count; 53318781Sgibbs u_int8_t isa_dma_speed; 53439217Sgibbs u_int8_t isa_dma_channel; 53518781Sgibbs u_int8_t scsi_id; 53618781Sgibbs u_int8_t chip_version; 53718781Sgibbs u_int8_t max_tags_per_target; 53818781Sgibbs u_int8_t max_openings; 53918781Sgibbs u_int8_t cur_active; 54018781Sgibbs u_int8_t openings_needed; 54139217Sgibbs u_int8_t *sdtr_period_tbl; 54239217Sgibbs u_int8_t sdtr_period_tbl_size; 54339217Sgibbs struct cam_sim *sim; 54439217Sgibbs LIST_HEAD(, ccb_hdr) pending_ccbs; 54539217Sgibbs SLIST_HEAD(, adv_ccb_info) free_ccb_infos; 54618781Sgibbs}; 54718781Sgibbs 54818781Sgibbs/* 54918781Sgibbs * Structures for talking to the RISC engine. 55018781Sgibbs */ 55118781Sgibbsstruct adv_scsiq_1 { 55218781Sgibbs u_int8_t status; 55318781Sgibbs#define QS_FREE 0x00 55418781Sgibbs#define QS_READY 0x01 55518781Sgibbs#define QS_DISC1 0x02 55618781Sgibbs#define QS_DISC2 0x04 55718781Sgibbs#define QS_BUSY 0x08 55818781Sgibbs#define QS_ABORTED 0x40 55918781Sgibbs#define QS_DONE 0x80 56018781Sgibbs 56118781Sgibbs u_int8_t q_no; /* 56218781Sgibbs * Queue ID of the first queue 56318781Sgibbs * used in this transaction. 56418781Sgibbs */ 56518781Sgibbs u_int8_t cntl; 56618781Sgibbs#define QC_NO_CALLBACK 0x01 56718781Sgibbs#define QC_SG_SWAP_QUEUE 0x02 56818781Sgibbs#define QC_SG_HEAD 0x04 56918781Sgibbs#define QC_DATA_IN 0x08 57018781Sgibbs#define QC_DATA_OUT 0x10 57118781Sgibbs#define QC_URGENT 0x20 57218781Sgibbs#define QC_MSG_OUT 0x40 57318781Sgibbs#define QC_REQ_SENSE 0x80 57418781Sgibbs 57518781Sgibbs u_int8_t sg_queue_cnt; /* Number of SG entries */ 57618781Sgibbs 57718781Sgibbs u_int8_t target_id; /* target id as a bit vector */ 57818781Sgibbs u_int8_t target_lun; /* LUN - taken from our xs */ 57918781Sgibbs 58018781Sgibbs u_int32_t data_addr; /* 58118781Sgibbs * physical addres of first 58218781Sgibbs * (possibly only) segment 58318781Sgibbs * to transfer. 58418781Sgibbs */ 58518781Sgibbs u_int32_t data_cnt; /* 58618781Sgibbs * byte count of the first 58718781Sgibbs * (possibly only) segment 58818781Sgibbs * to transfer. 58918781Sgibbs */ 59018781Sgibbs u_int32_t sense_addr; /* 59118781Sgibbs * physical address of the sense 59218781Sgibbs * buffer. 59318781Sgibbs */ 59418781Sgibbs u_int8_t sense_len; /* length of sense buffer */ 59539217Sgibbs u_int8_t extra_bytes; 59618781Sgibbs}; 59718781Sgibbs 59818781Sgibbsstruct adv_scsiq_2 { 59939217Sgibbs u_int32_t ccb_ptr; /* Pointer to our CCB */ 60018781Sgibbs u_int8_t target_ix; /* Combined TID and LUN */ 60118781Sgibbs 60218781Sgibbs u_int8_t flag; 60318781Sgibbs u_int8_t cdb_len; /* 60418781Sgibbs * Number of bytes in the SCSI 60518781Sgibbs * command to execute. 60618781Sgibbs */ 60718781Sgibbs u_int8_t tag_code; /* 60818781Sgibbs * Tag type for this transaction 60918781Sgibbs * (SIMPLE, ORDERED, HEAD ) 61018781Sgibbs */ 61139217Sgibbs#define ADV_TAG_FLAG_EXTRA_BYTES 0x10 61239217Sgibbs#define ADV_TAG_FLAG_DISABLE_DISCONNECT 0x04 61339217Sgibbs#define ADV_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 61439217Sgibbs#define ADV_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 61518781Sgibbs 61618781Sgibbs u_int16_t vm_id; 61718781Sgibbs}; 61818781Sgibbs 61918781Sgibbsstruct adv_scsiq_3 { 62018781Sgibbs u_int8_t done_stat; 62118781Sgibbs#define QD_IN_PROGRESS 0x00 62218781Sgibbs#define QD_NO_ERROR 0x01 62318781Sgibbs#define QD_ABORTED_BY_HOST 0x02 62418781Sgibbs#define QD_WITH_ERROR 0x04 62518781Sgibbs#define QD_INVALID_REQUEST 0x80 62618781Sgibbs#define QD_INVALID_HOST_NUM 0x81 62718781Sgibbs#define QD_INVALID_DEVICE 0x82 62818781Sgibbs#define QD_ERR_INTERNAL 0xFF 62918781Sgibbs 63018781Sgibbs u_int8_t host_stat; 63118781Sgibbs#define QHSTA_NO_ERROR 0x00 63218781Sgibbs#define QHSTA_M_SEL_TIMEOUT 0x11 63318781Sgibbs#define QHSTA_M_DATA_OVER_RUN 0x12 63418781Sgibbs#define QHSTA_M_DATA_UNDER_RUN 0x12 63518781Sgibbs#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 63618781Sgibbs#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 63718781Sgibbs 63818781Sgibbs#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 63918781Sgibbs#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 64018781Sgibbs#define QHSTA_D_HOST_ABORT_FAILED 0x23 64118781Sgibbs#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24 64218781Sgibbs#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 64318781Sgibbs#define QHSTA_D_ASPI_NO_BUF_POOL 0x26 64418781Sgibbs 64518781Sgibbs#define QHSTA_M_WTM_TIMEOUT 0x41 64618781Sgibbs#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 64718781Sgibbs#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 64818781Sgibbs#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 64918781Sgibbs#define QHSTA_M_TARGET_STATUS_BUSY 0x45 65018781Sgibbs#define QHSTA_M_BAD_TAG_CODE 0x46 65118781Sgibbs 65218781Sgibbs#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 65339217Sgibbs#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 65418781Sgibbs 65518781Sgibbs#define QHSTA_D_LRAM_CMP_ERROR 0x81 65618781Sgibbs 65718781Sgibbs#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 65818781Sgibbs 65918781Sgibbs u_int8_t scsi_stat; 66018781Sgibbs u_int8_t scsi_msg; 66118781Sgibbs}; 66218781Sgibbs 66318781Sgibbsstruct adv_scsiq_4 { 66418781Sgibbs u_int8_t cdb[ADV_MAX_CDB_LEN]; 66518781Sgibbs u_int8_t y_first_sg_list_qp; 66618781Sgibbs u_int8_t y_working_sg_qp; 66718781Sgibbs u_int8_t y_working_sg_ix; 66839217Sgibbs u_int8_t y_res; 66918781Sgibbs u_int16_t x_req_count; 67018781Sgibbs u_int16_t x_reconnect_rtn; 67118781Sgibbs u_int32_t x_saved_data_addr; 67218781Sgibbs u_int32_t x_saved_data_cnt; 67318781Sgibbs}; 67418781Sgibbs 67518781Sgibbsstruct adv_q_done_info { 67618781Sgibbs struct adv_scsiq_2 d2; 67718781Sgibbs struct adv_scsiq_3 d3; 67818781Sgibbs u_int8_t q_status; 67918781Sgibbs u_int8_t q_no; 68018781Sgibbs u_int8_t cntl; 68118781Sgibbs u_int8_t sense_len; 68239217Sgibbs u_int8_t extra_bytes; 68318781Sgibbs u_int8_t res; 68418781Sgibbs u_int32_t remain_bytes; 68518781Sgibbs}; 68618781Sgibbs 68718781Sgibbsstruct adv_sg_entry { 68818781Sgibbs u_int32_t addr; 68918781Sgibbs u_int32_t bytes; 69018781Sgibbs}; 69118781Sgibbs 69218781Sgibbsstruct adv_sg_head { 69339217Sgibbs u_int16_t entry_cnt; /* 69439217Sgibbs * Number of SG entries 69539217Sgibbs * in this list 69639217Sgibbs */ 69718781Sgibbs 69839217Sgibbs u_int16_t queue_cnt; /* 69939217Sgibbs * Number of queues required 70039217Sgibbs * to store entry_cnt 70139217Sgibbs * SG entries. 70218781Sgibbs */ 70318781Sgibbs 70439217Sgibbs u_int16_t entry_to_copy; /* 70539217Sgibbs * Number of SG entries to 70639217Sgibbs * copy to the board. 70718781Sgibbs */ 70839217Sgibbs u_int16_t res; 70939217Sgibbs struct adv_sg_entry *sg_list; 71018781Sgibbs}; 71118781Sgibbs 71218781Sgibbs#define QCX_SORT (0x0001) 71318781Sgibbs#define QCX_COALEASE (0x0002) 71418781Sgibbs 71518781Sgibbsstruct adv_scsi_q { 71618781Sgibbs struct adv_scsiq_1 q1; 71718781Sgibbs struct adv_scsiq_2 q2; 71839217Sgibbs u_int8_t *cdbptr; /* 71918781Sgibbs * Pointer to the SCSI command 72018781Sgibbs * to execute. 72118781Sgibbs */ 72218781Sgibbs 72318781Sgibbs struct adv_sg_head *sg_head; /* 72418781Sgibbs * Pointer to possible SG list 72518781Sgibbs */ 72618781Sgibbs}; 72718781Sgibbs 72818781Sgibbsstruct adv_scsi_req_q { 72918781Sgibbs struct adv_scsiq_1 r1; 73018781Sgibbs struct adv_scsiq_2 r2; 73118781Sgibbs u_int8_t *cdbptr; 73218781Sgibbs struct adv_sg_head *sg_head; 73318781Sgibbs u_int8_t *sense_ptr; 73418781Sgibbs struct adv_scsiq_3 r3; 73518781Sgibbs u_int8_t cdb[ADV_MAX_CDB_LEN]; 73618781Sgibbs u_int8_t sense[ADV_MIN_SENSE_LEN]; 73718781Sgibbs}; 73818781Sgibbs 73918781Sgibbsstruct adv_risc_q { 74018781Sgibbs u_int8_t fwd; 74118781Sgibbs u_int8_t bwd; 74218781Sgibbs struct adv_scsiq_1 i1; 74318781Sgibbs struct adv_scsiq_2 i2; 74418781Sgibbs struct adv_scsiq_3 i3; 74518781Sgibbs struct adv_scsiq_4 i4; 74618781Sgibbs}; 74718781Sgibbs 74818781Sgibbsstruct adv_sg_list_q { 74918781Sgibbs u_int8_t seq_no; 75018781Sgibbs u_int8_t q_no; 75118781Sgibbs u_int8_t cntl; 75218781Sgibbs#define QCSG_SG_XFER_LIST 0x02 75318781Sgibbs#define QCSG_SG_XFER_MORE 0x04 75418781Sgibbs#define QCSG_SG_XFER_END 0x08 75518781Sgibbs 75618781Sgibbs u_int8_t sg_head_qp; 75718781Sgibbs u_int8_t sg_list_cnt; 75818781Sgibbs u_int8_t sg_cur_list_cnt; 75918781Sgibbs}; 76018781Sgibbs#define ADV_SGQ_B_SG_CNTL 4 76118781Sgibbs#define ADV_SGQ_B_SG_HEAD_QP 5 76218781Sgibbs#define ADV_SGQ_B_SG_LIST_CNT 6 76318781Sgibbs#define ADV_SGQ_B_SG_CUR_LIST_CNT 7 76418781Sgibbs#define ADV_SGQ_LIST_BEG 8 76518781Sgibbs 76618781Sgibbsstruct asc_risc_sg_list_q { 76718781Sgibbs u_int8_t fwd; 76818781Sgibbs u_int8_t bwd; 76918781Sgibbs struct adv_sg_list_q sg; 77039217Sgibbs struct adv_sg_entry sg_list[ADV_SG_LIST_PER_Q]; 77118781Sgibbs}; 77218781Sgibbs 77339217Sgibbs/* Chip Register functions */ 77439217Sgibbsvoid adv_set_bank(struct adv_softc *adv, u_int8_t bank); 77518781Sgibbs 77618781Sgibbs/* LRAM routines */ 77739217Sgibbsu_int8_t adv_read_lram_8(struct adv_softc *adv, u_int16_t addr); 77839217Sgibbsvoid adv_write_lram_8(struct adv_softc *adv, u_int16_t addr, 77939217Sgibbs u_int8_t value); 78039217Sgibbsu_int16_t adv_read_lram_16(struct adv_softc *adv, u_int16_t addr); 78139217Sgibbsvoid adv_write_lram_16(struct adv_softc *adv, u_int16_t addr, 78239217Sgibbs u_int16_t value); 78318781Sgibbs 78418781Sgibbs/* Intialization */ 78539217Sgibbsint adv_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh); 78639217Sgibbsvoid adv_lib_init(struct adv_softc *adv); 78718781Sgibbs 78839217Sgibbsu_int16_t adv_get_eeprom_config(struct adv_softc *adv, 78939217Sgibbs struct adv_eeprom_config *eeprom_config); 79039217Sgibbsint adv_set_eeprom_config(struct adv_softc *adv, 79139217Sgibbs struct adv_eeprom_config *eeprom_config); 79239217Sgibbsint adv_reset_chip_and_scsi_bus(struct adv_softc *adv); 79339217Sgibbsint adv_test_external_lram(struct adv_softc* adv); 79439217Sgibbsint adv_init_lram_and_mcode(struct adv_softc *adv); 79539217Sgibbsu_int8_t adv_get_chip_irq(struct adv_softc *adv); 79639217Sgibbsu_int8_t adv_set_chip_irq(struct adv_softc *adv, u_int8_t irq_no); 79739217Sgibbsvoid adv_set_chip_scsiid(struct adv_softc *adv, int new_id); 79839217Sgibbs 79918781Sgibbs/* Queue handling and execution */ 80039217Sgibbsint adv_execute_scsi_queue(struct adv_softc *adv, 80139217Sgibbs struct adv_scsi_q *scsiq, 80239217Sgibbs u_int32_t datalen); 80339217Sgibbsu_int8_t adv_copy_lram_doneq(struct adv_softc *adv, u_int16_t q_addr, 80439217Sgibbs struct adv_q_done_info *scsiq, u_int32_t max_dma_count); 80518781Sgibbs 80618781Sgibbs/* Chip Control */ 80739217Sgibbsint adv_start_chip(struct adv_softc *adv); 80839217Sgibbsvoid adv_start_execution(struct adv_softc *adv); 80939217Sgibbsint adv_stop_execution(struct adv_softc *adv); 81039217Sgibbsint adv_is_chip_halted(struct adv_softc *adv); 81118781Sgibbs 81218781Sgibbs/* Interrupt processing */ 81339217Sgibbsvoid adv_ack_interrupt(struct adv_softc *adv); 81439217Sgibbsvoid adv_isr_chip_halted(struct adv_softc *adv); 81539217Sgibbs 81639217Sgibbs/* SDTR Conversion */ 81739217Sgibbsvoid adv_set_syncrate(struct adv_softc *adv, struct cam_path *path, 81839217Sgibbs u_int target_id, u_int period, u_int offset, 81939217Sgibbs u_int type); 82039217Sgibbsvoid adv_sdtr_to_period_offset(struct adv_softc *adv, 82139217Sgibbs u_int8_t sync_data, u_int8_t *period, 82239217Sgibbs u_int8_t *offset, int tid); 82339217Sgibbsu_int8_t adv_period_offset_to_sdtr(struct adv_softc *adv, u_int *period, 82439217Sgibbs u_int *offset, int tid); 82539217Sgibbs 82639217Sgibbs/* Error recovery */ 82745964Sgibbsunion ccb; 82839217Sgibbsint adv_abort_ccb(struct adv_softc *adv, int target, int lun, 82939217Sgibbs union ccb *ccb, u_int32_t status, int queued_only); 83039217Sgibbsint adv_reset_bus(struct adv_softc *adv); 83139217Sgibbs 83239217Sgibbs/* Async event callback */ 83339217Sgibbsvoid advasync(void *callback_arg, u_int32_t code, 83439217Sgibbs struct cam_path *path, void *arg); 83539217Sgibbs 83639217Sgibbs#define ADV_INB(adv, offset) \ 83739217Sgibbs bus_space_read_1((adv)->tag, (adv)->bsh, offset) 83839217Sgibbs#define ADV_INW(adv, offset) \ 83939217Sgibbs bus_space_read_2((adv)->tag, (adv)->bsh, offset) 84039217Sgibbs#define ADV_INSB(adv, offset, valp, count) \ 84139217Sgibbs bus_space_read_multi_1((adv)->tag, (adv)->bsh, offset, valp, count) 84239217Sgibbs 84339217Sgibbs/* These controllers seem to have problems with PIO on some fast processors */ 84439217Sgibbsstatic __inline void ADV_INSW(struct adv_softc *, u_int, u_int16_t *, u_int); 84539217Sgibbsstatic __inline void 84639217SgibbsADV_INSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count) 84739217Sgibbs{ 84839217Sgibbs while (count--) 84939217Sgibbs *valp++ = bus_space_read_2(adv->tag, adv->bsh, offset); 85039217Sgibbs} 85139217Sgibbs 85239217Sgibbs#define ADV_OUTB(adv, offset, val) \ 85339217Sgibbs bus_space_write_1((adv)->tag, (adv)->bsh, offset, val) 85439217Sgibbs#define ADV_OUTW(adv, offset, val) \ 85539217Sgibbs bus_space_write_2((adv)->tag, (adv)->bsh, offset, val) 85639217Sgibbs 85739217Sgibbs/* These controllers seem to have problems with PIO on some fast processors */ 85839217Sgibbsstatic __inline void ADV_OUTSW(struct adv_softc *, u_int, u_int16_t *, u_int); 85939217Sgibbsstatic __inline void 86039217SgibbsADV_OUTSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count) 86139217Sgibbs{ 86239217Sgibbs while (count--) 86339217Sgibbs bus_space_write_2(adv->tag, adv->bsh, offset, *valp++); 86439217Sgibbs} 86539217Sgibbs 86639217Sgibbs#endif /* _ADVLIB_H_ */ 867