advlib.h revision 195534
1/*- 2 * Definitions for low level routines and data structures 3 * for the Advanced Systems Inc. SCSI controllers chips. 4 * 5 * Copyright (c) 1996-1997, 1999-2000 Justin T. Gibbs. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification, immediately at the beginning of the file. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/advansys/advlib.h 195534 2009-07-10 08:18:08Z scottl $ 33 */ 34/*- 35 * Ported from: 36 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 37 * 38 * Copyright (c) 1995-1996 Advanced System Products, Inc. 39 * All Rights Reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that redistributions of source 43 * code retain the above copyright notice and this comment without 44 * modification. 45 */ 46 47#ifndef _ADVLIB_H_ 48#define _ADVLIB_H_ 49 50#include <sys/queue.h> 51 52struct cam_path; 53union ccb; 54 55typedef u_int8_t target_bit_vector; 56#define TARGET_BIT_VECTOR_SET -1 57#define ADV_SCSI_ID_BITS 3 58#define ADV_MAX_TID 7 59#define ADV_MAX_LUN 7 60 61#define ADV_MAXPHYS (128 * 1024) 62 63/* Enumeration of board types */ 64typedef enum { 65 ADV_NONE = 0x000, 66 ADV_ISA = 0x001, 67 ADV_ISAPNP = 0x003, 68 ADV_VL = 0x004, 69 ADV_EISA = 0x008, 70 ADV_PCI = 0x010, 71 ADV_MCA = 0x020, 72 ADV_PCMCIA = 0x040, 73 ADV_ULTRA = 0x100, 74 ADV_WIDE = 0x200, 75 ADV_WIDE32 = 0x400 76} adv_btype; 77 78typedef enum { 79 ADV_STATE_NONE = 0x00, 80 ADV_RESOURCE_SHORTAGE = 0x01, 81 ADV_IN_TIMEOUT = 0x02, 82 ADV_BUSDMA_BLOCK = 0x04, 83 ADV_BUSDMA_BLOCK_CLEARED = 0x08 84 85} adv_state; 86 87typedef enum { 88 ACCB_FREE = 0x00, 89 ACCB_ACTIVE = 0x01, 90 ACCB_ABORT_QUEUED = 0x02, 91 ACCB_RECOVERY_CCB = 0x04 92} adv_ccb_state; 93 94struct adv_ccb_info { 95 adv_ccb_state state; 96 bus_dmamap_t dmamap; 97 union ccb* ccb; 98 SLIST_ENTRY(adv_ccb_info) links; 99}; 100 101#define ccb_cinfo_ptr spriv_ptr0 102 103#define ADV_SYN_XFER_NO 8 104#define ADV_SYN_MAX_OFFSET 0x0F 105#define ADV_DEF_SDTR_OFFSET 0x0F 106#define ADV_DEF_SDTR_INDEX 0x00 107#define ADV_OVERRUN_BSIZE 0x00000040 108#define ADV_MAX_CDB_LEN 12 109#define ADV_MAX_SENSE_LEN 32 110#define ADV_MIN_SENSE_LEN 14 111 112#define ADV_TIDLUN_TO_IX(tid, lun) ((tid) | ((lun) << ADV_SCSI_ID_BITS) ) 113#define ADV_TID_TO_TARGET_MASK(tid) (0x01 << (tid)) 114#define ADV_TIX_TO_TARGET_MASK(tix) (0x01 << ((tix) & ADV_MAX_TID)) 115#define ADV_TIX_TO_TID(tix) ((tix) & ADV_MAX_TID) 116#define ADV_TID_TO_TIX(tid) ((tid) & ADV_MAX_TID) 117#define ADV_TIX_TO_LUN(tix) (((tix) >> ADV_SCSI_ID_BITS) & ADV_MAX_LUN ) 118 119 120/* 121 * XXX 122 * PnP port addresses 123 * I believe that these are standard PnP address and should be replaced 124 * by the values in a central ISA PnP header file when we get one. 125 */ 126#define ADV_ISA_PNP_PORT_ADDR (0x279) 127#define ADV_ISA_PNP_PORT_WRITE (ADV_ISA_PNP_PORT_ADDR+0x800) 128 129/* 130 * Board Signatures 131 */ 132#define ADV_SIGNATURE_WORD 0x0000 133#define ADV_1000_ID0W 0x04C1 134#define ADV_1000_ID0W_FIX 0x00C1 135 136#define ADV_SIGNATURE_BYTE 0x0001 137#define ADV_1000_ID1B 0x25 138 139#define ADV_REG_IH 0x0002 140#define ADV_INS_HALTINT 0x6281 141#define ADV_INS_HALT 0x6280 142#define ADV_INS_SINT 0x6200 143#define ADV_INS_RFLAG_WTM 0x7380 144 145#define ADV_CONFIG_LSW 0x0002 146#define ADV_CFG_LSW_ISA_DMA_CHANNEL 0x0003 147#define ADV_CFG_LSW_HOST_INT_ON 0x0020 148#define ADV_CFG_LSW_BIOS_ON 0x0040 149#define ADV_CFG_LSW_VERA_BURST_ON 0x0080 150#define ADV_CFG_LSW_SCSI_PARITY_ON 0x0800 151#define ADV_CFG_LSW_SCSIID 0x0700 152#define ADV_CFG_LSW_SCSIID_SHIFT 8 153#define ADV_CONFIG_SCSIID(cfg) ((cfg >> ADV_CFG_LSW_SCSIID_SHIFT) & ADV_MAX_TID) 154 155/* 156 * Chip Revision Number 157 */ 158#define ADV_NONEISA_CHIP_REVISION 0x0003 159#define ADV_CHIP_MIN_VER_VL 0x01 160#define ADV_CHIP_MAX_VER_VL 0x07 161#define ADV_CHIP_MIN_VER_PCI 0x09 162#define ADV_CHIP_MAX_VER_PCI 0x0F 163#define ADV_CHIP_VER_PCI_BIT 0x08 164#define ADV_CHIP_VER_PCI_ULTRA_3150 (ADV_CHIP_VER_PCI_BIT | 0x02) 165#define ADV_CHIP_VER_PCI_ULTRA_3050 (ADV_CHIP_VER_PCI_BIT | 0x03) 166#define ADV_CHIP_MIN_VER_ISA 0x11 167#define ADV_CHIP_MIN_VER_ISA_PNP 0x21 168#define ADV_CHIP_MAX_VER_ISA 0x27 169#define ADV_CHIP_VER_ISA_BIT 0x30 170#define ADV_CHIP_VER_ISAPNP_BIT 0x20 171#define ADV_CHIP_VER_ASYN_BUG 0x21 172#define ADV_CHIP_MIN_VER_EISA 0x41 173#define ADV_CHIP_MAX_VER_EISA 0x47 174#define ADV_CHIP_VER_EISA_BIT 0x40 175 176#define ADV_CONFIG_MSW 0x0004 177#define ADV_CFG_MSW_SCSI_TARGET_ON 0x0080 178#define ADV_CFG_MSW_LRAM_8BITS_ON 0x0800 179#define ADV_CFG_MSW_CLR_MASK 0x30C0 180 181#define ADV_EEPROM_DATA 0x0006 182 183#define ADV_EEPROM_CMD 0x0007 184#define ADV_EEPROM_CMD_READ 0x80 185#define ADV_EEPROM_CMD_WRITE 0x40 186#define ADV_EEPROM_CMD_WRITE_ENABLE 0x30 187#define ADV_EEPROM_CMD_WRITE_DISABLE 0x00 188 189#define ADV_DMA_SPEED 0x0007 190#define ADV_DEF_ISA_DMA_SPEED 4 191#define ADV_REG_FLAG 0x0007 192 193#define ADV_LRAM_DATA 0x0008 194 195#define ADV_LRAM_ADDR 0x000A 196 197#define ADV_SYN_OFFSET 0x000B 198 199#define ADV_REG_PROG_COUNTER 0x000C 200#define ADV_MCODE_START_ADDR 0x0080 201 202#define ADV_REG_IFC 0x000D 203#define ADV_IFC_REG_LOCK 0x00 204#define ADV_IFC_REG_UNLOCK 0x09 205#define ADV_IFC_WR_EN_FILTER 0x10 206#define ADV_IFC_RD_NO_EEPROM 0x10 207#define ADV_IFC_SLEW_RATE 0x20 208#define ADV_IFC_ACT_NEG 0x40 209#define ADV_IFC_INP_FILTER 0x80 210#define ADV_IFC_INIT_DEFAULT (ADV_IFC_ACT_NEG | ADV_IFC_REG_UNLOCK) 211 212#define ADV_CHIP_STATUS 0x000E 213#define ADV_CSW_TEST1 0x8000 214#define ADV_CSW_AUTO_CONFIG 0x4000 215#define ADV_CSW_RESERVED1 0x2000 216#define ADV_CSW_IRQ_WRITTEN 0x1000 217#define ADV_CSW_33MHZ_SELECTED 0x0800 218#define ADV_CSW_TEST2 0x0400 219#define ADV_CSW_TEST3 0x0200 220#define ADV_CSW_RESERVED2 0x0100 221#define ADV_CSW_DMA_DONE 0x0080 222#define ADV_CSW_FIFO_RDY 0x0040 223#define ADV_CSW_EEP_READ_DONE 0x0020 224#define ADV_CSW_HALTED 0x0010 225#define ADV_CSW_SCSI_RESET_ACTIVE 0x0008 226#define ADV_CSW_PARITY_ERR 0x0004 227#define ADV_CSW_SCSI_RESET_LATCH 0x0002 228#define ADV_CSW_INT_PENDING 0x0001 229/* 230 * XXX I don't understand the relevence of the naming 231 * convention change here. What does CIW stand for? 232 * Perhaps this is to differentiate read and write 233 * values? 234 */ 235#define ADV_CIW_INT_ACK 0x0100 236#define ADV_CIW_TEST1 0x0200 237#define ADV_CIW_TEST2 0x0400 238#define ADV_CIW_SEL_33MHZ 0x0800 239#define ADV_CIW_IRQ_ACT 0x1000 240#define ADV_CIW_CLR_SCSI_RESET_INT 0x1000 241 242#define ADV_CHIP_CTRL 0x000F 243#define ADV_CC_CHIP_RESET 0x80 244#define ADV_CC_SCSI_RESET 0x40 245#define ADV_CC_HALT 0x20 246#define ADV_CC_SINGLE_STEP 0x10 247#define ADV_CC_DMA_ENABLE 0x08 248#define ADV_CC_TEST 0x04 249#define ADV_CC_BANK_ONE 0x02 250#define ADV_CC_DIAG 0x01 251 252#define ADV_HALTCODE_W 0x0040 253#define ADV_STOP_CODE_B 0x0034 254#define ADV_STOP_REQ_RISC_STOP 0x01 255#define ADV_STOP_ACK_RISC_STOP 0x03 256#define ADV_STOP_CLEAN_UP_BUSY_Q 0x10 257#define ADV_STOP_CLEAN_UP_DISC_Q 0x20 258#define ADV_STOP_HOST_REQ_RISC_HALT 0x40 259 260/* 261 * EEPROM routine constants 262 * XXX What about wide controllers? 263 * Surely they have space for 8 more targets. 264 */ 265#define ADV_EEPROM_CFG_BEG_VL 2 266#define ADV_EEPROM_MAX_ADDR_VL 15 267#define ADV_EEPROM_CFG_BEG 32 268#define ADV_EEPROM_MAX_ADDR 45 269#define ADV_EEPROM_MAX_RETRY 20 270 271struct adv_eeprom_config { 272 u_int16_t cfg_lsw; 273 274 u_int16_t cfg_msw; 275 276 u_int8_t init_sdtr; 277 u_int8_t disc_enable; 278 279 u_int8_t use_cmd_qng; 280 u_int8_t start_motor; 281 282 u_int8_t max_total_qng; 283 u_int8_t max_tag_qng; 284 285 u_int8_t bios_scan; 286 u_int8_t power_up_wait; 287 288 u_int8_t no_scam; 289 u_int8_t scsi_id_dma_speed; 290#define EEPROM_SCSI_ID_MASK 0x0F 291#define EEPROM_DMA_SPEED_MASK 0xF0 292#define EEPROM_DMA_SPEED(ep) \ 293 (((ep).scsi_id_dma_speed & EEPROM_DMA_SPEED_MASK) >> 4) 294#define EEPROM_SET_DMA_SPEED(ep, speed) \ 295 (ep).scsi_id_dma_speed &= ~EEPROM_DMA_SPEED_MASK; \ 296 (ep).scsi_id_dma_speed |= \ 297 (((speed) << 4) & EEPROM_DMA_SPEED_MASK) 298#define EEPROM_SCSIID(ep) ((ep).scsi_id_dma_speed & EEPROM_SCSI_ID_MASK) 299#define EEPROM_SET_SCSIID(ep, id) \ 300 (ep).scsi_id_dma_speed &= ~EEPROM_SCSI_ID_MASK; \ 301 (ep).scsi_id_dma_speed |= ((id) & EEPROM_SCSI_ID_MASK) 302 u_int8_t sdtr_data[8]; 303 u_int8_t adapter_info[6]; 304 305 u_int16_t cntl; 306 307 u_int16_t chksum; 308}; 309 310/* Bank 1 */ 311#define ADV_SEQ_ACCUM 0x0000 312#define ADV_QUEUE_ELEMENT_INDEX 0x0001 313#define ADV_SEQ_INSTRUCTION_HOLD 0x0002 314#define ADV_QUEUE_ELEMENT_POINTER 0x0003 315#define ADV_HOST_DATA_FIFO_L 0x0004 316#define ADV_HOST_SCSIID 0x0005 317#define ADV_HOST_DATA_FIFO_H 0x0006 318#define ADV_SCSI_CONTROL 0x0009 319#define SC_SEL 0x80 320#define SC_BSY 0x40 321#define SC_ACK 0x20 322#define SC_REQ 0x10 323#define SC_ATN 0x08 324#define SC_IO 0x04 325#define SC_CD 0x02 326#define SC_MSG 0x01 327#define ADV_SCSIDATL 0x000B 328#define ADV_DMA_TRANSFER_CNT 0x000C 329#define ADV_DMA_TRANSFER_CNT1 0x000E 330 331/* 332 * Instruction data and code segment addresses, 333 * and transaction address translation (queues). 334 * All addresses refer to on board LRAM. 335 */ 336#define ADV_DATA_SEC_BEG 0x0080 337#define ADV_DATA_SEC_END 0x0080 338#define ADV_CODE_SEC_BEG 0x0080 339#define ADV_CODE_SEC_END 0x0080 340#define ADV_QADR_BEG 0x4000 341#define ADV_QADR_END 0x7FFF 342#define ADV_QLAST_ADR 0x7FC0 343#define ADV_QBLK_SIZE 0x40 344#define ADV_BIOS_DATA_QBEG 0xF8 345#define ADV_MAX_QNO 0xF8 346#define ADV_QADR_USED (ADV_MAX_QNO * 64) 347#define ADV_QNO_TO_QADDR(q_no) ((ADV_QADR_BEG) + ((u_int16_t)(q_no) << 6)) 348 349#define ADV_MIN_ACTIVE_QNO 0x01 350#define ADV_QLINK_END 0xFF 351 352#define ADV_MAX_SG_QUEUE 5 353#define ADV_SG_LIST_PER_Q 7 354#define ADV_MAX_SG_LIST (1 + ((ADV_SG_LIST_PER_Q) * (ADV_MAX_SG_QUEUE))) 355 356#define ADV_MIN_REMAIN_Q 0x02 357#define ADV_DEF_MAX_TOTAL_QNG 0xF0 358#define ADV_MIN_TAG_Q_PER_DVC 0x04 359#define ADV_DEF_TAG_Q_PER_DVC 0x04 360#define ADV_MIN_FREE_Q ADV_MIN_REMAIN_Q 361#define ADV_MIN_TOTAL_QNG ((ADV_MAX_SG_QUEUE)+(ADV_MIN_FREE_Q)) 362#define ADV_MAX_TOTAL_QNG 240 363#define ADV_MAX_INRAM_TAG_QNG 16 364#define ADV_MAX_PCI_INRAM_TOTAL_QNG 20 365#define ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 366#define ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 367 368#define ADV_DEF_IRQ_NO 10 369#define ADV_MAX_IRQ_NO 15 370#define ADV_MIN_IRQ_NO 10 371 372#define ADV_SCSIQ_CPY_BEG 4 373#define ADV_SCSIQ_SGHD_CPY_BEG 2 374 375/* SCSIQ Microcode representation offsets */ 376#define ADV_SCSIQ_B_FWD 0 377#define ADV_SCSIQ_B_BWD 1 378#define ADV_SCSIQ_B_STATUS 2 379#define ADV_SCSIQ_B_QNO 3 380#define ADV_SCSIQ_B_CNTL 4 381#define ADV_SCSIQ_B_SG_QUEUE_CNT 5 382#define ADV_SCSIQ_B_LIST_CNT 6 383#define ADV_SCSIQ_B_CUR_LIST_CNT 7 384#define ADV_SCSIQ_D_DATA_ADDR 8 385#define ADV_SCSIQ_D_DATA_CNT 12 386#define ADV_SCSIQ_B_SENSE_LEN 20 387#define ADV_SCSIQ_DONE_INFO_BEG 22 388#define ADV_SCSIQ_D_CINFO_IDX 22 389#define ADV_SCSIQ_B_TARGET_IX 26 390#define ADV_SCSIQ_B_CDB_LEN 28 391#define ADV_SCSIQ_B_TAG_CODE 29 392#define ADV_SCSIQ_W_VM_ID 30 393#define ADV_SCSIQ_DONE_STATUS 32 394#define ADV_SCSIQ_HOST_STATUS 33 395#define ADV_SCSIQ_SCSI_STATUS 34 396#define ADV_SCSIQ_CDB_BEG 36 397#define ADV_SCSIQ_B_FIRST_SG_QK_QP 48 398#define ADV_SCSIQ_B_SG_WK_QP 49 399#define ADV_SCSIQ_B_SG_WK_IX 50 400#define ADV_SCSIQ_W_ALT_DC1 52 401#define ADV_SCSIQ_DW_REMAIN_XFER_ADDR 56 402#define ADV_SCSIQ_DW_REMAIN_XFER_CNT 60 403 404/* LRAM Offsets */ 405#define ADVV_MSGOUT_BEG 0x0000 406#define ADVV_MSGOUT_SDTR_PERIOD (ADVV_MSGOUT_BEG+3) 407#define ADVV_MSGOUT_SDTR_OFFSET (ADVV_MSGOUT_BEG+4) 408 409#define ADVV_BREAK_SAVED_CODE 0x0006 410 411#define ADVV_MSGIN_BEG (ADVV_MSGOUT_BEG+8) 412#define ADVV_MSGIN_SDTR_PERIOD (ADVV_MSGIN_BEG+3) 413#define ADVV_MSGIN_SDTR_OFFSET (ADVV_MSGIN_BEG+4) 414 415#define ADVV_SDTR_DATA_BEG (ADVV_MSGIN_BEG+8) 416#define ADVV_SDTR_DONE_BEG (ADVV_SDTR_DATA_BEG+8) 417#define ADVV_MAX_DVC_QNG_BEG 0x0020 418 419#define ADVV_BREAK_ADDR 0x0028 420#define ADVV_BREAK_NOTIFY_COUNT 0x002A 421#define ADVV_BREAK_CONTROL 0x002C 422#define ADVV_BREAK_HIT_COUNT 0x002E 423 424#define ADVV_ASCDVC_ERR_CODE_W 0x0030 425#define ADVV_MCODE_CHKSUM_W 0x0032 426#define ADVV_MCODE_SIZE_W 0x0034 427#define ADVV_STOP_CODE_B 0x0036 428#define ADVV_DVC_ERR_CODE_B 0x0037 429 430#define ADVV_OVERRUN_PADDR_D 0x0038 431#define ADVV_OVERRUN_BSIZE_D 0x003C 432 433#define ADVV_HALTCODE_W 0x0040 434#define ADV_HALT_EXTMSG_IN 0x8000 435#define ADV_HALT_CHK_CONDITION 0x8100 436#define ADV_HALT_SS_QUEUE_FULL 0x8200 437#define ADV_HALT_DISABLE_ASYN_USE_SYN_FIX 0x8300 438#define ADV_HALT_ENABLE_ASYN_USE_SYN_FIX 0x8400 439#define ADV_HALT_SDTR_REJECTED 0x4000 440#define ADV_HALT_HOST_COPY_SG_LIST_TO_RISC 0x2000 441 442#define ADVV_CHKSUM_W 0x0042 443#define ADVV_MC_DATE_W 0x0044 444#define ADVV_MC_VER_W 0x0046 445#define ADVV_NEXTRDY_B 0x0048 446#define ADVV_DONENEXT_B 0x0049 447#define ADVV_USE_TAGGED_QNG_B 0x004A 448#define ADVV_SCSIBUSY_B 0x004B 449#define ADVV_Q_DONE_IN_PROGRESS_B 0x004C 450#define ADVV_CURCDB_B 0x004D 451#define ADVV_RCLUN_B 0x004E 452#define ADVV_BUSY_QHEAD_B 0x004F 453#define ADVV_DISC1_QHEAD_B 0x0050 454 455#define ADVV_DISC_ENABLE_B 0x0052 456#define ADVV_CAN_TAGGED_QNG_B 0x0053 457#define ADVV_HOSTSCSI_ID_B 0x0055 458#define ADVV_MCODE_CNTL_B 0x0056 459#define ADVV_NULL_TARGET_B 0x0057 460 461#define ADVV_FREE_Q_HEAD_W 0x0058 462#define ADVV_DONE_Q_TAIL_W 0x005A 463#define ADVV_FREE_Q_HEAD_B (ADVV_FREE_Q_HEAD_W+1) 464#define ADVV_DONE_Q_TAIL_B (ADVV_DONE_Q_TAIL_W+1) 465 466#define ADVV_HOST_FLAG_B 0x005D 467#define ADV_HOST_FLAG_IN_ISR 0x01 468#define ADV_HOST_FLAG_ACK_INT 0x02 469 470 471#define ADVV_TOTAL_READY_Q_B 0x0064 472#define ADVV_VER_SERIAL_B 0x0065 473#define ADVV_HALTCODE_SAVED_W 0x0066 474#define ADVV_WTM_FLAG_B 0x0068 475#define ADVV_RISC_FLAG_B 0x006A 476#define ADV_RISC_FLAG_GEN_INT 0x01 477#define ADV_RISC_FLAG_REQ_SG_LIST 0x02 478 479#define ADVV_REQ_SG_LIST_QP 0x006B 480 481#define ADV_TRANS_CUR 0x01 /* Modify current neogtiation status */ 482#define ADV_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 483#define ADV_TRANS_GOAL 0x04 /* Modify negotiation goal */ 484#define ADV_TRANS_USER 0x08 /* Modify user negotiation settings */ 485 486struct adv_transinfo { 487 u_int8_t period; 488 u_int8_t offset; 489}; 490 491struct adv_target_transinfo { 492 struct adv_transinfo current; 493 struct adv_transinfo goal; 494 struct adv_transinfo user; 495}; 496 497struct adv_softc { 498 device_t dev; 499 bus_space_tag_t tag; 500 bus_space_handle_t bsh; 501 struct cam_sim *sim; 502 LIST_HEAD(, ccb_hdr) pending_ccbs; 503 struct adv_ccb_info *ccb_infos; 504 SLIST_HEAD(, adv_ccb_info) free_ccb_infos; 505 bus_dma_tag_t parent_dmat; 506 bus_dma_tag_t buffer_dmat; 507 bus_dma_tag_t sense_dmat; 508 bus_dmamap_t sense_dmamap; 509 struct scsi_sense_data *sense_buffers; 510 bus_addr_t sense_physbase; 511 bus_addr_t overrun_physbase; 512 adv_btype type; 513 struct adv_target_transinfo tinfo[8]; 514 target_bit_vector fix_asyn_xfer; 515 target_bit_vector fix_asyn_xfer_always; 516 target_bit_vector disc_enable; 517 target_bit_vector user_disc_enable; 518 target_bit_vector cmd_qng_enabled; 519 target_bit_vector user_cmd_qng_enabled; 520 u_int16_t control; 521#define ADV_CNTL_INITIATOR 0x0001 522#define ADV_CNTL_BIOS_GT_1GB 0x0002 523#define ADV_CNTL_BIOS_GT_2_DISK 0x0004 524#define ADV_CNTL_BIOS_REMOVABLE 0x0008 525#define ADV_CNTL_NO_SCAM 0x0010 526#define ADV_CNTL_INT_MULTI_Q 0x0080 527#define ADV_CNTL_NO_LUN_SUPPORT 0x0040 528#define ADV_CNTL_NO_VERIFY_COPY 0x0100 529#define ADV_CNTL_RESET_SCSI 0x0200 530#define ADV_CNTL_INIT_INQUIRY 0x0400 531#define ADV_CNTL_INIT_VERBOSE 0x0800 532#define ADV_CNTL_SCSI_PARITY 0x1000 533#define ADV_CNTL_BURST_MODE 0x2000 534#define ADV_CNTL_SDTR_ENABLE_ULTRA 0x4000 535 536 u_int16_t bug_fix_control; 537#define ADV_BUG_FIX_IF_NOT_DWB 0x0001 538#define ADV_BUG_FIX_ASYN_USE_SYN 0x0002 539 540 adv_state state; 541 struct cam_path *path; 542 int unit; 543 int init_level; 544 u_int32_t max_dma_addr; 545 u_int32_t max_dma_count; 546 u_int8_t isa_dma_speed; 547 u_int8_t isa_dma_channel; 548 u_int8_t scsi_id; 549 u_int8_t chip_version; 550 u_int8_t max_tags_per_target; 551 u_int8_t max_openings; 552 u_int8_t cur_active; 553 u_int8_t openings_needed; 554 u_int8_t ccb_infos_allocated; 555 u_int8_t *sdtr_period_tbl; 556 u_int8_t sdtr_period_tbl_size; 557}; 558 559/* 560 * Structures for talking to the RISC engine. 561 */ 562struct adv_scsiq_1 { 563 u_int8_t status; 564#define QS_FREE 0x00 565#define QS_READY 0x01 566#define QS_DISC1 0x02 567#define QS_DISC2 0x04 568#define QS_BUSY 0x08 569#define QS_ABORTED 0x40 570#define QS_DONE 0x80 571 572 u_int8_t q_no; /* 573 * Queue ID of the first queue 574 * used in this transaction. 575 */ 576 u_int8_t cntl; 577#define QC_NO_CALLBACK 0x01 578#define QC_SG_SWAP_QUEUE 0x02 579#define QC_SG_HEAD 0x04 580#define QC_DATA_IN 0x08 581#define QC_DATA_OUT 0x10 582#define QC_URGENT 0x20 583#define QC_MSG_OUT 0x40 584#define QC_REQ_SENSE 0x80 585 586 u_int8_t sg_queue_cnt; /* Number of SG entries */ 587 588 u_int8_t target_id; /* target id as a bit vector */ 589 u_int8_t target_lun; /* LUN - taken from our xs */ 590 591 u_int32_t data_addr; /* 592 * physical addres of first 593 * (possibly only) segment 594 * to transfer. 595 */ 596 u_int32_t data_cnt; /* 597 * byte count of the first 598 * (possibly only) segment 599 * to transfer. 600 */ 601 u_int32_t sense_addr; /* 602 * physical address of the sense 603 * buffer. 604 */ 605 u_int8_t sense_len; /* length of sense buffer */ 606 u_int8_t extra_bytes; 607}; 608 609struct adv_scsiq_2 { 610 u_int32_t ccb_index; /* Index to our CCB Info */ 611 u_int8_t target_ix; /* Combined TID and LUN */ 612 613 u_int8_t flag; 614 u_int8_t cdb_len; /* 615 * Number of bytes in the SCSI 616 * command to execute. 617 */ 618 u_int8_t tag_code; /* 619 * Tag type for this transaction 620 * (SIMPLE, ORDERED, HEAD ) 621 */ 622#define ADV_TAG_FLAG_EXTRA_BYTES 0x10 623#define ADV_TAG_FLAG_DISABLE_DISCONNECT 0x04 624#define ADV_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 625#define ADV_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 626 627 u_int16_t vm_id; 628}; 629 630struct adv_scsiq_3 { 631 u_int8_t done_stat; 632#define QD_IN_PROGRESS 0x00 633#define QD_NO_ERROR 0x01 634#define QD_ABORTED_BY_HOST 0x02 635#define QD_WITH_ERROR 0x04 636#define QD_INVALID_REQUEST 0x80 637#define QD_INVALID_HOST_NUM 0x81 638#define QD_INVALID_DEVICE 0x82 639#define QD_ERR_INTERNAL 0xFF 640 641 u_int8_t host_stat; 642#define QHSTA_NO_ERROR 0x00 643#define QHSTA_M_SEL_TIMEOUT 0x11 644#define QHSTA_M_DATA_OVER_RUN 0x12 645#define QHSTA_M_DATA_UNDER_RUN 0x12 646#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 647#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 648 649#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 650#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 651#define QHSTA_D_HOST_ABORT_FAILED 0x23 652#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24 653#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 654#define QHSTA_D_ASPI_NO_BUF_POOL 0x26 655 656#define QHSTA_M_WTM_TIMEOUT 0x41 657#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 658#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 659#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 660#define QHSTA_M_TARGET_STATUS_BUSY 0x45 661#define QHSTA_M_BAD_TAG_CODE 0x46 662 663#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 664#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 665 666#define QHSTA_D_LRAM_CMP_ERROR 0x81 667 668#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 669 670 u_int8_t scsi_stat; 671 u_int8_t scsi_msg; 672}; 673 674struct adv_scsiq_4 { 675 u_int8_t cdb[ADV_MAX_CDB_LEN]; 676 u_int8_t y_first_sg_list_qp; 677 u_int8_t y_working_sg_qp; 678 u_int8_t y_working_sg_ix; 679 u_int8_t y_res; 680 u_int16_t x_req_count; 681 u_int16_t x_reconnect_rtn; 682 u_int32_t x_saved_data_addr; 683 u_int32_t x_saved_data_cnt; 684}; 685 686struct adv_q_done_info { 687 struct adv_scsiq_2 d2; 688 struct adv_scsiq_3 d3; 689 u_int8_t q_status; 690 u_int8_t q_no; 691 u_int8_t cntl; 692 u_int8_t sense_len; 693 u_int8_t extra_bytes; 694 u_int8_t res; 695 u_int32_t remain_bytes; 696}; 697 698struct adv_sg_entry { 699 u_int32_t addr; 700 u_int32_t bytes; 701}; 702 703struct adv_sg_head { 704 u_int16_t entry_cnt; /* 705 * Number of SG entries 706 * in this list 707 */ 708 709 u_int16_t queue_cnt; /* 710 * Number of queues required 711 * to store entry_cnt 712 * SG entries. 713 */ 714 715 u_int16_t entry_to_copy; /* 716 * Number of SG entries to 717 * copy to the board. 718 */ 719 u_int16_t res; 720 struct adv_sg_entry *sg_list; 721}; 722 723#define QCX_SORT (0x0001) 724#define QCX_COALEASE (0x0002) 725 726struct adv_scsi_q { 727 struct adv_scsiq_1 q1; 728 struct adv_scsiq_2 q2; 729 u_int8_t *cdbptr; /* 730 * Pointer to the SCSI command 731 * to execute. 732 */ 733 734 struct adv_sg_head *sg_head; /* 735 * Pointer to possible SG list 736 */ 737}; 738 739struct adv_scsi_req_q { 740 struct adv_scsiq_1 r1; 741 struct adv_scsiq_2 r2; 742 u_int8_t *cdbptr; 743 struct adv_sg_head *sg_head; 744 u_int8_t *sense_ptr; 745 struct adv_scsiq_3 r3; 746 u_int8_t cdb[ADV_MAX_CDB_LEN]; 747 u_int8_t sense[ADV_MIN_SENSE_LEN]; 748}; 749 750struct adv_risc_q { 751 u_int8_t fwd; 752 u_int8_t bwd; 753 struct adv_scsiq_1 i1; 754 struct adv_scsiq_2 i2; 755 struct adv_scsiq_3 i3; 756 struct adv_scsiq_4 i4; 757}; 758 759struct adv_sg_list_q { 760 u_int8_t seq_no; 761 u_int8_t q_no; 762 u_int8_t cntl; 763#define QCSG_SG_XFER_LIST 0x02 764#define QCSG_SG_XFER_MORE 0x04 765#define QCSG_SG_XFER_END 0x08 766 767 u_int8_t sg_head_qp; 768 u_int8_t sg_list_cnt; 769 u_int8_t sg_cur_list_cnt; 770}; 771#define ADV_SGQ_B_SG_CNTL 4 772#define ADV_SGQ_B_SG_HEAD_QP 5 773#define ADV_SGQ_B_SG_LIST_CNT 6 774#define ADV_SGQ_B_SG_CUR_LIST_CNT 7 775#define ADV_SGQ_LIST_BEG 8 776 777struct asc_risc_sg_list_q { 778 u_int8_t fwd; 779 u_int8_t bwd; 780 struct adv_sg_list_q sg; 781 struct adv_sg_entry sg_list[ADV_SG_LIST_PER_Q]; 782}; 783 784/* Chip Register functions */ 785void adv_set_bank(struct adv_softc *adv, u_int8_t bank); 786 787/* LRAM routines */ 788u_int8_t adv_read_lram_8(struct adv_softc *adv, u_int16_t addr); 789void adv_write_lram_8(struct adv_softc *adv, u_int16_t addr, 790 u_int8_t value); 791u_int16_t adv_read_lram_16(struct adv_softc *adv, u_int16_t addr); 792void adv_write_lram_16(struct adv_softc *adv, u_int16_t addr, 793 u_int16_t value); 794 795/* Intialization */ 796int adv_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh); 797void adv_lib_init(struct adv_softc *adv); 798 799u_int16_t adv_get_eeprom_config(struct adv_softc *adv, 800 struct adv_eeprom_config *eeprom_config); 801int adv_set_eeprom_config(struct adv_softc *adv, 802 struct adv_eeprom_config *eeprom_config); 803int adv_reset_chip(struct adv_softc *adv, int reset_bus); 804int adv_test_external_lram(struct adv_softc* adv); 805int adv_init_lram_and_mcode(struct adv_softc *adv); 806u_int8_t adv_get_chip_irq(struct adv_softc *adv); 807u_int8_t adv_set_chip_irq(struct adv_softc *adv, u_int8_t irq_no); 808void adv_set_chip_scsiid(struct adv_softc *adv, int new_id); 809 810/* Queue handling and execution */ 811int adv_execute_scsi_queue(struct adv_softc *adv, 812 struct adv_scsi_q *scsiq, 813 u_int32_t datalen); 814u_int8_t adv_copy_lram_doneq(struct adv_softc *adv, u_int16_t q_addr, 815 struct adv_q_done_info *scsiq, u_int32_t max_dma_count); 816 817/* Chip Control */ 818int adv_start_chip(struct adv_softc *adv); 819void adv_start_execution(struct adv_softc *adv); 820int adv_stop_execution(struct adv_softc *adv); 821int adv_stop_chip(struct adv_softc *adv); 822int adv_is_chip_halted(struct adv_softc *adv); 823 824/* Interrupt processing */ 825void adv_ack_interrupt(struct adv_softc *adv); 826void adv_isr_chip_halted(struct adv_softc *adv); 827 828/* SDTR Conversion */ 829void adv_set_syncrate(struct adv_softc *adv, struct cam_path *path, 830 u_int target_id, u_int period, u_int offset, 831 u_int type); 832void adv_sdtr_to_period_offset(struct adv_softc *adv, 833 u_int8_t sync_data, u_int8_t *period, 834 u_int8_t *offset, int tid); 835u_int8_t adv_period_offset_to_sdtr(struct adv_softc *adv, u_int *period, 836 u_int *offset, int tid); 837 838/* Error recovery */ 839union ccb; 840int adv_abort_ccb(struct adv_softc *adv, int target, int lun, 841 union ccb *ccb, u_int32_t status, int queued_only); 842int adv_reset_bus(struct adv_softc *adv, int initiate_reset); 843 844/* Async event callback */ 845void advasync(void *callback_arg, u_int32_t code, 846 struct cam_path *path, void *arg); 847 848#define ADV_INB(adv, offset) \ 849 bus_space_read_1((adv)->tag, (adv)->bsh, offset) 850#define ADV_INW(adv, offset) \ 851 bus_space_read_2((adv)->tag, (adv)->bsh, offset) 852#define ADV_INSB(adv, offset, valp, count) \ 853 bus_space_read_multi_1((adv)->tag, (adv)->bsh, offset, valp, count) 854 855/* These controllers seem to have problems with PIO on some fast processors */ 856static __inline void ADV_INSW(struct adv_softc *, u_int, u_int16_t *, u_int); 857static __inline void 858ADV_INSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count) 859{ 860 while (count--) 861 *valp++ = bus_space_read_2(adv->tag, adv->bsh, offset); 862} 863 864#define ADV_OUTB(adv, offset, val) \ 865 bus_space_write_1((adv)->tag, (adv)->bsh, offset, val) 866#define ADV_OUTW(adv, offset, val) \ 867 bus_space_write_2((adv)->tag, (adv)->bsh, offset, val) 868 869/* These controllers seem to have problems with PIO on some fast processors */ 870static __inline void ADV_OUTSW(struct adv_softc *, u_int, u_int16_t *, u_int); 871static __inline void 872ADV_OUTSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count) 873{ 874 while (count--) 875 bus_space_write_2(adv->tag, adv->bsh, offset, *valp++); 876} 877 878#endif /* _ADVLIB_H_ */ 879