advlib.h revision 170872
1/*- 2 * Definitions for low level routines and data structures 3 * for the Advanced Systems Inc. SCSI controllers chips. 4 * 5 * Copyright (c) 1996-1997, 1999-2000 Justin T. Gibbs. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification, immediately at the beginning of the file. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/advansys/advlib.h 170872 2007-06-17 05:55:54Z scottl $ 33 */ 34/*- 35 * Ported from: 36 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 37 * 38 * Copyright (c) 1995-1996 Advanced System Products, Inc. 39 * All Rights Reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that redistributions of source 43 * code retain the above copyright notice and this comment without 44 * modification. 45 */ 46 47#ifndef _ADVLIB_H_ 48#define _ADVLIB_H_ 49 50#include <sys/queue.h> 51 52struct cam_path; 53union ccb; 54 55typedef u_int8_t target_bit_vector; 56#define TARGET_BIT_VECTOR_SET -1 57#define ADV_SCSI_ID_BITS 3 58#define ADV_MAX_TID 7 59#define ADV_MAX_LUN 7 60 61/* Enumeration of board types */ 62typedef enum { 63 ADV_NONE = 0x000, 64 ADV_ISA = 0x001, 65 ADV_ISAPNP = 0x003, 66 ADV_VL = 0x004, 67 ADV_EISA = 0x008, 68 ADV_PCI = 0x010, 69 ADV_MCA = 0x020, 70 ADV_PCMCIA = 0x040, 71 ADV_ULTRA = 0x100, 72 ADV_WIDE = 0x200, 73 ADV_WIDE32 = 0x400 74} adv_btype; 75 76typedef enum { 77 ADV_STATE_NONE = 0x00, 78 ADV_RESOURCE_SHORTAGE = 0x01, 79 ADV_IN_TIMEOUT = 0x02, 80 ADV_BUSDMA_BLOCK = 0x04, 81 ADV_BUSDMA_BLOCK_CLEARED = 0x08 82 83} adv_state; 84 85typedef enum { 86 ACCB_FREE = 0x00, 87 ACCB_ACTIVE = 0x01, 88 ACCB_ABORT_QUEUED = 0x02, 89 ACCB_RECOVERY_CCB = 0x04 90} adv_ccb_state; 91 92struct adv_ccb_info { 93 adv_ccb_state state; 94 bus_dmamap_t dmamap; 95 union ccb* ccb; 96 SLIST_ENTRY(adv_ccb_info) links; 97}; 98 99#define ccb_cinfo_ptr spriv_ptr0 100 101#define ADV_SYN_XFER_NO 8 102#define ADV_SYN_MAX_OFFSET 0x0F 103#define ADV_DEF_SDTR_OFFSET 0x0F 104#define ADV_DEF_SDTR_INDEX 0x00 105#define ADV_OVERRUN_BSIZE 0x00000040 106#define ADV_MAX_CDB_LEN 12 107#define ADV_MAX_SENSE_LEN 32 108#define ADV_MIN_SENSE_LEN 14 109 110#define ADV_TIDLUN_TO_IX(tid, lun) ((tid) | ((lun) << ADV_SCSI_ID_BITS) ) 111#define ADV_TID_TO_TARGET_MASK(tid) (0x01 << (tid)) 112#define ADV_TIX_TO_TARGET_MASK(tix) (0x01 << ((tix) & ADV_MAX_TID)) 113#define ADV_TIX_TO_TID(tix) ((tix) & ADV_MAX_TID) 114#define ADV_TID_TO_TIX(tid) ((tid) & ADV_MAX_TID) 115#define ADV_TIX_TO_LUN(tix) (((tix) >> ADV_SCSI_ID_BITS) & ADV_MAX_LUN ) 116 117 118/* 119 * XXX 120 * PnP port addresses 121 * I believe that these are standard PnP address and should be replaced 122 * by the values in a central ISA PnP header file when we get one. 123 */ 124#define ADV_ISA_PNP_PORT_ADDR (0x279) 125#define ADV_ISA_PNP_PORT_WRITE (ADV_ISA_PNP_PORT_ADDR+0x800) 126 127/* 128 * Board Signatures 129 */ 130#define ADV_SIGNATURE_WORD 0x0000 131#define ADV_1000_ID0W 0x04C1 132#define ADV_1000_ID0W_FIX 0x00C1 133 134#define ADV_SIGNATURE_BYTE 0x0001 135#define ADV_1000_ID1B 0x25 136 137#define ADV_REG_IH 0x0002 138#define ADV_INS_HALTINT 0x6281 139#define ADV_INS_HALT 0x6280 140#define ADV_INS_SINT 0x6200 141#define ADV_INS_RFLAG_WTM 0x7380 142 143#define ADV_CONFIG_LSW 0x0002 144#define ADV_CFG_LSW_ISA_DMA_CHANNEL 0x0003 145#define ADV_CFG_LSW_HOST_INT_ON 0x0020 146#define ADV_CFG_LSW_BIOS_ON 0x0040 147#define ADV_CFG_LSW_VERA_BURST_ON 0x0080 148#define ADV_CFG_LSW_SCSI_PARITY_ON 0x0800 149#define ADV_CFG_LSW_SCSIID 0x0700 150#define ADV_CFG_LSW_SCSIID_SHIFT 8 151#define ADV_CONFIG_SCSIID(cfg) ((cfg >> ADV_CFG_LSW_SCSIID_SHIFT) & ADV_MAX_TID) 152 153/* 154 * Chip Revision Number 155 */ 156#define ADV_NONEISA_CHIP_REVISION 0x0003 157#define ADV_CHIP_MIN_VER_VL 0x01 158#define ADV_CHIP_MAX_VER_VL 0x07 159#define ADV_CHIP_MIN_VER_PCI 0x09 160#define ADV_CHIP_MAX_VER_PCI 0x0F 161#define ADV_CHIP_VER_PCI_BIT 0x08 162#define ADV_CHIP_VER_PCI_ULTRA_3150 (ADV_CHIP_VER_PCI_BIT | 0x02) 163#define ADV_CHIP_VER_PCI_ULTRA_3050 (ADV_CHIP_VER_PCI_BIT | 0x03) 164#define ADV_CHIP_MIN_VER_ISA 0x11 165#define ADV_CHIP_MIN_VER_ISA_PNP 0x21 166#define ADV_CHIP_MAX_VER_ISA 0x27 167#define ADV_CHIP_VER_ISA_BIT 0x30 168#define ADV_CHIP_VER_ISAPNP_BIT 0x20 169#define ADV_CHIP_VER_ASYN_BUG 0x21 170#define ADV_CHIP_MIN_VER_EISA 0x41 171#define ADV_CHIP_MAX_VER_EISA 0x47 172#define ADV_CHIP_VER_EISA_BIT 0x40 173 174#define ADV_CONFIG_MSW 0x0004 175#define ADV_CFG_MSW_SCSI_TARGET_ON 0x0080 176#define ADV_CFG_MSW_LRAM_8BITS_ON 0x0800 177#define ADV_CFG_MSW_CLR_MASK 0x30C0 178 179#define ADV_EEPROM_DATA 0x0006 180 181#define ADV_EEPROM_CMD 0x0007 182#define ADV_EEPROM_CMD_READ 0x80 183#define ADV_EEPROM_CMD_WRITE 0x40 184#define ADV_EEPROM_CMD_WRITE_ENABLE 0x30 185#define ADV_EEPROM_CMD_WRITE_DISABLE 0x00 186 187#define ADV_DMA_SPEED 0x0007 188#define ADV_DEF_ISA_DMA_SPEED 4 189#define ADV_REG_FLAG 0x0007 190 191#define ADV_LRAM_DATA 0x0008 192 193#define ADV_LRAM_ADDR 0x000A 194 195#define ADV_SYN_OFFSET 0x000B 196 197#define ADV_REG_PROG_COUNTER 0x000C 198#define ADV_MCODE_START_ADDR 0x0080 199 200#define ADV_REG_IFC 0x000D 201#define ADV_IFC_REG_LOCK 0x00 202#define ADV_IFC_REG_UNLOCK 0x09 203#define ADV_IFC_WR_EN_FILTER 0x10 204#define ADV_IFC_RD_NO_EEPROM 0x10 205#define ADV_IFC_SLEW_RATE 0x20 206#define ADV_IFC_ACT_NEG 0x40 207#define ADV_IFC_INP_FILTER 0x80 208#define ADV_IFC_INIT_DEFAULT (ADV_IFC_ACT_NEG | ADV_IFC_REG_UNLOCK) 209 210#define ADV_CHIP_STATUS 0x000E 211#define ADV_CSW_TEST1 0x8000 212#define ADV_CSW_AUTO_CONFIG 0x4000 213#define ADV_CSW_RESERVED1 0x2000 214#define ADV_CSW_IRQ_WRITTEN 0x1000 215#define ADV_CSW_33MHZ_SELECTED 0x0800 216#define ADV_CSW_TEST2 0x0400 217#define ADV_CSW_TEST3 0x0200 218#define ADV_CSW_RESERVED2 0x0100 219#define ADV_CSW_DMA_DONE 0x0080 220#define ADV_CSW_FIFO_RDY 0x0040 221#define ADV_CSW_EEP_READ_DONE 0x0020 222#define ADV_CSW_HALTED 0x0010 223#define ADV_CSW_SCSI_RESET_ACTIVE 0x0008 224#define ADV_CSW_PARITY_ERR 0x0004 225#define ADV_CSW_SCSI_RESET_LATCH 0x0002 226#define ADV_CSW_INT_PENDING 0x0001 227/* 228 * XXX I don't understand the relevence of the naming 229 * convention change here. What does CIW stand for? 230 * Perhaps this is to differentiate read and write 231 * values? 232 */ 233#define ADV_CIW_INT_ACK 0x0100 234#define ADV_CIW_TEST1 0x0200 235#define ADV_CIW_TEST2 0x0400 236#define ADV_CIW_SEL_33MHZ 0x0800 237#define ADV_CIW_IRQ_ACT 0x1000 238#define ADV_CIW_CLR_SCSI_RESET_INT 0x1000 239 240#define ADV_CHIP_CTRL 0x000F 241#define ADV_CC_CHIP_RESET 0x80 242#define ADV_CC_SCSI_RESET 0x40 243#define ADV_CC_HALT 0x20 244#define ADV_CC_SINGLE_STEP 0x10 245#define ADV_CC_DMA_ENABLE 0x08 246#define ADV_CC_TEST 0x04 247#define ADV_CC_BANK_ONE 0x02 248#define ADV_CC_DIAG 0x01 249 250#define ADV_HALTCODE_W 0x0040 251#define ADV_STOP_CODE_B 0x0034 252#define ADV_STOP_REQ_RISC_STOP 0x01 253#define ADV_STOP_ACK_RISC_STOP 0x03 254#define ADV_STOP_CLEAN_UP_BUSY_Q 0x10 255#define ADV_STOP_CLEAN_UP_DISC_Q 0x20 256#define ADV_STOP_HOST_REQ_RISC_HALT 0x40 257 258/* 259 * EEPROM routine constants 260 * XXX What about wide controllers? 261 * Surely they have space for 8 more targets. 262 */ 263#define ADV_EEPROM_CFG_BEG_VL 2 264#define ADV_EEPROM_MAX_ADDR_VL 15 265#define ADV_EEPROM_CFG_BEG 32 266#define ADV_EEPROM_MAX_ADDR 45 267#define ADV_EEPROM_MAX_RETRY 20 268 269struct adv_eeprom_config { 270 u_int16_t cfg_lsw; 271 272 u_int16_t cfg_msw; 273 274 u_int8_t init_sdtr; 275 u_int8_t disc_enable; 276 277 u_int8_t use_cmd_qng; 278 u_int8_t start_motor; 279 280 u_int8_t max_total_qng; 281 u_int8_t max_tag_qng; 282 283 u_int8_t bios_scan; 284 u_int8_t power_up_wait; 285 286 u_int8_t no_scam; 287 u_int8_t scsi_id_dma_speed; 288#define EEPROM_SCSI_ID_MASK 0x0F 289#define EEPROM_DMA_SPEED_MASK 0xF0 290#define EEPROM_DMA_SPEED(ep) \ 291 (((ep).scsi_id_dma_speed & EEPROM_DMA_SPEED_MASK) >> 4) 292#define EEPROM_SET_DMA_SPEED(ep, speed) \ 293 (ep).scsi_id_dma_speed &= ~EEPROM_DMA_SPEED_MASK; \ 294 (ep).scsi_id_dma_speed |= \ 295 (((speed) << 4) & EEPROM_DMA_SPEED_MASK) 296#define EEPROM_SCSIID(ep) ((ep).scsi_id_dma_speed & EEPROM_SCSI_ID_MASK) 297#define EEPROM_SET_SCSIID(ep, id) \ 298 (ep).scsi_id_dma_speed &= ~EEPROM_SCSI_ID_MASK; \ 299 (ep).scsi_id_dma_speed |= ((id) & EEPROM_SCSI_ID_MASK) 300 u_int8_t sdtr_data[8]; 301 u_int8_t adapter_info[6]; 302 303 u_int16_t cntl; 304 305 u_int16_t chksum; 306}; 307 308/* Bank 1 */ 309#define ADV_SEQ_ACCUM 0x0000 310#define ADV_QUEUE_ELEMENT_INDEX 0x0001 311#define ADV_SEQ_INSTRUCTION_HOLD 0x0002 312#define ADV_QUEUE_ELEMENT_POINTER 0x0003 313#define ADV_HOST_DATA_FIFO_L 0x0004 314#define ADV_HOST_SCSIID 0x0005 315#define ADV_HOST_DATA_FIFO_H 0x0006 316#define ADV_SCSI_CONTROL 0x0009 317#define SC_SEL 0x80 318#define SC_BSY 0x40 319#define SC_ACK 0x20 320#define SC_REQ 0x10 321#define SC_ATN 0x08 322#define SC_IO 0x04 323#define SC_CD 0x02 324#define SC_MSG 0x01 325#define ADV_SCSIDATL 0x000B 326#define ADV_DMA_TRANSFER_CNT 0x000C 327#define ADV_DMA_TRANSFER_CNT1 0x000E 328 329/* 330 * Instruction data and code segment addresses, 331 * and transaction address translation (queues). 332 * All addresses refer to on board LRAM. 333 */ 334#define ADV_DATA_SEC_BEG 0x0080 335#define ADV_DATA_SEC_END 0x0080 336#define ADV_CODE_SEC_BEG 0x0080 337#define ADV_CODE_SEC_END 0x0080 338#define ADV_QADR_BEG 0x4000 339#define ADV_QADR_END 0x7FFF 340#define ADV_QLAST_ADR 0x7FC0 341#define ADV_QBLK_SIZE 0x40 342#define ADV_BIOS_DATA_QBEG 0xF8 343#define ADV_MAX_QNO 0xF8 344#define ADV_QADR_USED (ADV_MAX_QNO * 64) 345#define ADV_QNO_TO_QADDR(q_no) ((ADV_QADR_BEG) + ((u_int16_t)(q_no) << 6)) 346 347#define ADV_MIN_ACTIVE_QNO 0x01 348#define ADV_QLINK_END 0xFF 349 350#define ADV_MAX_SG_QUEUE 5 351#define ADV_SG_LIST_PER_Q 7 352#define ADV_MAX_SG_LIST (1 + ((ADV_SG_LIST_PER_Q) * (ADV_MAX_SG_QUEUE))) 353 354#define ADV_MIN_REMAIN_Q 0x02 355#define ADV_DEF_MAX_TOTAL_QNG 0xF0 356#define ADV_MIN_TAG_Q_PER_DVC 0x04 357#define ADV_DEF_TAG_Q_PER_DVC 0x04 358#define ADV_MIN_FREE_Q ADV_MIN_REMAIN_Q 359#define ADV_MIN_TOTAL_QNG ((ADV_MAX_SG_QUEUE)+(ADV_MIN_FREE_Q)) 360#define ADV_MAX_TOTAL_QNG 240 361#define ADV_MAX_INRAM_TAG_QNG 16 362#define ADV_MAX_PCI_INRAM_TOTAL_QNG 20 363#define ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 364#define ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 365 366#define ADV_DEF_IRQ_NO 10 367#define ADV_MAX_IRQ_NO 15 368#define ADV_MIN_IRQ_NO 10 369 370#define ADV_SCSIQ_CPY_BEG 4 371#define ADV_SCSIQ_SGHD_CPY_BEG 2 372 373/* SCSIQ Microcode representation offsets */ 374#define ADV_SCSIQ_B_FWD 0 375#define ADV_SCSIQ_B_BWD 1 376#define ADV_SCSIQ_B_STATUS 2 377#define ADV_SCSIQ_B_QNO 3 378#define ADV_SCSIQ_B_CNTL 4 379#define ADV_SCSIQ_B_SG_QUEUE_CNT 5 380#define ADV_SCSIQ_B_LIST_CNT 6 381#define ADV_SCSIQ_B_CUR_LIST_CNT 7 382#define ADV_SCSIQ_D_DATA_ADDR 8 383#define ADV_SCSIQ_D_DATA_CNT 12 384#define ADV_SCSIQ_B_SENSE_LEN 20 385#define ADV_SCSIQ_DONE_INFO_BEG 22 386#define ADV_SCSIQ_D_CINFO_IDX 22 387#define ADV_SCSIQ_B_TARGET_IX 26 388#define ADV_SCSIQ_B_CDB_LEN 28 389#define ADV_SCSIQ_B_TAG_CODE 29 390#define ADV_SCSIQ_W_VM_ID 30 391#define ADV_SCSIQ_DONE_STATUS 32 392#define ADV_SCSIQ_HOST_STATUS 33 393#define ADV_SCSIQ_SCSI_STATUS 34 394#define ADV_SCSIQ_CDB_BEG 36 395#define ADV_SCSIQ_B_FIRST_SG_QK_QP 48 396#define ADV_SCSIQ_B_SG_WK_QP 49 397#define ADV_SCSIQ_B_SG_WK_IX 50 398#define ADV_SCSIQ_W_ALT_DC1 52 399#define ADV_SCSIQ_DW_REMAIN_XFER_ADDR 56 400#define ADV_SCSIQ_DW_REMAIN_XFER_CNT 60 401 402/* LRAM Offsets */ 403#define ADVV_MSGOUT_BEG 0x0000 404#define ADVV_MSGOUT_SDTR_PERIOD (ADVV_MSGOUT_BEG+3) 405#define ADVV_MSGOUT_SDTR_OFFSET (ADVV_MSGOUT_BEG+4) 406 407#define ADVV_BREAK_SAVED_CODE 0x0006 408 409#define ADVV_MSGIN_BEG (ADVV_MSGOUT_BEG+8) 410#define ADVV_MSGIN_SDTR_PERIOD (ADVV_MSGIN_BEG+3) 411#define ADVV_MSGIN_SDTR_OFFSET (ADVV_MSGIN_BEG+4) 412 413#define ADVV_SDTR_DATA_BEG (ADVV_MSGIN_BEG+8) 414#define ADVV_SDTR_DONE_BEG (ADVV_SDTR_DATA_BEG+8) 415#define ADVV_MAX_DVC_QNG_BEG 0x0020 416 417#define ADVV_BREAK_ADDR 0x0028 418#define ADVV_BREAK_NOTIFY_COUNT 0x002A 419#define ADVV_BREAK_CONTROL 0x002C 420#define ADVV_BREAK_HIT_COUNT 0x002E 421 422#define ADVV_ASCDVC_ERR_CODE_W 0x0030 423#define ADVV_MCODE_CHKSUM_W 0x0032 424#define ADVV_MCODE_SIZE_W 0x0034 425#define ADVV_STOP_CODE_B 0x0036 426#define ADVV_DVC_ERR_CODE_B 0x0037 427 428#define ADVV_OVERRUN_PADDR_D 0x0038 429#define ADVV_OVERRUN_BSIZE_D 0x003C 430 431#define ADVV_HALTCODE_W 0x0040 432#define ADV_HALT_EXTMSG_IN 0x8000 433#define ADV_HALT_CHK_CONDITION 0x8100 434#define ADV_HALT_SS_QUEUE_FULL 0x8200 435#define ADV_HALT_DISABLE_ASYN_USE_SYN_FIX 0x8300 436#define ADV_HALT_ENABLE_ASYN_USE_SYN_FIX 0x8400 437#define ADV_HALT_SDTR_REJECTED 0x4000 438#define ADV_HALT_HOST_COPY_SG_LIST_TO_RISC 0x2000 439 440#define ADVV_CHKSUM_W 0x0042 441#define ADVV_MC_DATE_W 0x0044 442#define ADVV_MC_VER_W 0x0046 443#define ADVV_NEXTRDY_B 0x0048 444#define ADVV_DONENEXT_B 0x0049 445#define ADVV_USE_TAGGED_QNG_B 0x004A 446#define ADVV_SCSIBUSY_B 0x004B 447#define ADVV_Q_DONE_IN_PROGRESS_B 0x004C 448#define ADVV_CURCDB_B 0x004D 449#define ADVV_RCLUN_B 0x004E 450#define ADVV_BUSY_QHEAD_B 0x004F 451#define ADVV_DISC1_QHEAD_B 0x0050 452 453#define ADVV_DISC_ENABLE_B 0x0052 454#define ADVV_CAN_TAGGED_QNG_B 0x0053 455#define ADVV_HOSTSCSI_ID_B 0x0055 456#define ADVV_MCODE_CNTL_B 0x0056 457#define ADVV_NULL_TARGET_B 0x0057 458 459#define ADVV_FREE_Q_HEAD_W 0x0058 460#define ADVV_DONE_Q_TAIL_W 0x005A 461#define ADVV_FREE_Q_HEAD_B (ADVV_FREE_Q_HEAD_W+1) 462#define ADVV_DONE_Q_TAIL_B (ADVV_DONE_Q_TAIL_W+1) 463 464#define ADVV_HOST_FLAG_B 0x005D 465#define ADV_HOST_FLAG_IN_ISR 0x01 466#define ADV_HOST_FLAG_ACK_INT 0x02 467 468 469#define ADVV_TOTAL_READY_Q_B 0x0064 470#define ADVV_VER_SERIAL_B 0x0065 471#define ADVV_HALTCODE_SAVED_W 0x0066 472#define ADVV_WTM_FLAG_B 0x0068 473#define ADVV_RISC_FLAG_B 0x006A 474#define ADV_RISC_FLAG_GEN_INT 0x01 475#define ADV_RISC_FLAG_REQ_SG_LIST 0x02 476 477#define ADVV_REQ_SG_LIST_QP 0x006B 478 479#define ADV_TRANS_CUR 0x01 /* Modify current neogtiation status */ 480#define ADV_TRANS_ACTIVE 0x03 /* Assume this is the active target */ 481#define ADV_TRANS_GOAL 0x04 /* Modify negotiation goal */ 482#define ADV_TRANS_USER 0x08 /* Modify user negotiation settings */ 483 484struct adv_transinfo { 485 u_int8_t period; 486 u_int8_t offset; 487}; 488 489struct adv_target_transinfo { 490 struct adv_transinfo current; 491 struct adv_transinfo goal; 492 struct adv_transinfo user; 493}; 494 495struct adv_softc { 496 device_t dev; 497 bus_space_tag_t tag; 498 bus_space_handle_t bsh; 499 struct cam_sim *sim; 500 LIST_HEAD(, ccb_hdr) pending_ccbs; 501 struct adv_ccb_info *ccb_infos; 502 SLIST_HEAD(, adv_ccb_info) free_ccb_infos; 503 bus_dma_tag_t parent_dmat; 504 bus_dma_tag_t buffer_dmat; 505 bus_dma_tag_t sense_dmat; 506 bus_dmamap_t sense_dmamap; 507 struct scsi_sense_data *sense_buffers; 508 bus_addr_t sense_physbase; 509 bus_addr_t overrun_physbase; 510 adv_btype type; 511 struct adv_target_transinfo tinfo[8]; 512 target_bit_vector fix_asyn_xfer; 513 target_bit_vector fix_asyn_xfer_always; 514 target_bit_vector disc_enable; 515 target_bit_vector user_disc_enable; 516 target_bit_vector cmd_qng_enabled; 517 target_bit_vector user_cmd_qng_enabled; 518 u_int16_t control; 519#define ADV_CNTL_INITIATOR 0x0001 520#define ADV_CNTL_BIOS_GT_1GB 0x0002 521#define ADV_CNTL_BIOS_GT_2_DISK 0x0004 522#define ADV_CNTL_BIOS_REMOVABLE 0x0008 523#define ADV_CNTL_NO_SCAM 0x0010 524#define ADV_CNTL_INT_MULTI_Q 0x0080 525#define ADV_CNTL_NO_LUN_SUPPORT 0x0040 526#define ADV_CNTL_NO_VERIFY_COPY 0x0100 527#define ADV_CNTL_RESET_SCSI 0x0200 528#define ADV_CNTL_INIT_INQUIRY 0x0400 529#define ADV_CNTL_INIT_VERBOSE 0x0800 530#define ADV_CNTL_SCSI_PARITY 0x1000 531#define ADV_CNTL_BURST_MODE 0x2000 532#define ADV_CNTL_SDTR_ENABLE_ULTRA 0x4000 533 534 u_int16_t bug_fix_control; 535#define ADV_BUG_FIX_IF_NOT_DWB 0x0001 536#define ADV_BUG_FIX_ASYN_USE_SYN 0x0002 537 538 adv_state state; 539 struct cam_path *path; 540 int unit; 541 int init_level; 542 u_int32_t max_dma_addr; 543 u_int32_t max_dma_count; 544 u_int8_t isa_dma_speed; 545 u_int8_t isa_dma_channel; 546 u_int8_t scsi_id; 547 u_int8_t chip_version; 548 u_int8_t max_tags_per_target; 549 u_int8_t max_openings; 550 u_int8_t cur_active; 551 u_int8_t openings_needed; 552 u_int8_t ccb_infos_allocated; 553 u_int8_t *sdtr_period_tbl; 554 u_int8_t sdtr_period_tbl_size; 555}; 556 557/* 558 * Structures for talking to the RISC engine. 559 */ 560struct adv_scsiq_1 { 561 u_int8_t status; 562#define QS_FREE 0x00 563#define QS_READY 0x01 564#define QS_DISC1 0x02 565#define QS_DISC2 0x04 566#define QS_BUSY 0x08 567#define QS_ABORTED 0x40 568#define QS_DONE 0x80 569 570 u_int8_t q_no; /* 571 * Queue ID of the first queue 572 * used in this transaction. 573 */ 574 u_int8_t cntl; 575#define QC_NO_CALLBACK 0x01 576#define QC_SG_SWAP_QUEUE 0x02 577#define QC_SG_HEAD 0x04 578#define QC_DATA_IN 0x08 579#define QC_DATA_OUT 0x10 580#define QC_URGENT 0x20 581#define QC_MSG_OUT 0x40 582#define QC_REQ_SENSE 0x80 583 584 u_int8_t sg_queue_cnt; /* Number of SG entries */ 585 586 u_int8_t target_id; /* target id as a bit vector */ 587 u_int8_t target_lun; /* LUN - taken from our xs */ 588 589 u_int32_t data_addr; /* 590 * physical addres of first 591 * (possibly only) segment 592 * to transfer. 593 */ 594 u_int32_t data_cnt; /* 595 * byte count of the first 596 * (possibly only) segment 597 * to transfer. 598 */ 599 u_int32_t sense_addr; /* 600 * physical address of the sense 601 * buffer. 602 */ 603 u_int8_t sense_len; /* length of sense buffer */ 604 u_int8_t extra_bytes; 605}; 606 607struct adv_scsiq_2 { 608 u_int32_t ccb_index; /* Index to our CCB Info */ 609 u_int8_t target_ix; /* Combined TID and LUN */ 610 611 u_int8_t flag; 612 u_int8_t cdb_len; /* 613 * Number of bytes in the SCSI 614 * command to execute. 615 */ 616 u_int8_t tag_code; /* 617 * Tag type for this transaction 618 * (SIMPLE, ORDERED, HEAD ) 619 */ 620#define ADV_TAG_FLAG_EXTRA_BYTES 0x10 621#define ADV_TAG_FLAG_DISABLE_DISCONNECT 0x04 622#define ADV_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 623#define ADV_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 624 625 u_int16_t vm_id; 626}; 627 628struct adv_scsiq_3 { 629 u_int8_t done_stat; 630#define QD_IN_PROGRESS 0x00 631#define QD_NO_ERROR 0x01 632#define QD_ABORTED_BY_HOST 0x02 633#define QD_WITH_ERROR 0x04 634#define QD_INVALID_REQUEST 0x80 635#define QD_INVALID_HOST_NUM 0x81 636#define QD_INVALID_DEVICE 0x82 637#define QD_ERR_INTERNAL 0xFF 638 639 u_int8_t host_stat; 640#define QHSTA_NO_ERROR 0x00 641#define QHSTA_M_SEL_TIMEOUT 0x11 642#define QHSTA_M_DATA_OVER_RUN 0x12 643#define QHSTA_M_DATA_UNDER_RUN 0x12 644#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 645#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 646 647#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 648#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 649#define QHSTA_D_HOST_ABORT_FAILED 0x23 650#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24 651#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 652#define QHSTA_D_ASPI_NO_BUF_POOL 0x26 653 654#define QHSTA_M_WTM_TIMEOUT 0x41 655#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 656#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 657#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 658#define QHSTA_M_TARGET_STATUS_BUSY 0x45 659#define QHSTA_M_BAD_TAG_CODE 0x46 660 661#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 662#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 663 664#define QHSTA_D_LRAM_CMP_ERROR 0x81 665 666#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 667 668 u_int8_t scsi_stat; 669 u_int8_t scsi_msg; 670}; 671 672struct adv_scsiq_4 { 673 u_int8_t cdb[ADV_MAX_CDB_LEN]; 674 u_int8_t y_first_sg_list_qp; 675 u_int8_t y_working_sg_qp; 676 u_int8_t y_working_sg_ix; 677 u_int8_t y_res; 678 u_int16_t x_req_count; 679 u_int16_t x_reconnect_rtn; 680 u_int32_t x_saved_data_addr; 681 u_int32_t x_saved_data_cnt; 682}; 683 684struct adv_q_done_info { 685 struct adv_scsiq_2 d2; 686 struct adv_scsiq_3 d3; 687 u_int8_t q_status; 688 u_int8_t q_no; 689 u_int8_t cntl; 690 u_int8_t sense_len; 691 u_int8_t extra_bytes; 692 u_int8_t res; 693 u_int32_t remain_bytes; 694}; 695 696struct adv_sg_entry { 697 u_int32_t addr; 698 u_int32_t bytes; 699}; 700 701struct adv_sg_head { 702 u_int16_t entry_cnt; /* 703 * Number of SG entries 704 * in this list 705 */ 706 707 u_int16_t queue_cnt; /* 708 * Number of queues required 709 * to store entry_cnt 710 * SG entries. 711 */ 712 713 u_int16_t entry_to_copy; /* 714 * Number of SG entries to 715 * copy to the board. 716 */ 717 u_int16_t res; 718 struct adv_sg_entry *sg_list; 719}; 720 721#define QCX_SORT (0x0001) 722#define QCX_COALEASE (0x0002) 723 724struct adv_scsi_q { 725 struct adv_scsiq_1 q1; 726 struct adv_scsiq_2 q2; 727 u_int8_t *cdbptr; /* 728 * Pointer to the SCSI command 729 * to execute. 730 */ 731 732 struct adv_sg_head *sg_head; /* 733 * Pointer to possible SG list 734 */ 735}; 736 737struct adv_scsi_req_q { 738 struct adv_scsiq_1 r1; 739 struct adv_scsiq_2 r2; 740 u_int8_t *cdbptr; 741 struct adv_sg_head *sg_head; 742 u_int8_t *sense_ptr; 743 struct adv_scsiq_3 r3; 744 u_int8_t cdb[ADV_MAX_CDB_LEN]; 745 u_int8_t sense[ADV_MIN_SENSE_LEN]; 746}; 747 748struct adv_risc_q { 749 u_int8_t fwd; 750 u_int8_t bwd; 751 struct adv_scsiq_1 i1; 752 struct adv_scsiq_2 i2; 753 struct adv_scsiq_3 i3; 754 struct adv_scsiq_4 i4; 755}; 756 757struct adv_sg_list_q { 758 u_int8_t seq_no; 759 u_int8_t q_no; 760 u_int8_t cntl; 761#define QCSG_SG_XFER_LIST 0x02 762#define QCSG_SG_XFER_MORE 0x04 763#define QCSG_SG_XFER_END 0x08 764 765 u_int8_t sg_head_qp; 766 u_int8_t sg_list_cnt; 767 u_int8_t sg_cur_list_cnt; 768}; 769#define ADV_SGQ_B_SG_CNTL 4 770#define ADV_SGQ_B_SG_HEAD_QP 5 771#define ADV_SGQ_B_SG_LIST_CNT 6 772#define ADV_SGQ_B_SG_CUR_LIST_CNT 7 773#define ADV_SGQ_LIST_BEG 8 774 775struct asc_risc_sg_list_q { 776 u_int8_t fwd; 777 u_int8_t bwd; 778 struct adv_sg_list_q sg; 779 struct adv_sg_entry sg_list[ADV_SG_LIST_PER_Q]; 780}; 781 782/* Chip Register functions */ 783void adv_set_bank(struct adv_softc *adv, u_int8_t bank); 784 785/* LRAM routines */ 786u_int8_t adv_read_lram_8(struct adv_softc *adv, u_int16_t addr); 787void adv_write_lram_8(struct adv_softc *adv, u_int16_t addr, 788 u_int8_t value); 789u_int16_t adv_read_lram_16(struct adv_softc *adv, u_int16_t addr); 790void adv_write_lram_16(struct adv_softc *adv, u_int16_t addr, 791 u_int16_t value); 792 793/* Intialization */ 794int adv_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh); 795void adv_lib_init(struct adv_softc *adv); 796 797u_int16_t adv_get_eeprom_config(struct adv_softc *adv, 798 struct adv_eeprom_config *eeprom_config); 799int adv_set_eeprom_config(struct adv_softc *adv, 800 struct adv_eeprom_config *eeprom_config); 801int adv_reset_chip(struct adv_softc *adv, int reset_bus); 802int adv_test_external_lram(struct adv_softc* adv); 803int adv_init_lram_and_mcode(struct adv_softc *adv); 804u_int8_t adv_get_chip_irq(struct adv_softc *adv); 805u_int8_t adv_set_chip_irq(struct adv_softc *adv, u_int8_t irq_no); 806void adv_set_chip_scsiid(struct adv_softc *adv, int new_id); 807 808/* Queue handling and execution */ 809int adv_execute_scsi_queue(struct adv_softc *adv, 810 struct adv_scsi_q *scsiq, 811 u_int32_t datalen); 812u_int8_t adv_copy_lram_doneq(struct adv_softc *adv, u_int16_t q_addr, 813 struct adv_q_done_info *scsiq, u_int32_t max_dma_count); 814 815/* Chip Control */ 816int adv_start_chip(struct adv_softc *adv); 817void adv_start_execution(struct adv_softc *adv); 818int adv_stop_execution(struct adv_softc *adv); 819int adv_stop_chip(struct adv_softc *adv); 820int adv_is_chip_halted(struct adv_softc *adv); 821 822/* Interrupt processing */ 823void adv_ack_interrupt(struct adv_softc *adv); 824void adv_isr_chip_halted(struct adv_softc *adv); 825 826/* SDTR Conversion */ 827void adv_set_syncrate(struct adv_softc *adv, struct cam_path *path, 828 u_int target_id, u_int period, u_int offset, 829 u_int type); 830void adv_sdtr_to_period_offset(struct adv_softc *adv, 831 u_int8_t sync_data, u_int8_t *period, 832 u_int8_t *offset, int tid); 833u_int8_t adv_period_offset_to_sdtr(struct adv_softc *adv, u_int *period, 834 u_int *offset, int tid); 835 836/* Error recovery */ 837union ccb; 838int adv_abort_ccb(struct adv_softc *adv, int target, int lun, 839 union ccb *ccb, u_int32_t status, int queued_only); 840int adv_reset_bus(struct adv_softc *adv, int initiate_reset); 841 842/* Async event callback */ 843void advasync(void *callback_arg, u_int32_t code, 844 struct cam_path *path, void *arg); 845 846#define ADV_INB(adv, offset) \ 847 bus_space_read_1((adv)->tag, (adv)->bsh, offset) 848#define ADV_INW(adv, offset) \ 849 bus_space_read_2((adv)->tag, (adv)->bsh, offset) 850#define ADV_INSB(adv, offset, valp, count) \ 851 bus_space_read_multi_1((adv)->tag, (adv)->bsh, offset, valp, count) 852 853/* These controllers seem to have problems with PIO on some fast processors */ 854static __inline void ADV_INSW(struct adv_softc *, u_int, u_int16_t *, u_int); 855static __inline void 856ADV_INSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count) 857{ 858 while (count--) 859 *valp++ = bus_space_read_2(adv->tag, adv->bsh, offset); 860} 861 862#define ADV_OUTB(adv, offset, val) \ 863 bus_space_write_1((adv)->tag, (adv)->bsh, offset, val) 864#define ADV_OUTW(adv, offset, val) \ 865 bus_space_write_2((adv)->tag, (adv)->bsh, offset, val) 866 867/* These controllers seem to have problems with PIO on some fast processors */ 868static __inline void ADV_OUTSW(struct adv_softc *, u_int, u_int16_t *, u_int); 869static __inline void 870ADV_OUTSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count) 871{ 872 while (count--) 873 bus_space_write_2(adv->tag, adv->bsh, offset, *valp++); 874} 875 876#endif /* _ADVLIB_H_ */ 877