acpi_hpet.c revision 273607
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 273607 2014-10-24 21:08:36Z rpaulo $"); 30 31#include "opt_acpi.h" 32#if defined(__amd64__) 33#define DEV_APIC 34#else 35#include "opt_apic.h" 36#endif 37#include <sys/param.h> 38#include <sys/conf.h> 39#include <sys/bus.h> 40#include <sys/kernel.h> 41#include <sys/module.h> 42#include <sys/proc.h> 43#include <sys/rman.h> 44#include <sys/mman.h> 45#include <sys/time.h> 46#include <sys/smp.h> 47#include <sys/sysctl.h> 48#include <sys/timeet.h> 49#include <sys/timetc.h> 50 51#include <contrib/dev/acpica/include/acpi.h> 52#include <contrib/dev/acpica/include/accommon.h> 53 54#include <dev/acpica/acpivar.h> 55#include <dev/acpica/acpi_hpet.h> 56 57#ifdef DEV_APIC 58#include "pcib_if.h" 59#endif 60 61#define HPET_VENDID_AMD 0x4353 62#define HPET_VENDID_AMD2 0x1022 63#define HPET_VENDID_INTEL 0x8086 64#define HPET_VENDID_NVIDIA 0x10de 65#define HPET_VENDID_SW 0x1166 66 67ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 68 69static devclass_t hpet_devclass; 70 71/* ACPI CA debugging */ 72#define _COMPONENT ACPI_TIMER 73ACPI_MODULE_NAME("HPET") 74 75struct hpet_softc { 76 device_t dev; 77 int mem_rid; 78 int intr_rid; 79 int irq; 80 int useirq; 81 int legacy_route; 82 int per_cpu; 83 uint32_t allowed_irqs; 84 struct resource *mem_res; 85 struct resource *intr_res; 86 void *intr_handle; 87 ACPI_HANDLE handle; 88 uint64_t freq; 89 uint32_t caps; 90 struct timecounter tc; 91 struct hpet_timer { 92 struct eventtimer et; 93 struct hpet_softc *sc; 94 int num; 95 int mode; 96 int intr_rid; 97 int irq; 98 int pcpu_cpu; 99 int pcpu_misrouted; 100 int pcpu_master; 101 int pcpu_slaves[MAXCPU]; 102 struct resource *intr_res; 103 void *intr_handle; 104 uint32_t caps; 105 uint32_t vectors; 106 uint32_t div; 107 uint32_t next; 108 char name[8]; 109 } t[32]; 110 int num_timers; 111 struct cdev *pdev; 112 int mmap_allow; 113 int mmap_allow_write; 114}; 115 116static d_open_t hpet_open; 117static d_mmap_t hpet_mmap; 118 119static struct cdevsw hpet_cdevsw = { 120 .d_version = D_VERSION, 121 .d_name = "hpet", 122 .d_open = hpet_open, 123 .d_mmap = hpet_mmap, 124}; 125 126static u_int hpet_get_timecount(struct timecounter *tc); 127static void hpet_test(struct hpet_softc *sc); 128 129static char *hpet_ids[] = { "PNP0103", NULL }; 130 131/* Knob to disable acpi_hpet device */ 132bool acpi_hpet_disabled = false; 133 134static u_int 135hpet_get_timecount(struct timecounter *tc) 136{ 137 struct hpet_softc *sc; 138 139 sc = tc->tc_priv; 140 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 141} 142 143static void 144hpet_enable(struct hpet_softc *sc) 145{ 146 uint32_t val; 147 148 val = bus_read_4(sc->mem_res, HPET_CONFIG); 149 if (sc->legacy_route) 150 val |= HPET_CNF_LEG_RT; 151 else 152 val &= ~HPET_CNF_LEG_RT; 153 val |= HPET_CNF_ENABLE; 154 bus_write_4(sc->mem_res, HPET_CONFIG, val); 155} 156 157static void 158hpet_disable(struct hpet_softc *sc) 159{ 160 uint32_t val; 161 162 val = bus_read_4(sc->mem_res, HPET_CONFIG); 163 val &= ~HPET_CNF_ENABLE; 164 bus_write_4(sc->mem_res, HPET_CONFIG, val); 165} 166 167static int 168hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 169{ 170 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 171 struct hpet_timer *t; 172 struct hpet_softc *sc = mt->sc; 173 uint32_t fdiv, now; 174 175 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 176 if (period != 0) { 177 t->mode = 1; 178 t->div = (sc->freq * period) >> 32; 179 } else { 180 t->mode = 2; 181 t->div = 0; 182 } 183 if (first != 0) 184 fdiv = (sc->freq * first) >> 32; 185 else 186 fdiv = t->div; 187 if (t->irq < 0) 188 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 189 t->caps |= HPET_TCNF_INT_ENB; 190 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 191restart: 192 t->next = now + fdiv; 193 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 194 t->caps |= HPET_TCNF_TYPE; 195 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 196 t->caps | HPET_TCNF_VAL_SET); 197 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 198 t->next); 199 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 200 t->div); 201 } else { 202 t->caps &= ~HPET_TCNF_TYPE; 203 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 204 t->caps); 205 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 206 t->next); 207 } 208 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 209 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 210 fdiv *= 2; 211 goto restart; 212 } 213 return (0); 214} 215 216static int 217hpet_stop(struct eventtimer *et) 218{ 219 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 220 struct hpet_timer *t; 221 struct hpet_softc *sc = mt->sc; 222 223 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 224 t->mode = 0; 225 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 226 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 227 return (0); 228} 229 230static int 231hpet_intr_single(void *arg) 232{ 233 struct hpet_timer *t = (struct hpet_timer *)arg; 234 struct hpet_timer *mt; 235 struct hpet_softc *sc = t->sc; 236 uint32_t now; 237 238 if (t->mode == 0) 239 return (FILTER_STRAY); 240 /* Check that per-CPU timer interrupt reached right CPU. */ 241 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 242 if ((++t->pcpu_misrouted) % 32 == 0) { 243 printf("HPET interrupt routed to the wrong CPU" 244 " (timer %d CPU %d -> %d)!\n", 245 t->num, t->pcpu_cpu, curcpu); 246 } 247 248 /* 249 * Reload timer, hoping that next time may be more lucky 250 * (system will manage proper interrupt binding). 251 */ 252 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 253 t->mode == 2) { 254 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 255 sc->freq / 8; 256 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 257 t->next); 258 } 259 return (FILTER_HANDLED); 260 } 261 if (t->mode == 1 && 262 (t->caps & HPET_TCAP_PER_INT) == 0) { 263 t->next += t->div; 264 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 265 if ((int32_t)((now + t->div / 2) - t->next) > 0) 266 t->next = now + t->div / 2; 267 bus_write_4(sc->mem_res, 268 HPET_TIMER_COMPARATOR(t->num), t->next); 269 } else if (t->mode == 2) 270 t->mode = 0; 271 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 272 if (mt->et.et_active) 273 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 274 return (FILTER_HANDLED); 275} 276 277static int 278hpet_intr(void *arg) 279{ 280 struct hpet_softc *sc = (struct hpet_softc *)arg; 281 int i; 282 uint32_t val; 283 284 val = bus_read_4(sc->mem_res, HPET_ISR); 285 if (val) { 286 bus_write_4(sc->mem_res, HPET_ISR, val); 287 val &= sc->useirq; 288 for (i = 0; i < sc->num_timers; i++) { 289 if ((val & (1 << i)) == 0) 290 continue; 291 hpet_intr_single(&sc->t[i]); 292 } 293 return (FILTER_HANDLED); 294 } 295 return (FILTER_STRAY); 296} 297 298static ACPI_STATUS 299hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 300 void **status) 301{ 302 char **ids; 303 uint32_t id = (uint32_t)(uintptr_t)context; 304 uint32_t uid = 0; 305 306 for (ids = hpet_ids; *ids != NULL; ids++) { 307 if (acpi_MatchHid(handle, *ids)) 308 break; 309 } 310 if (*ids == NULL) 311 return (AE_OK); 312 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 313 id == uid) 314 *status = acpi_get_device(handle); 315 return (AE_OK); 316} 317 318/* 319 * Find an existing IRQ resource that matches the requested IRQ range 320 * and return its RID. If one is not found, use a new RID. 321 */ 322static int 323hpet_find_irq_rid(device_t dev, u_long start, u_long end) 324{ 325 u_long irq; 326 int error, rid; 327 328 for (rid = 0;; rid++) { 329 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 330 if (error != 0 || (start <= irq && irq <= end)) 331 return (rid); 332 } 333} 334 335static int 336hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td) 337{ 338 struct hpet_softc *sc; 339 340 sc = cdev->si_drv1; 341 if (!sc->mmap_allow) 342 return (EPERM); 343 else 344 return (0); 345} 346 347static int 348hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr, 349 int nprot, vm_memattr_t *memattr) 350{ 351 struct hpet_softc *sc; 352 353 sc = cdev->si_drv1; 354 if (offset > rman_get_size(sc->mem_res)) 355 return (EINVAL); 356 if (!sc->mmap_allow_write && (nprot & PROT_WRITE)) 357 return (EPERM); 358 *paddr = rman_get_start(sc->mem_res) + offset; 359 360 return (0); 361} 362 363/* Discover the HPET via the ACPI table of the same name. */ 364static void 365hpet_identify(driver_t *driver, device_t parent) 366{ 367 ACPI_TABLE_HPET *hpet; 368 ACPI_STATUS status; 369 device_t child; 370 int i; 371 372 /* Only one HPET device can be added. */ 373 if (devclass_get_device(hpet_devclass, 0)) 374 return; 375 for (i = 1; ; i++) { 376 /* Search for HPET table. */ 377 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 378 if (ACPI_FAILURE(status)) 379 return; 380 /* Search for HPET device with same ID. */ 381 child = NULL; 382 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 383 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, 384 (void *)&child); 385 /* If found - let it be probed in normal way. */ 386 if (child) { 387 if (bus_get_resource(child, SYS_RES_MEMORY, 0, 388 NULL, NULL) != 0) 389 bus_set_resource(child, SYS_RES_MEMORY, 0, 390 hpet->Address.Address, HPET_MEM_WIDTH); 391 continue; 392 } 393 /* If not - create it from table info. */ 394 child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 395 if (child == NULL) { 396 printf("%s: can't add child\n", __func__); 397 continue; 398 } 399 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 400 HPET_MEM_WIDTH); 401 } 402} 403 404static int 405hpet_probe(device_t dev) 406{ 407 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 408 409 if (acpi_disabled("hpet") || acpi_hpet_disabled) 410 return (ENXIO); 411 if (acpi_get_handle(dev) != NULL && 412 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 413 return (ENXIO); 414 415 device_set_desc(dev, "High Precision Event Timer"); 416 return (0); 417} 418 419static int 420hpet_attach(device_t dev) 421{ 422 struct hpet_softc *sc; 423 struct hpet_timer *t; 424 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 425 int pcpu_master; 426 static int maxhpetet = 0; 427 uint32_t val, val2, cvectors, dvectors; 428 uint16_t vendor, rev; 429 430 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 431 432 sc = device_get_softc(dev); 433 sc->dev = dev; 434 sc->handle = acpi_get_handle(dev); 435 436 sc->mem_rid = 0; 437 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 438 RF_ACTIVE); 439 if (sc->mem_res == NULL) 440 return (ENOMEM); 441 442 /* Validate that we can access the whole region. */ 443 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 444 device_printf(dev, "memory region width %ld too small\n", 445 rman_get_size(sc->mem_res)); 446 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 447 return (ENXIO); 448 } 449 450 /* Be sure timer is enabled. */ 451 hpet_enable(sc); 452 453 /* Read basic statistics about the timer. */ 454 val = bus_read_4(sc->mem_res, HPET_PERIOD); 455 if (val == 0) { 456 device_printf(dev, "invalid period\n"); 457 hpet_disable(sc); 458 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 459 return (ENXIO); 460 } 461 462 sc->freq = (1000000000000000LL + val / 2) / val; 463 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 464 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 465 rev = sc->caps & HPET_CAP_REV_ID; 466 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 467 /* 468 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 469 * Specification and provides an off by one number 470 * of timers/comparators. 471 * Additionally, they use unregistered value in VENDOR_ID field. 472 */ 473 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 474 num_timers--; 475 sc->num_timers = num_timers; 476 if (bootverbose) { 477 device_printf(dev, 478 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 479 vendor, rev, sc->freq, 480 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 481 num_timers, 482 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 483 } 484 for (i = 0; i < num_timers; i++) { 485 t = &sc->t[i]; 486 t->sc = sc; 487 t->num = i; 488 t->mode = 0; 489 t->intr_rid = -1; 490 t->irq = -1; 491 t->pcpu_cpu = -1; 492 t->pcpu_misrouted = 0; 493 t->pcpu_master = -1; 494 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 495 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 496 if (bootverbose) { 497 device_printf(dev, 498 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 499 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 500 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 501 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 502 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 503 } 504 } 505 if (testenv("debug.acpi.hpet_test")) 506 hpet_test(sc); 507 /* 508 * Don't attach if the timer never increments. Since the spec 509 * requires it to be at least 10 MHz, it has to change in 1 us. 510 */ 511 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 512 DELAY(1); 513 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 514 if (val == val2) { 515 device_printf(dev, "HPET never increments, disabling\n"); 516 hpet_disable(sc); 517 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 518 return (ENXIO); 519 } 520 /* Announce first HPET as timecounter. */ 521 if (device_get_unit(dev) == 0) { 522 sc->tc.tc_get_timecount = hpet_get_timecount, 523 sc->tc.tc_counter_mask = ~0u, 524 sc->tc.tc_name = "HPET", 525 sc->tc.tc_quality = 950, 526 sc->tc.tc_frequency = sc->freq; 527 sc->tc.tc_priv = sc; 528 tc_init(&sc->tc); 529 } 530 /* If not disabled - setup and announce event timers. */ 531 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 532 "clock", &i) == 0 && i == 0) 533 return (0); 534 535 /* Check whether we can and want legacy routing. */ 536 sc->legacy_route = 0; 537 resource_int_value(device_get_name(dev), device_get_unit(dev), 538 "legacy_route", &sc->legacy_route); 539 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 540 sc->legacy_route = 0; 541 if (sc->legacy_route) { 542 sc->t[0].vectors = 0; 543 sc->t[1].vectors = 0; 544 } 545 546 /* Check what IRQs we want use. */ 547 /* By default allow any PCI IRQs. */ 548 sc->allowed_irqs = 0xffff0000; 549 /* 550 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 551 * Lower are also not always working for different reasons. 552 * SB800 fixed it, but seems do not implements level triggering 553 * properly, that makes it very unreliable - it freezes after any 554 * interrupt loss. Avoid legacy IRQs for AMD. 555 */ 556 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2) 557 sc->allowed_irqs = 0x00000000; 558 /* 559 * NVidia MCP5x chipsets have number of unexplained interrupt 560 * problems. For some reason, using HPET interrupts breaks HDA sound. 561 */ 562 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 563 sc->allowed_irqs = 0x00000000; 564 /* 565 * ServerWorks HT1000 reported to have problems with IRQs >= 16. 566 * Lower IRQs are working, but allowed mask is not set correctly. 567 * Legacy_route mode works fine. 568 */ 569 if (vendor == HPET_VENDID_SW && rev <= 0x01) 570 sc->allowed_irqs = 0x00000000; 571 /* 572 * Neither QEMU nor VirtualBox report supported IRQs correctly. 573 * The only way to use HPET there is to specify IRQs manually 574 * and/or use legacy_route. Legacy_route mode works on both. 575 */ 576 if (vm_guest) 577 sc->allowed_irqs = 0x00000000; 578 /* Let user override. */ 579 resource_int_value(device_get_name(dev), device_get_unit(dev), 580 "allowed_irqs", &sc->allowed_irqs); 581 582 /* Get how much per-CPU timers we should try to provide. */ 583 sc->per_cpu = 1; 584 resource_int_value(device_get_name(dev), device_get_unit(dev), 585 "per_cpu", &sc->per_cpu); 586 587 num_msi = 0; 588 sc->useirq = 0; 589 /* Find IRQ vectors for all timers. */ 590 cvectors = sc->allowed_irqs & 0xffff0000; 591 dvectors = sc->allowed_irqs & 0x0000ffff; 592 if (sc->legacy_route) 593 dvectors &= 0x0000fefe; 594 for (i = 0; i < num_timers; i++) { 595 t = &sc->t[i]; 596 if (sc->legacy_route && i < 2) 597 t->irq = (i == 0) ? 0 : 8; 598#ifdef DEV_APIC 599 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 600 if ((j = PCIB_ALLOC_MSIX( 601 device_get_parent(device_get_parent(dev)), dev, 602 &t->irq))) { 603 device_printf(dev, 604 "Can't allocate interrupt for t%d: %d\n", 605 i, j); 606 } 607 } 608#endif 609 else if (dvectors & t->vectors) { 610 t->irq = ffs(dvectors & t->vectors) - 1; 611 dvectors &= ~(1 << t->irq); 612 } 613 if (t->irq >= 0) { 614 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 615 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 616 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 617 if (t->intr_res == NULL) { 618 t->irq = -1; 619 device_printf(dev, 620 "Can't map interrupt for t%d.\n", i); 621 } else if (bus_setup_intr(dev, t->intr_res, 622 INTR_TYPE_CLK, hpet_intr_single, NULL, t, 623 &t->intr_handle) != 0) { 624 t->irq = -1; 625 device_printf(dev, 626 "Can't setup interrupt for t%d.\n", i); 627 } else { 628 bus_describe_intr(dev, t->intr_res, 629 t->intr_handle, "t%d", i); 630 num_msi++; 631 } 632 } 633 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 634 cvectors &= t->vectors; 635 sc->useirq |= (1 << i); 636 } 637 } 638 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 639 sc->legacy_route = 0; 640 if (sc->legacy_route) 641 hpet_enable(sc); 642 /* Group timers for per-CPU operation. */ 643 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 644 num_percpu_t = num_percpu_et * mp_ncpus; 645 pcpu_master = 0; 646 cur_cpu = CPU_FIRST(); 647 for (i = 0; i < num_timers; i++) { 648 t = &sc->t[i]; 649 if (t->irq >= 0 && num_percpu_t > 0) { 650 if (cur_cpu == CPU_FIRST()) 651 pcpu_master = i; 652 t->pcpu_cpu = cur_cpu; 653 t->pcpu_master = pcpu_master; 654 sc->t[pcpu_master]. 655 pcpu_slaves[cur_cpu] = i; 656 bus_bind_intr(dev, t->intr_res, cur_cpu); 657 cur_cpu = CPU_NEXT(cur_cpu); 658 num_percpu_t--; 659 } else if (t->irq >= 0) 660 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 661 } 662 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 663 sc->irq = -1; 664 /* If at least one timer needs legacy IRQ - set it up. */ 665 if (sc->useirq) { 666 j = i = fls(cvectors) - 1; 667 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 668 j--; 669 sc->intr_rid = hpet_find_irq_rid(dev, j, i); 670 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 671 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 672 if (sc->intr_res == NULL) 673 device_printf(dev, "Can't map interrupt.\n"); 674 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 675 hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 676 device_printf(dev, "Can't setup interrupt.\n"); 677 } else { 678 sc->irq = rman_get_start(sc->intr_res); 679 /* Bind IRQ to BSP to avoid live migration. */ 680 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 681 } 682 } 683 /* Program and announce event timers. */ 684 for (i = 0; i < num_timers; i++) { 685 t = &sc->t[i]; 686 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 687 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 688 t->caps &= ~(HPET_TCNF_INT_TYPE); 689 t->caps |= HPET_TCNF_32MODE; 690 if (t->irq >= 0 && sc->legacy_route && i < 2) { 691 /* Legacy route doesn't need more configuration. */ 692 } else 693#ifdef DEV_APIC 694 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 695 uint64_t addr; 696 uint32_t data; 697 698 if (PCIB_MAP_MSI( 699 device_get_parent(device_get_parent(dev)), dev, 700 t->irq, &addr, &data) == 0) { 701 bus_write_4(sc->mem_res, 702 HPET_TIMER_FSB_ADDR(i), addr); 703 bus_write_4(sc->mem_res, 704 HPET_TIMER_FSB_VAL(i), data); 705 t->caps |= HPET_TCNF_FSB_EN; 706 } else 707 t->irq = -2; 708 } else 709#endif 710 if (t->irq >= 0) 711 t->caps |= (t->irq << 9); 712 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 713 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 714 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 715 /* Skip event timers without set up IRQ. */ 716 if (t->irq < 0 && 717 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 718 continue; 719 /* Announce the reset. */ 720 if (maxhpetet == 0) 721 t->et.et_name = "HPET"; 722 else { 723 sprintf(t->name, "HPET%d", maxhpetet); 724 t->et.et_name = t->name; 725 } 726 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 727 t->et.et_quality = 450; 728 if (t->pcpu_master >= 0) { 729 t->et.et_flags |= ET_FLAGS_PERCPU; 730 t->et.et_quality += 100; 731 } else if (mp_ncpus >= 8) 732 t->et.et_quality -= 100; 733 if ((t->caps & HPET_TCAP_PER_INT) == 0) 734 t->et.et_quality -= 10; 735 t->et.et_frequency = sc->freq; 736 t->et.et_min_period = 737 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; 738 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; 739 t->et.et_start = hpet_start; 740 t->et.et_stop = hpet_stop; 741 t->et.et_priv = &sc->t[i]; 742 if (t->pcpu_master < 0 || t->pcpu_master == i) { 743 et_register(&t->et); 744 maxhpetet++; 745 } 746 } 747 748 sc->pdev = make_dev(&hpet_cdevsw, 0, UID_ROOT, GID_WHEEL, 749 0600, "hpet%d", device_get_unit(dev)); 750 if (sc->pdev) { 751 sc->pdev->si_drv1 = sc; 752 sc->mmap_allow = 1; 753 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow", 754 &sc->mmap_allow); 755 sc->mmap_allow_write = 1; 756 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write", 757 &sc->mmap_allow_write); 758 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 759 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 760 OID_AUTO, "mmap_allow", 761 CTLFLAG_RW, &sc->mmap_allow, 0, 762 "Allow userland to memory map HPET"); 763 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 764 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 765 OID_AUTO, "mmap_allow_write", 766 CTLFLAG_RW, &sc->mmap_allow_write, 0, 767 "Allow userland write to the HPET register space"); 768 } else 769 device_printf(dev, "could not create /dev/hpet%d\n", 770 device_get_unit(dev)); 771 772 return (0); 773} 774 775static int 776hpet_detach(device_t dev) 777{ 778 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 779 780 /* XXX Without a tc_remove() function, we can't detach. */ 781 return (EBUSY); 782} 783 784static int 785hpet_suspend(device_t dev) 786{ 787// struct hpet_softc *sc; 788 789 /* 790 * Disable the timer during suspend. The timer will not lose 791 * its state in S1 or S2, but we are required to disable 792 * it. 793 */ 794// sc = device_get_softc(dev); 795// hpet_disable(sc); 796 797 return (0); 798} 799 800static int 801hpet_resume(device_t dev) 802{ 803 struct hpet_softc *sc; 804 struct hpet_timer *t; 805 int i; 806 807 /* Re-enable the timer after a resume to keep the clock advancing. */ 808 sc = device_get_softc(dev); 809 hpet_enable(sc); 810 /* Restart event timers that were running on suspend. */ 811 for (i = 0; i < sc->num_timers; i++) { 812 t = &sc->t[i]; 813#ifdef DEV_APIC 814 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 815 uint64_t addr; 816 uint32_t data; 817 818 if (PCIB_MAP_MSI( 819 device_get_parent(device_get_parent(dev)), dev, 820 t->irq, &addr, &data) == 0) { 821 bus_write_4(sc->mem_res, 822 HPET_TIMER_FSB_ADDR(i), addr); 823 bus_write_4(sc->mem_res, 824 HPET_TIMER_FSB_VAL(i), data); 825 } 826 } 827#endif 828 if (t->mode == 0) 829 continue; 830 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 831 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 832 t->caps |= HPET_TCNF_TYPE; 833 t->next += t->div; 834 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 835 t->caps | HPET_TCNF_VAL_SET); 836 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 837 t->next); 838 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 839 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 840 t->div); 841 } else { 842 t->next += sc->freq / 1024; 843 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 844 t->next); 845 } 846 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 847 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 848 } 849 return (0); 850} 851 852/* Print some basic latency/rate information to assist in debugging. */ 853static void 854hpet_test(struct hpet_softc *sc) 855{ 856 int i; 857 uint32_t u1, u2; 858 struct bintime b0, b1, b2; 859 struct timespec ts; 860 861 binuptime(&b0); 862 binuptime(&b0); 863 binuptime(&b1); 864 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 865 for (i = 1; i < 1000; i++) 866 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 867 binuptime(&b2); 868 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 869 870 bintime_sub(&b2, &b1); 871 bintime_sub(&b1, &b0); 872 bintime_sub(&b2, &b1); 873 bintime2timespec(&b2, &ts); 874 875 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 876 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 877 878 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 879} 880 881#ifdef DEV_APIC 882static int 883hpet_remap_intr(device_t dev, device_t child, u_int irq) 884{ 885 struct hpet_softc *sc = device_get_softc(dev); 886 struct hpet_timer *t; 887 uint64_t addr; 888 uint32_t data; 889 int error, i; 890 891 for (i = 0; i < sc->num_timers; i++) { 892 t = &sc->t[i]; 893 if (t->irq != irq) 894 continue; 895 error = PCIB_MAP_MSI( 896 device_get_parent(device_get_parent(dev)), dev, 897 irq, &addr, &data); 898 if (error) 899 return (error); 900 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 901 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 902 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 903 hpet_enable(sc); 904 return (0); 905 } 906 return (ENOENT); 907} 908#endif 909 910static device_method_t hpet_methods[] = { 911 /* Device interface */ 912 DEVMETHOD(device_identify, hpet_identify), 913 DEVMETHOD(device_probe, hpet_probe), 914 DEVMETHOD(device_attach, hpet_attach), 915 DEVMETHOD(device_detach, hpet_detach), 916 DEVMETHOD(device_suspend, hpet_suspend), 917 DEVMETHOD(device_resume, hpet_resume), 918 919#ifdef DEV_APIC 920 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 921#endif 922 923 DEVMETHOD_END 924}; 925 926static driver_t hpet_driver = { 927 "hpet", 928 hpet_methods, 929 sizeof(struct hpet_softc), 930}; 931 932DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 933MODULE_DEPEND(hpet, acpi, 1, 1, 1); 934