acpi_hpet.c revision 248154
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 248154 2013-03-11 12:02:03Z mav $"); 30 31#include "opt_acpi.h" 32#if defined(__amd64__) || defined(__ia64__) 33#define DEV_APIC 34#else 35#include "opt_apic.h" 36#endif 37#include <sys/param.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/proc.h> 42#include <sys/rman.h> 43#include <sys/time.h> 44#include <sys/smp.h> 45#include <sys/sysctl.h> 46#include <sys/timeet.h> 47#include <sys/timetc.h> 48 49#include <contrib/dev/acpica/include/acpi.h> 50#include <contrib/dev/acpica/include/accommon.h> 51 52#include <dev/acpica/acpivar.h> 53#include <dev/acpica/acpi_hpet.h> 54 55#ifdef DEV_APIC 56#include "pcib_if.h" 57#endif 58 59#define HPET_VENDID_AMD 0x4353 60#define HPET_VENDID_AMD2 0x1022 61#define HPET_VENDID_INTEL 0x8086 62#define HPET_VENDID_NVIDIA 0x10de 63#define HPET_VENDID_SW 0x1166 64 65ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 66 67static devclass_t hpet_devclass; 68 69/* ACPI CA debugging */ 70#define _COMPONENT ACPI_TIMER 71ACPI_MODULE_NAME("HPET") 72 73struct hpet_softc { 74 device_t dev; 75 int mem_rid; 76 int intr_rid; 77 int irq; 78 int useirq; 79 int legacy_route; 80 int per_cpu; 81 uint32_t allowed_irqs; 82 struct resource *mem_res; 83 struct resource *intr_res; 84 void *intr_handle; 85 ACPI_HANDLE handle; 86 uint64_t freq; 87 uint32_t caps; 88 struct timecounter tc; 89 struct hpet_timer { 90 struct eventtimer et; 91 struct hpet_softc *sc; 92 int num; 93 int mode; 94 int intr_rid; 95 int irq; 96 int pcpu_cpu; 97 int pcpu_misrouted; 98 int pcpu_master; 99 int pcpu_slaves[MAXCPU]; 100 struct resource *intr_res; 101 void *intr_handle; 102 uint32_t caps; 103 uint32_t vectors; 104 uint32_t div; 105 uint32_t next; 106 char name[8]; 107 } t[32]; 108 int num_timers; 109}; 110 111static u_int hpet_get_timecount(struct timecounter *tc); 112static void hpet_test(struct hpet_softc *sc); 113 114static char *hpet_ids[] = { "PNP0103", NULL }; 115 116static u_int 117hpet_get_timecount(struct timecounter *tc) 118{ 119 struct hpet_softc *sc; 120 121 sc = tc->tc_priv; 122 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 123} 124 125static void 126hpet_enable(struct hpet_softc *sc) 127{ 128 uint32_t val; 129 130 val = bus_read_4(sc->mem_res, HPET_CONFIG); 131 if (sc->legacy_route) 132 val |= HPET_CNF_LEG_RT; 133 else 134 val &= ~HPET_CNF_LEG_RT; 135 val |= HPET_CNF_ENABLE; 136 bus_write_4(sc->mem_res, HPET_CONFIG, val); 137} 138 139static void 140hpet_disable(struct hpet_softc *sc) 141{ 142 uint32_t val; 143 144 val = bus_read_4(sc->mem_res, HPET_CONFIG); 145 val &= ~HPET_CNF_ENABLE; 146 bus_write_4(sc->mem_res, HPET_CONFIG, val); 147} 148 149static int 150hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 151{ 152 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 153 struct hpet_timer *t; 154 struct hpet_softc *sc = mt->sc; 155 uint32_t fdiv, now; 156 157 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 158 if (period != 0) { 159 t->mode = 1; 160 t->div = (sc->freq * period) >> 32; 161 } else { 162 t->mode = 2; 163 t->div = 0; 164 } 165 if (first != 0) 166 fdiv = (sc->freq * first) >> 32; 167 else 168 fdiv = t->div; 169 if (t->irq < 0) 170 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 171 t->caps |= HPET_TCNF_INT_ENB; 172 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 173restart: 174 t->next = now + fdiv; 175 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 176 t->caps |= HPET_TCNF_TYPE; 177 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 178 t->caps | HPET_TCNF_VAL_SET); 179 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 180 t->next); 181 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 182 t->div); 183 } else { 184 t->caps &= ~HPET_TCNF_TYPE; 185 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 186 t->caps); 187 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 188 t->next); 189 } 190 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 191 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 192 fdiv *= 2; 193 goto restart; 194 } 195 return (0); 196} 197 198static int 199hpet_stop(struct eventtimer *et) 200{ 201 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 202 struct hpet_timer *t; 203 struct hpet_softc *sc = mt->sc; 204 205 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 206 t->mode = 0; 207 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 208 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 209 return (0); 210} 211 212static int 213hpet_intr_single(void *arg) 214{ 215 struct hpet_timer *t = (struct hpet_timer *)arg; 216 struct hpet_timer *mt; 217 struct hpet_softc *sc = t->sc; 218 uint32_t now; 219 220 if (t->mode == 0) 221 return (FILTER_STRAY); 222 /* Check that per-CPU timer interrupt reached right CPU. */ 223 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 224 if ((++t->pcpu_misrouted) % 32 == 0) { 225 printf("HPET interrupt routed to the wrong CPU" 226 " (timer %d CPU %d -> %d)!\n", 227 t->num, t->pcpu_cpu, curcpu); 228 } 229 230 /* 231 * Reload timer, hoping that next time may be more lucky 232 * (system will manage proper interrupt binding). 233 */ 234 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 235 t->mode == 2) { 236 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 237 sc->freq / 8; 238 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 239 t->next); 240 } 241 return (FILTER_HANDLED); 242 } 243 if (t->mode == 1 && 244 (t->caps & HPET_TCAP_PER_INT) == 0) { 245 t->next += t->div; 246 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 247 if ((int32_t)((now + t->div / 2) - t->next) > 0) 248 t->next = now + t->div / 2; 249 bus_write_4(sc->mem_res, 250 HPET_TIMER_COMPARATOR(t->num), t->next); 251 } else if (t->mode == 2) 252 t->mode = 0; 253 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 254 if (mt->et.et_active) 255 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 256 return (FILTER_HANDLED); 257} 258 259static int 260hpet_intr(void *arg) 261{ 262 struct hpet_softc *sc = (struct hpet_softc *)arg; 263 int i; 264 uint32_t val; 265 266 val = bus_read_4(sc->mem_res, HPET_ISR); 267 if (val) { 268 bus_write_4(sc->mem_res, HPET_ISR, val); 269 val &= sc->useirq; 270 for (i = 0; i < sc->num_timers; i++) { 271 if ((val & (1 << i)) == 0) 272 continue; 273 hpet_intr_single(&sc->t[i]); 274 } 275 return (FILTER_HANDLED); 276 } 277 return (FILTER_STRAY); 278} 279 280static ACPI_STATUS 281hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 282 void **status) 283{ 284 char **ids; 285 uint32_t id = (uint32_t)(uintptr_t)context; 286 uint32_t uid = 0; 287 288 for (ids = hpet_ids; *ids != NULL; ids++) { 289 if (acpi_MatchHid(handle, *ids)) 290 break; 291 } 292 if (*ids == NULL) 293 return (AE_OK); 294 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 295 id == uid) 296 *((int *)status) = 1; 297 return (AE_OK); 298} 299 300/* 301 * Find an existing IRQ resource that matches the requested IRQ range 302 * and return its RID. If one is not found, use a new RID. 303 */ 304static int 305hpet_find_irq_rid(device_t dev, u_long start, u_long end) 306{ 307 u_long irq; 308 int error, rid; 309 310 for (rid = 0;; rid++) { 311 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 312 if (error != 0 || (start <= irq && irq <= end)) 313 return (rid); 314 } 315} 316 317/* Discover the HPET via the ACPI table of the same name. */ 318static void 319hpet_identify(driver_t *driver, device_t parent) 320{ 321 ACPI_TABLE_HPET *hpet; 322 ACPI_STATUS status; 323 device_t child; 324 int i, found; 325 326 /* Only one HPET device can be added. */ 327 if (devclass_get_device(hpet_devclass, 0)) 328 return; 329 for (i = 1; ; i++) { 330 /* Search for HPET table. */ 331 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 332 if (ACPI_FAILURE(status)) 333 return; 334 /* Search for HPET device with same ID. */ 335 found = 0; 336 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 337 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 338 /* If found - let it be probed in normal way. */ 339 if (found) 340 continue; 341 /* If not - create it from table info. */ 342 child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 343 if (child == NULL) { 344 printf("%s: can't add child\n", __func__); 345 continue; 346 } 347 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 348 HPET_MEM_WIDTH); 349 } 350} 351 352static int 353hpet_probe(device_t dev) 354{ 355 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 356 357 if (acpi_disabled("hpet")) 358 return (ENXIO); 359 if (acpi_get_handle(dev) != NULL && 360 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 361 return (ENXIO); 362 363 device_set_desc(dev, "High Precision Event Timer"); 364 return (0); 365} 366 367static int 368hpet_attach(device_t dev) 369{ 370 struct hpet_softc *sc; 371 struct hpet_timer *t; 372 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 373 int pcpu_master; 374 static int maxhpetet = 0; 375 uint32_t val, val2, cvectors, dvectors; 376 uint16_t vendor, rev; 377 378 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 379 380 sc = device_get_softc(dev); 381 sc->dev = dev; 382 sc->handle = acpi_get_handle(dev); 383 384 sc->mem_rid = 0; 385 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 386 RF_ACTIVE); 387 if (sc->mem_res == NULL) 388 return (ENOMEM); 389 390 /* Validate that we can access the whole region. */ 391 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 392 device_printf(dev, "memory region width %ld too small\n", 393 rman_get_size(sc->mem_res)); 394 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 395 return (ENXIO); 396 } 397 398 /* Be sure timer is enabled. */ 399 hpet_enable(sc); 400 401 /* Read basic statistics about the timer. */ 402 val = bus_read_4(sc->mem_res, HPET_PERIOD); 403 if (val == 0) { 404 device_printf(dev, "invalid period\n"); 405 hpet_disable(sc); 406 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 407 return (ENXIO); 408 } 409 410 sc->freq = (1000000000000000LL + val / 2) / val; 411 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 412 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 413 rev = sc->caps & HPET_CAP_REV_ID; 414 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 415 /* 416 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 417 * Specification and provides an off by one number 418 * of timers/comparators. 419 * Additionally, they use unregistered value in VENDOR_ID field. 420 */ 421 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 422 num_timers--; 423 sc->num_timers = num_timers; 424 if (bootverbose) { 425 device_printf(dev, 426 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 427 vendor, rev, sc->freq, 428 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 429 num_timers, 430 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 431 } 432 for (i = 0; i < num_timers; i++) { 433 t = &sc->t[i]; 434 t->sc = sc; 435 t->num = i; 436 t->mode = 0; 437 t->intr_rid = -1; 438 t->irq = -1; 439 t->pcpu_cpu = -1; 440 t->pcpu_misrouted = 0; 441 t->pcpu_master = -1; 442 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 443 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 444 if (bootverbose) { 445 device_printf(dev, 446 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 447 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 448 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 449 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 450 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 451 } 452 } 453 if (testenv("debug.acpi.hpet_test")) 454 hpet_test(sc); 455 /* 456 * Don't attach if the timer never increments. Since the spec 457 * requires it to be at least 10 MHz, it has to change in 1 us. 458 */ 459 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 460 DELAY(1); 461 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 462 if (val == val2) { 463 device_printf(dev, "HPET never increments, disabling\n"); 464 hpet_disable(sc); 465 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 466 return (ENXIO); 467 } 468 /* Announce first HPET as timecounter. */ 469 if (device_get_unit(dev) == 0) { 470 sc->tc.tc_get_timecount = hpet_get_timecount, 471 sc->tc.tc_counter_mask = ~0u, 472 sc->tc.tc_name = "HPET", 473 sc->tc.tc_quality = 950, 474 sc->tc.tc_frequency = sc->freq; 475 sc->tc.tc_priv = sc; 476 tc_init(&sc->tc); 477 } 478 /* If not disabled - setup and announce event timers. */ 479 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 480 "clock", &i) == 0 && i == 0) 481 return (0); 482 483 /* Check whether we can and want legacy routing. */ 484 sc->legacy_route = 0; 485 resource_int_value(device_get_name(dev), device_get_unit(dev), 486 "legacy_route", &sc->legacy_route); 487 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 488 sc->legacy_route = 0; 489 if (sc->legacy_route) { 490 sc->t[0].vectors = 0; 491 sc->t[1].vectors = 0; 492 } 493 494 /* Check what IRQs we want use. */ 495 /* By default allow any PCI IRQs. */ 496 sc->allowed_irqs = 0xffff0000; 497 /* 498 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 499 * Lower are also not always working for different reasons. 500 * SB800 fixed it, but seems do not implements level triggering 501 * properly, that makes it very unreliable - it freezes after any 502 * interrupt loss. Avoid legacy IRQs for AMD. 503 */ 504 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2) 505 sc->allowed_irqs = 0x00000000; 506 /* 507 * NVidia MCP5x chipsets have number of unexplained interrupt 508 * problems. For some reason, using HPET interrupts breaks HDA sound. 509 */ 510 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 511 sc->allowed_irqs = 0x00000000; 512 /* 513 * ServerWorks HT1000 reported to have problems with IRQs >= 16. 514 * Lower IRQs are working, but allowed mask is not set correctly. 515 * Legacy_route mode works fine. 516 */ 517 if (vendor == HPET_VENDID_SW && rev <= 0x01) 518 sc->allowed_irqs = 0x00000000; 519 /* 520 * Neither QEMU nor VirtualBox report supported IRQs correctly. 521 * The only way to use HPET there is to specify IRQs manually 522 * and/or use legacy_route. Legacy_route mode works on both. 523 */ 524 if (vm_guest) 525 sc->allowed_irqs = 0x00000000; 526 /* Let user override. */ 527 resource_int_value(device_get_name(dev), device_get_unit(dev), 528 "allowed_irqs", &sc->allowed_irqs); 529 530 /* Get how much per-CPU timers we should try to provide. */ 531 sc->per_cpu = 1; 532 resource_int_value(device_get_name(dev), device_get_unit(dev), 533 "per_cpu", &sc->per_cpu); 534 535 num_msi = 0; 536 sc->useirq = 0; 537 /* Find IRQ vectors for all timers. */ 538 cvectors = sc->allowed_irqs & 0xffff0000; 539 dvectors = sc->allowed_irqs & 0x0000ffff; 540 if (sc->legacy_route) 541 dvectors &= 0x0000fefe; 542 for (i = 0; i < num_timers; i++) { 543 t = &sc->t[i]; 544 if (sc->legacy_route && i < 2) 545 t->irq = (i == 0) ? 0 : 8; 546#ifdef DEV_APIC 547 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 548 if ((j = PCIB_ALLOC_MSIX( 549 device_get_parent(device_get_parent(dev)), dev, 550 &t->irq))) { 551 device_printf(dev, 552 "Can't allocate interrupt for t%d.\n", j); 553 } 554 } 555#endif 556 else if (dvectors & t->vectors) { 557 t->irq = ffs(dvectors & t->vectors) - 1; 558 dvectors &= ~(1 << t->irq); 559 } 560 if (t->irq >= 0) { 561 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 562 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 563 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 564 if (t->intr_res == NULL) { 565 t->irq = -1; 566 device_printf(dev, 567 "Can't map interrupt for t%d.\n", i); 568 } else if (bus_setup_intr(dev, t->intr_res, 569 INTR_TYPE_CLK, hpet_intr_single, NULL, t, 570 &t->intr_handle) != 0) { 571 t->irq = -1; 572 device_printf(dev, 573 "Can't setup interrupt for t%d.\n", i); 574 } else { 575 bus_describe_intr(dev, t->intr_res, 576 t->intr_handle, "t%d", i); 577 num_msi++; 578 } 579 } 580 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 581 cvectors &= t->vectors; 582 sc->useirq |= (1 << i); 583 } 584 } 585 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 586 sc->legacy_route = 0; 587 if (sc->legacy_route) 588 hpet_enable(sc); 589 /* Group timers for per-CPU operation. */ 590 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 591 num_percpu_t = num_percpu_et * mp_ncpus; 592 pcpu_master = 0; 593 cur_cpu = CPU_FIRST(); 594 for (i = 0; i < num_timers; i++) { 595 t = &sc->t[i]; 596 if (t->irq >= 0 && num_percpu_t > 0) { 597 if (cur_cpu == CPU_FIRST()) 598 pcpu_master = i; 599 t->pcpu_cpu = cur_cpu; 600 t->pcpu_master = pcpu_master; 601 sc->t[pcpu_master]. 602 pcpu_slaves[cur_cpu] = i; 603 bus_bind_intr(dev, t->intr_res, cur_cpu); 604 cur_cpu = CPU_NEXT(cur_cpu); 605 num_percpu_t--; 606 } else if (t->irq >= 0) 607 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 608 } 609 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 610 sc->irq = -1; 611 /* If at least one timer needs legacy IRQ - set it up. */ 612 if (sc->useirq) { 613 j = i = fls(cvectors) - 1; 614 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 615 j--; 616 sc->intr_rid = hpet_find_irq_rid(dev, j, i); 617 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 618 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 619 if (sc->intr_res == NULL) 620 device_printf(dev, "Can't map interrupt.\n"); 621 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 622 hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 623 device_printf(dev, "Can't setup interrupt.\n"); 624 } else { 625 sc->irq = rman_get_start(sc->intr_res); 626 /* Bind IRQ to BSP to avoid live migration. */ 627 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 628 } 629 } 630 /* Program and announce event timers. */ 631 for (i = 0; i < num_timers; i++) { 632 t = &sc->t[i]; 633 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 634 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 635 t->caps &= ~(HPET_TCNF_INT_TYPE); 636 t->caps |= HPET_TCNF_32MODE; 637 if (t->irq >= 0 && sc->legacy_route && i < 2) { 638 /* Legacy route doesn't need more configuration. */ 639 } else 640#ifdef DEV_APIC 641 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 642 uint64_t addr; 643 uint32_t data; 644 645 if (PCIB_MAP_MSI( 646 device_get_parent(device_get_parent(dev)), dev, 647 t->irq, &addr, &data) == 0) { 648 bus_write_4(sc->mem_res, 649 HPET_TIMER_FSB_ADDR(i), addr); 650 bus_write_4(sc->mem_res, 651 HPET_TIMER_FSB_VAL(i), data); 652 t->caps |= HPET_TCNF_FSB_EN; 653 } else 654 t->irq = -2; 655 } else 656#endif 657 if (t->irq >= 0) 658 t->caps |= (t->irq << 9); 659 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 660 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 661 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 662 /* Skip event timers without set up IRQ. */ 663 if (t->irq < 0 && 664 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 665 continue; 666 /* Announce the reset. */ 667 if (maxhpetet == 0) 668 t->et.et_name = "HPET"; 669 else { 670 sprintf(t->name, "HPET%d", maxhpetet); 671 t->et.et_name = t->name; 672 } 673 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 674 t->et.et_quality = 450; 675 if (t->pcpu_master >= 0) { 676 t->et.et_flags |= ET_FLAGS_PERCPU; 677 t->et.et_quality += 100; 678 } if (mp_ncpus >= 8) 679 t->et.et_quality -= 100; 680 if ((t->caps & HPET_TCAP_PER_INT) == 0) 681 t->et.et_quality -= 10; 682 t->et.et_frequency = sc->freq; 683 t->et.et_min_period = 684 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; 685 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; 686 t->et.et_start = hpet_start; 687 t->et.et_stop = hpet_stop; 688 t->et.et_priv = &sc->t[i]; 689 if (t->pcpu_master < 0 || t->pcpu_master == i) { 690 et_register(&t->et); 691 maxhpetet++; 692 } 693 } 694 return (0); 695} 696 697static int 698hpet_detach(device_t dev) 699{ 700 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 701 702 /* XXX Without a tc_remove() function, we can't detach. */ 703 return (EBUSY); 704} 705 706static int 707hpet_suspend(device_t dev) 708{ 709// struct hpet_softc *sc; 710 711 /* 712 * Disable the timer during suspend. The timer will not lose 713 * its state in S1 or S2, but we are required to disable 714 * it. 715 */ 716// sc = device_get_softc(dev); 717// hpet_disable(sc); 718 719 return (0); 720} 721 722static int 723hpet_resume(device_t dev) 724{ 725 struct hpet_softc *sc; 726 struct hpet_timer *t; 727 int i; 728 729 /* Re-enable the timer after a resume to keep the clock advancing. */ 730 sc = device_get_softc(dev); 731 hpet_enable(sc); 732 /* Restart event timers that were running on suspend. */ 733 for (i = 0; i < sc->num_timers; i++) { 734 t = &sc->t[i]; 735#ifdef DEV_APIC 736 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 737 uint64_t addr; 738 uint32_t data; 739 740 if (PCIB_MAP_MSI( 741 device_get_parent(device_get_parent(dev)), dev, 742 t->irq, &addr, &data) == 0) { 743 bus_write_4(sc->mem_res, 744 HPET_TIMER_FSB_ADDR(i), addr); 745 bus_write_4(sc->mem_res, 746 HPET_TIMER_FSB_VAL(i), data); 747 } 748 } 749#endif 750 if (t->mode == 0) 751 continue; 752 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 753 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 754 t->caps |= HPET_TCNF_TYPE; 755 t->next += t->div; 756 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 757 t->caps | HPET_TCNF_VAL_SET); 758 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 759 t->next); 760 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 761 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 762 t->div); 763 } else { 764 t->next += sc->freq / 1024; 765 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 766 t->next); 767 } 768 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 769 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 770 } 771 return (0); 772} 773 774/* Print some basic latency/rate information to assist in debugging. */ 775static void 776hpet_test(struct hpet_softc *sc) 777{ 778 int i; 779 uint32_t u1, u2; 780 struct bintime b0, b1, b2; 781 struct timespec ts; 782 783 binuptime(&b0); 784 binuptime(&b0); 785 binuptime(&b1); 786 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 787 for (i = 1; i < 1000; i++) 788 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 789 binuptime(&b2); 790 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 791 792 bintime_sub(&b2, &b1); 793 bintime_sub(&b1, &b0); 794 bintime_sub(&b2, &b1); 795 bintime2timespec(&b2, &ts); 796 797 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 798 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 799 800 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 801} 802 803#ifdef DEV_APIC 804static int 805hpet_remap_intr(device_t dev, device_t child, u_int irq) 806{ 807 struct hpet_softc *sc = device_get_softc(dev); 808 struct hpet_timer *t; 809 uint64_t addr; 810 uint32_t data; 811 int error, i; 812 813 for (i = 0; i < sc->num_timers; i++) { 814 t = &sc->t[i]; 815 if (t->irq != irq) 816 continue; 817 error = PCIB_MAP_MSI( 818 device_get_parent(device_get_parent(dev)), dev, 819 irq, &addr, &data); 820 if (error) 821 return (error); 822 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 823 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 824 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 825 hpet_enable(sc); 826 return (0); 827 } 828 return (ENOENT); 829} 830#endif 831 832static device_method_t hpet_methods[] = { 833 /* Device interface */ 834 DEVMETHOD(device_identify, hpet_identify), 835 DEVMETHOD(device_probe, hpet_probe), 836 DEVMETHOD(device_attach, hpet_attach), 837 DEVMETHOD(device_detach, hpet_detach), 838 DEVMETHOD(device_suspend, hpet_suspend), 839 DEVMETHOD(device_resume, hpet_resume), 840 841#ifdef DEV_APIC 842 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 843#endif 844 845 DEVMETHOD_END 846}; 847 848static driver_t hpet_driver = { 849 "hpet", 850 hpet_methods, 851 sizeof(struct hpet_softc), 852}; 853 854DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 855MODULE_DEPEND(hpet, acpi, 1, 1, 1); 856