acpi_hpet.c revision 212533
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 212533 2010-09-13 06:32:56Z mav $"); 30 31#include "opt_acpi.h" 32#if defined(__amd64__) || defined(__ia64__) 33#define DEV_APIC 34#else 35#include "opt_apic.h" 36#endif 37#include <sys/param.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/proc.h> 42#include <sys/rman.h> 43#include <sys/time.h> 44#include <sys/smp.h> 45#include <sys/sysctl.h> 46#include <sys/timeet.h> 47#include <sys/timetc.h> 48 49#include <contrib/dev/acpica/include/acpi.h> 50#include <contrib/dev/acpica/include/accommon.h> 51 52#include <dev/acpica/acpivar.h> 53#include <dev/acpica/acpi_hpet.h> 54 55#ifdef DEV_APIC 56#include "pcib_if.h" 57#endif 58 59#define HPET_VENDID_AMD 0x4353 60#define HPET_VENDID_INTEL 0x8086 61 62ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 63 64static devclass_t hpet_devclass; 65 66/* ACPI CA debugging */ 67#define _COMPONENT ACPI_TIMER 68ACPI_MODULE_NAME("HPET") 69 70struct hpet_softc { 71 device_t dev; 72 int mem_rid; 73 int intr_rid; 74 int irq; 75 int useirq; 76 int legacy_route; 77 int per_cpu; 78 uint32_t allowed_irqs; 79 struct resource *mem_res; 80 struct resource *intr_res; 81 void *intr_handle; 82 ACPI_HANDLE handle; 83 uint64_t freq; 84 uint32_t caps; 85 struct timecounter tc; 86 struct hpet_timer { 87 struct eventtimer et; 88 struct hpet_softc *sc; 89 int num; 90 int mode; 91 int intr_rid; 92 int irq; 93 int pcpu_cpu; 94 int pcpu_misrouted; 95 int pcpu_master; 96 int pcpu_slaves[MAXCPU]; 97 struct resource *intr_res; 98 void *intr_handle; 99 uint32_t caps; 100 uint32_t vectors; 101 uint32_t div; 102 uint32_t next; 103 char name[8]; 104 } t[32]; 105 int num_timers; 106}; 107 108static u_int hpet_get_timecount(struct timecounter *tc); 109static void hpet_test(struct hpet_softc *sc); 110 111static char *hpet_ids[] = { "PNP0103", NULL }; 112 113static u_int 114hpet_get_timecount(struct timecounter *tc) 115{ 116 struct hpet_softc *sc; 117 118 sc = tc->tc_priv; 119 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 120} 121 122static void 123hpet_enable(struct hpet_softc *sc) 124{ 125 uint32_t val; 126 127 val = bus_read_4(sc->mem_res, HPET_CONFIG); 128 if (sc->legacy_route) 129 val |= HPET_CNF_LEG_RT; 130 else 131 val &= ~HPET_CNF_LEG_RT; 132 val |= HPET_CNF_ENABLE; 133 bus_write_4(sc->mem_res, HPET_CONFIG, val); 134} 135 136static void 137hpet_disable(struct hpet_softc *sc) 138{ 139 uint32_t val; 140 141 val = bus_read_4(sc->mem_res, HPET_CONFIG); 142 val &= ~HPET_CNF_ENABLE; 143 bus_write_4(sc->mem_res, HPET_CONFIG, val); 144} 145 146static int 147hpet_start(struct eventtimer *et, 148 struct bintime *first, struct bintime *period) 149{ 150 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 151 struct hpet_timer *t; 152 struct hpet_softc *sc = mt->sc; 153 uint32_t fdiv, now; 154 155 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 156 if (period != NULL) { 157 t->mode = 1; 158 t->div = (sc->freq * (period->frac >> 32)) >> 32; 159 if (period->sec != 0) 160 t->div += sc->freq * period->sec; 161 } else { 162 t->mode = 2; 163 t->div = 0; 164 } 165 if (first != NULL) { 166 fdiv = (sc->freq * (first->frac >> 32)) >> 32; 167 if (first->sec != 0) 168 fdiv += sc->freq * first->sec; 169 } else 170 fdiv = t->div; 171 if (t->irq < 0) 172 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 173 t->caps |= HPET_TCNF_INT_ENB; 174 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 175restart: 176 t->next = now + fdiv; 177 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 178 t->caps |= HPET_TCNF_TYPE; 179 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 180 t->caps | HPET_TCNF_VAL_SET); 181 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 182 t->next); 183 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 184 t->div); 185 } else { 186 t->caps &= ~HPET_TCNF_TYPE; 187 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 188 t->caps); 189 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 190 t->next); 191 } 192 if (fdiv < 5000) { 193 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 194 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 195 if ((int32_t)(now - t->next) >= 0) { 196 fdiv *= 2; 197 goto restart; 198 } 199 } 200 return (0); 201} 202 203static int 204hpet_stop(struct eventtimer *et) 205{ 206 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 207 struct hpet_timer *t; 208 struct hpet_softc *sc = mt->sc; 209 210 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 211 t->mode = 0; 212 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 213 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 214 return (0); 215} 216 217static int 218hpet_intr_single(void *arg) 219{ 220 struct hpet_timer *t = (struct hpet_timer *)arg; 221 struct hpet_timer *mt; 222 struct hpet_softc *sc = t->sc; 223 uint32_t now; 224 225 if (t->mode == 0) 226 return (FILTER_STRAY); 227 /* Check that per-CPU timer interrupt reached right CPU. */ 228 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 229 if ((++t->pcpu_misrouted) % 32 == 0) { 230 printf("HPET interrupt routed to the wrong CPU" 231 " (timer %d CPU %d -> %d)!\n", 232 t->num, t->pcpu_cpu, curcpu); 233 } 234 235 /* 236 * Reload timer, hoping that next time may be more lucky 237 * (system will manage proper interrupt binding). 238 */ 239 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 240 t->mode == 2) { 241 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 242 sc->freq / 8; 243 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 244 t->next); 245 } 246 return (FILTER_HANDLED); 247 } 248 if (t->mode == 1 && 249 (t->caps & HPET_TCAP_PER_INT) == 0) { 250 t->next += t->div; 251 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 252 if ((int32_t)((now + t->div / 2) - t->next) > 0) 253 t->next = now + t->div / 2; 254 bus_write_4(sc->mem_res, 255 HPET_TIMER_COMPARATOR(t->num), t->next); 256 } else if (t->mode == 2) 257 t->mode = 0; 258 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 259 if (mt->et.et_active) 260 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 261 return (FILTER_HANDLED); 262} 263 264static int 265hpet_intr(void *arg) 266{ 267 struct hpet_softc *sc = (struct hpet_softc *)arg; 268 int i; 269 uint32_t val; 270 271 val = bus_read_4(sc->mem_res, HPET_ISR); 272 if (val) { 273 bus_write_4(sc->mem_res, HPET_ISR, val); 274 val &= sc->useirq; 275 for (i = 0; i < sc->num_timers; i++) { 276 if ((val & (1 << i)) == 0) 277 continue; 278 hpet_intr_single(&sc->t[i]); 279 } 280 return (FILTER_HANDLED); 281 } 282 return (FILTER_STRAY); 283} 284 285static ACPI_STATUS 286hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 287 void **status) 288{ 289 char **ids; 290 uint32_t id = (uint32_t)(uintptr_t)context; 291 uint32_t uid = 0; 292 293 for (ids = hpet_ids; *ids != NULL; ids++) { 294 if (acpi_MatchHid(handle, *ids)) 295 break; 296 } 297 if (*ids == NULL) 298 return (AE_OK); 299 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 300 id == uid) 301 *((int *)status) = 1; 302 return (AE_OK); 303} 304 305/* Discover the HPET via the ACPI table of the same name. */ 306static void 307hpet_identify(driver_t *driver, device_t parent) 308{ 309 ACPI_TABLE_HPET *hpet; 310 ACPI_STATUS status; 311 device_t child; 312 int i, found; 313 314 /* Only one HPET device can be added. */ 315 if (devclass_get_device(hpet_devclass, 0)) 316 return; 317 for (i = 1; ; i++) { 318 /* Search for HPET table. */ 319 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 320 if (ACPI_FAILURE(status)) 321 return; 322 /* Search for HPET device with same ID. */ 323 found = 0; 324 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 325 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 326 /* If found - let it be probed in normal way. */ 327 if (found) 328 continue; 329 /* If not - create it from table info. */ 330 child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0); 331 if (child == NULL) { 332 printf("%s: can't add child\n", __func__); 333 continue; 334 } 335 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 336 HPET_MEM_WIDTH); 337 } 338} 339 340static int 341hpet_probe(device_t dev) 342{ 343 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 344 345 if (acpi_disabled("hpet")) 346 return (ENXIO); 347 if (acpi_get_handle(dev) != NULL && 348 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 349 return (ENXIO); 350 351 device_set_desc(dev, "High Precision Event Timer"); 352 return (0); 353} 354 355static int 356hpet_attach(device_t dev) 357{ 358 struct hpet_softc *sc; 359 struct hpet_timer *t; 360 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 361 int pcpu_master; 362 static int maxhpetet = 0; 363 uint32_t val, val2, cvectors, dvectors; 364 uint16_t vendor, rev; 365 366 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 367 368 sc = device_get_softc(dev); 369 sc->dev = dev; 370 sc->handle = acpi_get_handle(dev); 371 372 sc->mem_rid = 0; 373 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 374 RF_ACTIVE); 375 if (sc->mem_res == NULL) 376 return (ENOMEM); 377 378 /* Validate that we can access the whole region. */ 379 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 380 device_printf(dev, "memory region width %ld too small\n", 381 rman_get_size(sc->mem_res)); 382 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 383 return (ENXIO); 384 } 385 386 /* Be sure timer is enabled. */ 387 hpet_enable(sc); 388 389 /* Read basic statistics about the timer. */ 390 val = bus_read_4(sc->mem_res, HPET_PERIOD); 391 if (val == 0) { 392 device_printf(dev, "invalid period\n"); 393 hpet_disable(sc); 394 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 395 return (ENXIO); 396 } 397 398 sc->freq = (1000000000000000LL + val / 2) / val; 399 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 400 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 401 rev = sc->caps & HPET_CAP_REV_ID; 402 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 403 /* 404 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 405 * Specification and provides an off by one number 406 * of timers/comparators. 407 * Additionally, they use unregistered value in VENDOR_ID field. 408 */ 409 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 410 num_timers--; 411 sc->num_timers = num_timers; 412 if (bootverbose) { 413 device_printf(dev, 414 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 415 vendor, rev, sc->freq, 416 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 417 num_timers, 418 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 419 } 420 for (i = 0; i < num_timers; i++) { 421 t = &sc->t[i]; 422 t->sc = sc; 423 t->num = i; 424 t->mode = 0; 425 t->intr_rid = -1; 426 t->irq = -1; 427 t->pcpu_cpu = -1; 428 t->pcpu_misrouted = 0; 429 t->pcpu_master = -1; 430 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 431 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 432 if (bootverbose) { 433 device_printf(dev, 434 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 435 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 436 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 437 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 438 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 439 } 440 } 441 if (testenv("debug.acpi.hpet_test")) 442 hpet_test(sc); 443 /* 444 * Don't attach if the timer never increments. Since the spec 445 * requires it to be at least 10 MHz, it has to change in 1 us. 446 */ 447 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 448 DELAY(1); 449 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 450 if (val == val2) { 451 device_printf(dev, "HPET never increments, disabling\n"); 452 hpet_disable(sc); 453 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 454 return (ENXIO); 455 } 456 /* Announce first HPET as timecounter. */ 457 if (device_get_unit(dev) == 0) { 458 sc->tc.tc_get_timecount = hpet_get_timecount, 459 sc->tc.tc_counter_mask = ~0u, 460 sc->tc.tc_name = "HPET", 461 sc->tc.tc_quality = 900, 462 sc->tc.tc_frequency = sc->freq; 463 sc->tc.tc_priv = sc; 464 tc_init(&sc->tc); 465 } 466 /* If not disabled - setup and announce event timers. */ 467 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 468 "clock", &i) == 0 && i == 0) 469 return (0); 470 471 /* Check whether we can and want legacy routing. */ 472 sc->legacy_route = 0; 473 resource_int_value(device_get_name(dev), device_get_unit(dev), 474 "legacy_route", &sc->legacy_route); 475 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 476 sc->legacy_route = 0; 477 if (sc->legacy_route) { 478 sc->t[0].vectors = 0; 479 sc->t[1].vectors = 0; 480 } 481 482 /* Check what IRQs we want use. */ 483 /* By default allow any PCI IRQs. */ 484 sc->allowed_irqs = 0xffff0000; 485 /* 486 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 487 * Lower are also not always working for different reasons. 488 * SB800 fixed it, but seems do not implements level triggering 489 * properly, that makes it very unreliable - it freezes after any 490 * interrupt loss. Avoid legacy IRQs for AMD. 491 */ 492 if (vendor == HPET_VENDID_AMD) 493 sc->allowed_irqs = 0x00000000; 494 /* 495 * Neither QEMU nor VirtualBox report supported IRQs correctly. 496 * The only way to use HPET there is to specify IRQs manually 497 * and/or use legacy_route. Legacy_route mode work on both. 498 */ 499 if (vm_guest) 500 sc->allowed_irqs = 0x00000000; 501 /* Let user override. */ 502 resource_int_value(device_get_name(dev), device_get_unit(dev), 503 "allowed_irqs", &sc->allowed_irqs); 504 505 /* Get how much per-CPU timers we should try to provide. */ 506 sc->per_cpu = 1; 507 resource_int_value(device_get_name(dev), device_get_unit(dev), 508 "per_cpu", &sc->per_cpu); 509 510 num_msi = 0; 511 sc->useirq = 0; 512 /* Find IRQ vectors for all timers. */ 513 cvectors = sc->allowed_irqs & 0xffff0000; 514 dvectors = sc->allowed_irqs & 0x0000ffff; 515 if (sc->legacy_route) 516 dvectors &= 0x0000fefe; 517 for (i = 0; i < num_timers; i++) { 518 t = &sc->t[i]; 519 if (sc->legacy_route && i < 2) 520 t->irq = (i == 0) ? 0 : 8; 521#ifdef DEV_APIC 522 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 523 if ((j = PCIB_ALLOC_MSIX( 524 device_get_parent(device_get_parent(dev)), dev, 525 &t->irq))) { 526 device_printf(dev, 527 "Can't allocate interrupt for t%d.\n", j); 528 } 529 } 530#endif 531 else if (dvectors & t->vectors) { 532 t->irq = ffs(dvectors & t->vectors) - 1; 533 dvectors &= ~(1 << t->irq); 534 } 535 if (t->irq >= 0) { 536 if (!(t->intr_res = 537 bus_alloc_resource(dev, SYS_RES_IRQ, &t->intr_rid, 538 t->irq, t->irq, 1, RF_ACTIVE))) { 539 t->irq = -1; 540 device_printf(dev, 541 "Can't map interrupt for t%d.\n", i); 542 } else if ((bus_setup_intr(dev, t->intr_res, 543 INTR_MPSAFE | INTR_TYPE_CLK, 544 (driver_filter_t *)hpet_intr_single, NULL, 545 t, &t->intr_handle))) { 546 t->irq = -1; 547 device_printf(dev, 548 "Can't setup interrupt for t%d.\n", i); 549 } else { 550 bus_describe_intr(dev, t->intr_res, 551 t->intr_handle, "t%d", i); 552 num_msi++; 553 } 554 } 555 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 556 cvectors &= t->vectors; 557 sc->useirq |= (1 << i); 558 } 559 } 560 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 561 sc->legacy_route = 0; 562 if (sc->legacy_route) 563 hpet_enable(sc); 564 /* Group timers for per-CPU operation. */ 565 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 566 num_percpu_t = num_percpu_et * mp_ncpus; 567 pcpu_master = 0; 568 cur_cpu = CPU_FIRST(); 569 for (i = 0; i < num_timers; i++) { 570 t = &sc->t[i]; 571 if (t->irq >= 0 && num_percpu_t > 0) { 572 if (cur_cpu == CPU_FIRST()) 573 pcpu_master = i; 574 t->pcpu_cpu = cur_cpu; 575 t->pcpu_master = pcpu_master; 576 sc->t[pcpu_master]. 577 pcpu_slaves[cur_cpu] = i; 578 bus_bind_intr(dev, t->intr_res, cur_cpu); 579 cur_cpu = CPU_NEXT(cur_cpu); 580 num_percpu_t--; 581 } else if (t->irq >= 0) 582 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 583 } 584 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 585 sc->irq = -1; 586 sc->intr_rid = -1; 587 /* If at least one timer needs legacy IRQ - setup it. */ 588 if (sc->useirq) { 589 j = i = fls(cvectors) - 1; 590 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 591 j--; 592 if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 593 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE))) 594 device_printf(dev,"Can't map interrupt.\n"); 595 else if ((bus_setup_intr(dev, sc->intr_res, 596 INTR_MPSAFE | INTR_TYPE_CLK, 597 (driver_filter_t *)hpet_intr, NULL, 598 sc, &sc->intr_handle))) { 599 device_printf(dev, "Can't setup interrupt.\n"); 600 } else { 601 sc->irq = rman_get_start(sc->intr_res); 602 /* Bind IRQ to BSP to avoid live migration. */ 603 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 604 } 605 } 606 /* Program and announce event timers. */ 607 for (i = 0; i < num_timers; i++) { 608 t = &sc->t[i]; 609 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 610 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 611 t->caps &= ~(HPET_TCNF_INT_TYPE); 612 t->caps |= HPET_TCNF_32MODE; 613 if (t->irq >= 0 && sc->legacy_route && i < 2) { 614 /* Legacy route doesn't need more configuration. */ 615 } else 616#ifdef DEV_APIC 617 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 618 uint64_t addr; 619 uint32_t data; 620 621 if (PCIB_MAP_MSI( 622 device_get_parent(device_get_parent(dev)), dev, 623 t->irq, &addr, &data) == 0) { 624 bus_write_4(sc->mem_res, 625 HPET_TIMER_FSB_ADDR(i), addr); 626 bus_write_4(sc->mem_res, 627 HPET_TIMER_FSB_VAL(i), data); 628 t->caps |= HPET_TCNF_FSB_EN; 629 } else 630 t->irq = -2; 631 } else 632#endif 633 if (t->irq >= 0) 634 t->caps |= (t->irq << 9); 635 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 636 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 637 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 638 /* Skip event timers without set up IRQ. */ 639 if (t->irq < 0 && 640 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 641 continue; 642 /* Announce the reset. */ 643 if (maxhpetet == 0) 644 t->et.et_name = "HPET"; 645 else { 646 sprintf(t->name, "HPET%d", maxhpetet); 647 t->et.et_name = t->name; 648 } 649 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 650 t->et.et_quality = 450; 651 if (t->pcpu_master >= 0) { 652 t->et.et_flags |= ET_FLAGS_PERCPU; 653 t->et.et_quality += 100; 654 } 655 if ((t->caps & HPET_TCAP_PER_INT) == 0) 656 t->et.et_quality -= 10; 657 t->et.et_frequency = sc->freq; 658 t->et.et_min_period.sec = 0; 659 t->et.et_min_period.frac = 0x00008000LLU << 32; 660 t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq; 661 t->et.et_max_period.frac = 662 ((0xfffffffeLLU << 32) / sc->freq) << 32; 663 t->et.et_start = hpet_start; 664 t->et.et_stop = hpet_stop; 665 t->et.et_priv = &sc->t[i]; 666 if (t->pcpu_master < 0 || t->pcpu_master == i) { 667 et_register(&t->et); 668 maxhpetet++; 669 } 670 } 671 return (0); 672} 673 674static int 675hpet_detach(device_t dev) 676{ 677 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 678 679 /* XXX Without a tc_remove() function, we can't detach. */ 680 return (EBUSY); 681} 682 683static int 684hpet_suspend(device_t dev) 685{ 686 struct hpet_softc *sc; 687 688 /* 689 * Disable the timer during suspend. The timer will not lose 690 * its state in S1 or S2, but we are required to disable 691 * it. 692 */ 693 sc = device_get_softc(dev); 694 hpet_disable(sc); 695 696 return (0); 697} 698 699static int 700hpet_resume(device_t dev) 701{ 702 struct hpet_softc *sc; 703 struct hpet_timer *t; 704 int i; 705 706 /* Re-enable the timer after a resume to keep the clock advancing. */ 707 sc = device_get_softc(dev); 708 hpet_enable(sc); 709 /* Restart event timers that were running on suspend. */ 710 for (i = 0; i < sc->num_timers; i++) { 711 t = &sc->t[i]; 712#ifdef DEV_APIC 713 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 714 uint64_t addr; 715 uint32_t data; 716 717 if (PCIB_MAP_MSI( 718 device_get_parent(device_get_parent(dev)), dev, 719 t->irq, &addr, &data) == 0) { 720 bus_write_4(sc->mem_res, 721 HPET_TIMER_FSB_ADDR(i), addr); 722 bus_write_4(sc->mem_res, 723 HPET_TIMER_FSB_VAL(i), data); 724 } 725 } 726#endif 727 if (t->mode == 0) 728 continue; 729 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 730 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 731 t->caps |= HPET_TCNF_TYPE; 732 t->next += t->div; 733 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 734 t->caps | HPET_TCNF_VAL_SET); 735 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 736 t->next); 737 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 738 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 739 t->div); 740 } else { 741 t->next += sc->freq / 1024; 742 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 743 t->next); 744 } 745 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 746 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 747 } 748 return (0); 749} 750 751/* Print some basic latency/rate information to assist in debugging. */ 752static void 753hpet_test(struct hpet_softc *sc) 754{ 755 int i; 756 uint32_t u1, u2; 757 struct bintime b0, b1, b2; 758 struct timespec ts; 759 760 binuptime(&b0); 761 binuptime(&b0); 762 binuptime(&b1); 763 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 764 for (i = 1; i < 1000; i++) 765 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 766 binuptime(&b2); 767 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 768 769 bintime_sub(&b2, &b1); 770 bintime_sub(&b1, &b0); 771 bintime_sub(&b2, &b1); 772 bintime2timespec(&b2, &ts); 773 774 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 775 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 776 777 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 778} 779 780#ifdef DEV_APIC 781static int 782hpet_remap_intr(device_t dev, device_t child, u_int irq) 783{ 784 struct hpet_softc *sc = device_get_softc(dev); 785 struct hpet_timer *t; 786 uint64_t addr; 787 uint32_t data; 788 int error, i; 789 790 for (i = 0; i < sc->num_timers; i++) { 791 t = &sc->t[i]; 792 if (t->irq != irq) 793 continue; 794 error = PCIB_MAP_MSI( 795 device_get_parent(device_get_parent(dev)), dev, 796 irq, &addr, &data); 797 if (error) 798 return (error); 799 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 800 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 801 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 802 hpet_enable(sc); 803 return (0); 804 } 805 return (ENOENT); 806} 807#endif 808 809static device_method_t hpet_methods[] = { 810 /* Device interface */ 811 DEVMETHOD(device_identify, hpet_identify), 812 DEVMETHOD(device_probe, hpet_probe), 813 DEVMETHOD(device_attach, hpet_attach), 814 DEVMETHOD(device_detach, hpet_detach), 815 DEVMETHOD(device_suspend, hpet_suspend), 816 DEVMETHOD(device_resume, hpet_resume), 817 818#ifdef DEV_APIC 819 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 820#endif 821 822 {0, 0} 823}; 824 825static driver_t hpet_driver = { 826 "hpet", 827 hpet_methods, 828 sizeof(struct hpet_softc), 829}; 830 831DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 832MODULE_DEPEND(hpet, acpi, 1, 1, 1); 833