acpi_hpet.c revision 210298
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 210298 2010-07-20 15:48:29Z mav $"); 30 31#include "opt_acpi.h" 32#if defined(__amd64__) || defined(__ia64__) 33#define DEV_APIC 34#else 35#include "opt_apic.h" 36#endif 37#include <sys/param.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/proc.h> 42#include <sys/rman.h> 43#include <sys/time.h> 44#include <sys/smp.h> 45#include <sys/sysctl.h> 46#include <sys/timeet.h> 47#include <sys/timetc.h> 48 49#include <contrib/dev/acpica/include/acpi.h> 50#include <contrib/dev/acpica/include/accommon.h> 51 52#include <dev/acpica/acpivar.h> 53#include <dev/acpica/acpi_hpet.h> 54 55#ifdef DEV_APIC 56#include "pcib_if.h" 57#endif 58 59#define HPET_VENDID_AMD 0x4353 60#define HPET_VENDID_INTEL 0x8086 61 62ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 63 64static devclass_t hpet_devclass; 65 66/* ACPI CA debugging */ 67#define _COMPONENT ACPI_TIMER 68ACPI_MODULE_NAME("HPET") 69 70struct hpet_softc { 71 device_t dev; 72 int mem_rid; 73 int intr_rid; 74 int irq; 75 int useirq; 76 int legacy_route; 77 struct resource *mem_res; 78 struct resource *intr_res; 79 void *intr_handle; 80 ACPI_HANDLE handle; 81 uint64_t freq; 82 uint32_t caps; 83 struct timecounter tc; 84 struct hpet_timer { 85 struct eventtimer et; 86 struct hpet_softc *sc; 87 int num; 88 int mode; 89 int intr_rid; 90 int irq; 91 int pcpu_master; 92 int pcpu_slaves[MAXCPU]; 93 struct resource *intr_res; 94 void *intr_handle; 95 uint32_t caps; 96 uint32_t vectors; 97 uint32_t div; 98 uint32_t last; 99 char name[8]; 100 } t[32]; 101 int num_timers; 102}; 103 104static u_int hpet_get_timecount(struct timecounter *tc); 105static void hpet_test(struct hpet_softc *sc); 106 107static char *hpet_ids[] = { "PNP0103", NULL }; 108 109static u_int 110hpet_get_timecount(struct timecounter *tc) 111{ 112 struct hpet_softc *sc; 113 114 sc = tc->tc_priv; 115 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 116} 117 118static void 119hpet_enable(struct hpet_softc *sc) 120{ 121 uint32_t val; 122 123 val = bus_read_4(sc->mem_res, HPET_CONFIG); 124 if (sc->legacy_route) 125 val |= HPET_CNF_LEG_RT; 126 else 127 val &= ~HPET_CNF_LEG_RT; 128 val |= HPET_CNF_ENABLE; 129 bus_write_4(sc->mem_res, HPET_CONFIG, val); 130} 131 132static void 133hpet_disable(struct hpet_softc *sc) 134{ 135 uint32_t val; 136 137 val = bus_read_4(sc->mem_res, HPET_CONFIG); 138 val &= ~HPET_CNF_ENABLE; 139 bus_write_4(sc->mem_res, HPET_CONFIG, val); 140} 141 142static int 143hpet_start(struct eventtimer *et, 144 struct bintime *first, struct bintime *period) 145{ 146 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 147 struct hpet_timer *t; 148 struct hpet_softc *sc = mt->sc; 149 uint32_t fdiv; 150 151 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 152 if (period != NULL) { 153 t->mode = 1; 154 t->div = (sc->freq * (period->frac >> 32)) >> 32; 155 if (period->sec != 0) 156 t->div += sc->freq * period->sec; 157 } else { 158 t->mode = 2; 159 t->div = 0; 160 } 161 if (first != NULL) { 162 fdiv = (sc->freq * (first->frac >> 32)) >> 32; 163 if (first->sec != 0) 164 fdiv += sc->freq * first->sec; 165 } else 166 fdiv = t->div; 167 t->last = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 168 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 169 t->caps |= HPET_TCNF_TYPE; 170 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 171 t->caps | HPET_TCNF_VAL_SET); 172 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 173 t->last + fdiv); 174 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 175 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 176 t->div); 177 } else { 178 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 179 t->last + fdiv); 180 } 181 t->caps |= HPET_TCNF_INT_ENB; 182 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 183 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 184 return (0); 185} 186 187static int 188hpet_stop(struct eventtimer *et) 189{ 190 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 191 struct hpet_timer *t; 192 struct hpet_softc *sc = mt->sc; 193 194 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 195 t->mode = 0; 196 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 197 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 198 return (0); 199} 200 201static int 202hpet_intr_single(void *arg) 203{ 204 struct hpet_timer *t = (struct hpet_timer *)arg; 205 struct hpet_timer *mt; 206 struct hpet_softc *sc = t->sc; 207 uint32_t now; 208 209 if (t->mode == 1 && 210 (t->caps & HPET_TCAP_PER_INT) == 0) { 211 t->last += t->div; 212 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 213 if ((int32_t)(now - (t->last + t->div / 2)) > 0) 214 t->last = now - t->div / 2; 215 bus_write_4(sc->mem_res, 216 HPET_TIMER_COMPARATOR(t->num), t->last + t->div); 217 } else if (t->mode == 2) 218 t->mode = 0; 219 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 220 if (mt->et.et_active) 221 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 222 return (FILTER_HANDLED); 223} 224 225static int 226hpet_intr(void *arg) 227{ 228 struct hpet_softc *sc = (struct hpet_softc *)arg; 229 int i; 230 uint32_t val; 231 232 val = bus_read_4(sc->mem_res, HPET_ISR); 233 if (val) { 234 bus_write_4(sc->mem_res, HPET_ISR, val); 235 val &= sc->useirq; 236 for (i = 0; i < sc->num_timers; i++) { 237 if ((val & (1 << i)) == 0) 238 continue; 239 hpet_intr_single(&sc->t[i]); 240 } 241 return (FILTER_HANDLED); 242 } 243 return (FILTER_STRAY); 244} 245 246static ACPI_STATUS 247hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 248 void **status) 249{ 250 char **ids; 251 uint32_t id = (uint32_t)(uintptr_t)context; 252 uint32_t uid = 0; 253 254 for (ids = hpet_ids; *ids != NULL; ids++) { 255 if (acpi_MatchHid(handle, *ids)) 256 break; 257 } 258 if (*ids == NULL) 259 return (AE_OK); 260 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 261 id == uid) 262 *((int *)status) = 1; 263 return (AE_OK); 264} 265 266/* Discover the HPET via the ACPI table of the same name. */ 267static void 268hpet_identify(driver_t *driver, device_t parent) 269{ 270 ACPI_TABLE_HPET *hpet; 271 ACPI_STATUS status; 272 device_t child; 273 int i, found; 274 275 /* Only one HPET device can be added. */ 276 if (devclass_get_device(hpet_devclass, 0)) 277 return; 278 for (i = 1; ; i++) { 279 /* Search for HPET table. */ 280 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 281 if (ACPI_FAILURE(status)) 282 return; 283 /* Search for HPET device with same ID. */ 284 found = 0; 285 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 286 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 287 /* If found - let it be probed in normal way. */ 288 if (found) 289 continue; 290 /* If not - create it from table info. */ 291 child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0); 292 if (child == NULL) { 293 printf("%s: can't add child\n", __func__); 294 continue; 295 } 296 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 297 HPET_MEM_WIDTH); 298 } 299} 300 301static int 302hpet_probe(device_t dev) 303{ 304 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 305 306 if (acpi_disabled("hpet")) 307 return (ENXIO); 308 if (acpi_get_handle(dev) != NULL && 309 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 310 return (ENXIO); 311 312 device_set_desc(dev, "High Precision Event Timer"); 313 return (0); 314} 315 316static int 317hpet_attach(device_t dev) 318{ 319 struct hpet_softc *sc; 320 struct hpet_timer *t; 321 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 322 int pcpu_master; 323 static int maxhpetet = 0; 324 uint32_t val, val2, cvectors; 325 uint16_t vendor, rev; 326 327 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 328 329 sc = device_get_softc(dev); 330 sc->dev = dev; 331 sc->handle = acpi_get_handle(dev); 332 333 sc->mem_rid = 0; 334 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 335 RF_ACTIVE); 336 if (sc->mem_res == NULL) 337 return (ENOMEM); 338 339 /* Validate that we can access the whole region. */ 340 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 341 device_printf(dev, "memory region width %ld too small\n", 342 rman_get_size(sc->mem_res)); 343 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 344 return (ENXIO); 345 } 346 347 /* Be sure timer is enabled. */ 348 hpet_enable(sc); 349 350 /* Read basic statistics about the timer. */ 351 val = bus_read_4(sc->mem_res, HPET_PERIOD); 352 if (val == 0) { 353 device_printf(dev, "invalid period\n"); 354 hpet_disable(sc); 355 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 356 return (ENXIO); 357 } 358 359 sc->freq = (1000000000000000LL + val / 2) / val; 360 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 361 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 362 rev = sc->caps & HPET_CAP_REV_ID; 363 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 364 /* 365 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 366 * Specification and provides an off by one number 367 * of timers/comparators. 368 * Additionally, they use unregistered value in VENDOR_ID field. 369 */ 370 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 371 num_timers--; 372 sc->num_timers = num_timers; 373 if (bootverbose) { 374 device_printf(dev, 375 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 376 vendor, rev, sc->freq, 377 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 378 num_timers, 379 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 380 } 381 for (i = 0; i < num_timers; i++) { 382 t = &sc->t[i]; 383 t->sc = sc; 384 t->num = i; 385 t->mode = 0; 386 t->intr_rid = -1; 387 t->irq = -1; 388 t->pcpu_master = -1; 389 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 390 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 391 if (bootverbose) { 392 device_printf(dev, 393 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 394 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 395 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 396 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 397 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 398 } 399 } 400 if (testenv("debug.acpi.hpet_test")) 401 hpet_test(sc); 402 /* 403 * Don't attach if the timer never increments. Since the spec 404 * requires it to be at least 10 MHz, it has to change in 1 us. 405 */ 406 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 407 DELAY(1); 408 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 409 if (val == val2) { 410 device_printf(dev, "HPET never increments, disabling\n"); 411 hpet_disable(sc); 412 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 413 return (ENXIO); 414 } 415 /* Announce first HPET as timecounter. */ 416 if (device_get_unit(dev) == 0) { 417 sc->tc.tc_get_timecount = hpet_get_timecount, 418 sc->tc.tc_counter_mask = ~0u, 419 sc->tc.tc_name = "HPET", 420 sc->tc.tc_quality = 900, 421 sc->tc.tc_frequency = sc->freq; 422 sc->tc.tc_priv = sc; 423 tc_init(&sc->tc); 424 } 425 /* If not disabled - setup and announce event timers. */ 426 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 427 "clock", &i) == 0 && i == 0) 428 return (0); 429 430 /* Check whether we can and want legacy routing. */ 431 sc->legacy_route = 0; 432 resource_int_value(device_get_name(dev), device_get_unit(dev), 433 "legacy_route", &sc->legacy_route); 434 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 435 sc->legacy_route = 0; 436 if (sc->legacy_route) { 437 sc->t[0].vectors = 0; 438 sc->t[1].vectors = 0; 439 } 440 441 num_msi = 0; 442 sc->useirq = 0; 443 /* Find common legacy IRQ vectors for all timers. */ 444 cvectors = 0xffff0000; 445 /* 446 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 447 * Lower are also not always working for different reasons. 448 * SB800 fixed it, but seems do not implements level triggering 449 * properly, that makes it very unreliable - it freezes after any 450 * interrupt loss. Avoid legacy IRQs for AMD. 451 */ 452 if (vendor == HPET_VENDID_AMD) 453 cvectors = 0x00000000; 454 for (i = 0; i < num_timers; i++) { 455 t = &sc->t[i]; 456 if (sc->legacy_route && i < 2) 457 t->irq = (i == 0) ? 0 : 8; 458#ifdef DEV_APIC 459 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 460 if ((j = PCIB_ALLOC_MSIX( 461 device_get_parent(device_get_parent(dev)), dev, 462 &t->irq))) { 463 device_printf(dev, 464 "Can't allocate interrupt for t%d.\n", j); 465 } 466 } 467#endif 468 if (t->irq >= 0) { 469 if (!(t->intr_res = 470 bus_alloc_resource(dev, SYS_RES_IRQ, &t->intr_rid, 471 t->irq, t->irq, 1, RF_ACTIVE))) { 472 t->irq = -1; 473 device_printf(dev, 474 "Can't map interrupt for t%d.\n", i); 475 } else if ((bus_setup_intr(dev, t->intr_res, 476 INTR_MPSAFE | INTR_TYPE_CLK, 477 (driver_filter_t *)hpet_intr_single, NULL, 478 t, &t->intr_handle))) { 479 t->irq = -1; 480 device_printf(dev, 481 "Can't setup interrupt for t%d.\n", i); 482 } else { 483 bus_describe_intr(dev, t->intr_res, 484 t->intr_handle, "t%d", i); 485 num_msi++; 486 } 487 } 488 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 489 cvectors &= t->vectors; 490 sc->useirq |= (1 << i); 491 } 492 } 493 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 494 sc->legacy_route = 0; 495 if (sc->legacy_route) 496 hpet_enable(sc); 497 /* Group timers for per-CPU operation. */ 498 num_percpu_et = min(num_msi / mp_ncpus, 2); 499 num_percpu_t = num_percpu_et * mp_ncpus; 500 pcpu_master = 0; 501 cur_cpu = CPU_FIRST(); 502 for (i = 0; i < num_timers; i++) { 503 t = &sc->t[i]; 504 if (t->irq >= 0 && num_percpu_t > 0) { 505 if (cur_cpu == CPU_FIRST()) 506 pcpu_master = i; 507 t->pcpu_master = pcpu_master; 508 sc->t[pcpu_master]. 509 pcpu_slaves[cur_cpu] = i; 510 bus_bind_intr(dev, t->intr_res, cur_cpu); 511 cur_cpu = CPU_NEXT(cur_cpu); 512 num_percpu_t--; 513 } 514 } 515 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 516 sc->irq = -1; 517 sc->intr_rid = -1; 518 /* If at least one timer needs legacy IRQ - setup it. */ 519 if (sc->useirq) { 520 j = i = fls(cvectors) - 1; 521 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 522 j--; 523 if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 524 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE))) 525 device_printf(dev,"Can't map interrupt.\n"); 526 else if ((bus_setup_intr(dev, sc->intr_res, 527 INTR_MPSAFE | INTR_TYPE_CLK, 528 (driver_filter_t *)hpet_intr, NULL, 529 sc, &sc->intr_handle))) { 530 device_printf(dev, "Can't setup interrupt.\n"); 531 } else { 532 sc->irq = rman_get_start(sc->intr_res); 533 /* Bind IRQ to BSP to avoid live migration. */ 534 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 535 } 536 } 537 /* Program and announce event timers. */ 538 for (i = 0; i < num_timers; i++) { 539 t = &sc->t[i]; 540 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 541 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 542 t->caps &= ~(HPET_TCNF_INT_TYPE); 543 t->caps |= HPET_TCNF_32MODE; 544 if (t->irq >= 0 && sc->legacy_route && i < 2) { 545 /* Legacy route doesn't need more configuration. */ 546 } else 547#ifdef DEV_APIC 548 if (t->irq >= 0) { 549 uint64_t addr; 550 uint32_t data; 551 552 if (PCIB_MAP_MSI( 553 device_get_parent(device_get_parent(dev)), dev, 554 t->irq, &addr, &data) == 0) { 555 bus_write_4(sc->mem_res, 556 HPET_TIMER_FSB_ADDR(i), addr); 557 bus_write_4(sc->mem_res, 558 HPET_TIMER_FSB_VAL(i), data); 559 t->caps |= HPET_TCNF_FSB_EN; 560 } else 561 t->irq = -2; 562 } else 563#endif 564 if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 565 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 566 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 567 /* Skip event timers without set up IRQ. */ 568 if (t->irq < 0 && 569 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 570 continue; 571 /* Announce the reset. */ 572 if (maxhpetet == 0) 573 t->et.et_name = "HPET"; 574 else { 575 sprintf(t->name, "HPET%d", maxhpetet); 576 t->et.et_name = t->name; 577 } 578 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 579 t->et.et_quality = 450; 580 if (t->pcpu_master >= 0) { 581 t->et.et_flags |= ET_FLAGS_PERCPU; 582 t->et.et_quality += 100; 583 } 584 if ((t->caps & HPET_TCAP_PER_INT) == 0) 585 t->et.et_quality -= 10; 586 t->et.et_frequency = sc->freq; 587 t->et.et_min_period.sec = 0; 588 t->et.et_min_period.frac = 0x00004000LLU << 32; 589 t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq; 590 t->et.et_max_period.frac = 591 ((0xfffffffeLLU << 32) / sc->freq) << 32; 592 t->et.et_start = hpet_start; 593 t->et.et_stop = hpet_stop; 594 t->et.et_priv = &sc->t[i]; 595 if (t->pcpu_master < 0 || t->pcpu_master == i) { 596 et_register(&t->et); 597 maxhpetet++; 598 } 599 } 600 return (0); 601} 602 603static int 604hpet_detach(device_t dev) 605{ 606 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 607 608 /* XXX Without a tc_remove() function, we can't detach. */ 609 return (EBUSY); 610} 611 612static int 613hpet_suspend(device_t dev) 614{ 615 struct hpet_softc *sc; 616 617 /* 618 * Disable the timer during suspend. The timer will not lose 619 * its state in S1 or S2, but we are required to disable 620 * it. 621 */ 622 sc = device_get_softc(dev); 623 hpet_disable(sc); 624 625 return (0); 626} 627 628static int 629hpet_resume(device_t dev) 630{ 631 struct hpet_softc *sc; 632 struct hpet_timer *t; 633 int i; 634 635 /* Re-enable the timer after a resume to keep the clock advancing. */ 636 sc = device_get_softc(dev); 637 hpet_enable(sc); 638 /* Restart event timers that were running on suspend. */ 639 for (i = 0; i < sc->num_timers; i++) { 640 t = &sc->t[i]; 641#ifdef DEV_APIC 642 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 643 uint64_t addr; 644 uint32_t data; 645 646 if (PCIB_MAP_MSI( 647 device_get_parent(device_get_parent(dev)), dev, 648 t->irq, &addr, &data) == 0) { 649 bus_write_4(sc->mem_res, 650 HPET_TIMER_FSB_ADDR(i), addr); 651 bus_write_4(sc->mem_res, 652 HPET_TIMER_FSB_VAL(i), data); 653 } 654 } 655#endif 656 if (t->mode == 0) 657 continue; 658 t->last = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 659 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 660 t->caps |= HPET_TCNF_TYPE; 661 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 662 t->caps | HPET_TCNF_VAL_SET); 663 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 664 t->last + t->div); 665 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 666 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 667 t->div); 668 } else { 669 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 670 t->last + sc->freq / 1024); 671 } 672 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 673 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 674 } 675 return (0); 676} 677 678/* Print some basic latency/rate information to assist in debugging. */ 679static void 680hpet_test(struct hpet_softc *sc) 681{ 682 int i; 683 uint32_t u1, u2; 684 struct bintime b0, b1, b2; 685 struct timespec ts; 686 687 binuptime(&b0); 688 binuptime(&b0); 689 binuptime(&b1); 690 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 691 for (i = 1; i < 1000; i++) 692 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 693 binuptime(&b2); 694 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 695 696 bintime_sub(&b2, &b1); 697 bintime_sub(&b1, &b0); 698 bintime_sub(&b2, &b1); 699 bintime2timespec(&b2, &ts); 700 701 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 702 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 703 704 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 705} 706 707#ifdef DEV_APIC 708static int 709hpet_remap_intr(device_t dev, device_t child, u_int irq) 710{ 711 struct hpet_softc *sc = device_get_softc(dev); 712 struct hpet_timer *t; 713 uint64_t addr; 714 uint32_t data; 715 int error, i; 716 717 for (i = 0; i < sc->num_timers; i++) { 718 t = &sc->t[i]; 719 if (t->irq != irq) 720 continue; 721 error = PCIB_MAP_MSI( 722 device_get_parent(device_get_parent(dev)), dev, 723 irq, &addr, &data); 724 if (error) 725 return (error); 726 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 727 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 728 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 729 hpet_enable(sc); 730 return (0); 731 } 732 return (ENOENT); 733} 734#endif 735 736static device_method_t hpet_methods[] = { 737 /* Device interface */ 738 DEVMETHOD(device_identify, hpet_identify), 739 DEVMETHOD(device_probe, hpet_probe), 740 DEVMETHOD(device_attach, hpet_attach), 741 DEVMETHOD(device_detach, hpet_detach), 742 DEVMETHOD(device_suspend, hpet_suspend), 743 DEVMETHOD(device_resume, hpet_resume), 744 745#ifdef DEV_APIC 746 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 747#endif 748 749 {0, 0} 750}; 751 752static driver_t hpet_driver = { 753 "hpet", 754 hpet_methods, 755 sizeof(struct hpet_softc), 756}; 757 758DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 759MODULE_DEPEND(hpet, acpi, 1, 1, 1); 760