acpi_hpet.c revision 209990
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 209990 2010-07-13 12:46:06Z mav $"); 30 31#include "opt_acpi.h" 32#if defined(__amd64__) || defined(__ia64__) 33#define DEV_APIC 34#else 35#include "opt_apic.h" 36#endif 37#include <sys/param.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/proc.h> 42#include <sys/rman.h> 43#include <sys/time.h> 44#include <sys/smp.h> 45#include <sys/sysctl.h> 46#include <sys/timeet.h> 47#include <sys/timetc.h> 48 49#include <contrib/dev/acpica/include/acpi.h> 50#include <contrib/dev/acpica/include/accommon.h> 51 52#include <dev/acpica/acpivar.h> 53#include <dev/acpica/acpi_hpet.h> 54 55#ifdef DEV_APIC 56#include "pcib_if.h" 57#endif 58 59#define HPET_VENDID_AMD 0x4353 60#define HPET_VENDID_INTEL 0x8086 61 62ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 63 64static devclass_t hpet_devclass; 65 66/* ACPI CA debugging */ 67#define _COMPONENT ACPI_TIMER 68ACPI_MODULE_NAME("HPET") 69 70struct hpet_softc { 71 device_t dev; 72 int mem_rid; 73 int intr_rid; 74 int irq; 75 int useirq; 76 int legacy_route; 77 struct resource *mem_res; 78 struct resource *intr_res; 79 void *intr_handle; 80 ACPI_HANDLE handle; 81 uint64_t freq; 82 uint32_t caps; 83 struct timecounter tc; 84 struct hpet_timer { 85 struct eventtimer et; 86 struct hpet_softc *sc; 87 int num; 88 int mode; 89 int intr_rid; 90 int irq; 91 int pcpu_master; 92 int pcpu_slaves[MAXCPU]; 93 struct resource *intr_res; 94 void *intr_handle; 95 uint32_t caps; 96 uint32_t vectors; 97 uint32_t div; 98 uint32_t last; 99 char name[8]; 100 } t[32]; 101 int num_timers; 102}; 103 104static u_int hpet_get_timecount(struct timecounter *tc); 105static void hpet_test(struct hpet_softc *sc); 106 107static char *hpet_ids[] = { "PNP0103", NULL }; 108 109static u_int 110hpet_get_timecount(struct timecounter *tc) 111{ 112 struct hpet_softc *sc; 113 114 sc = tc->tc_priv; 115 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 116} 117 118static void 119hpet_enable(struct hpet_softc *sc) 120{ 121 uint32_t val; 122 123 val = bus_read_4(sc->mem_res, HPET_CONFIG); 124 if (sc->legacy_route) 125 val |= HPET_CNF_LEG_RT; 126 else 127 val &= ~HPET_CNF_LEG_RT; 128 val |= HPET_CNF_ENABLE; 129 bus_write_4(sc->mem_res, HPET_CONFIG, val); 130} 131 132static void 133hpet_disable(struct hpet_softc *sc) 134{ 135 uint32_t val; 136 137 val = bus_read_4(sc->mem_res, HPET_CONFIG); 138 val &= ~HPET_CNF_ENABLE; 139 bus_write_4(sc->mem_res, HPET_CONFIG, val); 140} 141 142static int 143hpet_start(struct eventtimer *et, 144 struct bintime *first, struct bintime *period) 145{ 146 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 147 struct hpet_timer *t; 148 struct hpet_softc *sc = mt->sc; 149 uint32_t fdiv; 150 151 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 152 if (period != NULL) { 153 t->mode = 1; 154 t->div = (sc->freq * (period->frac >> 32)) >> 32; 155 if (period->sec != 0) 156 t->div += sc->freq * period->sec; 157 if (first == NULL) 158 first = period; 159 } else { 160 t->mode = 2; 161 t->div = 0; 162 } 163 fdiv = (sc->freq * (first->frac >> 32)) >> 32; 164 if (first->sec != 0) 165 fdiv += sc->freq * first->sec; 166 t->last = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 167 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 168 t->caps |= HPET_TCNF_TYPE; 169 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 170 t->caps | HPET_TCNF_VAL_SET); 171 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 172 t->last + fdiv); 173 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 174 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 175 t->div); 176 } else { 177 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 178 t->last + fdiv); 179 } 180 t->caps |= HPET_TCNF_INT_ENB; 181 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 182 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 183 return (0); 184} 185 186static int 187hpet_stop(struct eventtimer *et) 188{ 189 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 190 struct hpet_timer *t; 191 struct hpet_softc *sc = mt->sc; 192 193 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 194 t->mode = 0; 195 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 196 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 197 return (0); 198} 199 200static int 201hpet_intr_single(void *arg) 202{ 203 struct hpet_timer *t = (struct hpet_timer *)arg; 204 struct hpet_timer *mt; 205 struct hpet_softc *sc = t->sc; 206 uint32_t now; 207 208 if (t->mode == 1 && 209 (t->caps & HPET_TCAP_PER_INT) == 0) { 210 t->last += t->div; 211 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 212 if ((int32_t)(now - (t->last + t->div / 2)) > 0) 213 t->last = now - t->div / 2; 214 bus_write_4(sc->mem_res, 215 HPET_TIMER_COMPARATOR(t->num), t->last + t->div); 216 } else if (t->mode == 2) 217 t->mode = 0; 218 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 219 if (mt->et.et_active) 220 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 221 return (FILTER_HANDLED); 222} 223 224static int 225hpet_intr(void *arg) 226{ 227 struct hpet_softc *sc = (struct hpet_softc *)arg; 228 int i; 229 uint32_t val; 230 231 val = bus_read_4(sc->mem_res, HPET_ISR); 232 if (val) { 233 bus_write_4(sc->mem_res, HPET_ISR, val); 234 val &= sc->useirq; 235 for (i = 0; i < sc->num_timers; i++) { 236 if ((val & (1 << i)) == 0) 237 continue; 238 hpet_intr_single(&sc->t[i]); 239 } 240 return (FILTER_HANDLED); 241 } 242 return (FILTER_STRAY); 243} 244 245static ACPI_STATUS 246hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 247 void **status) 248{ 249 char **ids; 250 uint32_t id = (uint32_t)(uintptr_t)context; 251 uint32_t uid = 0; 252 253 for (ids = hpet_ids; *ids != NULL; ids++) { 254 if (acpi_MatchHid(handle, *ids)) 255 break; 256 } 257 if (*ids == NULL) 258 return (AE_OK); 259 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 260 id == uid) 261 *((int *)status) = 1; 262 return (AE_OK); 263} 264 265/* Discover the HPET via the ACPI table of the same name. */ 266static void 267hpet_identify(driver_t *driver, device_t parent) 268{ 269 ACPI_TABLE_HPET *hpet; 270 ACPI_STATUS status; 271 device_t child; 272 int i, found; 273 274 /* Only one HPET device can be added. */ 275 if (devclass_get_device(hpet_devclass, 0)) 276 return; 277 for (i = 1; ; i++) { 278 /* Search for HPET table. */ 279 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 280 if (ACPI_FAILURE(status)) 281 return; 282 /* Search for HPET device with same ID. */ 283 found = 0; 284 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 285 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 286 /* If found - let it be probed in normal way. */ 287 if (found) 288 continue; 289 /* If not - create it from table info. */ 290 child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0); 291 if (child == NULL) { 292 printf("%s: can't add child\n", __func__); 293 continue; 294 } 295 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 296 HPET_MEM_WIDTH); 297 } 298} 299 300static int 301hpet_probe(device_t dev) 302{ 303 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 304 305 if (acpi_disabled("hpet")) 306 return (ENXIO); 307 if (acpi_get_handle(dev) != NULL && 308 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 309 return (ENXIO); 310 311 device_set_desc(dev, "High Precision Event Timer"); 312 return (0); 313} 314 315static int 316hpet_attach(device_t dev) 317{ 318 struct hpet_softc *sc; 319 struct hpet_timer *t; 320 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 321 int pcpu_master; 322 static int maxhpetet = 0; 323 uint32_t val, val2, cvectors; 324 uint16_t vendor, rev; 325 326 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 327 328 sc = device_get_softc(dev); 329 sc->dev = dev; 330 sc->handle = acpi_get_handle(dev); 331 332 sc->mem_rid = 0; 333 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 334 RF_ACTIVE); 335 if (sc->mem_res == NULL) 336 return (ENOMEM); 337 338 /* Validate that we can access the whole region. */ 339 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 340 device_printf(dev, "memory region width %ld too small\n", 341 rman_get_size(sc->mem_res)); 342 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 343 return (ENXIO); 344 } 345 346 /* Be sure timer is enabled. */ 347 hpet_enable(sc); 348 349 /* Read basic statistics about the timer. */ 350 val = bus_read_4(sc->mem_res, HPET_PERIOD); 351 if (val == 0) { 352 device_printf(dev, "invalid period\n"); 353 hpet_disable(sc); 354 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 355 return (ENXIO); 356 } 357 358 sc->freq = (1000000000000000LL + val / 2) / val; 359 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 360 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 361 rev = sc->caps & HPET_CAP_REV_ID; 362 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 363 /* 364 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 365 * Specification and provides an off by one number 366 * of timers/comparators. 367 * Additionally, they use unregistered value in VENDOR_ID field. 368 */ 369 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 370 num_timers--; 371 sc->num_timers = num_timers; 372 if (bootverbose) { 373 device_printf(dev, 374 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 375 vendor, rev, sc->freq, 376 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 377 num_timers, 378 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 379 } 380 for (i = 0; i < num_timers; i++) { 381 t = &sc->t[i]; 382 t->sc = sc; 383 t->num = i; 384 t->mode = 0; 385 t->intr_rid = -1; 386 t->irq = -1; 387 t->pcpu_master = -1; 388 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 389 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 390 if (bootverbose) { 391 device_printf(dev, 392 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 393 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 394 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 395 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 396 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 397 } 398 } 399 if (testenv("debug.acpi.hpet_test")) 400 hpet_test(sc); 401 /* 402 * Don't attach if the timer never increments. Since the spec 403 * requires it to be at least 10 MHz, it has to change in 1 us. 404 */ 405 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 406 DELAY(1); 407 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 408 if (val == val2) { 409 device_printf(dev, "HPET never increments, disabling\n"); 410 hpet_disable(sc); 411 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 412 return (ENXIO); 413 } 414 /* Announce first HPET as timecounter. */ 415 if (device_get_unit(dev) == 0) { 416 sc->tc.tc_get_timecount = hpet_get_timecount, 417 sc->tc.tc_counter_mask = ~0u, 418 sc->tc.tc_name = "HPET", 419 sc->tc.tc_quality = 900, 420 sc->tc.tc_frequency = sc->freq; 421 sc->tc.tc_priv = sc; 422 tc_init(&sc->tc); 423 } 424 /* If not disabled - setup and announce event timers. */ 425 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 426 "clock", &i) == 0 && i == 0) 427 return (0); 428 429 /* Check whether we can and want legacy routing. */ 430 sc->legacy_route = 0; 431 resource_int_value(device_get_name(dev), device_get_unit(dev), 432 "legacy_route", &sc->legacy_route); 433 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 434 sc->legacy_route = 0; 435 if (sc->legacy_route) { 436 sc->t[0].vectors = 0; 437 sc->t[1].vectors = 0; 438 } 439 440 num_msi = 0; 441 sc->useirq = 0; 442 /* Find common legacy IRQ vectors for all timers. */ 443 cvectors = 0xffff0000; 444 /* 445 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 446 * Lower are also not always working for different reasons. 447 * SB800 fixed it, but seems do not implements level triggering 448 * properly, that makes it very unreliable - it freezes after any 449 * interrupt loss. Avoid legacy IRQs for AMD. 450 */ 451 if (vendor == HPET_VENDID_AMD) 452 cvectors = 0x00000000; 453 for (i = 0; i < num_timers; i++) { 454 t = &sc->t[i]; 455 if (sc->legacy_route && i < 2) 456 t->irq = (i == 0) ? 0 : 8; 457#ifdef DEV_APIC 458 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 459 if ((j = PCIB_ALLOC_MSIX( 460 device_get_parent(device_get_parent(dev)), dev, 461 &t->irq))) { 462 device_printf(dev, 463 "Can't allocate interrupt for t%d.\n", j); 464 } 465 } 466#endif 467 if (t->irq >= 0) { 468 if (!(t->intr_res = 469 bus_alloc_resource(dev, SYS_RES_IRQ, &t->intr_rid, 470 t->irq, t->irq, 1, RF_ACTIVE))) { 471 t->irq = -1; 472 device_printf(dev, 473 "Can't map interrupt for t%d.\n", i); 474 } else if ((bus_setup_intr(dev, t->intr_res, 475 INTR_MPSAFE | INTR_TYPE_CLK, 476 (driver_filter_t *)hpet_intr_single, NULL, 477 t, &t->intr_handle))) { 478 t->irq = -1; 479 device_printf(dev, 480 "Can't setup interrupt for t%d.\n", i); 481 } else { 482 bus_describe_intr(dev, t->intr_res, 483 t->intr_handle, "t%d", i); 484 num_msi++; 485 } 486 } 487 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 488 cvectors &= t->vectors; 489 sc->useirq |= (1 << i); 490 } 491 } 492 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 493 sc->legacy_route = 0; 494 if (sc->legacy_route) 495 hpet_enable(sc); 496 /* Group timers for per-CPU operation. */ 497 num_percpu_et = min(num_msi / mp_ncpus, 2); 498 num_percpu_t = num_percpu_et * mp_ncpus; 499 pcpu_master = 0; 500 cur_cpu = CPU_FIRST(); 501 for (i = 0; i < num_timers; i++) { 502 t = &sc->t[i]; 503 if (t->irq >= 0 && num_percpu_t > 0) { 504 if (cur_cpu == CPU_FIRST()) 505 pcpu_master = i; 506 t->pcpu_master = pcpu_master; 507 sc->t[pcpu_master]. 508 pcpu_slaves[cur_cpu] = i; 509 bus_bind_intr(dev, t->intr_res, cur_cpu); 510 cur_cpu = CPU_NEXT(cur_cpu); 511 num_percpu_t--; 512 } 513 } 514 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 515 sc->irq = -1; 516 sc->intr_rid = -1; 517 /* If at least one timer needs legacy IRQ - setup it. */ 518 if (sc->useirq) { 519 j = i = fls(cvectors) - 1; 520 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 521 j--; 522 if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 523 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE))) 524 device_printf(dev,"Can't map interrupt.\n"); 525 else if ((bus_setup_intr(dev, sc->intr_res, 526 INTR_MPSAFE | INTR_TYPE_CLK, 527 (driver_filter_t *)hpet_intr, NULL, 528 sc, &sc->intr_handle))) { 529 device_printf(dev, "Can't setup interrupt.\n"); 530 } else { 531 sc->irq = rman_get_start(sc->intr_res); 532 /* Bind IRQ to BSP to avoid live migration. */ 533 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 534 } 535 } 536 /* Program and announce event timers. */ 537 for (i = 0; i < num_timers; i++) { 538 t = &sc->t[i]; 539 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 540 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 541 t->caps &= ~(HPET_TCNF_INT_TYPE); 542 t->caps |= HPET_TCNF_32MODE; 543 if (t->irq >= 0 && sc->legacy_route && i < 2) { 544 /* Legacy route doesn't need more configuration. */ 545 } else 546#ifdef DEV_APIC 547 if (t->irq >= 0) { 548 uint64_t addr; 549 uint32_t data; 550 551 if (PCIB_MAP_MSI( 552 device_get_parent(device_get_parent(dev)), dev, 553 t->irq, &addr, &data) == 0) { 554 bus_write_4(sc->mem_res, 555 HPET_TIMER_FSB_ADDR(i), addr); 556 bus_write_4(sc->mem_res, 557 HPET_TIMER_FSB_VAL(i), data); 558 t->caps |= HPET_TCNF_FSB_EN; 559 } else 560 t->irq = -2; 561 } else 562#endif 563 if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 564 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 565 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 566 /* Skip event timers without set up IRQ. */ 567 if (t->irq < 0 && 568 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 569 continue; 570 /* Announce the reset. */ 571 if (maxhpetet == 0) 572 t->et.et_name = "HPET"; 573 else { 574 sprintf(t->name, "HPET%d", maxhpetet); 575 t->et.et_name = t->name; 576 } 577 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 578 t->et.et_quality = 450; 579 if (t->pcpu_master >= 0) { 580 t->et.et_flags |= ET_FLAGS_PERCPU; 581 t->et.et_quality += 100; 582 } 583 if ((t->caps & HPET_TCAP_PER_INT) == 0) 584 t->et.et_quality -= 10; 585 t->et.et_frequency = sc->freq; 586 t->et.et_start = hpet_start; 587 t->et.et_stop = hpet_stop; 588 t->et.et_priv = &sc->t[i]; 589 if (t->pcpu_master < 0 || t->pcpu_master == i) { 590 et_register(&t->et); 591 maxhpetet++; 592 } 593 } 594 return (0); 595} 596 597static int 598hpet_detach(device_t dev) 599{ 600 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 601 602 /* XXX Without a tc_remove() function, we can't detach. */ 603 return (EBUSY); 604} 605 606static int 607hpet_suspend(device_t dev) 608{ 609 struct hpet_softc *sc; 610 611 /* 612 * Disable the timer during suspend. The timer will not lose 613 * its state in S1 or S2, but we are required to disable 614 * it. 615 */ 616 sc = device_get_softc(dev); 617 hpet_disable(sc); 618 619 return (0); 620} 621 622static int 623hpet_resume(device_t dev) 624{ 625 struct hpet_softc *sc; 626 struct hpet_timer *t; 627 int i; 628 629 /* Re-enable the timer after a resume to keep the clock advancing. */ 630 sc = device_get_softc(dev); 631 hpet_enable(sc); 632 /* Restart event timers that were running on suspend. */ 633 for (i = 0; i < sc->num_timers; i++) { 634 t = &sc->t[i]; 635#ifdef DEV_APIC 636 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 637 uint64_t addr; 638 uint32_t data; 639 640 if (PCIB_MAP_MSI( 641 device_get_parent(device_get_parent(dev)), dev, 642 t->irq, &addr, &data) == 0) { 643 bus_write_4(sc->mem_res, 644 HPET_TIMER_FSB_ADDR(i), addr); 645 bus_write_4(sc->mem_res, 646 HPET_TIMER_FSB_VAL(i), data); 647 } 648 } 649#endif 650 if (t->mode == 0) 651 continue; 652 t->last = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 653 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 654 t->caps |= HPET_TCNF_TYPE; 655 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 656 t->caps | HPET_TCNF_VAL_SET); 657 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 658 t->last + t->div); 659 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 660 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 661 t->div); 662 } else { 663 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 664 t->last + sc->freq / 1024); 665 } 666 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 667 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 668 } 669 return (0); 670} 671 672/* Print some basic latency/rate information to assist in debugging. */ 673static void 674hpet_test(struct hpet_softc *sc) 675{ 676 int i; 677 uint32_t u1, u2; 678 struct bintime b0, b1, b2; 679 struct timespec ts; 680 681 binuptime(&b0); 682 binuptime(&b0); 683 binuptime(&b1); 684 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 685 for (i = 1; i < 1000; i++) 686 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 687 binuptime(&b2); 688 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 689 690 bintime_sub(&b2, &b1); 691 bintime_sub(&b1, &b0); 692 bintime_sub(&b2, &b1); 693 bintime2timespec(&b2, &ts); 694 695 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 696 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 697 698 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 699} 700 701#ifdef DEV_APIC 702static int 703hpet_remap_intr(device_t dev, device_t child, u_int irq) 704{ 705 struct hpet_softc *sc = device_get_softc(dev); 706 struct hpet_timer *t; 707 uint64_t addr; 708 uint32_t data; 709 int error, i; 710 711 for (i = 0; i < sc->num_timers; i++) { 712 t = &sc->t[i]; 713 if (t->irq != irq) 714 continue; 715 error = PCIB_MAP_MSI( 716 device_get_parent(device_get_parent(dev)), dev, 717 irq, &addr, &data); 718 if (error) 719 return (error); 720 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 721 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 722 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 723 hpet_enable(sc); 724 return (0); 725 } 726 return (ENOENT); 727} 728#endif 729 730static device_method_t hpet_methods[] = { 731 /* Device interface */ 732 DEVMETHOD(device_identify, hpet_identify), 733 DEVMETHOD(device_probe, hpet_probe), 734 DEVMETHOD(device_attach, hpet_attach), 735 DEVMETHOD(device_detach, hpet_detach), 736 DEVMETHOD(device_suspend, hpet_suspend), 737 DEVMETHOD(device_resume, hpet_resume), 738 739#ifdef DEV_APIC 740 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 741#endif 742 743 {0, 0} 744}; 745 746static driver_t hpet_driver = { 747 "hpet", 748 hpet_methods, 749 sizeof(struct hpet_softc), 750}; 751 752DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 753MODULE_DEPEND(hpet, acpi, 1, 1, 1); 754