acpi_hpet.c revision 209431
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 209431 2010-06-22 16:10:48Z mav $"); 29 30#include "opt_acpi.h" 31#if defined(__amd64__) || defined(__ia64__) 32#define DEV_APIC 33#else 34#include "opt_apic.h" 35#endif 36#include <sys/param.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/proc.h> 41#include <sys/rman.h> 42#include <sys/time.h> 43#include <sys/smp.h> 44#include <sys/sysctl.h> 45#include <sys/timeet.h> 46#include <sys/timetc.h> 47 48#include <contrib/dev/acpica/include/acpi.h> 49#include <contrib/dev/acpica/include/accommon.h> 50 51#include <dev/acpica/acpivar.h> 52#include <dev/acpica/acpi_hpet.h> 53 54#ifdef DEV_APIC 55#include "pcib_if.h" 56#endif 57 58#define HPET_VENDID_AMD 0x4353 59#define HPET_VENDID_INTEL 0x8086 60 61ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 62 63static devclass_t hpet_devclass; 64 65/* ACPI CA debugging */ 66#define _COMPONENT ACPI_TIMER 67ACPI_MODULE_NAME("HPET") 68 69struct hpet_softc { 70 device_t dev; 71 int mem_rid; 72 int intr_rid; 73 int irq; 74 int useirq; 75 struct resource *mem_res; 76 struct resource *intr_res; 77 void *intr_handle; 78 ACPI_HANDLE handle; 79 uint64_t freq; 80 struct timecounter tc; 81 struct hpet_timer { 82 struct eventtimer et; 83 struct hpet_softc *sc; 84 int num; 85 int mode; 86 int intr_rid; 87 int irq; 88 int pcpu_master; 89 int pcpu_slaves[MAXCPU]; 90 struct resource *intr_res; 91 void *intr_handle; 92 uint32_t caps; 93 uint32_t vectors; 94 uint32_t div; 95 uint32_t last; 96 char name[8]; 97 } t[32]; 98 int num_timers; 99}; 100 101static u_int hpet_get_timecount(struct timecounter *tc); 102static void hpet_test(struct hpet_softc *sc); 103 104static char *hpet_ids[] = { "PNP0103", NULL }; 105 106static u_int 107hpet_get_timecount(struct timecounter *tc) 108{ 109 struct hpet_softc *sc; 110 111 sc = tc->tc_priv; 112 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 113} 114 115static void 116hpet_enable(struct hpet_softc *sc) 117{ 118 uint32_t val; 119 120 val = bus_read_4(sc->mem_res, HPET_CONFIG); 121 val &= ~HPET_CNF_LEG_RT; 122 val |= HPET_CNF_ENABLE; 123 bus_write_4(sc->mem_res, HPET_CONFIG, val); 124} 125 126static void 127hpet_disable(struct hpet_softc *sc) 128{ 129 uint32_t val; 130 131 val = bus_read_4(sc->mem_res, HPET_CONFIG); 132 val &= ~HPET_CNF_ENABLE; 133 bus_write_4(sc->mem_res, HPET_CONFIG, val); 134} 135 136static int 137hpet_start(struct eventtimer *et, 138 struct bintime *first, struct bintime *period) 139{ 140 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 141 struct hpet_timer *t; 142 struct hpet_softc *sc = mt->sc; 143 uint32_t fdiv; 144 145 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 146 if (period != NULL) { 147 t->mode = 1; 148 t->div = (sc->freq * (period->frac >> 32)) >> 32; 149 if (period->sec != 0) 150 t->div += sc->freq * period->sec; 151 if (first == NULL) 152 first = period; 153 } else { 154 t->mode = 2; 155 t->div = 0; 156 } 157 fdiv = (sc->freq * (first->frac >> 32)) >> 32; 158 if (first->sec != 0) 159 fdiv += sc->freq * first->sec; 160 t->last = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 161 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 162 t->caps |= HPET_TCNF_TYPE; 163 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 164 t->caps | HPET_TCNF_VAL_SET); 165 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 166 t->last + fdiv); 167 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 168 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 169 t->div); 170 } else { 171 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 172 t->last + fdiv); 173 } 174 t->caps |= HPET_TCNF_INT_ENB; 175 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 176 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 177 return (0); 178} 179 180static int 181hpet_stop(struct eventtimer *et) 182{ 183 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 184 struct hpet_timer *t; 185 struct hpet_softc *sc = mt->sc; 186 187 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 188 t->mode = 0; 189 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 190 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 191 return (0); 192} 193 194static int 195hpet_intr_single(void *arg) 196{ 197 struct hpet_timer *t = (struct hpet_timer *)arg; 198 struct hpet_timer *mt; 199 struct hpet_softc *sc = t->sc; 200 uint32_t now; 201 202 if (t->mode == 1 && 203 (t->caps & HPET_TCAP_PER_INT) == 0) { 204 t->last += t->div; 205 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 206 if ((int32_t)(now - (t->last + t->div / 2)) > 0) 207 t->last = now - t->div / 2; 208 bus_write_4(sc->mem_res, 209 HPET_TIMER_COMPARATOR(t->num), t->last + t->div); 210 } else if (t->mode == 2) 211 t->mode = 0; 212 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 213 if (mt->et.et_active) { 214 mt->et.et_event_cb(&mt->et, 215 mt->et.et_arg ? mt->et.et_arg : curthread->td_intr_frame); 216 } 217 return (FILTER_HANDLED); 218} 219 220static int 221hpet_intr(void *arg) 222{ 223 struct hpet_softc *sc = (struct hpet_softc *)arg; 224 int i; 225 uint32_t val; 226 227 val = bus_read_4(sc->mem_res, HPET_ISR); 228 if (val) { 229 bus_write_4(sc->mem_res, HPET_ISR, val); 230 val &= sc->useirq; 231 for (i = 0; i < sc->num_timers; i++) { 232 if ((val & (1 << i)) == 0) 233 continue; 234 hpet_intr_single(&sc->t[i]); 235 } 236 return (FILTER_HANDLED); 237 } 238 return (FILTER_STRAY); 239} 240 241static ACPI_STATUS 242hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 243 void **status) 244{ 245 char **ids; 246 uint32_t id = (uint32_t)(uintptr_t)context; 247 uint32_t uid = 0; 248 249 for (ids = hpet_ids; *ids != NULL; ids++) { 250 if (acpi_MatchHid(handle, *ids)) 251 break; 252 } 253 if (*ids == NULL) 254 return (AE_OK); 255 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 256 id == uid) 257 *((int *)status) = 1; 258 return (AE_OK); 259} 260 261/* Discover the HPET via the ACPI table of the same name. */ 262static void 263hpet_identify(driver_t *driver, device_t parent) 264{ 265 ACPI_TABLE_HPET *hpet; 266 ACPI_STATUS status; 267 device_t child; 268 int i, found; 269 270 /* Only one HPET device can be added. */ 271 if (devclass_get_device(hpet_devclass, 0)) 272 return; 273 for (i = 1; ; i++) { 274 /* Search for HPET table. */ 275 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 276 if (ACPI_FAILURE(status)) 277 return; 278 /* Search for HPET device with same ID. */ 279 found = 0; 280 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 281 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 282 /* If found - let it be probed in normal way. */ 283 if (found) 284 continue; 285 /* If not - create it from table info. */ 286 child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0); 287 if (child == NULL) { 288 printf("%s: can't add child\n", __func__); 289 continue; 290 } 291 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 292 HPET_MEM_WIDTH); 293 } 294} 295 296static int 297hpet_probe(device_t dev) 298{ 299 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 300 301 if (acpi_disabled("hpet")) 302 return (ENXIO); 303 if (acpi_get_handle(dev) != NULL && 304 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 305 return (ENXIO); 306 307 device_set_desc(dev, "High Precision Event Timer"); 308 return (0); 309} 310 311static int 312hpet_attach(device_t dev) 313{ 314 struct hpet_softc *sc; 315 struct hpet_timer *t; 316 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 317 int pcpu_master; 318 static int maxhpetet = 0; 319 uint32_t val, val2, cvectors; 320 uint16_t vendor, rev; 321 322 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 323 324 sc = device_get_softc(dev); 325 sc->dev = dev; 326 sc->handle = acpi_get_handle(dev); 327 328 sc->mem_rid = 0; 329 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 330 RF_ACTIVE); 331 if (sc->mem_res == NULL) 332 return (ENOMEM); 333 334 /* Validate that we can access the whole region. */ 335 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 336 device_printf(dev, "memory region width %ld too small\n", 337 rman_get_size(sc->mem_res)); 338 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 339 return (ENXIO); 340 } 341 342 /* Be sure timer is enabled. */ 343 hpet_enable(sc); 344 345 /* Read basic statistics about the timer. */ 346 val = bus_read_4(sc->mem_res, HPET_PERIOD); 347 if (val == 0) { 348 device_printf(dev, "invalid period\n"); 349 hpet_disable(sc); 350 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 351 return (ENXIO); 352 } 353 354 sc->freq = (1000000000000000LL + val / 2) / val; 355 val = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 356 vendor = (val & HPET_CAP_VENDOR_ID) >> 16; 357 rev = val & HPET_CAP_REV_ID; 358 num_timers = 1 + ((val & HPET_CAP_NUM_TIM) >> 8); 359 /* 360 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 361 * Specification and provides an off by one number 362 * of timers/comparators. 363 * Additionally, they use unregistered value in VENDOR_ID field. 364 */ 365 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 366 num_timers--; 367 sc->num_timers = num_timers; 368 if (bootverbose) { 369 device_printf(dev, 370 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 371 vendor, rev, 372 sc->freq, (val & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 373 num_timers, (val & HPET_CAP_LEG_RT) ? " legacy route" : ""); 374 } 375 num_msi = 0; 376 for (i = 0; i < num_timers; i++) { 377 t = &sc->t[i]; 378 t->sc = sc; 379 t->num = i; 380 t->mode = 0; 381 t->intr_rid = -1; 382 t->irq = -1; 383 t->pcpu_master = -1; 384 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 385 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 386 if (bootverbose) { 387 device_printf(dev, 388 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 389 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 390 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 391 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 392 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 393 } 394#ifdef DEV_APIC 395 if (t->caps & HPET_TCAP_FSB_INT_DEL) 396 num_msi++; 397#endif 398 } 399 if (testenv("debug.acpi.hpet_test")) 400 hpet_test(sc); 401 /* 402 * Don't attach if the timer never increments. Since the spec 403 * requires it to be at least 10 MHz, it has to change in 1 us. 404 */ 405 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 406 DELAY(1); 407 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 408 if (val == val2) { 409 device_printf(dev, "HPET never increments, disabling\n"); 410 hpet_disable(sc); 411 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 412 return (ENXIO); 413 } 414 /* Announce first HPET as timecounter. */ 415 if (device_get_unit(dev) == 0) { 416 sc->tc.tc_get_timecount = hpet_get_timecount, 417 sc->tc.tc_counter_mask = ~0u, 418 sc->tc.tc_name = "HPET", 419 sc->tc.tc_quality = 900, 420 sc->tc.tc_frequency = sc->freq; 421 sc->tc.tc_priv = sc; 422 tc_init(&sc->tc); 423 } 424 /* If not disabled - setup and announce event timers. */ 425 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 426 "clock", &i) == 0 && i == 0) 427 return (0); 428 num_percpu_et = min(num_msi / mp_ncpus, 2); 429 num_percpu_t = num_percpu_et * mp_ncpus; 430 cur_cpu = CPU_FIRST(); 431 pcpu_master = 0; 432 /* Find common legacy IRQ vectors for all timers. */ 433 cvectors = 0xffff0000; 434 /* 435 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 436 * Lower are also not always working for different reasons. 437 * SB800 fixed it, but seems do not implements level triggering 438 * properly, that makes it very unreliable - it freezes after any 439 * interrupt loss. Avoid legacy IRQs for AMD. 440 */ 441 if (vendor == HPET_VENDID_AMD) 442 cvectors = 0x00000000; 443 sc->useirq = 0; 444 for (i = 0; i < num_timers; i++) { 445 t = &sc->t[i]; 446#ifdef DEV_APIC 447 if (t->caps & HPET_TCAP_FSB_INT_DEL) { 448 if ((j = PCIB_ALLOC_MSIX( 449 device_get_parent(device_get_parent(dev)), dev, 450 &t->irq))) { 451 device_printf(dev, 452 "Can't allocate interrupt: %d.\n", j); 453 } else if (!(t->intr_res = 454 bus_alloc_resource(dev, SYS_RES_IRQ, &t->intr_rid, 455 t->irq, t->irq, 1, RF_SHAREABLE | RF_ACTIVE))) { 456 device_printf(dev, "Can't map interrupt.\n"); 457 } else if ((bus_setup_intr(dev, t->intr_res, 458 INTR_MPSAFE | INTR_TYPE_CLK, 459 (driver_filter_t *)hpet_intr_single, NULL, 460 t, &t->intr_handle))) { 461 device_printf(dev, "Can't setup interrupt.\n"); 462 } else { 463 bus_describe_intr(dev, t->intr_res, 464 t->intr_handle, "t%d", i); 465 num_msi++; 466 if (num_percpu_t > 0) { 467 if (cur_cpu == CPU_FIRST()) 468 pcpu_master = i; 469 t->pcpu_master = pcpu_master; 470 sc->t[pcpu_master]. 471 pcpu_slaves[cur_cpu] = i; 472 bus_bind_intr(dev, t->intr_res, cur_cpu); 473 cur_cpu = CPU_NEXT(cur_cpu); 474 num_percpu_t--; 475 } 476 } 477 } else 478#endif 479 if ((cvectors & t->vectors) != 0) { 480 cvectors &= t->vectors; 481 sc->useirq |= (1 << i); 482 } 483 } 484 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 485 sc->irq = -1; 486 sc->intr_rid = -1; 487 /* If at least one timer needs legacy IRQ - setup it. */ 488 if (sc->useirq) { 489 j = i = fls(cvectors) - 1; 490 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 491 j--; 492 if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 493 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE))) 494 device_printf(dev,"Can't map interrupt.\n"); 495 else if ((bus_setup_intr(dev, sc->intr_res, 496 INTR_MPSAFE | INTR_TYPE_CLK, 497 (driver_filter_t *)hpet_intr, NULL, 498 sc, &sc->intr_handle))) { 499 device_printf(dev, "Can't setup interrupt.\n"); 500 } else { 501 sc->irq = rman_get_start(sc->intr_res); 502 /* Bind IRQ to BSP to avoid live migration. */ 503 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 504 } 505 } 506 /* Program and announce event timers. */ 507 for (i = 0; i < num_timers; i++) { 508 t = &sc->t[i]; 509 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 510 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 511 t->caps |= HPET_TCNF_32MODE; 512#ifdef DEV_APIC 513 if (t->irq >= 0) { 514 uint64_t addr; 515 uint32_t data; 516 517 if (PCIB_MAP_MSI( 518 device_get_parent(device_get_parent(dev)), dev, 519 t->irq, &addr, &data) == 0) { 520 bus_write_4(sc->mem_res, 521 HPET_TIMER_FSB_ADDR(i), addr); 522 bus_write_4(sc->mem_res, 523 HPET_TIMER_FSB_VAL(i), data); 524 t->caps |= HPET_TCNF_FSB_EN; 525 } else 526 t->irq = -2; 527 } else 528#endif 529 if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 530 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 531 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 532 /* Skip event timers without set up IRQ. */ 533 if (t->irq < 0 && 534 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 535 continue; 536 /* Announce the reset. */ 537 if (maxhpetet == 0) 538 t->et.et_name = "HPET"; 539 else { 540 sprintf(t->name, "HPET%d", maxhpetet); 541 t->et.et_name = t->name; 542 } 543 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 544 t->et.et_quality = 450; 545 if (t->pcpu_master >= 0) { 546 t->et.et_flags |= ET_FLAGS_PERCPU; 547 t->et.et_quality += 100; 548 } 549 if ((t->caps & HPET_TCAP_PER_INT) == 0) 550 t->et.et_quality -= 10; 551 t->et.et_frequency = sc->freq; 552 t->et.et_start = hpet_start; 553 t->et.et_stop = hpet_stop; 554 t->et.et_priv = &sc->t[i]; 555 if (t->pcpu_master < 0 || t->pcpu_master == i) { 556 et_register(&t->et); 557 maxhpetet++; 558 } 559 } 560 return (0); 561} 562 563static int 564hpet_detach(device_t dev) 565{ 566 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 567 568 /* XXX Without a tc_remove() function, we can't detach. */ 569 return (EBUSY); 570} 571 572static int 573hpet_suspend(device_t dev) 574{ 575 struct hpet_softc *sc; 576 577 /* 578 * Disable the timer during suspend. The timer will not lose 579 * its state in S1 or S2, but we are required to disable 580 * it. 581 */ 582 sc = device_get_softc(dev); 583 hpet_disable(sc); 584 585 return (0); 586} 587 588static int 589hpet_resume(device_t dev) 590{ 591 struct hpet_softc *sc; 592 struct hpet_timer *t; 593 int i; 594 595 /* Re-enable the timer after a resume to keep the clock advancing. */ 596 sc = device_get_softc(dev); 597 hpet_enable(sc); 598 /* Restart event timers that were running on suspend. */ 599 for (i = 0; i < sc->num_timers; i++) { 600 t = &sc->t[i]; 601#ifdef DEV_APIC 602 if (t->irq >= 0) { 603 uint64_t addr; 604 uint32_t data; 605 606 if (PCIB_MAP_MSI( 607 device_get_parent(device_get_parent(dev)), dev, 608 t->irq, &addr, &data) == 0) { 609 bus_write_4(sc->mem_res, 610 HPET_TIMER_FSB_ADDR(i), addr); 611 bus_write_4(sc->mem_res, 612 HPET_TIMER_FSB_VAL(i), data); 613 } 614 } 615#endif 616 if (t->mode == 0) 617 continue; 618 t->last = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 619 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 620 t->caps |= HPET_TCNF_TYPE; 621 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 622 t->caps | HPET_TCNF_VAL_SET); 623 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 624 t->last + t->div); 625 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 626 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 627 t->div); 628 } else { 629 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 630 t->last + sc->freq / 1024); 631 } 632 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 633 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 634 } 635 return (0); 636} 637 638/* Print some basic latency/rate information to assist in debugging. */ 639static void 640hpet_test(struct hpet_softc *sc) 641{ 642 int i; 643 uint32_t u1, u2; 644 struct bintime b0, b1, b2; 645 struct timespec ts; 646 647 binuptime(&b0); 648 binuptime(&b0); 649 binuptime(&b1); 650 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 651 for (i = 1; i < 1000; i++) 652 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 653 binuptime(&b2); 654 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 655 656 bintime_sub(&b2, &b1); 657 bintime_sub(&b1, &b0); 658 bintime_sub(&b2, &b1); 659 bintime2timespec(&b2, &ts); 660 661 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 662 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 663 664 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 665} 666 667#ifdef DEV_APIC 668static int 669hpet_remap_intr(device_t dev, device_t child, u_int irq) 670{ 671 struct hpet_softc *sc = device_get_softc(dev); 672 struct hpet_timer *t; 673 uint64_t addr; 674 uint32_t data; 675 int error, i; 676 677 for (i = 0; i < sc->num_timers; i++) { 678 t = &sc->t[i]; 679 if (t->irq != irq) 680 continue; 681 error = PCIB_MAP_MSI( 682 device_get_parent(device_get_parent(dev)), dev, 683 irq, &addr, &data); 684 if (error) 685 return (error); 686 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 687 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 688 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 689 hpet_enable(sc); 690 return (0); 691 } 692 return (ENOENT); 693} 694#endif 695 696static device_method_t hpet_methods[] = { 697 /* Device interface */ 698 DEVMETHOD(device_identify, hpet_identify), 699 DEVMETHOD(device_probe, hpet_probe), 700 DEVMETHOD(device_attach, hpet_attach), 701 DEVMETHOD(device_detach, hpet_detach), 702 DEVMETHOD(device_suspend, hpet_suspend), 703 DEVMETHOD(device_resume, hpet_resume), 704 705#ifdef DEV_APIC 706 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 707#endif 708 709 {0, 0} 710}; 711 712static driver_t hpet_driver = { 713 "hpet", 714 hpet_methods, 715 sizeof(struct hpet_softc), 716}; 717 718DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 719MODULE_DEPEND(hpet, acpi, 1, 1, 1); 720