acpi_hpet.c revision 295839
1151912Sphk/*- 2151912Sphk * Copyright (c) 2005 Poul-Henning Kamp 3209440Smav * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4151912Sphk * All rights reserved. 5151912Sphk * 6151912Sphk * Redistribution and use in source and binary forms, with or without 7151912Sphk * modification, are permitted provided that the following conditions 8151912Sphk * are met: 9151912Sphk * 1. Redistributions of source code must retain the above copyright 10151912Sphk * notice, this list of conditions and the following disclaimer. 11151912Sphk * 2. Redistributions in binary form must reproduce the above copyright 12151912Sphk * notice, this list of conditions and the following disclaimer in the 13151912Sphk * documentation and/or other materials provided with the distribution. 14151912Sphk * 15151912Sphk * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16151912Sphk * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17151912Sphk * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18151912Sphk * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19151912Sphk * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20151912Sphk * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21151912Sphk * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22151912Sphk * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23151912Sphk * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24151912Sphk * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25151912Sphk * SUCH DAMAGE. 26151912Sphk */ 27151912Sphk 28151912Sphk#include <sys/cdefs.h> 29151912Sphk__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 295839 2016-02-20 13:21:59Z kib $"); 30151912Sphk 31151912Sphk#include "opt_acpi.h" 32268351Smarcel#if defined(__amd64__) 33209371Smav#define DEV_APIC 34209371Smav#else 35209371Smav#include "opt_apic.h" 36209371Smav#endif 37151912Sphk#include <sys/param.h> 38273598Srpaulo#include <sys/conf.h> 39159217Snjl#include <sys/bus.h> 40151912Sphk#include <sys/kernel.h> 41151912Sphk#include <sys/module.h> 42209371Smav#include <sys/proc.h> 43151912Sphk#include <sys/rman.h> 44273598Srpaulo#include <sys/mman.h> 45151912Sphk#include <sys/time.h> 46209371Smav#include <sys/smp.h> 47209371Smav#include <sys/sysctl.h> 48209371Smav#include <sys/timeet.h> 49151912Sphk#include <sys/timetc.h> 50159217Snjl 51193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 52193530Sjkim#include <contrib/dev/acpica/include/accommon.h> 53193530Sjkim 54151912Sphk#include <dev/acpica/acpivar.h> 55175385Sjhb#include <dev/acpica/acpi_hpet.h> 56151912Sphk 57209371Smav#ifdef DEV_APIC 58209371Smav#include "pcib_if.h" 59209371Smav#endif 60209371Smav 61203062Savg#define HPET_VENDID_AMD 0x4353 62240286Smav#define HPET_VENDID_AMD2 0x1022 63203062Savg#define HPET_VENDID_INTEL 0x8086 64213302Smav#define HPET_VENDID_NVIDIA 0x10de 65232797Smav#define HPET_VENDID_SW 0x1166 66203062Savg 67151912SphkACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 68151912Sphk 69209371Smavstatic devclass_t hpet_devclass; 70169574Stakawata 71151931Sscottl/* ACPI CA debugging */ 72151935Sscottl#define _COMPONENT ACPI_TIMER 73151931SscottlACPI_MODULE_NAME("HPET") 74151931Sscottl 75209371Smavstruct hpet_softc { 76151912Sphk device_t dev; 77209371Smav int mem_rid; 78209371Smav int intr_rid; 79209371Smav int irq; 80209371Smav int useirq; 81209440Smav int legacy_route; 82212533Smav int per_cpu; 83212238Smav uint32_t allowed_irqs; 84159217Snjl struct resource *mem_res; 85209371Smav struct resource *intr_res; 86209371Smav void *intr_handle; 87151912Sphk ACPI_HANDLE handle; 88209371Smav uint64_t freq; 89209440Smav uint32_t caps; 90209371Smav struct timecounter tc; 91209371Smav struct hpet_timer { 92209371Smav struct eventtimer et; 93209371Smav struct hpet_softc *sc; 94209371Smav int num; 95209371Smav int mode; 96209371Smav int intr_rid; 97209371Smav int irq; 98212323Smav int pcpu_cpu; 99212323Smav int pcpu_misrouted; 100209371Smav int pcpu_master; 101209371Smav int pcpu_slaves[MAXCPU]; 102209371Smav struct resource *intr_res; 103209371Smav void *intr_handle; 104209371Smav uint32_t caps; 105209371Smav uint32_t vectors; 106209371Smav uint32_t div; 107212491Smav uint32_t next; 108209371Smav char name[8]; 109209371Smav } t[32]; 110209371Smav int num_timers; 111273598Srpaulo struct cdev *pdev; 112273598Srpaulo int mmap_allow; 113273598Srpaulo int mmap_allow_write; 114151912Sphk}; 115151912Sphk 116273598Srpaulostatic d_open_t hpet_open; 117273598Srpaulostatic d_mmap_t hpet_mmap; 118273598Srpaulo 119273598Srpaulostatic struct cdevsw hpet_cdevsw = { 120273598Srpaulo .d_version = D_VERSION, 121273598Srpaulo .d_name = "hpet", 122273598Srpaulo .d_open = hpet_open, 123273598Srpaulo .d_mmap = hpet_mmap, 124273598Srpaulo}; 125273598Srpaulo 126159217Snjlstatic u_int hpet_get_timecount(struct timecounter *tc); 127209371Smavstatic void hpet_test(struct hpet_softc *sc); 128151912Sphk 129159217Snjlstatic char *hpet_ids[] = { "PNP0103", NULL }; 130159217Snjl 131269515Sroyger/* Knob to disable acpi_hpet device */ 132269515Sroygerbool acpi_hpet_disabled = false; 133269515Sroyger 134159217Snjlstatic u_int 135151912Sphkhpet_get_timecount(struct timecounter *tc) 136151912Sphk{ 137209371Smav struct hpet_softc *sc; 138151912Sphk 139151912Sphk sc = tc->tc_priv; 140175385Sjhb return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 141151912Sphk} 142151912Sphk 143175361Sjhbstatic void 144209371Smavhpet_enable(struct hpet_softc *sc) 145175361Sjhb{ 146175361Sjhb uint32_t val; 147175385Sjhb 148175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 149209440Smav if (sc->legacy_route) 150209440Smav val |= HPET_CNF_LEG_RT; 151209440Smav else 152209440Smav val &= ~HPET_CNF_LEG_RT; 153185103Sjkim val |= HPET_CNF_ENABLE; 154185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 155175361Sjhb} 156175361Sjhb 157175361Sjhbstatic void 158209371Smavhpet_disable(struct hpet_softc *sc) 159175361Sjhb{ 160175361Sjhb uint32_t val; 161175385Sjhb 162175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 163185103Sjkim val &= ~HPET_CNF_ENABLE; 164185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 165175361Sjhb} 166175361Sjhb 167209371Smavstatic int 168247463Smavhpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 169209371Smav{ 170209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 171209371Smav struct hpet_timer *t; 172209371Smav struct hpet_softc *sc = mt->sc; 173212491Smav uint32_t fdiv, now; 174209371Smav 175209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 176247463Smav if (period != 0) { 177209371Smav t->mode = 1; 178247463Smav t->div = (sc->freq * period) >> 32; 179209371Smav } else { 180209371Smav t->mode = 2; 181209371Smav t->div = 0; 182209371Smav } 183247463Smav if (first != 0) 184247463Smav fdiv = (sc->freq * first) >> 32; 185247463Smav else 186210290Smav fdiv = t->div; 187212238Smav if (t->irq < 0) 188212238Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 189212238Smav t->caps |= HPET_TCNF_INT_ENB; 190212491Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 191212238Smavrestart: 192212491Smav t->next = now + fdiv; 193209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 194209371Smav t->caps |= HPET_TCNF_TYPE; 195209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 196209371Smav t->caps | HPET_TCNF_VAL_SET); 197212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 198212491Smav t->next); 199212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 200212491Smav t->div); 201209371Smav } else { 202212238Smav t->caps &= ~HPET_TCNF_TYPE; 203212491Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 204212491Smav t->caps); 205212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 206212491Smav t->next); 207209371Smav } 208224919Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 209224919Smav if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 210224919Smav fdiv *= 2; 211224919Smav goto restart; 212212238Smav } 213209371Smav return (0); 214209371Smav} 215209371Smav 216209371Smavstatic int 217209371Smavhpet_stop(struct eventtimer *et) 218209371Smav{ 219209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 220209371Smav struct hpet_timer *t; 221209371Smav struct hpet_softc *sc = mt->sc; 222209371Smav 223209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 224209371Smav t->mode = 0; 225209371Smav t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 226209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 227209371Smav return (0); 228209371Smav} 229209371Smav 230209371Smavstatic int 231209371Smavhpet_intr_single(void *arg) 232209371Smav{ 233209371Smav struct hpet_timer *t = (struct hpet_timer *)arg; 234209371Smav struct hpet_timer *mt; 235209371Smav struct hpet_softc *sc = t->sc; 236209371Smav uint32_t now; 237209371Smav 238212491Smav if (t->mode == 0) 239212491Smav return (FILTER_STRAY); 240212323Smav /* Check that per-CPU timer interrupt reached right CPU. */ 241212323Smav if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 242212323Smav if ((++t->pcpu_misrouted) % 32 == 0) { 243212323Smav printf("HPET interrupt routed to the wrong CPU" 244212323Smav " (timer %d CPU %d -> %d)!\n", 245212323Smav t->num, t->pcpu_cpu, curcpu); 246212323Smav } 247212323Smav 248212323Smav /* 249212323Smav * Reload timer, hoping that next time may be more lucky 250212323Smav * (system will manage proper interrupt binding). 251212323Smav */ 252212323Smav if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 253212323Smav t->mode == 2) { 254212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 255212491Smav sc->freq / 8; 256212323Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 257212491Smav t->next); 258212323Smav } 259212323Smav return (FILTER_HANDLED); 260212323Smav } 261209371Smav if (t->mode == 1 && 262209371Smav (t->caps & HPET_TCAP_PER_INT) == 0) { 263212491Smav t->next += t->div; 264209371Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 265212491Smav if ((int32_t)((now + t->div / 2) - t->next) > 0) 266212491Smav t->next = now + t->div / 2; 267209371Smav bus_write_4(sc->mem_res, 268212491Smav HPET_TIMER_COMPARATOR(t->num), t->next); 269209371Smav } else if (t->mode == 2) 270209371Smav t->mode = 0; 271209371Smav mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 272209990Smav if (mt->et.et_active) 273209990Smav mt->et.et_event_cb(&mt->et, mt->et.et_arg); 274209371Smav return (FILTER_HANDLED); 275209371Smav} 276209371Smav 277209371Smavstatic int 278209371Smavhpet_intr(void *arg) 279209371Smav{ 280209371Smav struct hpet_softc *sc = (struct hpet_softc *)arg; 281209371Smav int i; 282209371Smav uint32_t val; 283209371Smav 284209371Smav val = bus_read_4(sc->mem_res, HPET_ISR); 285209371Smav if (val) { 286209371Smav bus_write_4(sc->mem_res, HPET_ISR, val); 287209371Smav val &= sc->useirq; 288209371Smav for (i = 0; i < sc->num_timers; i++) { 289209371Smav if ((val & (1 << i)) == 0) 290209371Smav continue; 291209371Smav hpet_intr_single(&sc->t[i]); 292209371Smav } 293209371Smav return (FILTER_HANDLED); 294209371Smav } 295209371Smav return (FILTER_STRAY); 296209371Smav} 297209371Smav 298208436Smavstatic ACPI_STATUS 299209371Smavhpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 300208436Smav void **status) 301208436Smav{ 302208436Smav char **ids; 303208436Smav uint32_t id = (uint32_t)(uintptr_t)context; 304208438Smav uint32_t uid = 0; 305208436Smav 306208436Smav for (ids = hpet_ids; *ids != NULL; ids++) { 307208436Smav if (acpi_MatchHid(handle, *ids)) 308208436Smav break; 309208436Smav } 310208436Smav if (*ids == NULL) 311208436Smav return (AE_OK); 312209371Smav if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 313209371Smav id == uid) 314258164Smav *status = acpi_get_device(handle); 315208436Smav return (AE_OK); 316208436Smav} 317208436Smav 318216263Sjhb/* 319216263Sjhb * Find an existing IRQ resource that matches the requested IRQ range 320216263Sjhb * and return its RID. If one is not found, use a new RID. 321216263Sjhb */ 322216263Sjhbstatic int 323216263Sjhbhpet_find_irq_rid(device_t dev, u_long start, u_long end) 324216263Sjhb{ 325294883Sjhibbits rman_res_t irq; 326216263Sjhb int error, rid; 327216263Sjhb 328216263Sjhb for (rid = 0;; rid++) { 329216263Sjhb error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 330216263Sjhb if (error != 0 || (start <= irq && irq <= end)) 331216263Sjhb return (rid); 332216263Sjhb } 333216263Sjhb} 334216263Sjhb 335273598Srpaulostatic int 336273598Srpaulohpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td) 337273598Srpaulo{ 338273598Srpaulo struct hpet_softc *sc; 339273598Srpaulo 340273598Srpaulo sc = cdev->si_drv1; 341273598Srpaulo if (!sc->mmap_allow) 342273598Srpaulo return (EPERM); 343273598Srpaulo else 344273598Srpaulo return (0); 345273598Srpaulo} 346273598Srpaulo 347273598Srpaulostatic int 348273598Srpaulohpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr, 349273598Srpaulo int nprot, vm_memattr_t *memattr) 350273598Srpaulo{ 351273598Srpaulo struct hpet_softc *sc; 352273598Srpaulo 353273598Srpaulo sc = cdev->si_drv1; 354273598Srpaulo if (offset > rman_get_size(sc->mem_res)) 355273598Srpaulo return (EINVAL); 356273598Srpaulo if (!sc->mmap_allow_write && (nprot & PROT_WRITE)) 357273598Srpaulo return (EPERM); 358273598Srpaulo *paddr = rman_get_start(sc->mem_res) + offset; 359273647Skib *memattr = VM_MEMATTR_UNCACHEABLE; 360273598Srpaulo 361273598Srpaulo return (0); 362273598Srpaulo} 363273598Srpaulo 364169592Snjl/* Discover the HPET via the ACPI table of the same name. */ 365273602Srpaulostatic void 366209371Smavhpet_identify(driver_t *driver, device_t parent) 367169574Stakawata{ 368169574Stakawata ACPI_TABLE_HPET *hpet; 369169574Stakawata ACPI_STATUS status; 370169574Stakawata device_t child; 371258164Smav int i; 372169574Stakawata 373172489Snjl /* Only one HPET device can be added. */ 374209371Smav if (devclass_get_device(hpet_devclass, 0)) 375172489Snjl return; 376208436Smav for (i = 1; ; i++) { 377208436Smav /* Search for HPET table. */ 378208436Smav status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 379208436Smav if (ACPI_FAILURE(status)) 380208436Smav return; 381208436Smav /* Search for HPET device with same ID. */ 382258164Smav child = NULL; 383208436Smav AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 384258164Smav 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, 385258164Smav (void *)&child); 386208436Smav /* If found - let it be probed in normal way. */ 387258164Smav if (child) { 388258164Smav if (bus_get_resource(child, SYS_RES_MEMORY, 0, 389258164Smav NULL, NULL) != 0) 390258164Smav bus_set_resource(child, SYS_RES_MEMORY, 0, 391258164Smav hpet->Address.Address, HPET_MEM_WIDTH); 392208436Smav continue; 393258164Smav } 394208436Smav /* If not - create it from table info. */ 395231161Sjkim child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 396208436Smav if (child == NULL) { 397208436Smav printf("%s: can't add child\n", __func__); 398208436Smav continue; 399208436Smav } 400208436Smav bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 401208436Smav HPET_MEM_WIDTH); 402169574Stakawata } 403169574Stakawata} 404169574Stakawata 405151912Sphkstatic int 406209371Smavhpet_probe(device_t dev) 407151912Sphk{ 408159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 409159217Snjl 410269515Sroyger if (acpi_disabled("hpet") || acpi_hpet_disabled) 411151912Sphk return (ENXIO); 412199016Savg if (acpi_get_handle(dev) != NULL && 413208436Smav ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 414169592Snjl return (ENXIO); 415151912Sphk 416159217Snjl device_set_desc(dev, "High Precision Event Timer"); 417151912Sphk return (0); 418151912Sphk} 419151912Sphk 420151912Sphkstatic int 421209371Smavhpet_attach(device_t dev) 422151912Sphk{ 423209371Smav struct hpet_softc *sc; 424209371Smav struct hpet_timer *t; 425295839Skib struct make_dev_args mda; 426209371Smav int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 427295839Skib int pcpu_master, error; 428209371Smav static int maxhpetet = 0; 429212238Smav uint32_t val, val2, cvectors, dvectors; 430209371Smav uint16_t vendor, rev; 431151912Sphk 432151912Sphk ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 433151912Sphk 434151912Sphk sc = device_get_softc(dev); 435151912Sphk sc->dev = dev; 436151912Sphk sc->handle = acpi_get_handle(dev); 437151912Sphk 438209371Smav sc->mem_rid = 0; 439209371Smav sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 440159217Snjl RF_ACTIVE); 441159217Snjl if (sc->mem_res == NULL) 442159217Snjl return (ENOMEM); 443151912Sphk 444159217Snjl /* Validate that we can access the whole region. */ 445159217Snjl if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 446159217Snjl device_printf(dev, "memory region width %ld too small\n", 447159217Snjl rman_get_size(sc->mem_res)); 448159217Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 449159217Snjl return (ENXIO); 450159217Snjl } 451151912Sphk 452171547Snjl /* Be sure timer is enabled. */ 453175361Sjhb hpet_enable(sc); 454171547Snjl 455159217Snjl /* Read basic statistics about the timer. */ 456175385Sjhb val = bus_read_4(sc->mem_res, HPET_PERIOD); 457175361Sjhb if (val == 0) { 458175361Sjhb device_printf(dev, "invalid period\n"); 459175361Sjhb hpet_disable(sc); 460175361Sjhb bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 461175361Sjhb return (ENXIO); 462175361Sjhb } 463175361Sjhb 464209371Smav sc->freq = (1000000000000000LL + val / 2) / val; 465209440Smav sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 466209440Smav vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 467209440Smav rev = sc->caps & HPET_CAP_REV_ID; 468209440Smav num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 469209371Smav /* 470209371Smav * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 471209371Smav * Specification and provides an off by one number 472209371Smav * of timers/comparators. 473209371Smav * Additionally, they use unregistered value in VENDOR_ID field. 474209371Smav */ 475209371Smav if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 476209371Smav num_timers--; 477209371Smav sc->num_timers = num_timers; 478159217Snjl if (bootverbose) { 479159217Snjl device_printf(dev, 480209371Smav "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 481209440Smav vendor, rev, sc->freq, 482209440Smav (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 483209440Smav num_timers, 484209440Smav (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 485159217Snjl } 486209371Smav for (i = 0; i < num_timers; i++) { 487209371Smav t = &sc->t[i]; 488209371Smav t->sc = sc; 489209371Smav t->num = i; 490209371Smav t->mode = 0; 491209371Smav t->intr_rid = -1; 492209371Smav t->irq = -1; 493212323Smav t->pcpu_cpu = -1; 494212323Smav t->pcpu_misrouted = 0; 495209371Smav t->pcpu_master = -1; 496209371Smav t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 497209371Smav t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 498209371Smav if (bootverbose) { 499209371Smav device_printf(dev, 500209371Smav " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 501209371Smav t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 502209371Smav (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 503209371Smav (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 504209371Smav (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 505209371Smav } 506209371Smav } 507159217Snjl if (testenv("debug.acpi.hpet_test")) 508209371Smav hpet_test(sc); 509171547Snjl /* 510171547Snjl * Don't attach if the timer never increments. Since the spec 511171547Snjl * requires it to be at least 10 MHz, it has to change in 1 us. 512171547Snjl */ 513175385Sjhb val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 514171547Snjl DELAY(1); 515175385Sjhb val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 516171547Snjl if (val == val2) { 517171547Snjl device_printf(dev, "HPET never increments, disabling\n"); 518175361Sjhb hpet_disable(sc); 519171547Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 520171547Snjl return (ENXIO); 521171547Snjl } 522208436Smav /* Announce first HPET as timecounter. */ 523208436Smav if (device_get_unit(dev) == 0) { 524209371Smav sc->tc.tc_get_timecount = hpet_get_timecount, 525209371Smav sc->tc.tc_counter_mask = ~0u, 526209371Smav sc->tc.tc_name = "HPET", 527222222Sjkim sc->tc.tc_quality = 950, 528209371Smav sc->tc.tc_frequency = sc->freq; 529209371Smav sc->tc.tc_priv = sc; 530209371Smav tc_init(&sc->tc); 531208436Smav } 532209371Smav /* If not disabled - setup and announce event timers. */ 533209371Smav if (resource_int_value(device_get_name(dev), device_get_unit(dev), 534209371Smav "clock", &i) == 0 && i == 0) 535209371Smav return (0); 536209440Smav 537209440Smav /* Check whether we can and want legacy routing. */ 538209440Smav sc->legacy_route = 0; 539209440Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 540209440Smav "legacy_route", &sc->legacy_route); 541209440Smav if ((sc->caps & HPET_CAP_LEG_RT) == 0) 542209440Smav sc->legacy_route = 0; 543209440Smav if (sc->legacy_route) { 544209440Smav sc->t[0].vectors = 0; 545209440Smav sc->t[1].vectors = 0; 546209440Smav } 547209440Smav 548212238Smav /* Check what IRQs we want use. */ 549212238Smav /* By default allow any PCI IRQs. */ 550212238Smav sc->allowed_irqs = 0xffff0000; 551209371Smav /* 552209371Smav * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 553209371Smav * Lower are also not always working for different reasons. 554209371Smav * SB800 fixed it, but seems do not implements level triggering 555209371Smav * properly, that makes it very unreliable - it freezes after any 556209371Smav * interrupt loss. Avoid legacy IRQs for AMD. 557209371Smav */ 558240286Smav if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2) 559212238Smav sc->allowed_irqs = 0x00000000; 560212238Smav /* 561213302Smav * NVidia MCP5x chipsets have number of unexplained interrupt 562213302Smav * problems. For some reason, using HPET interrupts breaks HDA sound. 563213302Smav */ 564213302Smav if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 565213302Smav sc->allowed_irqs = 0x00000000; 566213302Smav /* 567232797Smav * ServerWorks HT1000 reported to have problems with IRQs >= 16. 568232797Smav * Lower IRQs are working, but allowed mask is not set correctly. 569232797Smav * Legacy_route mode works fine. 570232797Smav */ 571232797Smav if (vendor == HPET_VENDID_SW && rev <= 0x01) 572232797Smav sc->allowed_irqs = 0x00000000; 573232797Smav /* 574212238Smav * Neither QEMU nor VirtualBox report supported IRQs correctly. 575212238Smav * The only way to use HPET there is to specify IRQs manually 576215473Sjhb * and/or use legacy_route. Legacy_route mode works on both. 577212238Smav */ 578212238Smav if (vm_guest) 579212238Smav sc->allowed_irqs = 0x00000000; 580212238Smav /* Let user override. */ 581212238Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 582212238Smav "allowed_irqs", &sc->allowed_irqs); 583212238Smav 584212533Smav /* Get how much per-CPU timers we should try to provide. */ 585212533Smav sc->per_cpu = 1; 586212533Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 587212533Smav "per_cpu", &sc->per_cpu); 588212533Smav 589212238Smav num_msi = 0; 590212238Smav sc->useirq = 0; 591212238Smav /* Find IRQ vectors for all timers. */ 592212238Smav cvectors = sc->allowed_irqs & 0xffff0000; 593212238Smav dvectors = sc->allowed_irqs & 0x0000ffff; 594212238Smav if (sc->legacy_route) 595212238Smav dvectors &= 0x0000fefe; 596209371Smav for (i = 0; i < num_timers; i++) { 597209371Smav t = &sc->t[i]; 598209440Smav if (sc->legacy_route && i < 2) 599209440Smav t->irq = (i == 0) ? 0 : 8; 600209371Smav#ifdef DEV_APIC 601209440Smav else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 602209371Smav if ((j = PCIB_ALLOC_MSIX( 603209371Smav device_get_parent(device_get_parent(dev)), dev, 604209371Smav &t->irq))) { 605209371Smav device_printf(dev, 606269897Sneel "Can't allocate interrupt for t%d: %d\n", 607269897Sneel i, j); 608209440Smav } 609209440Smav } 610209440Smav#endif 611212238Smav else if (dvectors & t->vectors) { 612212238Smav t->irq = ffs(dvectors & t->vectors) - 1; 613212238Smav dvectors &= ~(1 << t->irq); 614212238Smav } 615209440Smav if (t->irq >= 0) { 616216263Sjhb t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 617216490Sjhb t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 618216490Sjhb &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 619216490Sjhb if (t->intr_res == NULL) { 620209440Smav t->irq = -1; 621209440Smav device_printf(dev, 622209440Smav "Can't map interrupt for t%d.\n", i); 623216490Sjhb } else if (bus_setup_intr(dev, t->intr_res, 624216490Sjhb INTR_TYPE_CLK, hpet_intr_single, NULL, t, 625216490Sjhb &t->intr_handle) != 0) { 626209440Smav t->irq = -1; 627209440Smav device_printf(dev, 628209440Smav "Can't setup interrupt for t%d.\n", i); 629209371Smav } else { 630209371Smav bus_describe_intr(dev, t->intr_res, 631209371Smav t->intr_handle, "t%d", i); 632209371Smav num_msi++; 633209371Smav } 634209440Smav } 635209440Smav if (t->irq < 0 && (cvectors & t->vectors) != 0) { 636209371Smav cvectors &= t->vectors; 637209371Smav sc->useirq |= (1 << i); 638209371Smav } 639209371Smav } 640209440Smav if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 641209440Smav sc->legacy_route = 0; 642209440Smav if (sc->legacy_route) 643209440Smav hpet_enable(sc); 644209440Smav /* Group timers for per-CPU operation. */ 645212533Smav num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 646209440Smav num_percpu_t = num_percpu_et * mp_ncpus; 647209440Smav pcpu_master = 0; 648209440Smav cur_cpu = CPU_FIRST(); 649209440Smav for (i = 0; i < num_timers; i++) { 650209440Smav t = &sc->t[i]; 651209440Smav if (t->irq >= 0 && num_percpu_t > 0) { 652209440Smav if (cur_cpu == CPU_FIRST()) 653209440Smav pcpu_master = i; 654212323Smav t->pcpu_cpu = cur_cpu; 655209440Smav t->pcpu_master = pcpu_master; 656209440Smav sc->t[pcpu_master]. 657209440Smav pcpu_slaves[cur_cpu] = i; 658209440Smav bus_bind_intr(dev, t->intr_res, cur_cpu); 659209440Smav cur_cpu = CPU_NEXT(cur_cpu); 660209440Smav num_percpu_t--; 661212238Smav } else if (t->irq >= 0) 662212238Smav bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 663209440Smav } 664209371Smav bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 665209371Smav sc->irq = -1; 666215473Sjhb /* If at least one timer needs legacy IRQ - set it up. */ 667209371Smav if (sc->useirq) { 668209371Smav j = i = fls(cvectors) - 1; 669209371Smav while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 670209371Smav j--; 671216263Sjhb sc->intr_rid = hpet_find_irq_rid(dev, j, i); 672216490Sjhb sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 673216490Sjhb &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 674216490Sjhb if (sc->intr_res == NULL) 675216490Sjhb device_printf(dev, "Can't map interrupt.\n"); 676216490Sjhb else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 677216490Sjhb hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 678209371Smav device_printf(dev, "Can't setup interrupt.\n"); 679209371Smav } else { 680209371Smav sc->irq = rman_get_start(sc->intr_res); 681209371Smav /* Bind IRQ to BSP to avoid live migration. */ 682209371Smav bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 683209371Smav } 684209371Smav } 685209371Smav /* Program and announce event timers. */ 686209371Smav for (i = 0; i < num_timers; i++) { 687209371Smav t = &sc->t[i]; 688209371Smav t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 689209371Smav t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 690209440Smav t->caps &= ~(HPET_TCNF_INT_TYPE); 691209371Smav t->caps |= HPET_TCNF_32MODE; 692209440Smav if (t->irq >= 0 && sc->legacy_route && i < 2) { 693209440Smav /* Legacy route doesn't need more configuration. */ 694209440Smav } else 695209371Smav#ifdef DEV_APIC 696212238Smav if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 697209371Smav uint64_t addr; 698273602Srpaulo uint32_t data; 699273602Srpaulo 700209371Smav if (PCIB_MAP_MSI( 701209371Smav device_get_parent(device_get_parent(dev)), dev, 702209371Smav t->irq, &addr, &data) == 0) { 703209371Smav bus_write_4(sc->mem_res, 704209371Smav HPET_TIMER_FSB_ADDR(i), addr); 705209371Smav bus_write_4(sc->mem_res, 706209371Smav HPET_TIMER_FSB_VAL(i), data); 707209371Smav t->caps |= HPET_TCNF_FSB_EN; 708209371Smav } else 709209371Smav t->irq = -2; 710209371Smav } else 711209371Smav#endif 712212238Smav if (t->irq >= 0) 713212238Smav t->caps |= (t->irq << 9); 714212238Smav else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 715209371Smav t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 716209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 717209371Smav /* Skip event timers without set up IRQ. */ 718209371Smav if (t->irq < 0 && 719209371Smav (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 720209371Smav continue; 721209371Smav /* Announce the reset. */ 722209371Smav if (maxhpetet == 0) 723209371Smav t->et.et_name = "HPET"; 724209371Smav else { 725209371Smav sprintf(t->name, "HPET%d", maxhpetet); 726209371Smav t->et.et_name = t->name; 727209371Smav } 728209371Smav t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 729209371Smav t->et.et_quality = 450; 730209371Smav if (t->pcpu_master >= 0) { 731209371Smav t->et.et_flags |= ET_FLAGS_PERCPU; 732209371Smav t->et.et_quality += 100; 733248170Smav } else if (mp_ncpus >= 8) 734248154Smav t->et.et_quality -= 100; 735209371Smav if ((t->caps & HPET_TCAP_PER_INT) == 0) 736209371Smav t->et.et_quality -= 10; 737209371Smav t->et.et_frequency = sc->freq; 738247463Smav t->et.et_min_period = 739247463Smav ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; 740247463Smav t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; 741209371Smav t->et.et_start = hpet_start; 742209371Smav t->et.et_stop = hpet_stop; 743209371Smav t->et.et_priv = &sc->t[i]; 744209371Smav if (t->pcpu_master < 0 || t->pcpu_master == i) { 745209371Smav et_register(&t->et); 746209371Smav maxhpetet++; 747209371Smav } 748209371Smav } 749273598Srpaulo 750295839Skib make_dev_args_init(&mda); 751295839Skib mda.mda_devsw = &hpet_cdevsw; 752295839Skib mda.mda_uid = UID_ROOT; 753295839Skib mda.mda_gid = GID_WHEEL; 754295839Skib mda.mda_mode = 0600; 755295839Skib mda.mda_si_drv1 = sc; 756295839Skib error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev)); 757295839Skib if (error == 0) { 758273598Srpaulo sc->mmap_allow = 1; 759273598Srpaulo TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow", 760273598Srpaulo &sc->mmap_allow); 761273598Srpaulo sc->mmap_allow_write = 1; 762273598Srpaulo TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write", 763273598Srpaulo &sc->mmap_allow_write); 764273598Srpaulo SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 765273598Srpaulo SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 766273598Srpaulo OID_AUTO, "mmap_allow", 767273598Srpaulo CTLFLAG_RW, &sc->mmap_allow, 0, 768273598Srpaulo "Allow userland to memory map HPET"); 769273607Srpaulo SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 770273607Srpaulo SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 771273607Srpaulo OID_AUTO, "mmap_allow_write", 772273607Srpaulo CTLFLAG_RW, &sc->mmap_allow_write, 0, 773273607Srpaulo "Allow userland write to the HPET register space"); 774295839Skib } else { 775295839Skib device_printf(dev, "could not create /dev/hpet%d, error %d\n", 776295839Skib device_get_unit(dev), error); 777295839Skib } 778273598Srpaulo 779159217Snjl return (0); 780159217Snjl} 781159217Snjl 782159217Snjlstatic int 783209371Smavhpet_detach(device_t dev) 784159217Snjl{ 785159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 786159217Snjl 787159217Snjl /* XXX Without a tc_remove() function, we can't detach. */ 788159217Snjl return (EBUSY); 789159217Snjl} 790159217Snjl 791168010Snjlstatic int 792209371Smavhpet_suspend(device_t dev) 793175361Sjhb{ 794212541Smav// struct hpet_softc *sc; 795175361Sjhb 796175361Sjhb /* 797175361Sjhb * Disable the timer during suspend. The timer will not lose 798175361Sjhb * its state in S1 or S2, but we are required to disable 799175361Sjhb * it. 800175361Sjhb */ 801212541Smav// sc = device_get_softc(dev); 802212541Smav// hpet_disable(sc); 803175361Sjhb 804175361Sjhb return (0); 805175361Sjhb} 806175361Sjhb 807175361Sjhbstatic int 808209371Smavhpet_resume(device_t dev) 809168010Snjl{ 810209371Smav struct hpet_softc *sc; 811209371Smav struct hpet_timer *t; 812209371Smav int i; 813168010Snjl 814168010Snjl /* Re-enable the timer after a resume to keep the clock advancing. */ 815168010Snjl sc = device_get_softc(dev); 816175361Sjhb hpet_enable(sc); 817209371Smav /* Restart event timers that were running on suspend. */ 818209371Smav for (i = 0; i < sc->num_timers; i++) { 819209371Smav t = &sc->t[i]; 820209371Smav#ifdef DEV_APIC 821209440Smav if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 822209371Smav uint64_t addr; 823273602Srpaulo uint32_t data; 824273602Srpaulo 825209371Smav if (PCIB_MAP_MSI( 826209371Smav device_get_parent(device_get_parent(dev)), dev, 827209371Smav t->irq, &addr, &data) == 0) { 828209371Smav bus_write_4(sc->mem_res, 829209371Smav HPET_TIMER_FSB_ADDR(i), addr); 830209371Smav bus_write_4(sc->mem_res, 831209371Smav HPET_TIMER_FSB_VAL(i), data); 832209371Smav } 833209371Smav } 834209371Smav#endif 835209371Smav if (t->mode == 0) 836209371Smav continue; 837212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 838209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 839209371Smav t->caps |= HPET_TCNF_TYPE; 840212491Smav t->next += t->div; 841209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 842209371Smav t->caps | HPET_TCNF_VAL_SET); 843209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 844212491Smav t->next); 845209371Smav bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 846209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 847209371Smav t->div); 848209371Smav } else { 849212491Smav t->next += sc->freq / 1024; 850209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 851212491Smav t->next); 852209371Smav } 853209371Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 854209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 855209371Smav } 856168010Snjl return (0); 857168010Snjl} 858168010Snjl 859159217Snjl/* Print some basic latency/rate information to assist in debugging. */ 860159217Snjlstatic void 861209371Smavhpet_test(struct hpet_softc *sc) 862159217Snjl{ 863151912Sphk int i; 864151912Sphk uint32_t u1, u2; 865151912Sphk struct bintime b0, b1, b2; 866151912Sphk struct timespec ts; 867151912Sphk 868151912Sphk binuptime(&b0); 869151912Sphk binuptime(&b0); 870151912Sphk binuptime(&b1); 871175385Sjhb u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 872151912Sphk for (i = 1; i < 1000; i++) 873175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 874151912Sphk binuptime(&b2); 875175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 876151912Sphk 877151912Sphk bintime_sub(&b2, &b1); 878151912Sphk bintime_sub(&b1, &b0); 879151912Sphk bintime_sub(&b2, &b1); 880151912Sphk bintime2timespec(&b2, &ts); 881151912Sphk 882159217Snjl device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 883151912Sphk (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 884151912Sphk 885159217Snjl device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 886151912Sphk} 887151912Sphk 888209371Smav#ifdef DEV_APIC 889209371Smavstatic int 890209371Smavhpet_remap_intr(device_t dev, device_t child, u_int irq) 891209371Smav{ 892209371Smav struct hpet_softc *sc = device_get_softc(dev); 893209371Smav struct hpet_timer *t; 894209371Smav uint64_t addr; 895273602Srpaulo uint32_t data; 896209371Smav int error, i; 897209371Smav 898209371Smav for (i = 0; i < sc->num_timers; i++) { 899209371Smav t = &sc->t[i]; 900209371Smav if (t->irq != irq) 901209371Smav continue; 902209371Smav error = PCIB_MAP_MSI( 903209371Smav device_get_parent(device_get_parent(dev)), dev, 904209371Smav irq, &addr, &data); 905209371Smav if (error) 906209371Smav return (error); 907209371Smav hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 908209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 909209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 910209371Smav hpet_enable(sc); 911209371Smav return (0); 912209371Smav } 913209371Smav return (ENOENT); 914209371Smav} 915209371Smav#endif 916209371Smav 917209371Smavstatic device_method_t hpet_methods[] = { 918151912Sphk /* Device interface */ 919209371Smav DEVMETHOD(device_identify, hpet_identify), 920209371Smav DEVMETHOD(device_probe, hpet_probe), 921209371Smav DEVMETHOD(device_attach, hpet_attach), 922209371Smav DEVMETHOD(device_detach, hpet_detach), 923209371Smav DEVMETHOD(device_suspend, hpet_suspend), 924209371Smav DEVMETHOD(device_resume, hpet_resume), 925151912Sphk 926209371Smav#ifdef DEV_APIC 927209371Smav DEVMETHOD(bus_remap_intr, hpet_remap_intr), 928209371Smav#endif 929209371Smav 930246128Ssbz DEVMETHOD_END 931151912Sphk}; 932151912Sphk 933209371Smavstatic driver_t hpet_driver = { 934209371Smav "hpet", 935209371Smav hpet_methods, 936209371Smav sizeof(struct hpet_softc), 937151912Sphk}; 938151912Sphk 939209371SmavDRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 940209371SmavMODULE_DEPEND(hpet, acpi, 1, 1, 1); 941