acpi_hpet.c revision 269897
1151912Sphk/*- 2151912Sphk * Copyright (c) 2005 Poul-Henning Kamp 3209440Smav * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4151912Sphk * All rights reserved. 5151912Sphk * 6151912Sphk * Redistribution and use in source and binary forms, with or without 7151912Sphk * modification, are permitted provided that the following conditions 8151912Sphk * are met: 9151912Sphk * 1. Redistributions of source code must retain the above copyright 10151912Sphk * notice, this list of conditions and the following disclaimer. 11151912Sphk * 2. Redistributions in binary form must reproduce the above copyright 12151912Sphk * notice, this list of conditions and the following disclaimer in the 13151912Sphk * documentation and/or other materials provided with the distribution. 14151912Sphk * 15151912Sphk * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16151912Sphk * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17151912Sphk * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18151912Sphk * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19151912Sphk * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20151912Sphk * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21151912Sphk * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22151912Sphk * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23151912Sphk * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24151912Sphk * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25151912Sphk * SUCH DAMAGE. 26151912Sphk */ 27151912Sphk 28151912Sphk#include <sys/cdefs.h> 29151912Sphk__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 269897 2014-08-13 00:18:16Z neel $"); 30151912Sphk 31151912Sphk#include "opt_acpi.h" 32268351Smarcel#if defined(__amd64__) 33209371Smav#define DEV_APIC 34209371Smav#else 35209371Smav#include "opt_apic.h" 36209371Smav#endif 37151912Sphk#include <sys/param.h> 38159217Snjl#include <sys/bus.h> 39151912Sphk#include <sys/kernel.h> 40151912Sphk#include <sys/module.h> 41209371Smav#include <sys/proc.h> 42151912Sphk#include <sys/rman.h> 43151912Sphk#include <sys/time.h> 44209371Smav#include <sys/smp.h> 45209371Smav#include <sys/sysctl.h> 46209371Smav#include <sys/timeet.h> 47151912Sphk#include <sys/timetc.h> 48159217Snjl 49193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 50193530Sjkim#include <contrib/dev/acpica/include/accommon.h> 51193530Sjkim 52151912Sphk#include <dev/acpica/acpivar.h> 53175385Sjhb#include <dev/acpica/acpi_hpet.h> 54151912Sphk 55209371Smav#ifdef DEV_APIC 56209371Smav#include "pcib_if.h" 57209371Smav#endif 58209371Smav 59203062Savg#define HPET_VENDID_AMD 0x4353 60240286Smav#define HPET_VENDID_AMD2 0x1022 61203062Savg#define HPET_VENDID_INTEL 0x8086 62213302Smav#define HPET_VENDID_NVIDIA 0x10de 63232797Smav#define HPET_VENDID_SW 0x1166 64203062Savg 65151912SphkACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 66151912Sphk 67209371Smavstatic devclass_t hpet_devclass; 68169574Stakawata 69151931Sscottl/* ACPI CA debugging */ 70151935Sscottl#define _COMPONENT ACPI_TIMER 71151931SscottlACPI_MODULE_NAME("HPET") 72151931Sscottl 73209371Smavstruct hpet_softc { 74151912Sphk device_t dev; 75209371Smav int mem_rid; 76209371Smav int intr_rid; 77209371Smav int irq; 78209371Smav int useirq; 79209440Smav int legacy_route; 80212533Smav int per_cpu; 81212238Smav uint32_t allowed_irqs; 82159217Snjl struct resource *mem_res; 83209371Smav struct resource *intr_res; 84209371Smav void *intr_handle; 85151912Sphk ACPI_HANDLE handle; 86209371Smav uint64_t freq; 87209440Smav uint32_t caps; 88209371Smav struct timecounter tc; 89209371Smav struct hpet_timer { 90209371Smav struct eventtimer et; 91209371Smav struct hpet_softc *sc; 92209371Smav int num; 93209371Smav int mode; 94209371Smav int intr_rid; 95209371Smav int irq; 96212323Smav int pcpu_cpu; 97212323Smav int pcpu_misrouted; 98209371Smav int pcpu_master; 99209371Smav int pcpu_slaves[MAXCPU]; 100209371Smav struct resource *intr_res; 101209371Smav void *intr_handle; 102209371Smav uint32_t caps; 103209371Smav uint32_t vectors; 104209371Smav uint32_t div; 105212491Smav uint32_t next; 106209371Smav char name[8]; 107209371Smav } t[32]; 108209371Smav int num_timers; 109151912Sphk}; 110151912Sphk 111159217Snjlstatic u_int hpet_get_timecount(struct timecounter *tc); 112209371Smavstatic void hpet_test(struct hpet_softc *sc); 113151912Sphk 114159217Snjlstatic char *hpet_ids[] = { "PNP0103", NULL }; 115159217Snjl 116269515Sroyger/* Knob to disable acpi_hpet device */ 117269515Sroygerbool acpi_hpet_disabled = false; 118269515Sroyger 119159217Snjlstatic u_int 120151912Sphkhpet_get_timecount(struct timecounter *tc) 121151912Sphk{ 122209371Smav struct hpet_softc *sc; 123151912Sphk 124151912Sphk sc = tc->tc_priv; 125175385Sjhb return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 126151912Sphk} 127151912Sphk 128175361Sjhbstatic void 129209371Smavhpet_enable(struct hpet_softc *sc) 130175361Sjhb{ 131175361Sjhb uint32_t val; 132175385Sjhb 133175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 134209440Smav if (sc->legacy_route) 135209440Smav val |= HPET_CNF_LEG_RT; 136209440Smav else 137209440Smav val &= ~HPET_CNF_LEG_RT; 138185103Sjkim val |= HPET_CNF_ENABLE; 139185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 140175361Sjhb} 141175361Sjhb 142175361Sjhbstatic void 143209371Smavhpet_disable(struct hpet_softc *sc) 144175361Sjhb{ 145175361Sjhb uint32_t val; 146175385Sjhb 147175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 148185103Sjkim val &= ~HPET_CNF_ENABLE; 149185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 150175361Sjhb} 151175361Sjhb 152209371Smavstatic int 153247463Smavhpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 154209371Smav{ 155209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 156209371Smav struct hpet_timer *t; 157209371Smav struct hpet_softc *sc = mt->sc; 158212491Smav uint32_t fdiv, now; 159209371Smav 160209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 161247463Smav if (period != 0) { 162209371Smav t->mode = 1; 163247463Smav t->div = (sc->freq * period) >> 32; 164209371Smav } else { 165209371Smav t->mode = 2; 166209371Smav t->div = 0; 167209371Smav } 168247463Smav if (first != 0) 169247463Smav fdiv = (sc->freq * first) >> 32; 170247463Smav else 171210290Smav fdiv = t->div; 172212238Smav if (t->irq < 0) 173212238Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 174212238Smav t->caps |= HPET_TCNF_INT_ENB; 175212491Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 176212238Smavrestart: 177212491Smav t->next = now + fdiv; 178209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 179209371Smav t->caps |= HPET_TCNF_TYPE; 180209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 181209371Smav t->caps | HPET_TCNF_VAL_SET); 182212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 183212491Smav t->next); 184212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 185212491Smav t->div); 186209371Smav } else { 187212238Smav t->caps &= ~HPET_TCNF_TYPE; 188212491Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 189212491Smav t->caps); 190212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 191212491Smav t->next); 192209371Smav } 193224919Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 194224919Smav if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 195224919Smav fdiv *= 2; 196224919Smav goto restart; 197212238Smav } 198209371Smav return (0); 199209371Smav} 200209371Smav 201209371Smavstatic int 202209371Smavhpet_stop(struct eventtimer *et) 203209371Smav{ 204209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 205209371Smav struct hpet_timer *t; 206209371Smav struct hpet_softc *sc = mt->sc; 207209371Smav 208209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 209209371Smav t->mode = 0; 210209371Smav t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 211209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 212209371Smav return (0); 213209371Smav} 214209371Smav 215209371Smavstatic int 216209371Smavhpet_intr_single(void *arg) 217209371Smav{ 218209371Smav struct hpet_timer *t = (struct hpet_timer *)arg; 219209371Smav struct hpet_timer *mt; 220209371Smav struct hpet_softc *sc = t->sc; 221209371Smav uint32_t now; 222209371Smav 223212491Smav if (t->mode == 0) 224212491Smav return (FILTER_STRAY); 225212323Smav /* Check that per-CPU timer interrupt reached right CPU. */ 226212323Smav if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 227212323Smav if ((++t->pcpu_misrouted) % 32 == 0) { 228212323Smav printf("HPET interrupt routed to the wrong CPU" 229212323Smav " (timer %d CPU %d -> %d)!\n", 230212323Smav t->num, t->pcpu_cpu, curcpu); 231212323Smav } 232212323Smav 233212323Smav /* 234212323Smav * Reload timer, hoping that next time may be more lucky 235212323Smav * (system will manage proper interrupt binding). 236212323Smav */ 237212323Smav if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 238212323Smav t->mode == 2) { 239212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 240212491Smav sc->freq / 8; 241212323Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 242212491Smav t->next); 243212323Smav } 244212323Smav return (FILTER_HANDLED); 245212323Smav } 246209371Smav if (t->mode == 1 && 247209371Smav (t->caps & HPET_TCAP_PER_INT) == 0) { 248212491Smav t->next += t->div; 249209371Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 250212491Smav if ((int32_t)((now + t->div / 2) - t->next) > 0) 251212491Smav t->next = now + t->div / 2; 252209371Smav bus_write_4(sc->mem_res, 253212491Smav HPET_TIMER_COMPARATOR(t->num), t->next); 254209371Smav } else if (t->mode == 2) 255209371Smav t->mode = 0; 256209371Smav mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 257209990Smav if (mt->et.et_active) 258209990Smav mt->et.et_event_cb(&mt->et, mt->et.et_arg); 259209371Smav return (FILTER_HANDLED); 260209371Smav} 261209371Smav 262209371Smavstatic int 263209371Smavhpet_intr(void *arg) 264209371Smav{ 265209371Smav struct hpet_softc *sc = (struct hpet_softc *)arg; 266209371Smav int i; 267209371Smav uint32_t val; 268209371Smav 269209371Smav val = bus_read_4(sc->mem_res, HPET_ISR); 270209371Smav if (val) { 271209371Smav bus_write_4(sc->mem_res, HPET_ISR, val); 272209371Smav val &= sc->useirq; 273209371Smav for (i = 0; i < sc->num_timers; i++) { 274209371Smav if ((val & (1 << i)) == 0) 275209371Smav continue; 276209371Smav hpet_intr_single(&sc->t[i]); 277209371Smav } 278209371Smav return (FILTER_HANDLED); 279209371Smav } 280209371Smav return (FILTER_STRAY); 281209371Smav} 282209371Smav 283208436Smavstatic ACPI_STATUS 284209371Smavhpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 285208436Smav void **status) 286208436Smav{ 287208436Smav char **ids; 288208436Smav uint32_t id = (uint32_t)(uintptr_t)context; 289208438Smav uint32_t uid = 0; 290208436Smav 291208436Smav for (ids = hpet_ids; *ids != NULL; ids++) { 292208436Smav if (acpi_MatchHid(handle, *ids)) 293208436Smav break; 294208436Smav } 295208436Smav if (*ids == NULL) 296208436Smav return (AE_OK); 297209371Smav if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 298209371Smav id == uid) 299258164Smav *status = acpi_get_device(handle); 300208436Smav return (AE_OK); 301208436Smav} 302208436Smav 303216263Sjhb/* 304216263Sjhb * Find an existing IRQ resource that matches the requested IRQ range 305216263Sjhb * and return its RID. If one is not found, use a new RID. 306216263Sjhb */ 307216263Sjhbstatic int 308216263Sjhbhpet_find_irq_rid(device_t dev, u_long start, u_long end) 309216263Sjhb{ 310216263Sjhb u_long irq; 311216263Sjhb int error, rid; 312216263Sjhb 313216263Sjhb for (rid = 0;; rid++) { 314216263Sjhb error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 315216263Sjhb if (error != 0 || (start <= irq && irq <= end)) 316216263Sjhb return (rid); 317216263Sjhb } 318216263Sjhb} 319216263Sjhb 320169592Snjl/* Discover the HPET via the ACPI table of the same name. */ 321172489Snjlstatic void 322209371Smavhpet_identify(driver_t *driver, device_t parent) 323169574Stakawata{ 324169574Stakawata ACPI_TABLE_HPET *hpet; 325169574Stakawata ACPI_STATUS status; 326169574Stakawata device_t child; 327258164Smav int i; 328169574Stakawata 329172489Snjl /* Only one HPET device can be added. */ 330209371Smav if (devclass_get_device(hpet_devclass, 0)) 331172489Snjl return; 332208436Smav for (i = 1; ; i++) { 333208436Smav /* Search for HPET table. */ 334208436Smav status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 335208436Smav if (ACPI_FAILURE(status)) 336208436Smav return; 337208436Smav /* Search for HPET device with same ID. */ 338258164Smav child = NULL; 339208436Smav AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 340258164Smav 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, 341258164Smav (void *)&child); 342208436Smav /* If found - let it be probed in normal way. */ 343258164Smav if (child) { 344258164Smav if (bus_get_resource(child, SYS_RES_MEMORY, 0, 345258164Smav NULL, NULL) != 0) 346258164Smav bus_set_resource(child, SYS_RES_MEMORY, 0, 347258164Smav hpet->Address.Address, HPET_MEM_WIDTH); 348208436Smav continue; 349258164Smav } 350208436Smav /* If not - create it from table info. */ 351231161Sjkim child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 352208436Smav if (child == NULL) { 353208436Smav printf("%s: can't add child\n", __func__); 354208436Smav continue; 355208436Smav } 356208436Smav bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 357208436Smav HPET_MEM_WIDTH); 358169574Stakawata } 359169574Stakawata} 360169574Stakawata 361151912Sphkstatic int 362209371Smavhpet_probe(device_t dev) 363151912Sphk{ 364159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 365159217Snjl 366269515Sroyger if (acpi_disabled("hpet") || acpi_hpet_disabled) 367151912Sphk return (ENXIO); 368199016Savg if (acpi_get_handle(dev) != NULL && 369208436Smav ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 370169592Snjl return (ENXIO); 371151912Sphk 372159217Snjl device_set_desc(dev, "High Precision Event Timer"); 373151912Sphk return (0); 374151912Sphk} 375151912Sphk 376151912Sphkstatic int 377209371Smavhpet_attach(device_t dev) 378151912Sphk{ 379209371Smav struct hpet_softc *sc; 380209371Smav struct hpet_timer *t; 381209371Smav int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 382209371Smav int pcpu_master; 383209371Smav static int maxhpetet = 0; 384212238Smav uint32_t val, val2, cvectors, dvectors; 385209371Smav uint16_t vendor, rev; 386151912Sphk 387151912Sphk ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 388151912Sphk 389151912Sphk sc = device_get_softc(dev); 390151912Sphk sc->dev = dev; 391151912Sphk sc->handle = acpi_get_handle(dev); 392151912Sphk 393209371Smav sc->mem_rid = 0; 394209371Smav sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 395159217Snjl RF_ACTIVE); 396159217Snjl if (sc->mem_res == NULL) 397159217Snjl return (ENOMEM); 398151912Sphk 399159217Snjl /* Validate that we can access the whole region. */ 400159217Snjl if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 401159217Snjl device_printf(dev, "memory region width %ld too small\n", 402159217Snjl rman_get_size(sc->mem_res)); 403159217Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 404159217Snjl return (ENXIO); 405159217Snjl } 406151912Sphk 407171547Snjl /* Be sure timer is enabled. */ 408175361Sjhb hpet_enable(sc); 409171547Snjl 410159217Snjl /* Read basic statistics about the timer. */ 411175385Sjhb val = bus_read_4(sc->mem_res, HPET_PERIOD); 412175361Sjhb if (val == 0) { 413175361Sjhb device_printf(dev, "invalid period\n"); 414175361Sjhb hpet_disable(sc); 415175361Sjhb bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 416175361Sjhb return (ENXIO); 417175361Sjhb } 418175361Sjhb 419209371Smav sc->freq = (1000000000000000LL + val / 2) / val; 420209440Smav sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 421209440Smav vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 422209440Smav rev = sc->caps & HPET_CAP_REV_ID; 423209440Smav num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 424209371Smav /* 425209371Smav * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 426209371Smav * Specification and provides an off by one number 427209371Smav * of timers/comparators. 428209371Smav * Additionally, they use unregistered value in VENDOR_ID field. 429209371Smav */ 430209371Smav if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 431209371Smav num_timers--; 432209371Smav sc->num_timers = num_timers; 433159217Snjl if (bootverbose) { 434159217Snjl device_printf(dev, 435209371Smav "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 436209440Smav vendor, rev, sc->freq, 437209440Smav (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 438209440Smav num_timers, 439209440Smav (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 440159217Snjl } 441209371Smav for (i = 0; i < num_timers; i++) { 442209371Smav t = &sc->t[i]; 443209371Smav t->sc = sc; 444209371Smav t->num = i; 445209371Smav t->mode = 0; 446209371Smav t->intr_rid = -1; 447209371Smav t->irq = -1; 448212323Smav t->pcpu_cpu = -1; 449212323Smav t->pcpu_misrouted = 0; 450209371Smav t->pcpu_master = -1; 451209371Smav t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 452209371Smav t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 453209371Smav if (bootverbose) { 454209371Smav device_printf(dev, 455209371Smav " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 456209371Smav t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 457209371Smav (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 458209371Smav (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 459209371Smav (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 460209371Smav } 461209371Smav } 462159217Snjl if (testenv("debug.acpi.hpet_test")) 463209371Smav hpet_test(sc); 464171547Snjl /* 465171547Snjl * Don't attach if the timer never increments. Since the spec 466171547Snjl * requires it to be at least 10 MHz, it has to change in 1 us. 467171547Snjl */ 468175385Sjhb val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 469171547Snjl DELAY(1); 470175385Sjhb val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 471171547Snjl if (val == val2) { 472171547Snjl device_printf(dev, "HPET never increments, disabling\n"); 473175361Sjhb hpet_disable(sc); 474171547Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 475171547Snjl return (ENXIO); 476171547Snjl } 477208436Smav /* Announce first HPET as timecounter. */ 478208436Smav if (device_get_unit(dev) == 0) { 479209371Smav sc->tc.tc_get_timecount = hpet_get_timecount, 480209371Smav sc->tc.tc_counter_mask = ~0u, 481209371Smav sc->tc.tc_name = "HPET", 482222222Sjkim sc->tc.tc_quality = 950, 483209371Smav sc->tc.tc_frequency = sc->freq; 484209371Smav sc->tc.tc_priv = sc; 485209371Smav tc_init(&sc->tc); 486208436Smav } 487209371Smav /* If not disabled - setup and announce event timers. */ 488209371Smav if (resource_int_value(device_get_name(dev), device_get_unit(dev), 489209371Smav "clock", &i) == 0 && i == 0) 490209371Smav return (0); 491209440Smav 492209440Smav /* Check whether we can and want legacy routing. */ 493209440Smav sc->legacy_route = 0; 494209440Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 495209440Smav "legacy_route", &sc->legacy_route); 496209440Smav if ((sc->caps & HPET_CAP_LEG_RT) == 0) 497209440Smav sc->legacy_route = 0; 498209440Smav if (sc->legacy_route) { 499209440Smav sc->t[0].vectors = 0; 500209440Smav sc->t[1].vectors = 0; 501209440Smav } 502209440Smav 503212238Smav /* Check what IRQs we want use. */ 504212238Smav /* By default allow any PCI IRQs. */ 505212238Smav sc->allowed_irqs = 0xffff0000; 506209371Smav /* 507209371Smav * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 508209371Smav * Lower are also not always working for different reasons. 509209371Smav * SB800 fixed it, but seems do not implements level triggering 510209371Smav * properly, that makes it very unreliable - it freezes after any 511209371Smav * interrupt loss. Avoid legacy IRQs for AMD. 512209371Smav */ 513240286Smav if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2) 514212238Smav sc->allowed_irqs = 0x00000000; 515212238Smav /* 516213302Smav * NVidia MCP5x chipsets have number of unexplained interrupt 517213302Smav * problems. For some reason, using HPET interrupts breaks HDA sound. 518213302Smav */ 519213302Smav if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 520213302Smav sc->allowed_irqs = 0x00000000; 521213302Smav /* 522232797Smav * ServerWorks HT1000 reported to have problems with IRQs >= 16. 523232797Smav * Lower IRQs are working, but allowed mask is not set correctly. 524232797Smav * Legacy_route mode works fine. 525232797Smav */ 526232797Smav if (vendor == HPET_VENDID_SW && rev <= 0x01) 527232797Smav sc->allowed_irqs = 0x00000000; 528232797Smav /* 529212238Smav * Neither QEMU nor VirtualBox report supported IRQs correctly. 530212238Smav * The only way to use HPET there is to specify IRQs manually 531215473Sjhb * and/or use legacy_route. Legacy_route mode works on both. 532212238Smav */ 533212238Smav if (vm_guest) 534212238Smav sc->allowed_irqs = 0x00000000; 535212238Smav /* Let user override. */ 536212238Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 537212238Smav "allowed_irqs", &sc->allowed_irqs); 538212238Smav 539212533Smav /* Get how much per-CPU timers we should try to provide. */ 540212533Smav sc->per_cpu = 1; 541212533Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 542212533Smav "per_cpu", &sc->per_cpu); 543212533Smav 544212238Smav num_msi = 0; 545212238Smav sc->useirq = 0; 546212238Smav /* Find IRQ vectors for all timers. */ 547212238Smav cvectors = sc->allowed_irqs & 0xffff0000; 548212238Smav dvectors = sc->allowed_irqs & 0x0000ffff; 549212238Smav if (sc->legacy_route) 550212238Smav dvectors &= 0x0000fefe; 551209371Smav for (i = 0; i < num_timers; i++) { 552209371Smav t = &sc->t[i]; 553209440Smav if (sc->legacy_route && i < 2) 554209440Smav t->irq = (i == 0) ? 0 : 8; 555209371Smav#ifdef DEV_APIC 556209440Smav else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 557209371Smav if ((j = PCIB_ALLOC_MSIX( 558209371Smav device_get_parent(device_get_parent(dev)), dev, 559209371Smav &t->irq))) { 560209371Smav device_printf(dev, 561269897Sneel "Can't allocate interrupt for t%d: %d\n", 562269897Sneel i, j); 563209440Smav } 564209440Smav } 565209440Smav#endif 566212238Smav else if (dvectors & t->vectors) { 567212238Smav t->irq = ffs(dvectors & t->vectors) - 1; 568212238Smav dvectors &= ~(1 << t->irq); 569212238Smav } 570209440Smav if (t->irq >= 0) { 571216263Sjhb t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 572216490Sjhb t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 573216490Sjhb &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 574216490Sjhb if (t->intr_res == NULL) { 575209440Smav t->irq = -1; 576209440Smav device_printf(dev, 577209440Smav "Can't map interrupt for t%d.\n", i); 578216490Sjhb } else if (bus_setup_intr(dev, t->intr_res, 579216490Sjhb INTR_TYPE_CLK, hpet_intr_single, NULL, t, 580216490Sjhb &t->intr_handle) != 0) { 581209440Smav t->irq = -1; 582209440Smav device_printf(dev, 583209440Smav "Can't setup interrupt for t%d.\n", i); 584209371Smav } else { 585209371Smav bus_describe_intr(dev, t->intr_res, 586209371Smav t->intr_handle, "t%d", i); 587209371Smav num_msi++; 588209371Smav } 589209440Smav } 590209440Smav if (t->irq < 0 && (cvectors & t->vectors) != 0) { 591209371Smav cvectors &= t->vectors; 592209371Smav sc->useirq |= (1 << i); 593209371Smav } 594209371Smav } 595209440Smav if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 596209440Smav sc->legacy_route = 0; 597209440Smav if (sc->legacy_route) 598209440Smav hpet_enable(sc); 599209440Smav /* Group timers for per-CPU operation. */ 600212533Smav num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 601209440Smav num_percpu_t = num_percpu_et * mp_ncpus; 602209440Smav pcpu_master = 0; 603209440Smav cur_cpu = CPU_FIRST(); 604209440Smav for (i = 0; i < num_timers; i++) { 605209440Smav t = &sc->t[i]; 606209440Smav if (t->irq >= 0 && num_percpu_t > 0) { 607209440Smav if (cur_cpu == CPU_FIRST()) 608209440Smav pcpu_master = i; 609212323Smav t->pcpu_cpu = cur_cpu; 610209440Smav t->pcpu_master = pcpu_master; 611209440Smav sc->t[pcpu_master]. 612209440Smav pcpu_slaves[cur_cpu] = i; 613209440Smav bus_bind_intr(dev, t->intr_res, cur_cpu); 614209440Smav cur_cpu = CPU_NEXT(cur_cpu); 615209440Smav num_percpu_t--; 616212238Smav } else if (t->irq >= 0) 617212238Smav bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 618209440Smav } 619209371Smav bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 620209371Smav sc->irq = -1; 621215473Sjhb /* If at least one timer needs legacy IRQ - set it up. */ 622209371Smav if (sc->useirq) { 623209371Smav j = i = fls(cvectors) - 1; 624209371Smav while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 625209371Smav j--; 626216263Sjhb sc->intr_rid = hpet_find_irq_rid(dev, j, i); 627216490Sjhb sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 628216490Sjhb &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 629216490Sjhb if (sc->intr_res == NULL) 630216490Sjhb device_printf(dev, "Can't map interrupt.\n"); 631216490Sjhb else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 632216490Sjhb hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 633209371Smav device_printf(dev, "Can't setup interrupt.\n"); 634209371Smav } else { 635209371Smav sc->irq = rman_get_start(sc->intr_res); 636209371Smav /* Bind IRQ to BSP to avoid live migration. */ 637209371Smav bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 638209371Smav } 639209371Smav } 640209371Smav /* Program and announce event timers. */ 641209371Smav for (i = 0; i < num_timers; i++) { 642209371Smav t = &sc->t[i]; 643209371Smav t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 644209371Smav t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 645209440Smav t->caps &= ~(HPET_TCNF_INT_TYPE); 646209371Smav t->caps |= HPET_TCNF_32MODE; 647209440Smav if (t->irq >= 0 && sc->legacy_route && i < 2) { 648209440Smav /* Legacy route doesn't need more configuration. */ 649209440Smav } else 650209371Smav#ifdef DEV_APIC 651212238Smav if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 652209371Smav uint64_t addr; 653209371Smav uint32_t data; 654209371Smav 655209371Smav if (PCIB_MAP_MSI( 656209371Smav device_get_parent(device_get_parent(dev)), dev, 657209371Smav t->irq, &addr, &data) == 0) { 658209371Smav bus_write_4(sc->mem_res, 659209371Smav HPET_TIMER_FSB_ADDR(i), addr); 660209371Smav bus_write_4(sc->mem_res, 661209371Smav HPET_TIMER_FSB_VAL(i), data); 662209371Smav t->caps |= HPET_TCNF_FSB_EN; 663209371Smav } else 664209371Smav t->irq = -2; 665209371Smav } else 666209371Smav#endif 667212238Smav if (t->irq >= 0) 668212238Smav t->caps |= (t->irq << 9); 669212238Smav else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 670209371Smav t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 671209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 672209371Smav /* Skip event timers without set up IRQ. */ 673209371Smav if (t->irq < 0 && 674209371Smav (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 675209371Smav continue; 676209371Smav /* Announce the reset. */ 677209371Smav if (maxhpetet == 0) 678209371Smav t->et.et_name = "HPET"; 679209371Smav else { 680209371Smav sprintf(t->name, "HPET%d", maxhpetet); 681209371Smav t->et.et_name = t->name; 682209371Smav } 683209371Smav t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 684209371Smav t->et.et_quality = 450; 685209371Smav if (t->pcpu_master >= 0) { 686209371Smav t->et.et_flags |= ET_FLAGS_PERCPU; 687209371Smav t->et.et_quality += 100; 688248170Smav } else if (mp_ncpus >= 8) 689248154Smav t->et.et_quality -= 100; 690209371Smav if ((t->caps & HPET_TCAP_PER_INT) == 0) 691209371Smav t->et.et_quality -= 10; 692209371Smav t->et.et_frequency = sc->freq; 693247463Smav t->et.et_min_period = 694247463Smav ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; 695247463Smav t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; 696209371Smav t->et.et_start = hpet_start; 697209371Smav t->et.et_stop = hpet_stop; 698209371Smav t->et.et_priv = &sc->t[i]; 699209371Smav if (t->pcpu_master < 0 || t->pcpu_master == i) { 700209371Smav et_register(&t->et); 701209371Smav maxhpetet++; 702209371Smav } 703209371Smav } 704159217Snjl return (0); 705159217Snjl} 706159217Snjl 707159217Snjlstatic int 708209371Smavhpet_detach(device_t dev) 709159217Snjl{ 710159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 711159217Snjl 712159217Snjl /* XXX Without a tc_remove() function, we can't detach. */ 713159217Snjl return (EBUSY); 714159217Snjl} 715159217Snjl 716168010Snjlstatic int 717209371Smavhpet_suspend(device_t dev) 718175361Sjhb{ 719212541Smav// struct hpet_softc *sc; 720175361Sjhb 721175361Sjhb /* 722175361Sjhb * Disable the timer during suspend. The timer will not lose 723175361Sjhb * its state in S1 or S2, but we are required to disable 724175361Sjhb * it. 725175361Sjhb */ 726212541Smav// sc = device_get_softc(dev); 727212541Smav// hpet_disable(sc); 728175361Sjhb 729175361Sjhb return (0); 730175361Sjhb} 731175361Sjhb 732175361Sjhbstatic int 733209371Smavhpet_resume(device_t dev) 734168010Snjl{ 735209371Smav struct hpet_softc *sc; 736209371Smav struct hpet_timer *t; 737209371Smav int i; 738168010Snjl 739168010Snjl /* Re-enable the timer after a resume to keep the clock advancing. */ 740168010Snjl sc = device_get_softc(dev); 741175361Sjhb hpet_enable(sc); 742209371Smav /* Restart event timers that were running on suspend. */ 743209371Smav for (i = 0; i < sc->num_timers; i++) { 744209371Smav t = &sc->t[i]; 745209371Smav#ifdef DEV_APIC 746209440Smav if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 747209371Smav uint64_t addr; 748209371Smav uint32_t data; 749209371Smav 750209371Smav if (PCIB_MAP_MSI( 751209371Smav device_get_parent(device_get_parent(dev)), dev, 752209371Smav t->irq, &addr, &data) == 0) { 753209371Smav bus_write_4(sc->mem_res, 754209371Smav HPET_TIMER_FSB_ADDR(i), addr); 755209371Smav bus_write_4(sc->mem_res, 756209371Smav HPET_TIMER_FSB_VAL(i), data); 757209371Smav } 758209371Smav } 759209371Smav#endif 760209371Smav if (t->mode == 0) 761209371Smav continue; 762212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 763209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 764209371Smav t->caps |= HPET_TCNF_TYPE; 765212491Smav t->next += t->div; 766209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 767209371Smav t->caps | HPET_TCNF_VAL_SET); 768209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 769212491Smav t->next); 770209371Smav bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 771209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 772209371Smav t->div); 773209371Smav } else { 774212491Smav t->next += sc->freq / 1024; 775209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 776212491Smav t->next); 777209371Smav } 778209371Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 779209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 780209371Smav } 781168010Snjl return (0); 782168010Snjl} 783168010Snjl 784159217Snjl/* Print some basic latency/rate information to assist in debugging. */ 785159217Snjlstatic void 786209371Smavhpet_test(struct hpet_softc *sc) 787159217Snjl{ 788151912Sphk int i; 789151912Sphk uint32_t u1, u2; 790151912Sphk struct bintime b0, b1, b2; 791151912Sphk struct timespec ts; 792151912Sphk 793151912Sphk binuptime(&b0); 794151912Sphk binuptime(&b0); 795151912Sphk binuptime(&b1); 796175385Sjhb u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 797151912Sphk for (i = 1; i < 1000; i++) 798175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 799151912Sphk binuptime(&b2); 800175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 801151912Sphk 802151912Sphk bintime_sub(&b2, &b1); 803151912Sphk bintime_sub(&b1, &b0); 804151912Sphk bintime_sub(&b2, &b1); 805151912Sphk bintime2timespec(&b2, &ts); 806151912Sphk 807159217Snjl device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 808151912Sphk (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 809151912Sphk 810159217Snjl device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 811151912Sphk} 812151912Sphk 813209371Smav#ifdef DEV_APIC 814209371Smavstatic int 815209371Smavhpet_remap_intr(device_t dev, device_t child, u_int irq) 816209371Smav{ 817209371Smav struct hpet_softc *sc = device_get_softc(dev); 818209371Smav struct hpet_timer *t; 819209371Smav uint64_t addr; 820209371Smav uint32_t data; 821209371Smav int error, i; 822209371Smav 823209371Smav for (i = 0; i < sc->num_timers; i++) { 824209371Smav t = &sc->t[i]; 825209371Smav if (t->irq != irq) 826209371Smav continue; 827209371Smav error = PCIB_MAP_MSI( 828209371Smav device_get_parent(device_get_parent(dev)), dev, 829209371Smav irq, &addr, &data); 830209371Smav if (error) 831209371Smav return (error); 832209371Smav hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 833209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 834209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 835209371Smav hpet_enable(sc); 836209371Smav return (0); 837209371Smav } 838209371Smav return (ENOENT); 839209371Smav} 840209371Smav#endif 841209371Smav 842209371Smavstatic device_method_t hpet_methods[] = { 843151912Sphk /* Device interface */ 844209371Smav DEVMETHOD(device_identify, hpet_identify), 845209371Smav DEVMETHOD(device_probe, hpet_probe), 846209371Smav DEVMETHOD(device_attach, hpet_attach), 847209371Smav DEVMETHOD(device_detach, hpet_detach), 848209371Smav DEVMETHOD(device_suspend, hpet_suspend), 849209371Smav DEVMETHOD(device_resume, hpet_resume), 850151912Sphk 851209371Smav#ifdef DEV_APIC 852209371Smav DEVMETHOD(bus_remap_intr, hpet_remap_intr), 853209371Smav#endif 854209371Smav 855246128Ssbz DEVMETHOD_END 856151912Sphk}; 857151912Sphk 858209371Smavstatic driver_t hpet_driver = { 859209371Smav "hpet", 860209371Smav hpet_methods, 861209371Smav sizeof(struct hpet_softc), 862151912Sphk}; 863151912Sphk 864209371SmavDRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 865209371SmavMODULE_DEPEND(hpet, acpi, 1, 1, 1); 866