acpi_hpet.c revision 258164
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 258164 2013-11-15 11:32:19Z mav $"); 30 31#include "opt_acpi.h" 32#if defined(__amd64__) || defined(__ia64__) 33#define DEV_APIC 34#else 35#include "opt_apic.h" 36#endif 37#include <sys/param.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/proc.h> 42#include <sys/rman.h> 43#include <sys/time.h> 44#include <sys/smp.h> 45#include <sys/sysctl.h> 46#include <sys/timeet.h> 47#include <sys/timetc.h> 48 49#include <contrib/dev/acpica/include/acpi.h> 50#include <contrib/dev/acpica/include/accommon.h> 51 52#include <dev/acpica/acpivar.h> 53#include <dev/acpica/acpi_hpet.h> 54 55#ifdef DEV_APIC 56#include "pcib_if.h" 57#endif 58 59#define HPET_VENDID_AMD 0x4353 60#define HPET_VENDID_AMD2 0x1022 61#define HPET_VENDID_INTEL 0x8086 62#define HPET_VENDID_NVIDIA 0x10de 63#define HPET_VENDID_SW 0x1166 64 65ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 66 67static devclass_t hpet_devclass; 68 69/* ACPI CA debugging */ 70#define _COMPONENT ACPI_TIMER 71ACPI_MODULE_NAME("HPET") 72 73struct hpet_softc { 74 device_t dev; 75 int mem_rid; 76 int intr_rid; 77 int irq; 78 int useirq; 79 int legacy_route; 80 int per_cpu; 81 uint32_t allowed_irqs; 82 struct resource *mem_res; 83 struct resource *intr_res; 84 void *intr_handle; 85 ACPI_HANDLE handle; 86 uint64_t freq; 87 uint32_t caps; 88 struct timecounter tc; 89 struct hpet_timer { 90 struct eventtimer et; 91 struct hpet_softc *sc; 92 int num; 93 int mode; 94 int intr_rid; 95 int irq; 96 int pcpu_cpu; 97 int pcpu_misrouted; 98 int pcpu_master; 99 int pcpu_slaves[MAXCPU]; 100 struct resource *intr_res; 101 void *intr_handle; 102 uint32_t caps; 103 uint32_t vectors; 104 uint32_t div; 105 uint32_t next; 106 char name[8]; 107 } t[32]; 108 int num_timers; 109}; 110 111static u_int hpet_get_timecount(struct timecounter *tc); 112static void hpet_test(struct hpet_softc *sc); 113 114static char *hpet_ids[] = { "PNP0103", NULL }; 115 116static u_int 117hpet_get_timecount(struct timecounter *tc) 118{ 119 struct hpet_softc *sc; 120 121 sc = tc->tc_priv; 122 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 123} 124 125static void 126hpet_enable(struct hpet_softc *sc) 127{ 128 uint32_t val; 129 130 val = bus_read_4(sc->mem_res, HPET_CONFIG); 131 if (sc->legacy_route) 132 val |= HPET_CNF_LEG_RT; 133 else 134 val &= ~HPET_CNF_LEG_RT; 135 val |= HPET_CNF_ENABLE; 136 bus_write_4(sc->mem_res, HPET_CONFIG, val); 137} 138 139static void 140hpet_disable(struct hpet_softc *sc) 141{ 142 uint32_t val; 143 144 val = bus_read_4(sc->mem_res, HPET_CONFIG); 145 val &= ~HPET_CNF_ENABLE; 146 bus_write_4(sc->mem_res, HPET_CONFIG, val); 147} 148 149static int 150hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 151{ 152 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 153 struct hpet_timer *t; 154 struct hpet_softc *sc = mt->sc; 155 uint32_t fdiv, now; 156 157 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 158 if (period != 0) { 159 t->mode = 1; 160 t->div = (sc->freq * period) >> 32; 161 } else { 162 t->mode = 2; 163 t->div = 0; 164 } 165 if (first != 0) 166 fdiv = (sc->freq * first) >> 32; 167 else 168 fdiv = t->div; 169 if (t->irq < 0) 170 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 171 t->caps |= HPET_TCNF_INT_ENB; 172 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 173restart: 174 t->next = now + fdiv; 175 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 176 t->caps |= HPET_TCNF_TYPE; 177 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 178 t->caps | HPET_TCNF_VAL_SET); 179 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 180 t->next); 181 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 182 t->div); 183 } else { 184 t->caps &= ~HPET_TCNF_TYPE; 185 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 186 t->caps); 187 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 188 t->next); 189 } 190 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 191 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 192 fdiv *= 2; 193 goto restart; 194 } 195 return (0); 196} 197 198static int 199hpet_stop(struct eventtimer *et) 200{ 201 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 202 struct hpet_timer *t; 203 struct hpet_softc *sc = mt->sc; 204 205 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 206 t->mode = 0; 207 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 208 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 209 return (0); 210} 211 212static int 213hpet_intr_single(void *arg) 214{ 215 struct hpet_timer *t = (struct hpet_timer *)arg; 216 struct hpet_timer *mt; 217 struct hpet_softc *sc = t->sc; 218 uint32_t now; 219 220 if (t->mode == 0) 221 return (FILTER_STRAY); 222 /* Check that per-CPU timer interrupt reached right CPU. */ 223 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 224 if ((++t->pcpu_misrouted) % 32 == 0) { 225 printf("HPET interrupt routed to the wrong CPU" 226 " (timer %d CPU %d -> %d)!\n", 227 t->num, t->pcpu_cpu, curcpu); 228 } 229 230 /* 231 * Reload timer, hoping that next time may be more lucky 232 * (system will manage proper interrupt binding). 233 */ 234 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 235 t->mode == 2) { 236 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 237 sc->freq / 8; 238 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 239 t->next); 240 } 241 return (FILTER_HANDLED); 242 } 243 if (t->mode == 1 && 244 (t->caps & HPET_TCAP_PER_INT) == 0) { 245 t->next += t->div; 246 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 247 if ((int32_t)((now + t->div / 2) - t->next) > 0) 248 t->next = now + t->div / 2; 249 bus_write_4(sc->mem_res, 250 HPET_TIMER_COMPARATOR(t->num), t->next); 251 } else if (t->mode == 2) 252 t->mode = 0; 253 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 254 if (mt->et.et_active) 255 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 256 return (FILTER_HANDLED); 257} 258 259static int 260hpet_intr(void *arg) 261{ 262 struct hpet_softc *sc = (struct hpet_softc *)arg; 263 int i; 264 uint32_t val; 265 266 val = bus_read_4(sc->mem_res, HPET_ISR); 267 if (val) { 268 bus_write_4(sc->mem_res, HPET_ISR, val); 269 val &= sc->useirq; 270 for (i = 0; i < sc->num_timers; i++) { 271 if ((val & (1 << i)) == 0) 272 continue; 273 hpet_intr_single(&sc->t[i]); 274 } 275 return (FILTER_HANDLED); 276 } 277 return (FILTER_STRAY); 278} 279 280static ACPI_STATUS 281hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 282 void **status) 283{ 284 char **ids; 285 uint32_t id = (uint32_t)(uintptr_t)context; 286 uint32_t uid = 0; 287 288 for (ids = hpet_ids; *ids != NULL; ids++) { 289 if (acpi_MatchHid(handle, *ids)) 290 break; 291 } 292 if (*ids == NULL) 293 return (AE_OK); 294 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 295 id == uid) 296 *status = acpi_get_device(handle); 297 return (AE_OK); 298} 299 300/* 301 * Find an existing IRQ resource that matches the requested IRQ range 302 * and return its RID. If one is not found, use a new RID. 303 */ 304static int 305hpet_find_irq_rid(device_t dev, u_long start, u_long end) 306{ 307 u_long irq; 308 int error, rid; 309 310 for (rid = 0;; rid++) { 311 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 312 if (error != 0 || (start <= irq && irq <= end)) 313 return (rid); 314 } 315} 316 317/* Discover the HPET via the ACPI table of the same name. */ 318static void 319hpet_identify(driver_t *driver, device_t parent) 320{ 321 ACPI_TABLE_HPET *hpet; 322 ACPI_STATUS status; 323 device_t child; 324 int i; 325 326 /* Only one HPET device can be added. */ 327 if (devclass_get_device(hpet_devclass, 0)) 328 return; 329 for (i = 1; ; i++) { 330 /* Search for HPET table. */ 331 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 332 if (ACPI_FAILURE(status)) 333 return; 334 /* Search for HPET device with same ID. */ 335 child = NULL; 336 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 337 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, 338 (void *)&child); 339 /* If found - let it be probed in normal way. */ 340 if (child) { 341 if (bus_get_resource(child, SYS_RES_MEMORY, 0, 342 NULL, NULL) != 0) 343 bus_set_resource(child, SYS_RES_MEMORY, 0, 344 hpet->Address.Address, HPET_MEM_WIDTH); 345 continue; 346 } 347 /* If not - create it from table info. */ 348 child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 349 if (child == NULL) { 350 printf("%s: can't add child\n", __func__); 351 continue; 352 } 353 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 354 HPET_MEM_WIDTH); 355 } 356} 357 358static int 359hpet_probe(device_t dev) 360{ 361 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 362 363 if (acpi_disabled("hpet")) 364 return (ENXIO); 365 if (acpi_get_handle(dev) != NULL && 366 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 367 return (ENXIO); 368 369 device_set_desc(dev, "High Precision Event Timer"); 370 return (0); 371} 372 373static int 374hpet_attach(device_t dev) 375{ 376 struct hpet_softc *sc; 377 struct hpet_timer *t; 378 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 379 int pcpu_master; 380 static int maxhpetet = 0; 381 uint32_t val, val2, cvectors, dvectors; 382 uint16_t vendor, rev; 383 384 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 385 386 sc = device_get_softc(dev); 387 sc->dev = dev; 388 sc->handle = acpi_get_handle(dev); 389 390 sc->mem_rid = 0; 391 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 392 RF_ACTIVE); 393 if (sc->mem_res == NULL) 394 return (ENOMEM); 395 396 /* Validate that we can access the whole region. */ 397 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 398 device_printf(dev, "memory region width %ld too small\n", 399 rman_get_size(sc->mem_res)); 400 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 401 return (ENXIO); 402 } 403 404 /* Be sure timer is enabled. */ 405 hpet_enable(sc); 406 407 /* Read basic statistics about the timer. */ 408 val = bus_read_4(sc->mem_res, HPET_PERIOD); 409 if (val == 0) { 410 device_printf(dev, "invalid period\n"); 411 hpet_disable(sc); 412 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 413 return (ENXIO); 414 } 415 416 sc->freq = (1000000000000000LL + val / 2) / val; 417 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 418 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 419 rev = sc->caps & HPET_CAP_REV_ID; 420 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 421 /* 422 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 423 * Specification and provides an off by one number 424 * of timers/comparators. 425 * Additionally, they use unregistered value in VENDOR_ID field. 426 */ 427 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 428 num_timers--; 429 sc->num_timers = num_timers; 430 if (bootverbose) { 431 device_printf(dev, 432 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 433 vendor, rev, sc->freq, 434 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 435 num_timers, 436 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 437 } 438 for (i = 0; i < num_timers; i++) { 439 t = &sc->t[i]; 440 t->sc = sc; 441 t->num = i; 442 t->mode = 0; 443 t->intr_rid = -1; 444 t->irq = -1; 445 t->pcpu_cpu = -1; 446 t->pcpu_misrouted = 0; 447 t->pcpu_master = -1; 448 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 449 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 450 if (bootverbose) { 451 device_printf(dev, 452 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 453 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 454 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 455 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 456 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 457 } 458 } 459 if (testenv("debug.acpi.hpet_test")) 460 hpet_test(sc); 461 /* 462 * Don't attach if the timer never increments. Since the spec 463 * requires it to be at least 10 MHz, it has to change in 1 us. 464 */ 465 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 466 DELAY(1); 467 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 468 if (val == val2) { 469 device_printf(dev, "HPET never increments, disabling\n"); 470 hpet_disable(sc); 471 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 472 return (ENXIO); 473 } 474 /* Announce first HPET as timecounter. */ 475 if (device_get_unit(dev) == 0) { 476 sc->tc.tc_get_timecount = hpet_get_timecount, 477 sc->tc.tc_counter_mask = ~0u, 478 sc->tc.tc_name = "HPET", 479 sc->tc.tc_quality = 950, 480 sc->tc.tc_frequency = sc->freq; 481 sc->tc.tc_priv = sc; 482 tc_init(&sc->tc); 483 } 484 /* If not disabled - setup and announce event timers. */ 485 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 486 "clock", &i) == 0 && i == 0) 487 return (0); 488 489 /* Check whether we can and want legacy routing. */ 490 sc->legacy_route = 0; 491 resource_int_value(device_get_name(dev), device_get_unit(dev), 492 "legacy_route", &sc->legacy_route); 493 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 494 sc->legacy_route = 0; 495 if (sc->legacy_route) { 496 sc->t[0].vectors = 0; 497 sc->t[1].vectors = 0; 498 } 499 500 /* Check what IRQs we want use. */ 501 /* By default allow any PCI IRQs. */ 502 sc->allowed_irqs = 0xffff0000; 503 /* 504 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 505 * Lower are also not always working for different reasons. 506 * SB800 fixed it, but seems do not implements level triggering 507 * properly, that makes it very unreliable - it freezes after any 508 * interrupt loss. Avoid legacy IRQs for AMD. 509 */ 510 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2) 511 sc->allowed_irqs = 0x00000000; 512 /* 513 * NVidia MCP5x chipsets have number of unexplained interrupt 514 * problems. For some reason, using HPET interrupts breaks HDA sound. 515 */ 516 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 517 sc->allowed_irqs = 0x00000000; 518 /* 519 * ServerWorks HT1000 reported to have problems with IRQs >= 16. 520 * Lower IRQs are working, but allowed mask is not set correctly. 521 * Legacy_route mode works fine. 522 */ 523 if (vendor == HPET_VENDID_SW && rev <= 0x01) 524 sc->allowed_irqs = 0x00000000; 525 /* 526 * Neither QEMU nor VirtualBox report supported IRQs correctly. 527 * The only way to use HPET there is to specify IRQs manually 528 * and/or use legacy_route. Legacy_route mode works on both. 529 */ 530 if (vm_guest) 531 sc->allowed_irqs = 0x00000000; 532 /* Let user override. */ 533 resource_int_value(device_get_name(dev), device_get_unit(dev), 534 "allowed_irqs", &sc->allowed_irqs); 535 536 /* Get how much per-CPU timers we should try to provide. */ 537 sc->per_cpu = 1; 538 resource_int_value(device_get_name(dev), device_get_unit(dev), 539 "per_cpu", &sc->per_cpu); 540 541 num_msi = 0; 542 sc->useirq = 0; 543 /* Find IRQ vectors for all timers. */ 544 cvectors = sc->allowed_irqs & 0xffff0000; 545 dvectors = sc->allowed_irqs & 0x0000ffff; 546 if (sc->legacy_route) 547 dvectors &= 0x0000fefe; 548 for (i = 0; i < num_timers; i++) { 549 t = &sc->t[i]; 550 if (sc->legacy_route && i < 2) 551 t->irq = (i == 0) ? 0 : 8; 552#ifdef DEV_APIC 553 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 554 if ((j = PCIB_ALLOC_MSIX( 555 device_get_parent(device_get_parent(dev)), dev, 556 &t->irq))) { 557 device_printf(dev, 558 "Can't allocate interrupt for t%d.\n", j); 559 } 560 } 561#endif 562 else if (dvectors & t->vectors) { 563 t->irq = ffs(dvectors & t->vectors) - 1; 564 dvectors &= ~(1 << t->irq); 565 } 566 if (t->irq >= 0) { 567 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 568 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 569 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 570 if (t->intr_res == NULL) { 571 t->irq = -1; 572 device_printf(dev, 573 "Can't map interrupt for t%d.\n", i); 574 } else if (bus_setup_intr(dev, t->intr_res, 575 INTR_TYPE_CLK, hpet_intr_single, NULL, t, 576 &t->intr_handle) != 0) { 577 t->irq = -1; 578 device_printf(dev, 579 "Can't setup interrupt for t%d.\n", i); 580 } else { 581 bus_describe_intr(dev, t->intr_res, 582 t->intr_handle, "t%d", i); 583 num_msi++; 584 } 585 } 586 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 587 cvectors &= t->vectors; 588 sc->useirq |= (1 << i); 589 } 590 } 591 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 592 sc->legacy_route = 0; 593 if (sc->legacy_route) 594 hpet_enable(sc); 595 /* Group timers for per-CPU operation. */ 596 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 597 num_percpu_t = num_percpu_et * mp_ncpus; 598 pcpu_master = 0; 599 cur_cpu = CPU_FIRST(); 600 for (i = 0; i < num_timers; i++) { 601 t = &sc->t[i]; 602 if (t->irq >= 0 && num_percpu_t > 0) { 603 if (cur_cpu == CPU_FIRST()) 604 pcpu_master = i; 605 t->pcpu_cpu = cur_cpu; 606 t->pcpu_master = pcpu_master; 607 sc->t[pcpu_master]. 608 pcpu_slaves[cur_cpu] = i; 609 bus_bind_intr(dev, t->intr_res, cur_cpu); 610 cur_cpu = CPU_NEXT(cur_cpu); 611 num_percpu_t--; 612 } else if (t->irq >= 0) 613 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 614 } 615 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 616 sc->irq = -1; 617 /* If at least one timer needs legacy IRQ - set it up. */ 618 if (sc->useirq) { 619 j = i = fls(cvectors) - 1; 620 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 621 j--; 622 sc->intr_rid = hpet_find_irq_rid(dev, j, i); 623 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 624 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 625 if (sc->intr_res == NULL) 626 device_printf(dev, "Can't map interrupt.\n"); 627 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 628 hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 629 device_printf(dev, "Can't setup interrupt.\n"); 630 } else { 631 sc->irq = rman_get_start(sc->intr_res); 632 /* Bind IRQ to BSP to avoid live migration. */ 633 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 634 } 635 } 636 /* Program and announce event timers. */ 637 for (i = 0; i < num_timers; i++) { 638 t = &sc->t[i]; 639 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 640 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 641 t->caps &= ~(HPET_TCNF_INT_TYPE); 642 t->caps |= HPET_TCNF_32MODE; 643 if (t->irq >= 0 && sc->legacy_route && i < 2) { 644 /* Legacy route doesn't need more configuration. */ 645 } else 646#ifdef DEV_APIC 647 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 648 uint64_t addr; 649 uint32_t data; 650 651 if (PCIB_MAP_MSI( 652 device_get_parent(device_get_parent(dev)), dev, 653 t->irq, &addr, &data) == 0) { 654 bus_write_4(sc->mem_res, 655 HPET_TIMER_FSB_ADDR(i), addr); 656 bus_write_4(sc->mem_res, 657 HPET_TIMER_FSB_VAL(i), data); 658 t->caps |= HPET_TCNF_FSB_EN; 659 } else 660 t->irq = -2; 661 } else 662#endif 663 if (t->irq >= 0) 664 t->caps |= (t->irq << 9); 665 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 666 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 667 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 668 /* Skip event timers without set up IRQ. */ 669 if (t->irq < 0 && 670 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 671 continue; 672 /* Announce the reset. */ 673 if (maxhpetet == 0) 674 t->et.et_name = "HPET"; 675 else { 676 sprintf(t->name, "HPET%d", maxhpetet); 677 t->et.et_name = t->name; 678 } 679 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 680 t->et.et_quality = 450; 681 if (t->pcpu_master >= 0) { 682 t->et.et_flags |= ET_FLAGS_PERCPU; 683 t->et.et_quality += 100; 684 } else if (mp_ncpus >= 8) 685 t->et.et_quality -= 100; 686 if ((t->caps & HPET_TCAP_PER_INT) == 0) 687 t->et.et_quality -= 10; 688 t->et.et_frequency = sc->freq; 689 t->et.et_min_period = 690 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; 691 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; 692 t->et.et_start = hpet_start; 693 t->et.et_stop = hpet_stop; 694 t->et.et_priv = &sc->t[i]; 695 if (t->pcpu_master < 0 || t->pcpu_master == i) { 696 et_register(&t->et); 697 maxhpetet++; 698 } 699 } 700 return (0); 701} 702 703static int 704hpet_detach(device_t dev) 705{ 706 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 707 708 /* XXX Without a tc_remove() function, we can't detach. */ 709 return (EBUSY); 710} 711 712static int 713hpet_suspend(device_t dev) 714{ 715// struct hpet_softc *sc; 716 717 /* 718 * Disable the timer during suspend. The timer will not lose 719 * its state in S1 or S2, but we are required to disable 720 * it. 721 */ 722// sc = device_get_softc(dev); 723// hpet_disable(sc); 724 725 return (0); 726} 727 728static int 729hpet_resume(device_t dev) 730{ 731 struct hpet_softc *sc; 732 struct hpet_timer *t; 733 int i; 734 735 /* Re-enable the timer after a resume to keep the clock advancing. */ 736 sc = device_get_softc(dev); 737 hpet_enable(sc); 738 /* Restart event timers that were running on suspend. */ 739 for (i = 0; i < sc->num_timers; i++) { 740 t = &sc->t[i]; 741#ifdef DEV_APIC 742 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 743 uint64_t addr; 744 uint32_t data; 745 746 if (PCIB_MAP_MSI( 747 device_get_parent(device_get_parent(dev)), dev, 748 t->irq, &addr, &data) == 0) { 749 bus_write_4(sc->mem_res, 750 HPET_TIMER_FSB_ADDR(i), addr); 751 bus_write_4(sc->mem_res, 752 HPET_TIMER_FSB_VAL(i), data); 753 } 754 } 755#endif 756 if (t->mode == 0) 757 continue; 758 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 759 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 760 t->caps |= HPET_TCNF_TYPE; 761 t->next += t->div; 762 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 763 t->caps | HPET_TCNF_VAL_SET); 764 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 765 t->next); 766 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 767 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 768 t->div); 769 } else { 770 t->next += sc->freq / 1024; 771 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 772 t->next); 773 } 774 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 775 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 776 } 777 return (0); 778} 779 780/* Print some basic latency/rate information to assist in debugging. */ 781static void 782hpet_test(struct hpet_softc *sc) 783{ 784 int i; 785 uint32_t u1, u2; 786 struct bintime b0, b1, b2; 787 struct timespec ts; 788 789 binuptime(&b0); 790 binuptime(&b0); 791 binuptime(&b1); 792 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 793 for (i = 1; i < 1000; i++) 794 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 795 binuptime(&b2); 796 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 797 798 bintime_sub(&b2, &b1); 799 bintime_sub(&b1, &b0); 800 bintime_sub(&b2, &b1); 801 bintime2timespec(&b2, &ts); 802 803 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 804 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 805 806 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 807} 808 809#ifdef DEV_APIC 810static int 811hpet_remap_intr(device_t dev, device_t child, u_int irq) 812{ 813 struct hpet_softc *sc = device_get_softc(dev); 814 struct hpet_timer *t; 815 uint64_t addr; 816 uint32_t data; 817 int error, i; 818 819 for (i = 0; i < sc->num_timers; i++) { 820 t = &sc->t[i]; 821 if (t->irq != irq) 822 continue; 823 error = PCIB_MAP_MSI( 824 device_get_parent(device_get_parent(dev)), dev, 825 irq, &addr, &data); 826 if (error) 827 return (error); 828 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 829 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 830 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 831 hpet_enable(sc); 832 return (0); 833 } 834 return (ENOENT); 835} 836#endif 837 838static device_method_t hpet_methods[] = { 839 /* Device interface */ 840 DEVMETHOD(device_identify, hpet_identify), 841 DEVMETHOD(device_probe, hpet_probe), 842 DEVMETHOD(device_attach, hpet_attach), 843 DEVMETHOD(device_detach, hpet_detach), 844 DEVMETHOD(device_suspend, hpet_suspend), 845 DEVMETHOD(device_resume, hpet_resume), 846 847#ifdef DEV_APIC 848 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 849#endif 850 851 DEVMETHOD_END 852}; 853 854static driver_t hpet_driver = { 855 "hpet", 856 hpet_methods, 857 sizeof(struct hpet_softc), 858}; 859 860DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 861MODULE_DEPEND(hpet, acpi, 1, 1, 1); 862