acpi_hpet.c revision 247463
1151912Sphk/*- 2151912Sphk * Copyright (c) 2005 Poul-Henning Kamp 3209440Smav * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4151912Sphk * All rights reserved. 5151912Sphk * 6151912Sphk * Redistribution and use in source and binary forms, with or without 7151912Sphk * modification, are permitted provided that the following conditions 8151912Sphk * are met: 9151912Sphk * 1. Redistributions of source code must retain the above copyright 10151912Sphk * notice, this list of conditions and the following disclaimer. 11151912Sphk * 2. Redistributions in binary form must reproduce the above copyright 12151912Sphk * notice, this list of conditions and the following disclaimer in the 13151912Sphk * documentation and/or other materials provided with the distribution. 14151912Sphk * 15151912Sphk * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16151912Sphk * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17151912Sphk * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18151912Sphk * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19151912Sphk * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20151912Sphk * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21151912Sphk * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22151912Sphk * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23151912Sphk * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24151912Sphk * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25151912Sphk * SUCH DAMAGE. 26151912Sphk */ 27151912Sphk 28151912Sphk#include <sys/cdefs.h> 29151912Sphk__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 247463 2013-02-28 13:46:03Z mav $"); 30151912Sphk 31151912Sphk#include "opt_acpi.h" 32209402Smav#if defined(__amd64__) || defined(__ia64__) 33209371Smav#define DEV_APIC 34209371Smav#else 35209371Smav#include "opt_apic.h" 36209371Smav#endif 37151912Sphk#include <sys/param.h> 38159217Snjl#include <sys/bus.h> 39151912Sphk#include <sys/kernel.h> 40151912Sphk#include <sys/module.h> 41209371Smav#include <sys/proc.h> 42151912Sphk#include <sys/rman.h> 43151912Sphk#include <sys/time.h> 44209371Smav#include <sys/smp.h> 45209371Smav#include <sys/sysctl.h> 46209371Smav#include <sys/timeet.h> 47151912Sphk#include <sys/timetc.h> 48159217Snjl 49193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 50193530Sjkim#include <contrib/dev/acpica/include/accommon.h> 51193530Sjkim 52151912Sphk#include <dev/acpica/acpivar.h> 53175385Sjhb#include <dev/acpica/acpi_hpet.h> 54151912Sphk 55209371Smav#ifdef DEV_APIC 56209371Smav#include "pcib_if.h" 57209371Smav#endif 58209371Smav 59203062Savg#define HPET_VENDID_AMD 0x4353 60240286Smav#define HPET_VENDID_AMD2 0x1022 61203062Savg#define HPET_VENDID_INTEL 0x8086 62213302Smav#define HPET_VENDID_NVIDIA 0x10de 63232797Smav#define HPET_VENDID_SW 0x1166 64203062Savg 65151912SphkACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 66151912Sphk 67209371Smavstatic devclass_t hpet_devclass; 68169574Stakawata 69151931Sscottl/* ACPI CA debugging */ 70151935Sscottl#define _COMPONENT ACPI_TIMER 71151931SscottlACPI_MODULE_NAME("HPET") 72151931Sscottl 73209371Smavstruct hpet_softc { 74151912Sphk device_t dev; 75209371Smav int mem_rid; 76209371Smav int intr_rid; 77209371Smav int irq; 78209371Smav int useirq; 79209440Smav int legacy_route; 80212533Smav int per_cpu; 81212238Smav uint32_t allowed_irqs; 82159217Snjl struct resource *mem_res; 83209371Smav struct resource *intr_res; 84209371Smav void *intr_handle; 85151912Sphk ACPI_HANDLE handle; 86209371Smav uint64_t freq; 87209440Smav uint32_t caps; 88209371Smav struct timecounter tc; 89209371Smav struct hpet_timer { 90209371Smav struct eventtimer et; 91209371Smav struct hpet_softc *sc; 92209371Smav int num; 93209371Smav int mode; 94209371Smav int intr_rid; 95209371Smav int irq; 96212323Smav int pcpu_cpu; 97212323Smav int pcpu_misrouted; 98209371Smav int pcpu_master; 99209371Smav int pcpu_slaves[MAXCPU]; 100209371Smav struct resource *intr_res; 101209371Smav void *intr_handle; 102209371Smav uint32_t caps; 103209371Smav uint32_t vectors; 104209371Smav uint32_t div; 105212491Smav uint32_t next; 106209371Smav char name[8]; 107209371Smav } t[32]; 108209371Smav int num_timers; 109151912Sphk}; 110151912Sphk 111159217Snjlstatic u_int hpet_get_timecount(struct timecounter *tc); 112209371Smavstatic void hpet_test(struct hpet_softc *sc); 113151912Sphk 114159217Snjlstatic char *hpet_ids[] = { "PNP0103", NULL }; 115159217Snjl 116159217Snjlstatic u_int 117151912Sphkhpet_get_timecount(struct timecounter *tc) 118151912Sphk{ 119209371Smav struct hpet_softc *sc; 120151912Sphk 121151912Sphk sc = tc->tc_priv; 122175385Sjhb return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 123151912Sphk} 124151912Sphk 125175361Sjhbstatic void 126209371Smavhpet_enable(struct hpet_softc *sc) 127175361Sjhb{ 128175361Sjhb uint32_t val; 129175385Sjhb 130175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 131209440Smav if (sc->legacy_route) 132209440Smav val |= HPET_CNF_LEG_RT; 133209440Smav else 134209440Smav val &= ~HPET_CNF_LEG_RT; 135185103Sjkim val |= HPET_CNF_ENABLE; 136185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 137175361Sjhb} 138175361Sjhb 139175361Sjhbstatic void 140209371Smavhpet_disable(struct hpet_softc *sc) 141175361Sjhb{ 142175361Sjhb uint32_t val; 143175385Sjhb 144175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 145185103Sjkim val &= ~HPET_CNF_ENABLE; 146185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 147175361Sjhb} 148175361Sjhb 149209371Smavstatic int 150247463Smavhpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 151209371Smav{ 152209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 153209371Smav struct hpet_timer *t; 154209371Smav struct hpet_softc *sc = mt->sc; 155212491Smav uint32_t fdiv, now; 156209371Smav 157209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 158247463Smav if (period != 0) { 159209371Smav t->mode = 1; 160247463Smav t->div = (sc->freq * period) >> 32; 161209371Smav } else { 162209371Smav t->mode = 2; 163209371Smav t->div = 0; 164209371Smav } 165247463Smav if (first != 0) 166247463Smav fdiv = (sc->freq * first) >> 32; 167247463Smav else 168210290Smav fdiv = t->div; 169212238Smav if (t->irq < 0) 170212238Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 171212238Smav t->caps |= HPET_TCNF_INT_ENB; 172212491Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 173212238Smavrestart: 174212491Smav t->next = now + fdiv; 175209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 176209371Smav t->caps |= HPET_TCNF_TYPE; 177209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 178209371Smav t->caps | HPET_TCNF_VAL_SET); 179212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 180212491Smav t->next); 181212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 182212491Smav t->div); 183209371Smav } else { 184212238Smav t->caps &= ~HPET_TCNF_TYPE; 185212491Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 186212491Smav t->caps); 187212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 188212491Smav t->next); 189209371Smav } 190224919Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 191224919Smav if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 192224919Smav fdiv *= 2; 193224919Smav goto restart; 194212238Smav } 195209371Smav return (0); 196209371Smav} 197209371Smav 198209371Smavstatic int 199209371Smavhpet_stop(struct eventtimer *et) 200209371Smav{ 201209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 202209371Smav struct hpet_timer *t; 203209371Smav struct hpet_softc *sc = mt->sc; 204209371Smav 205209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 206209371Smav t->mode = 0; 207209371Smav t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 208209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 209209371Smav return (0); 210209371Smav} 211209371Smav 212209371Smavstatic int 213209371Smavhpet_intr_single(void *arg) 214209371Smav{ 215209371Smav struct hpet_timer *t = (struct hpet_timer *)arg; 216209371Smav struct hpet_timer *mt; 217209371Smav struct hpet_softc *sc = t->sc; 218209371Smav uint32_t now; 219209371Smav 220212491Smav if (t->mode == 0) 221212491Smav return (FILTER_STRAY); 222212323Smav /* Check that per-CPU timer interrupt reached right CPU. */ 223212323Smav if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 224212323Smav if ((++t->pcpu_misrouted) % 32 == 0) { 225212323Smav printf("HPET interrupt routed to the wrong CPU" 226212323Smav " (timer %d CPU %d -> %d)!\n", 227212323Smav t->num, t->pcpu_cpu, curcpu); 228212323Smav } 229212323Smav 230212323Smav /* 231212323Smav * Reload timer, hoping that next time may be more lucky 232212323Smav * (system will manage proper interrupt binding). 233212323Smav */ 234212323Smav if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 235212323Smav t->mode == 2) { 236212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 237212491Smav sc->freq / 8; 238212323Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 239212491Smav t->next); 240212323Smav } 241212323Smav return (FILTER_HANDLED); 242212323Smav } 243209371Smav if (t->mode == 1 && 244209371Smav (t->caps & HPET_TCAP_PER_INT) == 0) { 245212491Smav t->next += t->div; 246209371Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 247212491Smav if ((int32_t)((now + t->div / 2) - t->next) > 0) 248212491Smav t->next = now + t->div / 2; 249209371Smav bus_write_4(sc->mem_res, 250212491Smav HPET_TIMER_COMPARATOR(t->num), t->next); 251209371Smav } else if (t->mode == 2) 252209371Smav t->mode = 0; 253209371Smav mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 254209990Smav if (mt->et.et_active) 255209990Smav mt->et.et_event_cb(&mt->et, mt->et.et_arg); 256209371Smav return (FILTER_HANDLED); 257209371Smav} 258209371Smav 259209371Smavstatic int 260209371Smavhpet_intr(void *arg) 261209371Smav{ 262209371Smav struct hpet_softc *sc = (struct hpet_softc *)arg; 263209371Smav int i; 264209371Smav uint32_t val; 265209371Smav 266209371Smav val = bus_read_4(sc->mem_res, HPET_ISR); 267209371Smav if (val) { 268209371Smav bus_write_4(sc->mem_res, HPET_ISR, val); 269209371Smav val &= sc->useirq; 270209371Smav for (i = 0; i < sc->num_timers; i++) { 271209371Smav if ((val & (1 << i)) == 0) 272209371Smav continue; 273209371Smav hpet_intr_single(&sc->t[i]); 274209371Smav } 275209371Smav return (FILTER_HANDLED); 276209371Smav } 277209371Smav return (FILTER_STRAY); 278209371Smav} 279209371Smav 280208436Smavstatic ACPI_STATUS 281209371Smavhpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 282208436Smav void **status) 283208436Smav{ 284208436Smav char **ids; 285208436Smav uint32_t id = (uint32_t)(uintptr_t)context; 286208438Smav uint32_t uid = 0; 287208436Smav 288208436Smav for (ids = hpet_ids; *ids != NULL; ids++) { 289208436Smav if (acpi_MatchHid(handle, *ids)) 290208436Smav break; 291208436Smav } 292208436Smav if (*ids == NULL) 293208436Smav return (AE_OK); 294209371Smav if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 295209371Smav id == uid) 296208436Smav *((int *)status) = 1; 297208436Smav return (AE_OK); 298208436Smav} 299208436Smav 300216263Sjhb/* 301216263Sjhb * Find an existing IRQ resource that matches the requested IRQ range 302216263Sjhb * and return its RID. If one is not found, use a new RID. 303216263Sjhb */ 304216263Sjhbstatic int 305216263Sjhbhpet_find_irq_rid(device_t dev, u_long start, u_long end) 306216263Sjhb{ 307216263Sjhb u_long irq; 308216263Sjhb int error, rid; 309216263Sjhb 310216263Sjhb for (rid = 0;; rid++) { 311216263Sjhb error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 312216263Sjhb if (error != 0 || (start <= irq && irq <= end)) 313216263Sjhb return (rid); 314216263Sjhb } 315216263Sjhb} 316216263Sjhb 317169592Snjl/* Discover the HPET via the ACPI table of the same name. */ 318172489Snjlstatic void 319209371Smavhpet_identify(driver_t *driver, device_t parent) 320169574Stakawata{ 321169574Stakawata ACPI_TABLE_HPET *hpet; 322169574Stakawata ACPI_STATUS status; 323169574Stakawata device_t child; 324208436Smav int i, found; 325169574Stakawata 326172489Snjl /* Only one HPET device can be added. */ 327209371Smav if (devclass_get_device(hpet_devclass, 0)) 328172489Snjl return; 329208436Smav for (i = 1; ; i++) { 330208436Smav /* Search for HPET table. */ 331208436Smav status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 332208436Smav if (ACPI_FAILURE(status)) 333208436Smav return; 334208436Smav /* Search for HPET device with same ID. */ 335208436Smav found = 0; 336208436Smav AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 337209371Smav 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 338208436Smav /* If found - let it be probed in normal way. */ 339208436Smav if (found) 340208436Smav continue; 341208436Smav /* If not - create it from table info. */ 342231161Sjkim child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 343208436Smav if (child == NULL) { 344208436Smav printf("%s: can't add child\n", __func__); 345208436Smav continue; 346208436Smav } 347208436Smav bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 348208436Smav HPET_MEM_WIDTH); 349169574Stakawata } 350169574Stakawata} 351169574Stakawata 352151912Sphkstatic int 353209371Smavhpet_probe(device_t dev) 354151912Sphk{ 355159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 356159217Snjl 357169592Snjl if (acpi_disabled("hpet")) 358151912Sphk return (ENXIO); 359199016Savg if (acpi_get_handle(dev) != NULL && 360208436Smav ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 361169592Snjl return (ENXIO); 362151912Sphk 363159217Snjl device_set_desc(dev, "High Precision Event Timer"); 364151912Sphk return (0); 365151912Sphk} 366151912Sphk 367151912Sphkstatic int 368209371Smavhpet_attach(device_t dev) 369151912Sphk{ 370209371Smav struct hpet_softc *sc; 371209371Smav struct hpet_timer *t; 372209371Smav int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 373209371Smav int pcpu_master; 374209371Smav static int maxhpetet = 0; 375212238Smav uint32_t val, val2, cvectors, dvectors; 376209371Smav uint16_t vendor, rev; 377151912Sphk 378151912Sphk ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 379151912Sphk 380151912Sphk sc = device_get_softc(dev); 381151912Sphk sc->dev = dev; 382151912Sphk sc->handle = acpi_get_handle(dev); 383151912Sphk 384209371Smav sc->mem_rid = 0; 385209371Smav sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 386159217Snjl RF_ACTIVE); 387159217Snjl if (sc->mem_res == NULL) 388159217Snjl return (ENOMEM); 389151912Sphk 390159217Snjl /* Validate that we can access the whole region. */ 391159217Snjl if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 392159217Snjl device_printf(dev, "memory region width %ld too small\n", 393159217Snjl rman_get_size(sc->mem_res)); 394159217Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 395159217Snjl return (ENXIO); 396159217Snjl } 397151912Sphk 398171547Snjl /* Be sure timer is enabled. */ 399175361Sjhb hpet_enable(sc); 400171547Snjl 401159217Snjl /* Read basic statistics about the timer. */ 402175385Sjhb val = bus_read_4(sc->mem_res, HPET_PERIOD); 403175361Sjhb if (val == 0) { 404175361Sjhb device_printf(dev, "invalid period\n"); 405175361Sjhb hpet_disable(sc); 406175361Sjhb bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 407175361Sjhb return (ENXIO); 408175361Sjhb } 409175361Sjhb 410209371Smav sc->freq = (1000000000000000LL + val / 2) / val; 411209440Smav sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 412209440Smav vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 413209440Smav rev = sc->caps & HPET_CAP_REV_ID; 414209440Smav num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 415209371Smav /* 416209371Smav * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 417209371Smav * Specification and provides an off by one number 418209371Smav * of timers/comparators. 419209371Smav * Additionally, they use unregistered value in VENDOR_ID field. 420209371Smav */ 421209371Smav if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 422209371Smav num_timers--; 423209371Smav sc->num_timers = num_timers; 424159217Snjl if (bootverbose) { 425159217Snjl device_printf(dev, 426209371Smav "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 427209440Smav vendor, rev, sc->freq, 428209440Smav (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 429209440Smav num_timers, 430209440Smav (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 431159217Snjl } 432209371Smav for (i = 0; i < num_timers; i++) { 433209371Smav t = &sc->t[i]; 434209371Smav t->sc = sc; 435209371Smav t->num = i; 436209371Smav t->mode = 0; 437209371Smav t->intr_rid = -1; 438209371Smav t->irq = -1; 439212323Smav t->pcpu_cpu = -1; 440212323Smav t->pcpu_misrouted = 0; 441209371Smav t->pcpu_master = -1; 442209371Smav t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 443209371Smav t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 444209371Smav if (bootverbose) { 445209371Smav device_printf(dev, 446209371Smav " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 447209371Smav t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 448209371Smav (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 449209371Smav (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 450209371Smav (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 451209371Smav } 452209371Smav } 453159217Snjl if (testenv("debug.acpi.hpet_test")) 454209371Smav hpet_test(sc); 455171547Snjl /* 456171547Snjl * Don't attach if the timer never increments. Since the spec 457171547Snjl * requires it to be at least 10 MHz, it has to change in 1 us. 458171547Snjl */ 459175385Sjhb val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 460171547Snjl DELAY(1); 461175385Sjhb val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 462171547Snjl if (val == val2) { 463171547Snjl device_printf(dev, "HPET never increments, disabling\n"); 464175361Sjhb hpet_disable(sc); 465171547Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 466171547Snjl return (ENXIO); 467171547Snjl } 468208436Smav /* Announce first HPET as timecounter. */ 469208436Smav if (device_get_unit(dev) == 0) { 470209371Smav sc->tc.tc_get_timecount = hpet_get_timecount, 471209371Smav sc->tc.tc_counter_mask = ~0u, 472209371Smav sc->tc.tc_name = "HPET", 473222222Sjkim sc->tc.tc_quality = 950, 474209371Smav sc->tc.tc_frequency = sc->freq; 475209371Smav sc->tc.tc_priv = sc; 476209371Smav tc_init(&sc->tc); 477208436Smav } 478209371Smav /* If not disabled - setup and announce event timers. */ 479209371Smav if (resource_int_value(device_get_name(dev), device_get_unit(dev), 480209371Smav "clock", &i) == 0 && i == 0) 481209371Smav return (0); 482209440Smav 483209440Smav /* Check whether we can and want legacy routing. */ 484209440Smav sc->legacy_route = 0; 485209440Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 486209440Smav "legacy_route", &sc->legacy_route); 487209440Smav if ((sc->caps & HPET_CAP_LEG_RT) == 0) 488209440Smav sc->legacy_route = 0; 489209440Smav if (sc->legacy_route) { 490209440Smav sc->t[0].vectors = 0; 491209440Smav sc->t[1].vectors = 0; 492209440Smav } 493209440Smav 494212238Smav /* Check what IRQs we want use. */ 495212238Smav /* By default allow any PCI IRQs. */ 496212238Smav sc->allowed_irqs = 0xffff0000; 497209371Smav /* 498209371Smav * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 499209371Smav * Lower are also not always working for different reasons. 500209371Smav * SB800 fixed it, but seems do not implements level triggering 501209371Smav * properly, that makes it very unreliable - it freezes after any 502209371Smav * interrupt loss. Avoid legacy IRQs for AMD. 503209371Smav */ 504240286Smav if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2) 505212238Smav sc->allowed_irqs = 0x00000000; 506212238Smav /* 507213302Smav * NVidia MCP5x chipsets have number of unexplained interrupt 508213302Smav * problems. For some reason, using HPET interrupts breaks HDA sound. 509213302Smav */ 510213302Smav if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 511213302Smav sc->allowed_irqs = 0x00000000; 512213302Smav /* 513232797Smav * ServerWorks HT1000 reported to have problems with IRQs >= 16. 514232797Smav * Lower IRQs are working, but allowed mask is not set correctly. 515232797Smav * Legacy_route mode works fine. 516232797Smav */ 517232797Smav if (vendor == HPET_VENDID_SW && rev <= 0x01) 518232797Smav sc->allowed_irqs = 0x00000000; 519232797Smav /* 520212238Smav * Neither QEMU nor VirtualBox report supported IRQs correctly. 521212238Smav * The only way to use HPET there is to specify IRQs manually 522215473Sjhb * and/or use legacy_route. Legacy_route mode works on both. 523212238Smav */ 524212238Smav if (vm_guest) 525212238Smav sc->allowed_irqs = 0x00000000; 526212238Smav /* Let user override. */ 527212238Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 528212238Smav "allowed_irqs", &sc->allowed_irqs); 529212238Smav 530212533Smav /* Get how much per-CPU timers we should try to provide. */ 531212533Smav sc->per_cpu = 1; 532212533Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 533212533Smav "per_cpu", &sc->per_cpu); 534212533Smav 535212238Smav num_msi = 0; 536212238Smav sc->useirq = 0; 537212238Smav /* Find IRQ vectors for all timers. */ 538212238Smav cvectors = sc->allowed_irqs & 0xffff0000; 539212238Smav dvectors = sc->allowed_irqs & 0x0000ffff; 540212238Smav if (sc->legacy_route) 541212238Smav dvectors &= 0x0000fefe; 542209371Smav for (i = 0; i < num_timers; i++) { 543209371Smav t = &sc->t[i]; 544209440Smav if (sc->legacy_route && i < 2) 545209440Smav t->irq = (i == 0) ? 0 : 8; 546209371Smav#ifdef DEV_APIC 547209440Smav else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 548209371Smav if ((j = PCIB_ALLOC_MSIX( 549209371Smav device_get_parent(device_get_parent(dev)), dev, 550209371Smav &t->irq))) { 551209371Smav device_printf(dev, 552209440Smav "Can't allocate interrupt for t%d.\n", j); 553209440Smav } 554209440Smav } 555209440Smav#endif 556212238Smav else if (dvectors & t->vectors) { 557212238Smav t->irq = ffs(dvectors & t->vectors) - 1; 558212238Smav dvectors &= ~(1 << t->irq); 559212238Smav } 560209440Smav if (t->irq >= 0) { 561216263Sjhb t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 562216490Sjhb t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 563216490Sjhb &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 564216490Sjhb if (t->intr_res == NULL) { 565209440Smav t->irq = -1; 566209440Smav device_printf(dev, 567209440Smav "Can't map interrupt for t%d.\n", i); 568216490Sjhb } else if (bus_setup_intr(dev, t->intr_res, 569216490Sjhb INTR_TYPE_CLK, hpet_intr_single, NULL, t, 570216490Sjhb &t->intr_handle) != 0) { 571209440Smav t->irq = -1; 572209440Smav device_printf(dev, 573209440Smav "Can't setup interrupt for t%d.\n", i); 574209371Smav } else { 575209371Smav bus_describe_intr(dev, t->intr_res, 576209371Smav t->intr_handle, "t%d", i); 577209371Smav num_msi++; 578209371Smav } 579209440Smav } 580209440Smav if (t->irq < 0 && (cvectors & t->vectors) != 0) { 581209371Smav cvectors &= t->vectors; 582209371Smav sc->useirq |= (1 << i); 583209371Smav } 584209371Smav } 585209440Smav if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 586209440Smav sc->legacy_route = 0; 587209440Smav if (sc->legacy_route) 588209440Smav hpet_enable(sc); 589209440Smav /* Group timers for per-CPU operation. */ 590212533Smav num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 591209440Smav num_percpu_t = num_percpu_et * mp_ncpus; 592209440Smav pcpu_master = 0; 593209440Smav cur_cpu = CPU_FIRST(); 594209440Smav for (i = 0; i < num_timers; i++) { 595209440Smav t = &sc->t[i]; 596209440Smav if (t->irq >= 0 && num_percpu_t > 0) { 597209440Smav if (cur_cpu == CPU_FIRST()) 598209440Smav pcpu_master = i; 599212323Smav t->pcpu_cpu = cur_cpu; 600209440Smav t->pcpu_master = pcpu_master; 601209440Smav sc->t[pcpu_master]. 602209440Smav pcpu_slaves[cur_cpu] = i; 603209440Smav bus_bind_intr(dev, t->intr_res, cur_cpu); 604209440Smav cur_cpu = CPU_NEXT(cur_cpu); 605209440Smav num_percpu_t--; 606212238Smav } else if (t->irq >= 0) 607212238Smav bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 608209440Smav } 609209371Smav bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 610209371Smav sc->irq = -1; 611215473Sjhb /* If at least one timer needs legacy IRQ - set it up. */ 612209371Smav if (sc->useirq) { 613209371Smav j = i = fls(cvectors) - 1; 614209371Smav while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 615209371Smav j--; 616216263Sjhb sc->intr_rid = hpet_find_irq_rid(dev, j, i); 617216490Sjhb sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 618216490Sjhb &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 619216490Sjhb if (sc->intr_res == NULL) 620216490Sjhb device_printf(dev, "Can't map interrupt.\n"); 621216490Sjhb else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 622216490Sjhb hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 623209371Smav device_printf(dev, "Can't setup interrupt.\n"); 624209371Smav } else { 625209371Smav sc->irq = rman_get_start(sc->intr_res); 626209371Smav /* Bind IRQ to BSP to avoid live migration. */ 627209371Smav bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 628209371Smav } 629209371Smav } 630209371Smav /* Program and announce event timers. */ 631209371Smav for (i = 0; i < num_timers; i++) { 632209371Smav t = &sc->t[i]; 633209371Smav t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 634209371Smav t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 635209440Smav t->caps &= ~(HPET_TCNF_INT_TYPE); 636209371Smav t->caps |= HPET_TCNF_32MODE; 637209440Smav if (t->irq >= 0 && sc->legacy_route && i < 2) { 638209440Smav /* Legacy route doesn't need more configuration. */ 639209440Smav } else 640209371Smav#ifdef DEV_APIC 641212238Smav if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 642209371Smav uint64_t addr; 643209371Smav uint32_t data; 644209371Smav 645209371Smav if (PCIB_MAP_MSI( 646209371Smav device_get_parent(device_get_parent(dev)), dev, 647209371Smav t->irq, &addr, &data) == 0) { 648209371Smav bus_write_4(sc->mem_res, 649209371Smav HPET_TIMER_FSB_ADDR(i), addr); 650209371Smav bus_write_4(sc->mem_res, 651209371Smav HPET_TIMER_FSB_VAL(i), data); 652209371Smav t->caps |= HPET_TCNF_FSB_EN; 653209371Smav } else 654209371Smav t->irq = -2; 655209371Smav } else 656209371Smav#endif 657212238Smav if (t->irq >= 0) 658212238Smav t->caps |= (t->irq << 9); 659212238Smav else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 660209371Smav t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 661209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 662209371Smav /* Skip event timers without set up IRQ. */ 663209371Smav if (t->irq < 0 && 664209371Smav (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 665209371Smav continue; 666209371Smav /* Announce the reset. */ 667209371Smav if (maxhpetet == 0) 668209371Smav t->et.et_name = "HPET"; 669209371Smav else { 670209371Smav sprintf(t->name, "HPET%d", maxhpetet); 671209371Smav t->et.et_name = t->name; 672209371Smav } 673209371Smav t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 674209371Smav t->et.et_quality = 450; 675209371Smav if (t->pcpu_master >= 0) { 676209371Smav t->et.et_flags |= ET_FLAGS_PERCPU; 677209371Smav t->et.et_quality += 100; 678209371Smav } 679209371Smav if ((t->caps & HPET_TCAP_PER_INT) == 0) 680209371Smav t->et.et_quality -= 10; 681209371Smav t->et.et_frequency = sc->freq; 682247463Smav t->et.et_min_period = 683247463Smav ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; 684247463Smav t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; 685209371Smav t->et.et_start = hpet_start; 686209371Smav t->et.et_stop = hpet_stop; 687209371Smav t->et.et_priv = &sc->t[i]; 688209371Smav if (t->pcpu_master < 0 || t->pcpu_master == i) { 689209371Smav et_register(&t->et); 690209371Smav maxhpetet++; 691209371Smav } 692209371Smav } 693159217Snjl return (0); 694159217Snjl} 695159217Snjl 696159217Snjlstatic int 697209371Smavhpet_detach(device_t dev) 698159217Snjl{ 699159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 700159217Snjl 701159217Snjl /* XXX Without a tc_remove() function, we can't detach. */ 702159217Snjl return (EBUSY); 703159217Snjl} 704159217Snjl 705168010Snjlstatic int 706209371Smavhpet_suspend(device_t dev) 707175361Sjhb{ 708212541Smav// struct hpet_softc *sc; 709175361Sjhb 710175361Sjhb /* 711175361Sjhb * Disable the timer during suspend. The timer will not lose 712175361Sjhb * its state in S1 or S2, but we are required to disable 713175361Sjhb * it. 714175361Sjhb */ 715212541Smav// sc = device_get_softc(dev); 716212541Smav// hpet_disable(sc); 717175361Sjhb 718175361Sjhb return (0); 719175361Sjhb} 720175361Sjhb 721175361Sjhbstatic int 722209371Smavhpet_resume(device_t dev) 723168010Snjl{ 724209371Smav struct hpet_softc *sc; 725209371Smav struct hpet_timer *t; 726209371Smav int i; 727168010Snjl 728168010Snjl /* Re-enable the timer after a resume to keep the clock advancing. */ 729168010Snjl sc = device_get_softc(dev); 730175361Sjhb hpet_enable(sc); 731209371Smav /* Restart event timers that were running on suspend. */ 732209371Smav for (i = 0; i < sc->num_timers; i++) { 733209371Smav t = &sc->t[i]; 734209371Smav#ifdef DEV_APIC 735209440Smav if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 736209371Smav uint64_t addr; 737209371Smav uint32_t data; 738209371Smav 739209371Smav if (PCIB_MAP_MSI( 740209371Smav device_get_parent(device_get_parent(dev)), dev, 741209371Smav t->irq, &addr, &data) == 0) { 742209371Smav bus_write_4(sc->mem_res, 743209371Smav HPET_TIMER_FSB_ADDR(i), addr); 744209371Smav bus_write_4(sc->mem_res, 745209371Smav HPET_TIMER_FSB_VAL(i), data); 746209371Smav } 747209371Smav } 748209371Smav#endif 749209371Smav if (t->mode == 0) 750209371Smav continue; 751212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 752209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 753209371Smav t->caps |= HPET_TCNF_TYPE; 754212491Smav t->next += t->div; 755209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 756209371Smav t->caps | HPET_TCNF_VAL_SET); 757209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 758212491Smav t->next); 759209371Smav bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 760209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 761209371Smav t->div); 762209371Smav } else { 763212491Smav t->next += sc->freq / 1024; 764209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 765212491Smav t->next); 766209371Smav } 767209371Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 768209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 769209371Smav } 770168010Snjl return (0); 771168010Snjl} 772168010Snjl 773159217Snjl/* Print some basic latency/rate information to assist in debugging. */ 774159217Snjlstatic void 775209371Smavhpet_test(struct hpet_softc *sc) 776159217Snjl{ 777151912Sphk int i; 778151912Sphk uint32_t u1, u2; 779151912Sphk struct bintime b0, b1, b2; 780151912Sphk struct timespec ts; 781151912Sphk 782151912Sphk binuptime(&b0); 783151912Sphk binuptime(&b0); 784151912Sphk binuptime(&b1); 785175385Sjhb u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 786151912Sphk for (i = 1; i < 1000; i++) 787175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 788151912Sphk binuptime(&b2); 789175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 790151912Sphk 791151912Sphk bintime_sub(&b2, &b1); 792151912Sphk bintime_sub(&b1, &b0); 793151912Sphk bintime_sub(&b2, &b1); 794151912Sphk bintime2timespec(&b2, &ts); 795151912Sphk 796159217Snjl device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 797151912Sphk (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 798151912Sphk 799159217Snjl device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 800151912Sphk} 801151912Sphk 802209371Smav#ifdef DEV_APIC 803209371Smavstatic int 804209371Smavhpet_remap_intr(device_t dev, device_t child, u_int irq) 805209371Smav{ 806209371Smav struct hpet_softc *sc = device_get_softc(dev); 807209371Smav struct hpet_timer *t; 808209371Smav uint64_t addr; 809209371Smav uint32_t data; 810209371Smav int error, i; 811209371Smav 812209371Smav for (i = 0; i < sc->num_timers; i++) { 813209371Smav t = &sc->t[i]; 814209371Smav if (t->irq != irq) 815209371Smav continue; 816209371Smav error = PCIB_MAP_MSI( 817209371Smav device_get_parent(device_get_parent(dev)), dev, 818209371Smav irq, &addr, &data); 819209371Smav if (error) 820209371Smav return (error); 821209371Smav hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 822209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 823209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 824209371Smav hpet_enable(sc); 825209371Smav return (0); 826209371Smav } 827209371Smav return (ENOENT); 828209371Smav} 829209371Smav#endif 830209371Smav 831209371Smavstatic device_method_t hpet_methods[] = { 832151912Sphk /* Device interface */ 833209371Smav DEVMETHOD(device_identify, hpet_identify), 834209371Smav DEVMETHOD(device_probe, hpet_probe), 835209371Smav DEVMETHOD(device_attach, hpet_attach), 836209371Smav DEVMETHOD(device_detach, hpet_detach), 837209371Smav DEVMETHOD(device_suspend, hpet_suspend), 838209371Smav DEVMETHOD(device_resume, hpet_resume), 839151912Sphk 840209371Smav#ifdef DEV_APIC 841209371Smav DEVMETHOD(bus_remap_intr, hpet_remap_intr), 842209371Smav#endif 843209371Smav 844246128Ssbz DEVMETHOD_END 845151912Sphk}; 846151912Sphk 847209371Smavstatic driver_t hpet_driver = { 848209371Smav "hpet", 849209371Smav hpet_methods, 850209371Smav sizeof(struct hpet_softc), 851151912Sphk}; 852151912Sphk 853209371SmavDRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 854209371SmavMODULE_DEPEND(hpet, acpi, 1, 1, 1); 855