acpi_hpet.c revision 240286
1151912Sphk/*- 2151912Sphk * Copyright (c) 2005 Poul-Henning Kamp 3209440Smav * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4151912Sphk * All rights reserved. 5151912Sphk * 6151912Sphk * Redistribution and use in source and binary forms, with or without 7151912Sphk * modification, are permitted provided that the following conditions 8151912Sphk * are met: 9151912Sphk * 1. Redistributions of source code must retain the above copyright 10151912Sphk * notice, this list of conditions and the following disclaimer. 11151912Sphk * 2. Redistributions in binary form must reproduce the above copyright 12151912Sphk * notice, this list of conditions and the following disclaimer in the 13151912Sphk * documentation and/or other materials provided with the distribution. 14151912Sphk * 15151912Sphk * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16151912Sphk * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17151912Sphk * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18151912Sphk * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19151912Sphk * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20151912Sphk * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21151912Sphk * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22151912Sphk * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23151912Sphk * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24151912Sphk * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25151912Sphk * SUCH DAMAGE. 26151912Sphk */ 27151912Sphk 28151912Sphk#include <sys/cdefs.h> 29151912Sphk__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 240286 2012-09-09 20:00:00Z mav $"); 30151912Sphk 31151912Sphk#include "opt_acpi.h" 32209402Smav#if defined(__amd64__) || defined(__ia64__) 33209371Smav#define DEV_APIC 34209371Smav#else 35209371Smav#include "opt_apic.h" 36209371Smav#endif 37151912Sphk#include <sys/param.h> 38159217Snjl#include <sys/bus.h> 39151912Sphk#include <sys/kernel.h> 40151912Sphk#include <sys/module.h> 41209371Smav#include <sys/proc.h> 42151912Sphk#include <sys/rman.h> 43151912Sphk#include <sys/time.h> 44209371Smav#include <sys/smp.h> 45209371Smav#include <sys/sysctl.h> 46209371Smav#include <sys/timeet.h> 47151912Sphk#include <sys/timetc.h> 48159217Snjl 49193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 50193530Sjkim#include <contrib/dev/acpica/include/accommon.h> 51193530Sjkim 52151912Sphk#include <dev/acpica/acpivar.h> 53175385Sjhb#include <dev/acpica/acpi_hpet.h> 54151912Sphk 55209371Smav#ifdef DEV_APIC 56209371Smav#include "pcib_if.h" 57209371Smav#endif 58209371Smav 59203062Savg#define HPET_VENDID_AMD 0x4353 60240286Smav#define HPET_VENDID_AMD2 0x1022 61203062Savg#define HPET_VENDID_INTEL 0x8086 62213302Smav#define HPET_VENDID_NVIDIA 0x10de 63232797Smav#define HPET_VENDID_SW 0x1166 64203062Savg 65151912SphkACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 66151912Sphk 67209371Smavstatic devclass_t hpet_devclass; 68169574Stakawata 69151931Sscottl/* ACPI CA debugging */ 70151935Sscottl#define _COMPONENT ACPI_TIMER 71151931SscottlACPI_MODULE_NAME("HPET") 72151931Sscottl 73209371Smavstruct hpet_softc { 74151912Sphk device_t dev; 75209371Smav int mem_rid; 76209371Smav int intr_rid; 77209371Smav int irq; 78209371Smav int useirq; 79209440Smav int legacy_route; 80212533Smav int per_cpu; 81212238Smav uint32_t allowed_irqs; 82159217Snjl struct resource *mem_res; 83209371Smav struct resource *intr_res; 84209371Smav void *intr_handle; 85151912Sphk ACPI_HANDLE handle; 86209371Smav uint64_t freq; 87209440Smav uint32_t caps; 88209371Smav struct timecounter tc; 89209371Smav struct hpet_timer { 90209371Smav struct eventtimer et; 91209371Smav struct hpet_softc *sc; 92209371Smav int num; 93209371Smav int mode; 94209371Smav int intr_rid; 95209371Smav int irq; 96212323Smav int pcpu_cpu; 97212323Smav int pcpu_misrouted; 98209371Smav int pcpu_master; 99209371Smav int pcpu_slaves[MAXCPU]; 100209371Smav struct resource *intr_res; 101209371Smav void *intr_handle; 102209371Smav uint32_t caps; 103209371Smav uint32_t vectors; 104209371Smav uint32_t div; 105212491Smav uint32_t next; 106209371Smav char name[8]; 107209371Smav } t[32]; 108209371Smav int num_timers; 109151912Sphk}; 110151912Sphk 111159217Snjlstatic u_int hpet_get_timecount(struct timecounter *tc); 112209371Smavstatic void hpet_test(struct hpet_softc *sc); 113151912Sphk 114159217Snjlstatic char *hpet_ids[] = { "PNP0103", NULL }; 115159217Snjl 116159217Snjlstatic u_int 117151912Sphkhpet_get_timecount(struct timecounter *tc) 118151912Sphk{ 119209371Smav struct hpet_softc *sc; 120151912Sphk 121151912Sphk sc = tc->tc_priv; 122175385Sjhb return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 123151912Sphk} 124151912Sphk 125175361Sjhbstatic void 126209371Smavhpet_enable(struct hpet_softc *sc) 127175361Sjhb{ 128175361Sjhb uint32_t val; 129175385Sjhb 130175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 131209440Smav if (sc->legacy_route) 132209440Smav val |= HPET_CNF_LEG_RT; 133209440Smav else 134209440Smav val &= ~HPET_CNF_LEG_RT; 135185103Sjkim val |= HPET_CNF_ENABLE; 136185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 137175361Sjhb} 138175361Sjhb 139175361Sjhbstatic void 140209371Smavhpet_disable(struct hpet_softc *sc) 141175361Sjhb{ 142175361Sjhb uint32_t val; 143175385Sjhb 144175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 145185103Sjkim val &= ~HPET_CNF_ENABLE; 146185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 147175361Sjhb} 148175361Sjhb 149209371Smavstatic int 150209371Smavhpet_start(struct eventtimer *et, 151209371Smav struct bintime *first, struct bintime *period) 152209371Smav{ 153209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 154209371Smav struct hpet_timer *t; 155209371Smav struct hpet_softc *sc = mt->sc; 156212491Smav uint32_t fdiv, now; 157209371Smav 158209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 159209371Smav if (period != NULL) { 160209371Smav t->mode = 1; 161209371Smav t->div = (sc->freq * (period->frac >> 32)) >> 32; 162209371Smav if (period->sec != 0) 163209371Smav t->div += sc->freq * period->sec; 164209371Smav } else { 165209371Smav t->mode = 2; 166209371Smav t->div = 0; 167209371Smav } 168210290Smav if (first != NULL) { 169210290Smav fdiv = (sc->freq * (first->frac >> 32)) >> 32; 170210290Smav if (first->sec != 0) 171210290Smav fdiv += sc->freq * first->sec; 172210290Smav } else 173210290Smav fdiv = t->div; 174212238Smav if (t->irq < 0) 175212238Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 176212238Smav t->caps |= HPET_TCNF_INT_ENB; 177212491Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 178212238Smavrestart: 179212491Smav t->next = now + fdiv; 180209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 181209371Smav t->caps |= HPET_TCNF_TYPE; 182209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 183209371Smav t->caps | HPET_TCNF_VAL_SET); 184212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 185212491Smav t->next); 186212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 187212491Smav t->div); 188209371Smav } else { 189212238Smav t->caps &= ~HPET_TCNF_TYPE; 190212491Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 191212491Smav t->caps); 192212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 193212491Smav t->next); 194209371Smav } 195224919Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 196224919Smav if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 197224919Smav fdiv *= 2; 198224919Smav goto restart; 199212238Smav } 200209371Smav return (0); 201209371Smav} 202209371Smav 203209371Smavstatic int 204209371Smavhpet_stop(struct eventtimer *et) 205209371Smav{ 206209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 207209371Smav struct hpet_timer *t; 208209371Smav struct hpet_softc *sc = mt->sc; 209209371Smav 210209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 211209371Smav t->mode = 0; 212209371Smav t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 213209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 214209371Smav return (0); 215209371Smav} 216209371Smav 217209371Smavstatic int 218209371Smavhpet_intr_single(void *arg) 219209371Smav{ 220209371Smav struct hpet_timer *t = (struct hpet_timer *)arg; 221209371Smav struct hpet_timer *mt; 222209371Smav struct hpet_softc *sc = t->sc; 223209371Smav uint32_t now; 224209371Smav 225212491Smav if (t->mode == 0) 226212491Smav return (FILTER_STRAY); 227212323Smav /* Check that per-CPU timer interrupt reached right CPU. */ 228212323Smav if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 229212323Smav if ((++t->pcpu_misrouted) % 32 == 0) { 230212323Smav printf("HPET interrupt routed to the wrong CPU" 231212323Smav " (timer %d CPU %d -> %d)!\n", 232212323Smav t->num, t->pcpu_cpu, curcpu); 233212323Smav } 234212323Smav 235212323Smav /* 236212323Smav * Reload timer, hoping that next time may be more lucky 237212323Smav * (system will manage proper interrupt binding). 238212323Smav */ 239212323Smav if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 240212323Smav t->mode == 2) { 241212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 242212491Smav sc->freq / 8; 243212323Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 244212491Smav t->next); 245212323Smav } 246212323Smav return (FILTER_HANDLED); 247212323Smav } 248209371Smav if (t->mode == 1 && 249209371Smav (t->caps & HPET_TCAP_PER_INT) == 0) { 250212491Smav t->next += t->div; 251209371Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 252212491Smav if ((int32_t)((now + t->div / 2) - t->next) > 0) 253212491Smav t->next = now + t->div / 2; 254209371Smav bus_write_4(sc->mem_res, 255212491Smav HPET_TIMER_COMPARATOR(t->num), t->next); 256209371Smav } else if (t->mode == 2) 257209371Smav t->mode = 0; 258209371Smav mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 259209990Smav if (mt->et.et_active) 260209990Smav mt->et.et_event_cb(&mt->et, mt->et.et_arg); 261209371Smav return (FILTER_HANDLED); 262209371Smav} 263209371Smav 264209371Smavstatic int 265209371Smavhpet_intr(void *arg) 266209371Smav{ 267209371Smav struct hpet_softc *sc = (struct hpet_softc *)arg; 268209371Smav int i; 269209371Smav uint32_t val; 270209371Smav 271209371Smav val = bus_read_4(sc->mem_res, HPET_ISR); 272209371Smav if (val) { 273209371Smav bus_write_4(sc->mem_res, HPET_ISR, val); 274209371Smav val &= sc->useirq; 275209371Smav for (i = 0; i < sc->num_timers; i++) { 276209371Smav if ((val & (1 << i)) == 0) 277209371Smav continue; 278209371Smav hpet_intr_single(&sc->t[i]); 279209371Smav } 280209371Smav return (FILTER_HANDLED); 281209371Smav } 282209371Smav return (FILTER_STRAY); 283209371Smav} 284209371Smav 285208436Smavstatic ACPI_STATUS 286209371Smavhpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 287208436Smav void **status) 288208436Smav{ 289208436Smav char **ids; 290208436Smav uint32_t id = (uint32_t)(uintptr_t)context; 291208438Smav uint32_t uid = 0; 292208436Smav 293208436Smav for (ids = hpet_ids; *ids != NULL; ids++) { 294208436Smav if (acpi_MatchHid(handle, *ids)) 295208436Smav break; 296208436Smav } 297208436Smav if (*ids == NULL) 298208436Smav return (AE_OK); 299209371Smav if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 300209371Smav id == uid) 301208436Smav *((int *)status) = 1; 302208436Smav return (AE_OK); 303208436Smav} 304208436Smav 305216263Sjhb/* 306216263Sjhb * Find an existing IRQ resource that matches the requested IRQ range 307216263Sjhb * and return its RID. If one is not found, use a new RID. 308216263Sjhb */ 309216263Sjhbstatic int 310216263Sjhbhpet_find_irq_rid(device_t dev, u_long start, u_long end) 311216263Sjhb{ 312216263Sjhb u_long irq; 313216263Sjhb int error, rid; 314216263Sjhb 315216263Sjhb for (rid = 0;; rid++) { 316216263Sjhb error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 317216263Sjhb if (error != 0 || (start <= irq && irq <= end)) 318216263Sjhb return (rid); 319216263Sjhb } 320216263Sjhb} 321216263Sjhb 322169592Snjl/* Discover the HPET via the ACPI table of the same name. */ 323172489Snjlstatic void 324209371Smavhpet_identify(driver_t *driver, device_t parent) 325169574Stakawata{ 326169574Stakawata ACPI_TABLE_HPET *hpet; 327169574Stakawata ACPI_STATUS status; 328169574Stakawata device_t child; 329208436Smav int i, found; 330169574Stakawata 331172489Snjl /* Only one HPET device can be added. */ 332209371Smav if (devclass_get_device(hpet_devclass, 0)) 333172489Snjl return; 334208436Smav for (i = 1; ; i++) { 335208436Smav /* Search for HPET table. */ 336208436Smav status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 337208436Smav if (ACPI_FAILURE(status)) 338208436Smav return; 339208436Smav /* Search for HPET device with same ID. */ 340208436Smav found = 0; 341208436Smav AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 342209371Smav 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 343208436Smav /* If found - let it be probed in normal way. */ 344208436Smav if (found) 345208436Smav continue; 346208436Smav /* If not - create it from table info. */ 347231161Sjkim child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 348208436Smav if (child == NULL) { 349208436Smav printf("%s: can't add child\n", __func__); 350208436Smav continue; 351208436Smav } 352208436Smav bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 353208436Smav HPET_MEM_WIDTH); 354169574Stakawata } 355169574Stakawata} 356169574Stakawata 357151912Sphkstatic int 358209371Smavhpet_probe(device_t dev) 359151912Sphk{ 360159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 361159217Snjl 362169592Snjl if (acpi_disabled("hpet")) 363151912Sphk return (ENXIO); 364199016Savg if (acpi_get_handle(dev) != NULL && 365208436Smav ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 366169592Snjl return (ENXIO); 367151912Sphk 368159217Snjl device_set_desc(dev, "High Precision Event Timer"); 369151912Sphk return (0); 370151912Sphk} 371151912Sphk 372151912Sphkstatic int 373209371Smavhpet_attach(device_t dev) 374151912Sphk{ 375209371Smav struct hpet_softc *sc; 376209371Smav struct hpet_timer *t; 377209371Smav int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 378209371Smav int pcpu_master; 379209371Smav static int maxhpetet = 0; 380212238Smav uint32_t val, val2, cvectors, dvectors; 381209371Smav uint16_t vendor, rev; 382151912Sphk 383151912Sphk ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 384151912Sphk 385151912Sphk sc = device_get_softc(dev); 386151912Sphk sc->dev = dev; 387151912Sphk sc->handle = acpi_get_handle(dev); 388151912Sphk 389209371Smav sc->mem_rid = 0; 390209371Smav sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 391159217Snjl RF_ACTIVE); 392159217Snjl if (sc->mem_res == NULL) 393159217Snjl return (ENOMEM); 394151912Sphk 395159217Snjl /* Validate that we can access the whole region. */ 396159217Snjl if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 397159217Snjl device_printf(dev, "memory region width %ld too small\n", 398159217Snjl rman_get_size(sc->mem_res)); 399159217Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 400159217Snjl return (ENXIO); 401159217Snjl } 402151912Sphk 403171547Snjl /* Be sure timer is enabled. */ 404175361Sjhb hpet_enable(sc); 405171547Snjl 406159217Snjl /* Read basic statistics about the timer. */ 407175385Sjhb val = bus_read_4(sc->mem_res, HPET_PERIOD); 408175361Sjhb if (val == 0) { 409175361Sjhb device_printf(dev, "invalid period\n"); 410175361Sjhb hpet_disable(sc); 411175361Sjhb bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 412175361Sjhb return (ENXIO); 413175361Sjhb } 414175361Sjhb 415209371Smav sc->freq = (1000000000000000LL + val / 2) / val; 416209440Smav sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 417209440Smav vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 418209440Smav rev = sc->caps & HPET_CAP_REV_ID; 419209440Smav num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 420209371Smav /* 421209371Smav * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 422209371Smav * Specification and provides an off by one number 423209371Smav * of timers/comparators. 424209371Smav * Additionally, they use unregistered value in VENDOR_ID field. 425209371Smav */ 426209371Smav if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 427209371Smav num_timers--; 428209371Smav sc->num_timers = num_timers; 429159217Snjl if (bootverbose) { 430159217Snjl device_printf(dev, 431209371Smav "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 432209440Smav vendor, rev, sc->freq, 433209440Smav (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 434209440Smav num_timers, 435209440Smav (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 436159217Snjl } 437209371Smav for (i = 0; i < num_timers; i++) { 438209371Smav t = &sc->t[i]; 439209371Smav t->sc = sc; 440209371Smav t->num = i; 441209371Smav t->mode = 0; 442209371Smav t->intr_rid = -1; 443209371Smav t->irq = -1; 444212323Smav t->pcpu_cpu = -1; 445212323Smav t->pcpu_misrouted = 0; 446209371Smav t->pcpu_master = -1; 447209371Smav t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 448209371Smav t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 449209371Smav if (bootverbose) { 450209371Smav device_printf(dev, 451209371Smav " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 452209371Smav t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 453209371Smav (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 454209371Smav (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 455209371Smav (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 456209371Smav } 457209371Smav } 458159217Snjl if (testenv("debug.acpi.hpet_test")) 459209371Smav hpet_test(sc); 460171547Snjl /* 461171547Snjl * Don't attach if the timer never increments. Since the spec 462171547Snjl * requires it to be at least 10 MHz, it has to change in 1 us. 463171547Snjl */ 464175385Sjhb val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 465171547Snjl DELAY(1); 466175385Sjhb val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 467171547Snjl if (val == val2) { 468171547Snjl device_printf(dev, "HPET never increments, disabling\n"); 469175361Sjhb hpet_disable(sc); 470171547Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 471171547Snjl return (ENXIO); 472171547Snjl } 473208436Smav /* Announce first HPET as timecounter. */ 474208436Smav if (device_get_unit(dev) == 0) { 475209371Smav sc->tc.tc_get_timecount = hpet_get_timecount, 476209371Smav sc->tc.tc_counter_mask = ~0u, 477209371Smav sc->tc.tc_name = "HPET", 478222222Sjkim sc->tc.tc_quality = 950, 479209371Smav sc->tc.tc_frequency = sc->freq; 480209371Smav sc->tc.tc_priv = sc; 481209371Smav tc_init(&sc->tc); 482208436Smav } 483209371Smav /* If not disabled - setup and announce event timers. */ 484209371Smav if (resource_int_value(device_get_name(dev), device_get_unit(dev), 485209371Smav "clock", &i) == 0 && i == 0) 486209371Smav return (0); 487209440Smav 488209440Smav /* Check whether we can and want legacy routing. */ 489209440Smav sc->legacy_route = 0; 490209440Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 491209440Smav "legacy_route", &sc->legacy_route); 492209440Smav if ((sc->caps & HPET_CAP_LEG_RT) == 0) 493209440Smav sc->legacy_route = 0; 494209440Smav if (sc->legacy_route) { 495209440Smav sc->t[0].vectors = 0; 496209440Smav sc->t[1].vectors = 0; 497209440Smav } 498209440Smav 499212238Smav /* Check what IRQs we want use. */ 500212238Smav /* By default allow any PCI IRQs. */ 501212238Smav sc->allowed_irqs = 0xffff0000; 502209371Smav /* 503209371Smav * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 504209371Smav * Lower are also not always working for different reasons. 505209371Smav * SB800 fixed it, but seems do not implements level triggering 506209371Smav * properly, that makes it very unreliable - it freezes after any 507209371Smav * interrupt loss. Avoid legacy IRQs for AMD. 508209371Smav */ 509240286Smav if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2) 510212238Smav sc->allowed_irqs = 0x00000000; 511212238Smav /* 512213302Smav * NVidia MCP5x chipsets have number of unexplained interrupt 513213302Smav * problems. For some reason, using HPET interrupts breaks HDA sound. 514213302Smav */ 515213302Smav if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 516213302Smav sc->allowed_irqs = 0x00000000; 517213302Smav /* 518232797Smav * ServerWorks HT1000 reported to have problems with IRQs >= 16. 519232797Smav * Lower IRQs are working, but allowed mask is not set correctly. 520232797Smav * Legacy_route mode works fine. 521232797Smav */ 522232797Smav if (vendor == HPET_VENDID_SW && rev <= 0x01) 523232797Smav sc->allowed_irqs = 0x00000000; 524232797Smav /* 525212238Smav * Neither QEMU nor VirtualBox report supported IRQs correctly. 526212238Smav * The only way to use HPET there is to specify IRQs manually 527215473Sjhb * and/or use legacy_route. Legacy_route mode works on both. 528212238Smav */ 529212238Smav if (vm_guest) 530212238Smav sc->allowed_irqs = 0x00000000; 531212238Smav /* Let user override. */ 532212238Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 533212238Smav "allowed_irqs", &sc->allowed_irqs); 534212238Smav 535212533Smav /* Get how much per-CPU timers we should try to provide. */ 536212533Smav sc->per_cpu = 1; 537212533Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 538212533Smav "per_cpu", &sc->per_cpu); 539212533Smav 540212238Smav num_msi = 0; 541212238Smav sc->useirq = 0; 542212238Smav /* Find IRQ vectors for all timers. */ 543212238Smav cvectors = sc->allowed_irqs & 0xffff0000; 544212238Smav dvectors = sc->allowed_irqs & 0x0000ffff; 545212238Smav if (sc->legacy_route) 546212238Smav dvectors &= 0x0000fefe; 547209371Smav for (i = 0; i < num_timers; i++) { 548209371Smav t = &sc->t[i]; 549209440Smav if (sc->legacy_route && i < 2) 550209440Smav t->irq = (i == 0) ? 0 : 8; 551209371Smav#ifdef DEV_APIC 552209440Smav else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 553209371Smav if ((j = PCIB_ALLOC_MSIX( 554209371Smav device_get_parent(device_get_parent(dev)), dev, 555209371Smav &t->irq))) { 556209371Smav device_printf(dev, 557209440Smav "Can't allocate interrupt for t%d.\n", j); 558209440Smav } 559209440Smav } 560209440Smav#endif 561212238Smav else if (dvectors & t->vectors) { 562212238Smav t->irq = ffs(dvectors & t->vectors) - 1; 563212238Smav dvectors &= ~(1 << t->irq); 564212238Smav } 565209440Smav if (t->irq >= 0) { 566216263Sjhb t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 567216490Sjhb t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 568216490Sjhb &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 569216490Sjhb if (t->intr_res == NULL) { 570209440Smav t->irq = -1; 571209440Smav device_printf(dev, 572209440Smav "Can't map interrupt for t%d.\n", i); 573216490Sjhb } else if (bus_setup_intr(dev, t->intr_res, 574216490Sjhb INTR_TYPE_CLK, hpet_intr_single, NULL, t, 575216490Sjhb &t->intr_handle) != 0) { 576209440Smav t->irq = -1; 577209440Smav device_printf(dev, 578209440Smav "Can't setup interrupt for t%d.\n", i); 579209371Smav } else { 580209371Smav bus_describe_intr(dev, t->intr_res, 581209371Smav t->intr_handle, "t%d", i); 582209371Smav num_msi++; 583209371Smav } 584209440Smav } 585209440Smav if (t->irq < 0 && (cvectors & t->vectors) != 0) { 586209371Smav cvectors &= t->vectors; 587209371Smav sc->useirq |= (1 << i); 588209371Smav } 589209371Smav } 590209440Smav if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 591209440Smav sc->legacy_route = 0; 592209440Smav if (sc->legacy_route) 593209440Smav hpet_enable(sc); 594209440Smav /* Group timers for per-CPU operation. */ 595212533Smav num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 596209440Smav num_percpu_t = num_percpu_et * mp_ncpus; 597209440Smav pcpu_master = 0; 598209440Smav cur_cpu = CPU_FIRST(); 599209440Smav for (i = 0; i < num_timers; i++) { 600209440Smav t = &sc->t[i]; 601209440Smav if (t->irq >= 0 && num_percpu_t > 0) { 602209440Smav if (cur_cpu == CPU_FIRST()) 603209440Smav pcpu_master = i; 604212323Smav t->pcpu_cpu = cur_cpu; 605209440Smav t->pcpu_master = pcpu_master; 606209440Smav sc->t[pcpu_master]. 607209440Smav pcpu_slaves[cur_cpu] = i; 608209440Smav bus_bind_intr(dev, t->intr_res, cur_cpu); 609209440Smav cur_cpu = CPU_NEXT(cur_cpu); 610209440Smav num_percpu_t--; 611212238Smav } else if (t->irq >= 0) 612212238Smav bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 613209440Smav } 614209371Smav bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 615209371Smav sc->irq = -1; 616215473Sjhb /* If at least one timer needs legacy IRQ - set it up. */ 617209371Smav if (sc->useirq) { 618209371Smav j = i = fls(cvectors) - 1; 619209371Smav while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 620209371Smav j--; 621216263Sjhb sc->intr_rid = hpet_find_irq_rid(dev, j, i); 622216490Sjhb sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 623216490Sjhb &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 624216490Sjhb if (sc->intr_res == NULL) 625216490Sjhb device_printf(dev, "Can't map interrupt.\n"); 626216490Sjhb else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 627216490Sjhb hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 628209371Smav device_printf(dev, "Can't setup interrupt.\n"); 629209371Smav } else { 630209371Smav sc->irq = rman_get_start(sc->intr_res); 631209371Smav /* Bind IRQ to BSP to avoid live migration. */ 632209371Smav bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 633209371Smav } 634209371Smav } 635209371Smav /* Program and announce event timers. */ 636209371Smav for (i = 0; i < num_timers; i++) { 637209371Smav t = &sc->t[i]; 638209371Smav t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 639209371Smav t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 640209440Smav t->caps &= ~(HPET_TCNF_INT_TYPE); 641209371Smav t->caps |= HPET_TCNF_32MODE; 642209440Smav if (t->irq >= 0 && sc->legacy_route && i < 2) { 643209440Smav /* Legacy route doesn't need more configuration. */ 644209440Smav } else 645209371Smav#ifdef DEV_APIC 646212238Smav if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 647209371Smav uint64_t addr; 648209371Smav uint32_t data; 649209371Smav 650209371Smav if (PCIB_MAP_MSI( 651209371Smav device_get_parent(device_get_parent(dev)), dev, 652209371Smav t->irq, &addr, &data) == 0) { 653209371Smav bus_write_4(sc->mem_res, 654209371Smav HPET_TIMER_FSB_ADDR(i), addr); 655209371Smav bus_write_4(sc->mem_res, 656209371Smav HPET_TIMER_FSB_VAL(i), data); 657209371Smav t->caps |= HPET_TCNF_FSB_EN; 658209371Smav } else 659209371Smav t->irq = -2; 660209371Smav } else 661209371Smav#endif 662212238Smav if (t->irq >= 0) 663212238Smav t->caps |= (t->irq << 9); 664212238Smav else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 665209371Smav t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 666209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 667209371Smav /* Skip event timers without set up IRQ. */ 668209371Smav if (t->irq < 0 && 669209371Smav (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 670209371Smav continue; 671209371Smav /* Announce the reset. */ 672209371Smav if (maxhpetet == 0) 673209371Smav t->et.et_name = "HPET"; 674209371Smav else { 675209371Smav sprintf(t->name, "HPET%d", maxhpetet); 676209371Smav t->et.et_name = t->name; 677209371Smav } 678209371Smav t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 679209371Smav t->et.et_quality = 450; 680209371Smav if (t->pcpu_master >= 0) { 681209371Smav t->et.et_flags |= ET_FLAGS_PERCPU; 682209371Smav t->et.et_quality += 100; 683209371Smav } 684209371Smav if ((t->caps & HPET_TCAP_PER_INT) == 0) 685209371Smav t->et.et_quality -= 10; 686209371Smav t->et.et_frequency = sc->freq; 687210290Smav t->et.et_min_period.sec = 0; 688224919Smav t->et.et_min_period.frac = 689224919Smav (((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq) << 32; 690210298Smav t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq; 691210290Smav t->et.et_max_period.frac = 692210298Smav ((0xfffffffeLLU << 32) / sc->freq) << 32; 693209371Smav t->et.et_start = hpet_start; 694209371Smav t->et.et_stop = hpet_stop; 695209371Smav t->et.et_priv = &sc->t[i]; 696209371Smav if (t->pcpu_master < 0 || t->pcpu_master == i) { 697209371Smav et_register(&t->et); 698209371Smav maxhpetet++; 699209371Smav } 700209371Smav } 701159217Snjl return (0); 702159217Snjl} 703159217Snjl 704159217Snjlstatic int 705209371Smavhpet_detach(device_t dev) 706159217Snjl{ 707159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 708159217Snjl 709159217Snjl /* XXX Without a tc_remove() function, we can't detach. */ 710159217Snjl return (EBUSY); 711159217Snjl} 712159217Snjl 713168010Snjlstatic int 714209371Smavhpet_suspend(device_t dev) 715175361Sjhb{ 716212541Smav// struct hpet_softc *sc; 717175361Sjhb 718175361Sjhb /* 719175361Sjhb * Disable the timer during suspend. The timer will not lose 720175361Sjhb * its state in S1 or S2, but we are required to disable 721175361Sjhb * it. 722175361Sjhb */ 723212541Smav// sc = device_get_softc(dev); 724212541Smav// hpet_disable(sc); 725175361Sjhb 726175361Sjhb return (0); 727175361Sjhb} 728175361Sjhb 729175361Sjhbstatic int 730209371Smavhpet_resume(device_t dev) 731168010Snjl{ 732209371Smav struct hpet_softc *sc; 733209371Smav struct hpet_timer *t; 734209371Smav int i; 735168010Snjl 736168010Snjl /* Re-enable the timer after a resume to keep the clock advancing. */ 737168010Snjl sc = device_get_softc(dev); 738175361Sjhb hpet_enable(sc); 739209371Smav /* Restart event timers that were running on suspend. */ 740209371Smav for (i = 0; i < sc->num_timers; i++) { 741209371Smav t = &sc->t[i]; 742209371Smav#ifdef DEV_APIC 743209440Smav if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 744209371Smav uint64_t addr; 745209371Smav uint32_t data; 746209371Smav 747209371Smav if (PCIB_MAP_MSI( 748209371Smav device_get_parent(device_get_parent(dev)), dev, 749209371Smav t->irq, &addr, &data) == 0) { 750209371Smav bus_write_4(sc->mem_res, 751209371Smav HPET_TIMER_FSB_ADDR(i), addr); 752209371Smav bus_write_4(sc->mem_res, 753209371Smav HPET_TIMER_FSB_VAL(i), data); 754209371Smav } 755209371Smav } 756209371Smav#endif 757209371Smav if (t->mode == 0) 758209371Smav continue; 759212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 760209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 761209371Smav t->caps |= HPET_TCNF_TYPE; 762212491Smav t->next += t->div; 763209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 764209371Smav t->caps | HPET_TCNF_VAL_SET); 765209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 766212491Smav t->next); 767209371Smav bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 768209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 769209371Smav t->div); 770209371Smav } else { 771212491Smav t->next += sc->freq / 1024; 772209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 773212491Smav t->next); 774209371Smav } 775209371Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 776209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 777209371Smav } 778168010Snjl return (0); 779168010Snjl} 780168010Snjl 781159217Snjl/* Print some basic latency/rate information to assist in debugging. */ 782159217Snjlstatic void 783209371Smavhpet_test(struct hpet_softc *sc) 784159217Snjl{ 785151912Sphk int i; 786151912Sphk uint32_t u1, u2; 787151912Sphk struct bintime b0, b1, b2; 788151912Sphk struct timespec ts; 789151912Sphk 790151912Sphk binuptime(&b0); 791151912Sphk binuptime(&b0); 792151912Sphk binuptime(&b1); 793175385Sjhb u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 794151912Sphk for (i = 1; i < 1000; i++) 795175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 796151912Sphk binuptime(&b2); 797175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 798151912Sphk 799151912Sphk bintime_sub(&b2, &b1); 800151912Sphk bintime_sub(&b1, &b0); 801151912Sphk bintime_sub(&b2, &b1); 802151912Sphk bintime2timespec(&b2, &ts); 803151912Sphk 804159217Snjl device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 805151912Sphk (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 806151912Sphk 807159217Snjl device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 808151912Sphk} 809151912Sphk 810209371Smav#ifdef DEV_APIC 811209371Smavstatic int 812209371Smavhpet_remap_intr(device_t dev, device_t child, u_int irq) 813209371Smav{ 814209371Smav struct hpet_softc *sc = device_get_softc(dev); 815209371Smav struct hpet_timer *t; 816209371Smav uint64_t addr; 817209371Smav uint32_t data; 818209371Smav int error, i; 819209371Smav 820209371Smav for (i = 0; i < sc->num_timers; i++) { 821209371Smav t = &sc->t[i]; 822209371Smav if (t->irq != irq) 823209371Smav continue; 824209371Smav error = PCIB_MAP_MSI( 825209371Smav device_get_parent(device_get_parent(dev)), dev, 826209371Smav irq, &addr, &data); 827209371Smav if (error) 828209371Smav return (error); 829209371Smav hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 830209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 831209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 832209371Smav hpet_enable(sc); 833209371Smav return (0); 834209371Smav } 835209371Smav return (ENOENT); 836209371Smav} 837209371Smav#endif 838209371Smav 839209371Smavstatic device_method_t hpet_methods[] = { 840151912Sphk /* Device interface */ 841209371Smav DEVMETHOD(device_identify, hpet_identify), 842209371Smav DEVMETHOD(device_probe, hpet_probe), 843209371Smav DEVMETHOD(device_attach, hpet_attach), 844209371Smav DEVMETHOD(device_detach, hpet_detach), 845209371Smav DEVMETHOD(device_suspend, hpet_suspend), 846209371Smav DEVMETHOD(device_resume, hpet_resume), 847151912Sphk 848209371Smav#ifdef DEV_APIC 849209371Smav DEVMETHOD(bus_remap_intr, hpet_remap_intr), 850209371Smav#endif 851209371Smav 852151912Sphk {0, 0} 853151912Sphk}; 854151912Sphk 855209371Smavstatic driver_t hpet_driver = { 856209371Smav "hpet", 857209371Smav hpet_methods, 858209371Smav sizeof(struct hpet_softc), 859151912Sphk}; 860151912Sphk 861209371SmavDRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 862209371SmavMODULE_DEPEND(hpet, acpi, 1, 1, 1); 863