acpi_hpet.c revision 231161
1151912Sphk/*- 2151912Sphk * Copyright (c) 2005 Poul-Henning Kamp 3209440Smav * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4151912Sphk * All rights reserved. 5151912Sphk * 6151912Sphk * Redistribution and use in source and binary forms, with or without 7151912Sphk * modification, are permitted provided that the following conditions 8151912Sphk * are met: 9151912Sphk * 1. Redistributions of source code must retain the above copyright 10151912Sphk * notice, this list of conditions and the following disclaimer. 11151912Sphk * 2. Redistributions in binary form must reproduce the above copyright 12151912Sphk * notice, this list of conditions and the following disclaimer in the 13151912Sphk * documentation and/or other materials provided with the distribution. 14151912Sphk * 15151912Sphk * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16151912Sphk * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17151912Sphk * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18151912Sphk * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19151912Sphk * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20151912Sphk * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21151912Sphk * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22151912Sphk * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23151912Sphk * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24151912Sphk * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25151912Sphk * SUCH DAMAGE. 26151912Sphk */ 27151912Sphk 28151912Sphk#include <sys/cdefs.h> 29151912Sphk__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 231161 2012-02-07 20:54:44Z jkim $"); 30151912Sphk 31151912Sphk#include "opt_acpi.h" 32209402Smav#if defined(__amd64__) || defined(__ia64__) 33209371Smav#define DEV_APIC 34209371Smav#else 35209371Smav#include "opt_apic.h" 36209371Smav#endif 37151912Sphk#include <sys/param.h> 38159217Snjl#include <sys/bus.h> 39151912Sphk#include <sys/kernel.h> 40151912Sphk#include <sys/module.h> 41209371Smav#include <sys/proc.h> 42151912Sphk#include <sys/rman.h> 43151912Sphk#include <sys/time.h> 44209371Smav#include <sys/smp.h> 45209371Smav#include <sys/sysctl.h> 46209371Smav#include <sys/timeet.h> 47151912Sphk#include <sys/timetc.h> 48159217Snjl 49193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 50193530Sjkim#include <contrib/dev/acpica/include/accommon.h> 51193530Sjkim 52151912Sphk#include <dev/acpica/acpivar.h> 53175385Sjhb#include <dev/acpica/acpi_hpet.h> 54151912Sphk 55209371Smav#ifdef DEV_APIC 56209371Smav#include "pcib_if.h" 57209371Smav#endif 58209371Smav 59203062Savg#define HPET_VENDID_AMD 0x4353 60203062Savg#define HPET_VENDID_INTEL 0x8086 61213302Smav#define HPET_VENDID_NVIDIA 0x10de 62203062Savg 63151912SphkACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 64151912Sphk 65209371Smavstatic devclass_t hpet_devclass; 66169574Stakawata 67151931Sscottl/* ACPI CA debugging */ 68151935Sscottl#define _COMPONENT ACPI_TIMER 69151931SscottlACPI_MODULE_NAME("HPET") 70151931Sscottl 71209371Smavstruct hpet_softc { 72151912Sphk device_t dev; 73209371Smav int mem_rid; 74209371Smav int intr_rid; 75209371Smav int irq; 76209371Smav int useirq; 77209440Smav int legacy_route; 78212533Smav int per_cpu; 79212238Smav uint32_t allowed_irqs; 80159217Snjl struct resource *mem_res; 81209371Smav struct resource *intr_res; 82209371Smav void *intr_handle; 83151912Sphk ACPI_HANDLE handle; 84209371Smav uint64_t freq; 85209440Smav uint32_t caps; 86209371Smav struct timecounter tc; 87209371Smav struct hpet_timer { 88209371Smav struct eventtimer et; 89209371Smav struct hpet_softc *sc; 90209371Smav int num; 91209371Smav int mode; 92209371Smav int intr_rid; 93209371Smav int irq; 94212323Smav int pcpu_cpu; 95212323Smav int pcpu_misrouted; 96209371Smav int pcpu_master; 97209371Smav int pcpu_slaves[MAXCPU]; 98209371Smav struct resource *intr_res; 99209371Smav void *intr_handle; 100209371Smav uint32_t caps; 101209371Smav uint32_t vectors; 102209371Smav uint32_t div; 103212491Smav uint32_t next; 104209371Smav char name[8]; 105209371Smav } t[32]; 106209371Smav int num_timers; 107151912Sphk}; 108151912Sphk 109159217Snjlstatic u_int hpet_get_timecount(struct timecounter *tc); 110209371Smavstatic void hpet_test(struct hpet_softc *sc); 111151912Sphk 112159217Snjlstatic char *hpet_ids[] = { "PNP0103", NULL }; 113159217Snjl 114159217Snjlstatic u_int 115151912Sphkhpet_get_timecount(struct timecounter *tc) 116151912Sphk{ 117209371Smav struct hpet_softc *sc; 118151912Sphk 119151912Sphk sc = tc->tc_priv; 120175385Sjhb return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 121151912Sphk} 122151912Sphk 123175361Sjhbstatic void 124209371Smavhpet_enable(struct hpet_softc *sc) 125175361Sjhb{ 126175361Sjhb uint32_t val; 127175385Sjhb 128175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 129209440Smav if (sc->legacy_route) 130209440Smav val |= HPET_CNF_LEG_RT; 131209440Smav else 132209440Smav val &= ~HPET_CNF_LEG_RT; 133185103Sjkim val |= HPET_CNF_ENABLE; 134185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 135175361Sjhb} 136175361Sjhb 137175361Sjhbstatic void 138209371Smavhpet_disable(struct hpet_softc *sc) 139175361Sjhb{ 140175361Sjhb uint32_t val; 141175385Sjhb 142175385Sjhb val = bus_read_4(sc->mem_res, HPET_CONFIG); 143185103Sjkim val &= ~HPET_CNF_ENABLE; 144185103Sjkim bus_write_4(sc->mem_res, HPET_CONFIG, val); 145175361Sjhb} 146175361Sjhb 147209371Smavstatic int 148209371Smavhpet_start(struct eventtimer *et, 149209371Smav struct bintime *first, struct bintime *period) 150209371Smav{ 151209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 152209371Smav struct hpet_timer *t; 153209371Smav struct hpet_softc *sc = mt->sc; 154212491Smav uint32_t fdiv, now; 155209371Smav 156209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 157209371Smav if (period != NULL) { 158209371Smav t->mode = 1; 159209371Smav t->div = (sc->freq * (period->frac >> 32)) >> 32; 160209371Smav if (period->sec != 0) 161209371Smav t->div += sc->freq * period->sec; 162209371Smav } else { 163209371Smav t->mode = 2; 164209371Smav t->div = 0; 165209371Smav } 166210290Smav if (first != NULL) { 167210290Smav fdiv = (sc->freq * (first->frac >> 32)) >> 32; 168210290Smav if (first->sec != 0) 169210290Smav fdiv += sc->freq * first->sec; 170210290Smav } else 171210290Smav fdiv = t->div; 172212238Smav if (t->irq < 0) 173212238Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 174212238Smav t->caps |= HPET_TCNF_INT_ENB; 175212491Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 176212238Smavrestart: 177212491Smav t->next = now + fdiv; 178209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 179209371Smav t->caps |= HPET_TCNF_TYPE; 180209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 181209371Smav t->caps | HPET_TCNF_VAL_SET); 182212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 183212491Smav t->next); 184212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 185212491Smav t->div); 186209371Smav } else { 187212238Smav t->caps &= ~HPET_TCNF_TYPE; 188212491Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 189212491Smav t->caps); 190212491Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 191212491Smav t->next); 192209371Smav } 193224919Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 194224919Smav if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 195224919Smav fdiv *= 2; 196224919Smav goto restart; 197212238Smav } 198209371Smav return (0); 199209371Smav} 200209371Smav 201209371Smavstatic int 202209371Smavhpet_stop(struct eventtimer *et) 203209371Smav{ 204209371Smav struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 205209371Smav struct hpet_timer *t; 206209371Smav struct hpet_softc *sc = mt->sc; 207209371Smav 208209371Smav t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 209209371Smav t->mode = 0; 210209371Smav t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 211209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 212209371Smav return (0); 213209371Smav} 214209371Smav 215209371Smavstatic int 216209371Smavhpet_intr_single(void *arg) 217209371Smav{ 218209371Smav struct hpet_timer *t = (struct hpet_timer *)arg; 219209371Smav struct hpet_timer *mt; 220209371Smav struct hpet_softc *sc = t->sc; 221209371Smav uint32_t now; 222209371Smav 223212491Smav if (t->mode == 0) 224212491Smav return (FILTER_STRAY); 225212323Smav /* Check that per-CPU timer interrupt reached right CPU. */ 226212323Smav if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 227212323Smav if ((++t->pcpu_misrouted) % 32 == 0) { 228212323Smav printf("HPET interrupt routed to the wrong CPU" 229212323Smav " (timer %d CPU %d -> %d)!\n", 230212323Smav t->num, t->pcpu_cpu, curcpu); 231212323Smav } 232212323Smav 233212323Smav /* 234212323Smav * Reload timer, hoping that next time may be more lucky 235212323Smav * (system will manage proper interrupt binding). 236212323Smav */ 237212323Smav if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 238212323Smav t->mode == 2) { 239212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 240212491Smav sc->freq / 8; 241212323Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 242212491Smav t->next); 243212323Smav } 244212323Smav return (FILTER_HANDLED); 245212323Smav } 246209371Smav if (t->mode == 1 && 247209371Smav (t->caps & HPET_TCAP_PER_INT) == 0) { 248212491Smav t->next += t->div; 249209371Smav now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 250212491Smav if ((int32_t)((now + t->div / 2) - t->next) > 0) 251212491Smav t->next = now + t->div / 2; 252209371Smav bus_write_4(sc->mem_res, 253212491Smav HPET_TIMER_COMPARATOR(t->num), t->next); 254209371Smav } else if (t->mode == 2) 255209371Smav t->mode = 0; 256209371Smav mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 257209990Smav if (mt->et.et_active) 258209990Smav mt->et.et_event_cb(&mt->et, mt->et.et_arg); 259209371Smav return (FILTER_HANDLED); 260209371Smav} 261209371Smav 262209371Smavstatic int 263209371Smavhpet_intr(void *arg) 264209371Smav{ 265209371Smav struct hpet_softc *sc = (struct hpet_softc *)arg; 266209371Smav int i; 267209371Smav uint32_t val; 268209371Smav 269209371Smav val = bus_read_4(sc->mem_res, HPET_ISR); 270209371Smav if (val) { 271209371Smav bus_write_4(sc->mem_res, HPET_ISR, val); 272209371Smav val &= sc->useirq; 273209371Smav for (i = 0; i < sc->num_timers; i++) { 274209371Smav if ((val & (1 << i)) == 0) 275209371Smav continue; 276209371Smav hpet_intr_single(&sc->t[i]); 277209371Smav } 278209371Smav return (FILTER_HANDLED); 279209371Smav } 280209371Smav return (FILTER_STRAY); 281209371Smav} 282209371Smav 283208436Smavstatic ACPI_STATUS 284209371Smavhpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 285208436Smav void **status) 286208436Smav{ 287208436Smav char **ids; 288208436Smav uint32_t id = (uint32_t)(uintptr_t)context; 289208438Smav uint32_t uid = 0; 290208436Smav 291208436Smav for (ids = hpet_ids; *ids != NULL; ids++) { 292208436Smav if (acpi_MatchHid(handle, *ids)) 293208436Smav break; 294208436Smav } 295208436Smav if (*ids == NULL) 296208436Smav return (AE_OK); 297209371Smav if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 298209371Smav id == uid) 299208436Smav *((int *)status) = 1; 300208436Smav return (AE_OK); 301208436Smav} 302208436Smav 303216263Sjhb/* 304216263Sjhb * Find an existing IRQ resource that matches the requested IRQ range 305216263Sjhb * and return its RID. If one is not found, use a new RID. 306216263Sjhb */ 307216263Sjhbstatic int 308216263Sjhbhpet_find_irq_rid(device_t dev, u_long start, u_long end) 309216263Sjhb{ 310216263Sjhb u_long irq; 311216263Sjhb int error, rid; 312216263Sjhb 313216263Sjhb for (rid = 0;; rid++) { 314216263Sjhb error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 315216263Sjhb if (error != 0 || (start <= irq && irq <= end)) 316216263Sjhb return (rid); 317216263Sjhb } 318216263Sjhb} 319216263Sjhb 320169592Snjl/* Discover the HPET via the ACPI table of the same name. */ 321172489Snjlstatic void 322209371Smavhpet_identify(driver_t *driver, device_t parent) 323169574Stakawata{ 324169574Stakawata ACPI_TABLE_HPET *hpet; 325169574Stakawata ACPI_STATUS status; 326169574Stakawata device_t child; 327208436Smav int i, found; 328169574Stakawata 329172489Snjl /* Only one HPET device can be added. */ 330209371Smav if (devclass_get_device(hpet_devclass, 0)) 331172489Snjl return; 332208436Smav for (i = 1; ; i++) { 333208436Smav /* Search for HPET table. */ 334208436Smav status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 335208436Smav if (ACPI_FAILURE(status)) 336208436Smav return; 337208436Smav /* Search for HPET device with same ID. */ 338208436Smav found = 0; 339208436Smav AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 340209371Smav 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 341208436Smav /* If found - let it be probed in normal way. */ 342208436Smav if (found) 343208436Smav continue; 344208436Smav /* If not - create it from table info. */ 345231161Sjkim child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 346208436Smav if (child == NULL) { 347208436Smav printf("%s: can't add child\n", __func__); 348208436Smav continue; 349208436Smav } 350208436Smav bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 351208436Smav HPET_MEM_WIDTH); 352169574Stakawata } 353169574Stakawata} 354169574Stakawata 355151912Sphkstatic int 356209371Smavhpet_probe(device_t dev) 357151912Sphk{ 358159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 359159217Snjl 360169592Snjl if (acpi_disabled("hpet")) 361151912Sphk return (ENXIO); 362199016Savg if (acpi_get_handle(dev) != NULL && 363208436Smav ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 364169592Snjl return (ENXIO); 365151912Sphk 366159217Snjl device_set_desc(dev, "High Precision Event Timer"); 367151912Sphk return (0); 368151912Sphk} 369151912Sphk 370151912Sphkstatic int 371209371Smavhpet_attach(device_t dev) 372151912Sphk{ 373209371Smav struct hpet_softc *sc; 374209371Smav struct hpet_timer *t; 375209371Smav int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 376209371Smav int pcpu_master; 377209371Smav static int maxhpetet = 0; 378212238Smav uint32_t val, val2, cvectors, dvectors; 379209371Smav uint16_t vendor, rev; 380151912Sphk 381151912Sphk ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 382151912Sphk 383151912Sphk sc = device_get_softc(dev); 384151912Sphk sc->dev = dev; 385151912Sphk sc->handle = acpi_get_handle(dev); 386151912Sphk 387209371Smav sc->mem_rid = 0; 388209371Smav sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 389159217Snjl RF_ACTIVE); 390159217Snjl if (sc->mem_res == NULL) 391159217Snjl return (ENOMEM); 392151912Sphk 393159217Snjl /* Validate that we can access the whole region. */ 394159217Snjl if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 395159217Snjl device_printf(dev, "memory region width %ld too small\n", 396159217Snjl rman_get_size(sc->mem_res)); 397159217Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 398159217Snjl return (ENXIO); 399159217Snjl } 400151912Sphk 401171547Snjl /* Be sure timer is enabled. */ 402175361Sjhb hpet_enable(sc); 403171547Snjl 404159217Snjl /* Read basic statistics about the timer. */ 405175385Sjhb val = bus_read_4(sc->mem_res, HPET_PERIOD); 406175361Sjhb if (val == 0) { 407175361Sjhb device_printf(dev, "invalid period\n"); 408175361Sjhb hpet_disable(sc); 409175361Sjhb bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 410175361Sjhb return (ENXIO); 411175361Sjhb } 412175361Sjhb 413209371Smav sc->freq = (1000000000000000LL + val / 2) / val; 414209440Smav sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 415209440Smav vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 416209440Smav rev = sc->caps & HPET_CAP_REV_ID; 417209440Smav num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 418209371Smav /* 419209371Smav * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 420209371Smav * Specification and provides an off by one number 421209371Smav * of timers/comparators. 422209371Smav * Additionally, they use unregistered value in VENDOR_ID field. 423209371Smav */ 424209371Smav if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 425209371Smav num_timers--; 426209371Smav sc->num_timers = num_timers; 427159217Snjl if (bootverbose) { 428159217Snjl device_printf(dev, 429209371Smav "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 430209440Smav vendor, rev, sc->freq, 431209440Smav (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 432209440Smav num_timers, 433209440Smav (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 434159217Snjl } 435209371Smav for (i = 0; i < num_timers; i++) { 436209371Smav t = &sc->t[i]; 437209371Smav t->sc = sc; 438209371Smav t->num = i; 439209371Smav t->mode = 0; 440209371Smav t->intr_rid = -1; 441209371Smav t->irq = -1; 442212323Smav t->pcpu_cpu = -1; 443212323Smav t->pcpu_misrouted = 0; 444209371Smav t->pcpu_master = -1; 445209371Smav t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 446209371Smav t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 447209371Smav if (bootverbose) { 448209371Smav device_printf(dev, 449209371Smav " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 450209371Smav t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 451209371Smav (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 452209371Smav (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 453209371Smav (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 454209371Smav } 455209371Smav } 456159217Snjl if (testenv("debug.acpi.hpet_test")) 457209371Smav hpet_test(sc); 458171547Snjl /* 459171547Snjl * Don't attach if the timer never increments. Since the spec 460171547Snjl * requires it to be at least 10 MHz, it has to change in 1 us. 461171547Snjl */ 462175385Sjhb val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 463171547Snjl DELAY(1); 464175385Sjhb val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 465171547Snjl if (val == val2) { 466171547Snjl device_printf(dev, "HPET never increments, disabling\n"); 467175361Sjhb hpet_disable(sc); 468171547Snjl bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 469171547Snjl return (ENXIO); 470171547Snjl } 471208436Smav /* Announce first HPET as timecounter. */ 472208436Smav if (device_get_unit(dev) == 0) { 473209371Smav sc->tc.tc_get_timecount = hpet_get_timecount, 474209371Smav sc->tc.tc_counter_mask = ~0u, 475209371Smav sc->tc.tc_name = "HPET", 476222222Sjkim sc->tc.tc_quality = 950, 477209371Smav sc->tc.tc_frequency = sc->freq; 478209371Smav sc->tc.tc_priv = sc; 479209371Smav tc_init(&sc->tc); 480208436Smav } 481209371Smav /* If not disabled - setup and announce event timers. */ 482209371Smav if (resource_int_value(device_get_name(dev), device_get_unit(dev), 483209371Smav "clock", &i) == 0 && i == 0) 484209371Smav return (0); 485209440Smav 486209440Smav /* Check whether we can and want legacy routing. */ 487209440Smav sc->legacy_route = 0; 488209440Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 489209440Smav "legacy_route", &sc->legacy_route); 490209440Smav if ((sc->caps & HPET_CAP_LEG_RT) == 0) 491209440Smav sc->legacy_route = 0; 492209440Smav if (sc->legacy_route) { 493209440Smav sc->t[0].vectors = 0; 494209440Smav sc->t[1].vectors = 0; 495209440Smav } 496209440Smav 497212238Smav /* Check what IRQs we want use. */ 498212238Smav /* By default allow any PCI IRQs. */ 499212238Smav sc->allowed_irqs = 0xffff0000; 500209371Smav /* 501209371Smav * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 502209371Smav * Lower are also not always working for different reasons. 503209371Smav * SB800 fixed it, but seems do not implements level triggering 504209371Smav * properly, that makes it very unreliable - it freezes after any 505209371Smav * interrupt loss. Avoid legacy IRQs for AMD. 506209371Smav */ 507209371Smav if (vendor == HPET_VENDID_AMD) 508212238Smav sc->allowed_irqs = 0x00000000; 509212238Smav /* 510213302Smav * NVidia MCP5x chipsets have number of unexplained interrupt 511213302Smav * problems. For some reason, using HPET interrupts breaks HDA sound. 512213302Smav */ 513213302Smav if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 514213302Smav sc->allowed_irqs = 0x00000000; 515213302Smav /* 516212238Smav * Neither QEMU nor VirtualBox report supported IRQs correctly. 517212238Smav * The only way to use HPET there is to specify IRQs manually 518215473Sjhb * and/or use legacy_route. Legacy_route mode works on both. 519212238Smav */ 520212238Smav if (vm_guest) 521212238Smav sc->allowed_irqs = 0x00000000; 522212238Smav /* Let user override. */ 523212238Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 524212238Smav "allowed_irqs", &sc->allowed_irqs); 525212238Smav 526212533Smav /* Get how much per-CPU timers we should try to provide. */ 527212533Smav sc->per_cpu = 1; 528212533Smav resource_int_value(device_get_name(dev), device_get_unit(dev), 529212533Smav "per_cpu", &sc->per_cpu); 530212533Smav 531212238Smav num_msi = 0; 532212238Smav sc->useirq = 0; 533212238Smav /* Find IRQ vectors for all timers. */ 534212238Smav cvectors = sc->allowed_irqs & 0xffff0000; 535212238Smav dvectors = sc->allowed_irqs & 0x0000ffff; 536212238Smav if (sc->legacy_route) 537212238Smav dvectors &= 0x0000fefe; 538209371Smav for (i = 0; i < num_timers; i++) { 539209371Smav t = &sc->t[i]; 540209440Smav if (sc->legacy_route && i < 2) 541209440Smav t->irq = (i == 0) ? 0 : 8; 542209371Smav#ifdef DEV_APIC 543209440Smav else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 544209371Smav if ((j = PCIB_ALLOC_MSIX( 545209371Smav device_get_parent(device_get_parent(dev)), dev, 546209371Smav &t->irq))) { 547209371Smav device_printf(dev, 548209440Smav "Can't allocate interrupt for t%d.\n", j); 549209440Smav } 550209440Smav } 551209440Smav#endif 552212238Smav else if (dvectors & t->vectors) { 553212238Smav t->irq = ffs(dvectors & t->vectors) - 1; 554212238Smav dvectors &= ~(1 << t->irq); 555212238Smav } 556209440Smav if (t->irq >= 0) { 557216263Sjhb t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 558216490Sjhb t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 559216490Sjhb &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 560216490Sjhb if (t->intr_res == NULL) { 561209440Smav t->irq = -1; 562209440Smav device_printf(dev, 563209440Smav "Can't map interrupt for t%d.\n", i); 564216490Sjhb } else if (bus_setup_intr(dev, t->intr_res, 565216490Sjhb INTR_TYPE_CLK, hpet_intr_single, NULL, t, 566216490Sjhb &t->intr_handle) != 0) { 567209440Smav t->irq = -1; 568209440Smav device_printf(dev, 569209440Smav "Can't setup interrupt for t%d.\n", i); 570209371Smav } else { 571209371Smav bus_describe_intr(dev, t->intr_res, 572209371Smav t->intr_handle, "t%d", i); 573209371Smav num_msi++; 574209371Smav } 575209440Smav } 576209440Smav if (t->irq < 0 && (cvectors & t->vectors) != 0) { 577209371Smav cvectors &= t->vectors; 578209371Smav sc->useirq |= (1 << i); 579209371Smav } 580209371Smav } 581209440Smav if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 582209440Smav sc->legacy_route = 0; 583209440Smav if (sc->legacy_route) 584209440Smav hpet_enable(sc); 585209440Smav /* Group timers for per-CPU operation. */ 586212533Smav num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 587209440Smav num_percpu_t = num_percpu_et * mp_ncpus; 588209440Smav pcpu_master = 0; 589209440Smav cur_cpu = CPU_FIRST(); 590209440Smav for (i = 0; i < num_timers; i++) { 591209440Smav t = &sc->t[i]; 592209440Smav if (t->irq >= 0 && num_percpu_t > 0) { 593209440Smav if (cur_cpu == CPU_FIRST()) 594209440Smav pcpu_master = i; 595212323Smav t->pcpu_cpu = cur_cpu; 596209440Smav t->pcpu_master = pcpu_master; 597209440Smav sc->t[pcpu_master]. 598209440Smav pcpu_slaves[cur_cpu] = i; 599209440Smav bus_bind_intr(dev, t->intr_res, cur_cpu); 600209440Smav cur_cpu = CPU_NEXT(cur_cpu); 601209440Smav num_percpu_t--; 602212238Smav } else if (t->irq >= 0) 603212238Smav bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 604209440Smav } 605209371Smav bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 606209371Smav sc->irq = -1; 607215473Sjhb /* If at least one timer needs legacy IRQ - set it up. */ 608209371Smav if (sc->useirq) { 609209371Smav j = i = fls(cvectors) - 1; 610209371Smav while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 611209371Smav j--; 612216263Sjhb sc->intr_rid = hpet_find_irq_rid(dev, j, i); 613216490Sjhb sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 614216490Sjhb &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 615216490Sjhb if (sc->intr_res == NULL) 616216490Sjhb device_printf(dev, "Can't map interrupt.\n"); 617216490Sjhb else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 618216490Sjhb hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 619209371Smav device_printf(dev, "Can't setup interrupt.\n"); 620209371Smav } else { 621209371Smav sc->irq = rman_get_start(sc->intr_res); 622209371Smav /* Bind IRQ to BSP to avoid live migration. */ 623209371Smav bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 624209371Smav } 625209371Smav } 626209371Smav /* Program and announce event timers. */ 627209371Smav for (i = 0; i < num_timers; i++) { 628209371Smav t = &sc->t[i]; 629209371Smav t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 630209371Smav t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 631209440Smav t->caps &= ~(HPET_TCNF_INT_TYPE); 632209371Smav t->caps |= HPET_TCNF_32MODE; 633209440Smav if (t->irq >= 0 && sc->legacy_route && i < 2) { 634209440Smav /* Legacy route doesn't need more configuration. */ 635209440Smav } else 636209371Smav#ifdef DEV_APIC 637212238Smav if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 638209371Smav uint64_t addr; 639209371Smav uint32_t data; 640209371Smav 641209371Smav if (PCIB_MAP_MSI( 642209371Smav device_get_parent(device_get_parent(dev)), dev, 643209371Smav t->irq, &addr, &data) == 0) { 644209371Smav bus_write_4(sc->mem_res, 645209371Smav HPET_TIMER_FSB_ADDR(i), addr); 646209371Smav bus_write_4(sc->mem_res, 647209371Smav HPET_TIMER_FSB_VAL(i), data); 648209371Smav t->caps |= HPET_TCNF_FSB_EN; 649209371Smav } else 650209371Smav t->irq = -2; 651209371Smav } else 652209371Smav#endif 653212238Smav if (t->irq >= 0) 654212238Smav t->caps |= (t->irq << 9); 655212238Smav else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 656209371Smav t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 657209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 658209371Smav /* Skip event timers without set up IRQ. */ 659209371Smav if (t->irq < 0 && 660209371Smav (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 661209371Smav continue; 662209371Smav /* Announce the reset. */ 663209371Smav if (maxhpetet == 0) 664209371Smav t->et.et_name = "HPET"; 665209371Smav else { 666209371Smav sprintf(t->name, "HPET%d", maxhpetet); 667209371Smav t->et.et_name = t->name; 668209371Smav } 669209371Smav t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 670209371Smav t->et.et_quality = 450; 671209371Smav if (t->pcpu_master >= 0) { 672209371Smav t->et.et_flags |= ET_FLAGS_PERCPU; 673209371Smav t->et.et_quality += 100; 674209371Smav } 675209371Smav if ((t->caps & HPET_TCAP_PER_INT) == 0) 676209371Smav t->et.et_quality -= 10; 677209371Smav t->et.et_frequency = sc->freq; 678210290Smav t->et.et_min_period.sec = 0; 679224919Smav t->et.et_min_period.frac = 680224919Smav (((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq) << 32; 681210298Smav t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq; 682210290Smav t->et.et_max_period.frac = 683210298Smav ((0xfffffffeLLU << 32) / sc->freq) << 32; 684209371Smav t->et.et_start = hpet_start; 685209371Smav t->et.et_stop = hpet_stop; 686209371Smav t->et.et_priv = &sc->t[i]; 687209371Smav if (t->pcpu_master < 0 || t->pcpu_master == i) { 688209371Smav et_register(&t->et); 689209371Smav maxhpetet++; 690209371Smav } 691209371Smav } 692159217Snjl return (0); 693159217Snjl} 694159217Snjl 695159217Snjlstatic int 696209371Smavhpet_detach(device_t dev) 697159217Snjl{ 698159217Snjl ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 699159217Snjl 700159217Snjl /* XXX Without a tc_remove() function, we can't detach. */ 701159217Snjl return (EBUSY); 702159217Snjl} 703159217Snjl 704168010Snjlstatic int 705209371Smavhpet_suspend(device_t dev) 706175361Sjhb{ 707212541Smav// struct hpet_softc *sc; 708175361Sjhb 709175361Sjhb /* 710175361Sjhb * Disable the timer during suspend. The timer will not lose 711175361Sjhb * its state in S1 or S2, but we are required to disable 712175361Sjhb * it. 713175361Sjhb */ 714212541Smav// sc = device_get_softc(dev); 715212541Smav// hpet_disable(sc); 716175361Sjhb 717175361Sjhb return (0); 718175361Sjhb} 719175361Sjhb 720175361Sjhbstatic int 721209371Smavhpet_resume(device_t dev) 722168010Snjl{ 723209371Smav struct hpet_softc *sc; 724209371Smav struct hpet_timer *t; 725209371Smav int i; 726168010Snjl 727168010Snjl /* Re-enable the timer after a resume to keep the clock advancing. */ 728168010Snjl sc = device_get_softc(dev); 729175361Sjhb hpet_enable(sc); 730209371Smav /* Restart event timers that were running on suspend. */ 731209371Smav for (i = 0; i < sc->num_timers; i++) { 732209371Smav t = &sc->t[i]; 733209371Smav#ifdef DEV_APIC 734209440Smav if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 735209371Smav uint64_t addr; 736209371Smav uint32_t data; 737209371Smav 738209371Smav if (PCIB_MAP_MSI( 739209371Smav device_get_parent(device_get_parent(dev)), dev, 740209371Smav t->irq, &addr, &data) == 0) { 741209371Smav bus_write_4(sc->mem_res, 742209371Smav HPET_TIMER_FSB_ADDR(i), addr); 743209371Smav bus_write_4(sc->mem_res, 744209371Smav HPET_TIMER_FSB_VAL(i), data); 745209371Smav } 746209371Smav } 747209371Smav#endif 748209371Smav if (t->mode == 0) 749209371Smav continue; 750212491Smav t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 751209371Smav if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 752209371Smav t->caps |= HPET_TCNF_TYPE; 753212491Smav t->next += t->div; 754209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 755209371Smav t->caps | HPET_TCNF_VAL_SET); 756209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 757212491Smav t->next); 758209371Smav bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 759209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 760209371Smav t->div); 761209371Smav } else { 762212491Smav t->next += sc->freq / 1024; 763209371Smav bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 764212491Smav t->next); 765209371Smav } 766209371Smav bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 767209371Smav bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 768209371Smav } 769168010Snjl return (0); 770168010Snjl} 771168010Snjl 772159217Snjl/* Print some basic latency/rate information to assist in debugging. */ 773159217Snjlstatic void 774209371Smavhpet_test(struct hpet_softc *sc) 775159217Snjl{ 776151912Sphk int i; 777151912Sphk uint32_t u1, u2; 778151912Sphk struct bintime b0, b1, b2; 779151912Sphk struct timespec ts; 780151912Sphk 781151912Sphk binuptime(&b0); 782151912Sphk binuptime(&b0); 783151912Sphk binuptime(&b1); 784175385Sjhb u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 785151912Sphk for (i = 1; i < 1000; i++) 786175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 787151912Sphk binuptime(&b2); 788175385Sjhb u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 789151912Sphk 790151912Sphk bintime_sub(&b2, &b1); 791151912Sphk bintime_sub(&b1, &b0); 792151912Sphk bintime_sub(&b2, &b1); 793151912Sphk bintime2timespec(&b2, &ts); 794151912Sphk 795159217Snjl device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 796151912Sphk (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 797151912Sphk 798159217Snjl device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 799151912Sphk} 800151912Sphk 801209371Smav#ifdef DEV_APIC 802209371Smavstatic int 803209371Smavhpet_remap_intr(device_t dev, device_t child, u_int irq) 804209371Smav{ 805209371Smav struct hpet_softc *sc = device_get_softc(dev); 806209371Smav struct hpet_timer *t; 807209371Smav uint64_t addr; 808209371Smav uint32_t data; 809209371Smav int error, i; 810209371Smav 811209371Smav for (i = 0; i < sc->num_timers; i++) { 812209371Smav t = &sc->t[i]; 813209371Smav if (t->irq != irq) 814209371Smav continue; 815209371Smav error = PCIB_MAP_MSI( 816209371Smav device_get_parent(device_get_parent(dev)), dev, 817209371Smav irq, &addr, &data); 818209371Smav if (error) 819209371Smav return (error); 820209371Smav hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 821209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 822209371Smav bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 823209371Smav hpet_enable(sc); 824209371Smav return (0); 825209371Smav } 826209371Smav return (ENOENT); 827209371Smav} 828209371Smav#endif 829209371Smav 830209371Smavstatic device_method_t hpet_methods[] = { 831151912Sphk /* Device interface */ 832209371Smav DEVMETHOD(device_identify, hpet_identify), 833209371Smav DEVMETHOD(device_probe, hpet_probe), 834209371Smav DEVMETHOD(device_attach, hpet_attach), 835209371Smav DEVMETHOD(device_detach, hpet_detach), 836209371Smav DEVMETHOD(device_suspend, hpet_suspend), 837209371Smav DEVMETHOD(device_resume, hpet_resume), 838151912Sphk 839209371Smav#ifdef DEV_APIC 840209371Smav DEVMETHOD(bus_remap_intr, hpet_remap_intr), 841209371Smav#endif 842209371Smav 843151912Sphk {0, 0} 844151912Sphk}; 845151912Sphk 846209371Smavstatic driver_t hpet_driver = { 847209371Smav "hpet", 848209371Smav hpet_methods, 849209371Smav sizeof(struct hpet_softc), 850151912Sphk}; 851151912Sphk 852209371SmavDRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 853209371SmavMODULE_DEPEND(hpet, acpi, 1, 1, 1); 854