acpi_hpet.c revision 215473
193000Sobrien/*- 293000Sobrien * Copyright (c) 2005 Poul-Henning Kamp 393000Sobrien * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 425045Sbde * All rights reserved. 525045Sbde * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 215473 2010-11-18 22:17:20Z jhb $"); 30 31#include "opt_acpi.h" 32#if defined(__amd64__) || defined(__ia64__) 33#define DEV_APIC 34#else 35#include "opt_apic.h" 36#endif 37#include <sys/param.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/proc.h> 42#include <sys/rman.h> 43#include <sys/time.h> 44#include <sys/smp.h> 45#include <sys/sysctl.h> 46#include <sys/timeet.h> 47#include <sys/timetc.h> 48 49#include <contrib/dev/acpica/include/acpi.h> 50#include <contrib/dev/acpica/include/accommon.h> 51 52#include <dev/acpica/acpivar.h> 53#include <dev/acpica/acpi_hpet.h> 54 55#ifdef DEV_APIC 56#include "pcib_if.h" 57#endif 58 59#define HPET_VENDID_AMD 0x4353 60#define HPET_VENDID_INTEL 0x8086 61#define HPET_VENDID_NVIDIA 0x10de 62 63ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 64 65static devclass_t hpet_devclass; 66 67/* ACPI CA debugging */ 68#define _COMPONENT ACPI_TIMER 69ACPI_MODULE_NAME("HPET") 70 71struct hpet_softc { 72 device_t dev; 73 int mem_rid; 74 int intr_rid; 75 int irq; 76 int useirq; 77 int legacy_route; 78 int per_cpu; 79 uint32_t allowed_irqs; 80 struct resource *mem_res; 81 struct resource *intr_res; 82 void *intr_handle; 83 ACPI_HANDLE handle; 84 uint64_t freq; 85 uint32_t caps; 86 struct timecounter tc; 87 struct hpet_timer { 88 struct eventtimer et; 89 struct hpet_softc *sc; 90 int num; 91 int mode; 92 int intr_rid; 93 int irq; 94 int pcpu_cpu; 95 int pcpu_misrouted; 96 int pcpu_master; 97 int pcpu_slaves[MAXCPU]; 98 struct resource *intr_res; 99 void *intr_handle; 100 uint32_t caps; 101 uint32_t vectors; 102 uint32_t div; 103 uint32_t next; 104 char name[8]; 105 } t[32]; 106 int num_timers; 107}; 108 109static u_int hpet_get_timecount(struct timecounter *tc); 110static void hpet_test(struct hpet_softc *sc); 111 112static char *hpet_ids[] = { "PNP0103", NULL }; 113 114static u_int 115hpet_get_timecount(struct timecounter *tc) 116{ 117 struct hpet_softc *sc; 118 119 sc = tc->tc_priv; 120 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 121} 122 123static void 124hpet_enable(struct hpet_softc *sc) 125{ 126 uint32_t val; 127 128 val = bus_read_4(sc->mem_res, HPET_CONFIG); 129 if (sc->legacy_route) 130 val |= HPET_CNF_LEG_RT; 131 else 132 val &= ~HPET_CNF_LEG_RT; 133 val |= HPET_CNF_ENABLE; 134 bus_write_4(sc->mem_res, HPET_CONFIG, val); 135} 136 137static void 138hpet_disable(struct hpet_softc *sc) 139{ 140 uint32_t val; 141 142 val = bus_read_4(sc->mem_res, HPET_CONFIG); 143 val &= ~HPET_CNF_ENABLE; 144 bus_write_4(sc->mem_res, HPET_CONFIG, val); 145} 146 147static int 148hpet_start(struct eventtimer *et, 149 struct bintime *first, struct bintime *period) 150{ 151 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 152 struct hpet_timer *t; 153 struct hpet_softc *sc = mt->sc; 154 uint32_t fdiv, now; 155 156 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 157 if (period != NULL) { 158 t->mode = 1; 159 t->div = (sc->freq * (period->frac >> 32)) >> 32; 160 if (period->sec != 0) 161 t->div += sc->freq * period->sec; 162 } else { 163 t->mode = 2; 164 t->div = 0; 165 } 166 if (first != NULL) { 167 fdiv = (sc->freq * (first->frac >> 32)) >> 32; 168 if (first->sec != 0) 169 fdiv += sc->freq * first->sec; 170 } else 171 fdiv = t->div; 172 if (t->irq < 0) 173 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 174 t->caps |= HPET_TCNF_INT_ENB; 175 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 176restart: 177 t->next = now + fdiv; 178 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 179 t->caps |= HPET_TCNF_TYPE; 180 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 181 t->caps | HPET_TCNF_VAL_SET); 182 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 183 t->next); 184 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 185 t->div); 186 } else { 187 t->caps &= ~HPET_TCNF_TYPE; 188 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 189 t->caps); 190 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 191 t->next); 192 } 193 if (fdiv < 5000) { 194 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 195 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 196 if ((int32_t)(now - t->next) >= 0) { 197 fdiv *= 2; 198 goto restart; 199 } 200 } 201 return (0); 202} 203 204static int 205hpet_stop(struct eventtimer *et) 206{ 207 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 208 struct hpet_timer *t; 209 struct hpet_softc *sc = mt->sc; 210 211 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 212 t->mode = 0; 213 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 214 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 215 return (0); 216} 217 218static int 219hpet_intr_single(void *arg) 220{ 221 struct hpet_timer *t = (struct hpet_timer *)arg; 222 struct hpet_timer *mt; 223 struct hpet_softc *sc = t->sc; 224 uint32_t now; 225 226 if (t->mode == 0) 227 return (FILTER_STRAY); 228 /* Check that per-CPU timer interrupt reached right CPU. */ 229 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 230 if ((++t->pcpu_misrouted) % 32 == 0) { 231 printf("HPET interrupt routed to the wrong CPU" 232 " (timer %d CPU %d -> %d)!\n", 233 t->num, t->pcpu_cpu, curcpu); 234 } 235 236 /* 237 * Reload timer, hoping that next time may be more lucky 238 * (system will manage proper interrupt binding). 239 */ 240 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 241 t->mode == 2) { 242 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 243 sc->freq / 8; 244 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 245 t->next); 246 } 247 return (FILTER_HANDLED); 248 } 249 if (t->mode == 1 && 250 (t->caps & HPET_TCAP_PER_INT) == 0) { 251 t->next += t->div; 252 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 253 if ((int32_t)((now + t->div / 2) - t->next) > 0) 254 t->next = now + t->div / 2; 255 bus_write_4(sc->mem_res, 256 HPET_TIMER_COMPARATOR(t->num), t->next); 257 } else if (t->mode == 2) 258 t->mode = 0; 259 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 260 if (mt->et.et_active) 261 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 262 return (FILTER_HANDLED); 263} 264 265static int 266hpet_intr(void *arg) 267{ 268 struct hpet_softc *sc = (struct hpet_softc *)arg; 269 int i; 270 uint32_t val; 271 272 val = bus_read_4(sc->mem_res, HPET_ISR); 273 if (val) { 274 bus_write_4(sc->mem_res, HPET_ISR, val); 275 val &= sc->useirq; 276 for (i = 0; i < sc->num_timers; i++) { 277 if ((val & (1 << i)) == 0) 278 continue; 279 hpet_intr_single(&sc->t[i]); 280 } 281 return (FILTER_HANDLED); 282 } 283 return (FILTER_STRAY); 284} 285 286static ACPI_STATUS 287hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 288 void **status) 289{ 290 char **ids; 291 uint32_t id = (uint32_t)(uintptr_t)context; 292 uint32_t uid = 0; 293 294 for (ids = hpet_ids; *ids != NULL; ids++) { 295 if (acpi_MatchHid(handle, *ids)) 296 break; 297 } 298 if (*ids == NULL) 299 return (AE_OK); 300 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 301 id == uid) 302 *((int *)status) = 1; 303 return (AE_OK); 304} 305 306/* Discover the HPET via the ACPI table of the same name. */ 307static void 308hpet_identify(driver_t *driver, device_t parent) 309{ 310 ACPI_TABLE_HPET *hpet; 311 ACPI_STATUS status; 312 device_t child; 313 int i, found; 314 315 /* Only one HPET device can be added. */ 316 if (devclass_get_device(hpet_devclass, 0)) 317 return; 318 for (i = 1; ; i++) { 319 /* Search for HPET table. */ 320 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 321 if (ACPI_FAILURE(status)) 322 return; 323 /* Search for HPET device with same ID. */ 324 found = 0; 325 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 326 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 327 /* If found - let it be probed in normal way. */ 328 if (found) 329 continue; 330 /* If not - create it from table info. */ 331 child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0); 332 if (child == NULL) { 333 printf("%s: can't add child\n", __func__); 334 continue; 335 } 336 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 337 HPET_MEM_WIDTH); 338 } 339} 340 341static int 342hpet_probe(device_t dev) 343{ 344 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 345 346 if (acpi_disabled("hpet")) 347 return (ENXIO); 348 if (acpi_get_handle(dev) != NULL && 349 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 350 return (ENXIO); 351 352 device_set_desc(dev, "High Precision Event Timer"); 353 return (0); 354} 355 356static int 357hpet_attach(device_t dev) 358{ 359 struct hpet_softc *sc; 360 struct hpet_timer *t; 361 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 362 int pcpu_master; 363 static int maxhpetet = 0; 364 uint32_t val, val2, cvectors, dvectors; 365 uint16_t vendor, rev; 366 367 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 368 369 sc = device_get_softc(dev); 370 sc->dev = dev; 371 sc->handle = acpi_get_handle(dev); 372 373 sc->mem_rid = 0; 374 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 375 RF_ACTIVE); 376 if (sc->mem_res == NULL) 377 return (ENOMEM); 378 379 /* Validate that we can access the whole region. */ 380 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 381 device_printf(dev, "memory region width %ld too small\n", 382 rman_get_size(sc->mem_res)); 383 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 384 return (ENXIO); 385 } 386 387 /* Be sure timer is enabled. */ 388 hpet_enable(sc); 389 390 /* Read basic statistics about the timer. */ 391 val = bus_read_4(sc->mem_res, HPET_PERIOD); 392 if (val == 0) { 393 device_printf(dev, "invalid period\n"); 394 hpet_disable(sc); 395 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 396 return (ENXIO); 397 } 398 399 sc->freq = (1000000000000000LL + val / 2) / val; 400 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 401 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 402 rev = sc->caps & HPET_CAP_REV_ID; 403 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 404 /* 405 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 406 * Specification and provides an off by one number 407 * of timers/comparators. 408 * Additionally, they use unregistered value in VENDOR_ID field. 409 */ 410 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 411 num_timers--; 412 sc->num_timers = num_timers; 413 if (bootverbose) { 414 device_printf(dev, 415 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 416 vendor, rev, sc->freq, 417 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 418 num_timers, 419 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 420 } 421 for (i = 0; i < num_timers; i++) { 422 t = &sc->t[i]; 423 t->sc = sc; 424 t->num = i; 425 t->mode = 0; 426 t->intr_rid = -1; 427 t->irq = -1; 428 t->pcpu_cpu = -1; 429 t->pcpu_misrouted = 0; 430 t->pcpu_master = -1; 431 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 432 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 433 if (bootverbose) { 434 device_printf(dev, 435 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 436 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 437 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 438 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 439 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 440 } 441 } 442 if (testenv("debug.acpi.hpet_test")) 443 hpet_test(sc); 444 /* 445 * Don't attach if the timer never increments. Since the spec 446 * requires it to be at least 10 MHz, it has to change in 1 us. 447 */ 448 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 449 DELAY(1); 450 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 451 if (val == val2) { 452 device_printf(dev, "HPET never increments, disabling\n"); 453 hpet_disable(sc); 454 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 455 return (ENXIO); 456 } 457 /* Announce first HPET as timecounter. */ 458 if (device_get_unit(dev) == 0) { 459 sc->tc.tc_get_timecount = hpet_get_timecount, 460 sc->tc.tc_counter_mask = ~0u, 461 sc->tc.tc_name = "HPET", 462 sc->tc.tc_quality = 900, 463 sc->tc.tc_frequency = sc->freq; 464 sc->tc.tc_priv = sc; 465 tc_init(&sc->tc); 466 } 467 /* If not disabled - setup and announce event timers. */ 468 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 469 "clock", &i) == 0 && i == 0) 470 return (0); 471 472 /* Check whether we can and want legacy routing. */ 473 sc->legacy_route = 0; 474 resource_int_value(device_get_name(dev), device_get_unit(dev), 475 "legacy_route", &sc->legacy_route); 476 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 477 sc->legacy_route = 0; 478 if (sc->legacy_route) { 479 sc->t[0].vectors = 0; 480 sc->t[1].vectors = 0; 481 } 482 483 /* Check what IRQs we want use. */ 484 /* By default allow any PCI IRQs. */ 485 sc->allowed_irqs = 0xffff0000; 486 /* 487 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 488 * Lower are also not always working for different reasons. 489 * SB800 fixed it, but seems do not implements level triggering 490 * properly, that makes it very unreliable - it freezes after any 491 * interrupt loss. Avoid legacy IRQs for AMD. 492 */ 493 if (vendor == HPET_VENDID_AMD) 494 sc->allowed_irqs = 0x00000000; 495 /* 496 * NVidia MCP5x chipsets have number of unexplained interrupt 497 * problems. For some reason, using HPET interrupts breaks HDA sound. 498 */ 499 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 500 sc->allowed_irqs = 0x00000000; 501 /* 502 * Neither QEMU nor VirtualBox report supported IRQs correctly. 503 * The only way to use HPET there is to specify IRQs manually 504 * and/or use legacy_route. Legacy_route mode works on both. 505 */ 506 if (vm_guest) 507 sc->allowed_irqs = 0x00000000; 508 /* Let user override. */ 509 resource_int_value(device_get_name(dev), device_get_unit(dev), 510 "allowed_irqs", &sc->allowed_irqs); 511 512 /* Get how much per-CPU timers we should try to provide. */ 513 sc->per_cpu = 1; 514 resource_int_value(device_get_name(dev), device_get_unit(dev), 515 "per_cpu", &sc->per_cpu); 516 517 num_msi = 0; 518 sc->useirq = 0; 519 /* Find IRQ vectors for all timers. */ 520 cvectors = sc->allowed_irqs & 0xffff0000; 521 dvectors = sc->allowed_irqs & 0x0000ffff; 522 if (sc->legacy_route) 523 dvectors &= 0x0000fefe; 524 for (i = 0; i < num_timers; i++) { 525 t = &sc->t[i]; 526 if (sc->legacy_route && i < 2) 527 t->irq = (i == 0) ? 0 : 8; 528#ifdef DEV_APIC 529 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 530 if ((j = PCIB_ALLOC_MSIX( 531 device_get_parent(device_get_parent(dev)), dev, 532 &t->irq))) { 533 device_printf(dev, 534 "Can't allocate interrupt for t%d.\n", j); 535 } 536 } 537#endif 538 else if (dvectors & t->vectors) { 539 t->irq = ffs(dvectors & t->vectors) - 1; 540 dvectors &= ~(1 << t->irq); 541 } 542 if (t->irq >= 0) { 543 if (!(t->intr_res = 544 bus_alloc_resource(dev, SYS_RES_IRQ, &t->intr_rid, 545 t->irq, t->irq, 1, RF_ACTIVE))) { 546 t->irq = -1; 547 device_printf(dev, 548 "Can't map interrupt for t%d.\n", i); 549 } else if ((bus_setup_intr(dev, t->intr_res, 550 INTR_MPSAFE | INTR_TYPE_CLK, 551 (driver_filter_t *)hpet_intr_single, NULL, 552 t, &t->intr_handle))) { 553 t->irq = -1; 554 device_printf(dev, 555 "Can't setup interrupt for t%d.\n", i); 556 } else { 557 bus_describe_intr(dev, t->intr_res, 558 t->intr_handle, "t%d", i); 559 num_msi++; 560 } 561 } 562 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 563 cvectors &= t->vectors; 564 sc->useirq |= (1 << i); 565 } 566 } 567 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 568 sc->legacy_route = 0; 569 if (sc->legacy_route) 570 hpet_enable(sc); 571 /* Group timers for per-CPU operation. */ 572 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 573 num_percpu_t = num_percpu_et * mp_ncpus; 574 pcpu_master = 0; 575 cur_cpu = CPU_FIRST(); 576 for (i = 0; i < num_timers; i++) { 577 t = &sc->t[i]; 578 if (t->irq >= 0 && num_percpu_t > 0) { 579 if (cur_cpu == CPU_FIRST()) 580 pcpu_master = i; 581 t->pcpu_cpu = cur_cpu; 582 t->pcpu_master = pcpu_master; 583 sc->t[pcpu_master]. 584 pcpu_slaves[cur_cpu] = i; 585 bus_bind_intr(dev, t->intr_res, cur_cpu); 586 cur_cpu = CPU_NEXT(cur_cpu); 587 num_percpu_t--; 588 } else if (t->irq >= 0) 589 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 590 } 591 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 592 sc->irq = -1; 593 sc->intr_rid = -1; 594 /* If at least one timer needs legacy IRQ - set it up. */ 595 if (sc->useirq) { 596 j = i = fls(cvectors) - 1; 597 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 598 j--; 599 if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 600 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE))) 601 device_printf(dev,"Can't map interrupt.\n"); 602 else if ((bus_setup_intr(dev, sc->intr_res, 603 INTR_MPSAFE | INTR_TYPE_CLK, 604 (driver_filter_t *)hpet_intr, NULL, 605 sc, &sc->intr_handle))) { 606 device_printf(dev, "Can't setup interrupt.\n"); 607 } else { 608 sc->irq = rman_get_start(sc->intr_res); 609 /* Bind IRQ to BSP to avoid live migration. */ 610 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 611 } 612 } 613 /* Program and announce event timers. */ 614 for (i = 0; i < num_timers; i++) { 615 t = &sc->t[i]; 616 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 617 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 618 t->caps &= ~(HPET_TCNF_INT_TYPE); 619 t->caps |= HPET_TCNF_32MODE; 620 if (t->irq >= 0 && sc->legacy_route && i < 2) { 621 /* Legacy route doesn't need more configuration. */ 622 } else 623#ifdef DEV_APIC 624 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 625 uint64_t addr; 626 uint32_t data; 627 628 if (PCIB_MAP_MSI( 629 device_get_parent(device_get_parent(dev)), dev, 630 t->irq, &addr, &data) == 0) { 631 bus_write_4(sc->mem_res, 632 HPET_TIMER_FSB_ADDR(i), addr); 633 bus_write_4(sc->mem_res, 634 HPET_TIMER_FSB_VAL(i), data); 635 t->caps |= HPET_TCNF_FSB_EN; 636 } else 637 t->irq = -2; 638 } else 639#endif 640 if (t->irq >= 0) 641 t->caps |= (t->irq << 9); 642 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 643 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 644 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 645 /* Skip event timers without set up IRQ. */ 646 if (t->irq < 0 && 647 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 648 continue; 649 /* Announce the reset. */ 650 if (maxhpetet == 0) 651 t->et.et_name = "HPET"; 652 else { 653 sprintf(t->name, "HPET%d", maxhpetet); 654 t->et.et_name = t->name; 655 } 656 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 657 t->et.et_quality = 450; 658 if (t->pcpu_master >= 0) { 659 t->et.et_flags |= ET_FLAGS_PERCPU; 660 t->et.et_quality += 100; 661 } 662 if ((t->caps & HPET_TCAP_PER_INT) == 0) 663 t->et.et_quality -= 10; 664 t->et.et_frequency = sc->freq; 665 t->et.et_min_period.sec = 0; 666 t->et.et_min_period.frac = 0x00008000LLU << 32; 667 t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq; 668 t->et.et_max_period.frac = 669 ((0xfffffffeLLU << 32) / sc->freq) << 32; 670 t->et.et_start = hpet_start; 671 t->et.et_stop = hpet_stop; 672 t->et.et_priv = &sc->t[i]; 673 if (t->pcpu_master < 0 || t->pcpu_master == i) { 674 et_register(&t->et); 675 maxhpetet++; 676 } 677 } 678 return (0); 679} 680 681static int 682hpet_detach(device_t dev) 683{ 684 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 685 686 /* XXX Without a tc_remove() function, we can't detach. */ 687 return (EBUSY); 688} 689 690static int 691hpet_suspend(device_t dev) 692{ 693// struct hpet_softc *sc; 694 695 /* 696 * Disable the timer during suspend. The timer will not lose 697 * its state in S1 or S2, but we are required to disable 698 * it. 699 */ 700// sc = device_get_softc(dev); 701// hpet_disable(sc); 702 703 return (0); 704} 705 706static int 707hpet_resume(device_t dev) 708{ 709 struct hpet_softc *sc; 710 struct hpet_timer *t; 711 int i; 712 713 /* Re-enable the timer after a resume to keep the clock advancing. */ 714 sc = device_get_softc(dev); 715 hpet_enable(sc); 716 /* Restart event timers that were running on suspend. */ 717 for (i = 0; i < sc->num_timers; i++) { 718 t = &sc->t[i]; 719#ifdef DEV_APIC 720 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 721 uint64_t addr; 722 uint32_t data; 723 724 if (PCIB_MAP_MSI( 725 device_get_parent(device_get_parent(dev)), dev, 726 t->irq, &addr, &data) == 0) { 727 bus_write_4(sc->mem_res, 728 HPET_TIMER_FSB_ADDR(i), addr); 729 bus_write_4(sc->mem_res, 730 HPET_TIMER_FSB_VAL(i), data); 731 } 732 } 733#endif 734 if (t->mode == 0) 735 continue; 736 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 737 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 738 t->caps |= HPET_TCNF_TYPE; 739 t->next += t->div; 740 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 741 t->caps | HPET_TCNF_VAL_SET); 742 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 743 t->next); 744 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 745 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 746 t->div); 747 } else { 748 t->next += sc->freq / 1024; 749 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 750 t->next); 751 } 752 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 753 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 754 } 755 return (0); 756} 757 758/* Print some basic latency/rate information to assist in debugging. */ 759static void 760hpet_test(struct hpet_softc *sc) 761{ 762 int i; 763 uint32_t u1, u2; 764 struct bintime b0, b1, b2; 765 struct timespec ts; 766 767 binuptime(&b0); 768 binuptime(&b0); 769 binuptime(&b1); 770 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 771 for (i = 1; i < 1000; i++) 772 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 773 binuptime(&b2); 774 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 775 776 bintime_sub(&b2, &b1); 777 bintime_sub(&b1, &b0); 778 bintime_sub(&b2, &b1); 779 bintime2timespec(&b2, &ts); 780 781 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 782 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 783 784 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 785} 786 787#ifdef DEV_APIC 788static int 789hpet_remap_intr(device_t dev, device_t child, u_int irq) 790{ 791 struct hpet_softc *sc = device_get_softc(dev); 792 struct hpet_timer *t; 793 uint64_t addr; 794 uint32_t data; 795 int error, i; 796 797 for (i = 0; i < sc->num_timers; i++) { 798 t = &sc->t[i]; 799 if (t->irq != irq) 800 continue; 801 error = PCIB_MAP_MSI( 802 device_get_parent(device_get_parent(dev)), dev, 803 irq, &addr, &data); 804 if (error) 805 return (error); 806 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 807 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 808 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 809 hpet_enable(sc); 810 return (0); 811 } 812 return (ENOENT); 813} 814#endif 815 816static device_method_t hpet_methods[] = { 817 /* Device interface */ 818 DEVMETHOD(device_identify, hpet_identify), 819 DEVMETHOD(device_probe, hpet_probe), 820 DEVMETHOD(device_attach, hpet_attach), 821 DEVMETHOD(device_detach, hpet_detach), 822 DEVMETHOD(device_suspend, hpet_suspend), 823 DEVMETHOD(device_resume, hpet_resume), 824 825#ifdef DEV_APIC 826 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 827#endif 828 829 {0, 0} 830}; 831 832static driver_t hpet_driver = { 833 "hpet", 834 hpet_methods, 835 sizeof(struct hpet_softc), 836}; 837 838DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 839MODULE_DEPEND(hpet, acpi, 1, 1, 1); 840