acpi_hpet.c revision 212491
1/*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/acpica/acpi_hpet.c 212491 2010-09-12 11:11:53Z mav $"); 30 31#include "opt_acpi.h" 32#if defined(__amd64__) || defined(__ia64__) 33#define DEV_APIC 34#else 35#include "opt_apic.h" 36#endif 37#include <sys/param.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/proc.h> 42#include <sys/rman.h> 43#include <sys/time.h> 44#include <sys/smp.h> 45#include <sys/sysctl.h> 46#include <sys/timeet.h> 47#include <sys/timetc.h> 48 49#include <contrib/dev/acpica/include/acpi.h> 50#include <contrib/dev/acpica/include/accommon.h> 51 52#include <dev/acpica/acpivar.h> 53#include <dev/acpica/acpi_hpet.h> 54 55#ifdef DEV_APIC 56#include "pcib_if.h" 57#endif 58 59#define HPET_VENDID_AMD 0x4353 60#define HPET_VENDID_INTEL 0x8086 61 62ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 63 64static devclass_t hpet_devclass; 65 66/* ACPI CA debugging */ 67#define _COMPONENT ACPI_TIMER 68ACPI_MODULE_NAME("HPET") 69 70struct hpet_softc { 71 device_t dev; 72 int mem_rid; 73 int intr_rid; 74 int irq; 75 int useirq; 76 int legacy_route; 77 uint32_t allowed_irqs; 78 struct resource *mem_res; 79 struct resource *intr_res; 80 void *intr_handle; 81 ACPI_HANDLE handle; 82 uint64_t freq; 83 uint32_t caps; 84 struct timecounter tc; 85 struct hpet_timer { 86 struct eventtimer et; 87 struct hpet_softc *sc; 88 int num; 89 int mode; 90 int intr_rid; 91 int irq; 92 int pcpu_cpu; 93 int pcpu_misrouted; 94 int pcpu_master; 95 int pcpu_slaves[MAXCPU]; 96 struct resource *intr_res; 97 void *intr_handle; 98 uint32_t caps; 99 uint32_t vectors; 100 uint32_t div; 101 uint32_t next; 102 char name[8]; 103 } t[32]; 104 int num_timers; 105}; 106 107static u_int hpet_get_timecount(struct timecounter *tc); 108static void hpet_test(struct hpet_softc *sc); 109 110static char *hpet_ids[] = { "PNP0103", NULL }; 111 112static u_int 113hpet_get_timecount(struct timecounter *tc) 114{ 115 struct hpet_softc *sc; 116 117 sc = tc->tc_priv; 118 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 119} 120 121static void 122hpet_enable(struct hpet_softc *sc) 123{ 124 uint32_t val; 125 126 val = bus_read_4(sc->mem_res, HPET_CONFIG); 127 if (sc->legacy_route) 128 val |= HPET_CNF_LEG_RT; 129 else 130 val &= ~HPET_CNF_LEG_RT; 131 val |= HPET_CNF_ENABLE; 132 bus_write_4(sc->mem_res, HPET_CONFIG, val); 133} 134 135static void 136hpet_disable(struct hpet_softc *sc) 137{ 138 uint32_t val; 139 140 val = bus_read_4(sc->mem_res, HPET_CONFIG); 141 val &= ~HPET_CNF_ENABLE; 142 bus_write_4(sc->mem_res, HPET_CONFIG, val); 143} 144 145static int 146hpet_start(struct eventtimer *et, 147 struct bintime *first, struct bintime *period) 148{ 149 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 150 struct hpet_timer *t; 151 struct hpet_softc *sc = mt->sc; 152 uint32_t fdiv, now; 153 154 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 155 if (period != NULL) { 156 t->mode = 1; 157 t->div = (sc->freq * (period->frac >> 32)) >> 32; 158 if (period->sec != 0) 159 t->div += sc->freq * period->sec; 160 } else { 161 t->mode = 2; 162 t->div = 0; 163 } 164 if (first != NULL) { 165 fdiv = (sc->freq * (first->frac >> 32)) >> 32; 166 if (first->sec != 0) 167 fdiv += sc->freq * first->sec; 168 } else 169 fdiv = t->div; 170 if (t->irq < 0) 171 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 172 t->caps |= HPET_TCNF_INT_ENB; 173 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 174restart: 175 t->next = now + fdiv; 176 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 177 t->caps |= HPET_TCNF_TYPE; 178 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 179 t->caps | HPET_TCNF_VAL_SET); 180 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 181 t->next); 182 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 183 t->div); 184 } else { 185 t->caps &= ~HPET_TCNF_TYPE; 186 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 187 t->caps); 188 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 189 t->next); 190 } 191 if (fdiv < 5000) { 192 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 193 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 194 if ((int32_t)(now - t->next) >= 0) { 195 fdiv *= 2; 196 goto restart; 197 } 198 } 199 return (0); 200} 201 202static int 203hpet_stop(struct eventtimer *et) 204{ 205 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 206 struct hpet_timer *t; 207 struct hpet_softc *sc = mt->sc; 208 209 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 210 t->mode = 0; 211 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 212 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 213 return (0); 214} 215 216static int 217hpet_intr_single(void *arg) 218{ 219 struct hpet_timer *t = (struct hpet_timer *)arg; 220 struct hpet_timer *mt; 221 struct hpet_softc *sc = t->sc; 222 uint32_t now; 223 224 if (t->mode == 0) 225 return (FILTER_STRAY); 226 /* Check that per-CPU timer interrupt reached right CPU. */ 227 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 228 if ((++t->pcpu_misrouted) % 32 == 0) { 229 printf("HPET interrupt routed to the wrong CPU" 230 " (timer %d CPU %d -> %d)!\n", 231 t->num, t->pcpu_cpu, curcpu); 232 } 233 234 /* 235 * Reload timer, hoping that next time may be more lucky 236 * (system will manage proper interrupt binding). 237 */ 238 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) || 239 t->mode == 2) { 240 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 241 sc->freq / 8; 242 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 243 t->next); 244 } 245 return (FILTER_HANDLED); 246 } 247 if (t->mode == 1 && 248 (t->caps & HPET_TCAP_PER_INT) == 0) { 249 t->next += t->div; 250 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 251 if ((int32_t)((now + t->div / 2) - t->next) > 0) 252 t->next = now + t->div / 2; 253 bus_write_4(sc->mem_res, 254 HPET_TIMER_COMPARATOR(t->num), t->next); 255 } else if (t->mode == 2) 256 t->mode = 0; 257 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 258 if (mt->et.et_active) 259 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 260 return (FILTER_HANDLED); 261} 262 263static int 264hpet_intr(void *arg) 265{ 266 struct hpet_softc *sc = (struct hpet_softc *)arg; 267 int i; 268 uint32_t val; 269 270 val = bus_read_4(sc->mem_res, HPET_ISR); 271 if (val) { 272 bus_write_4(sc->mem_res, HPET_ISR, val); 273 val &= sc->useirq; 274 for (i = 0; i < sc->num_timers; i++) { 275 if ((val & (1 << i)) == 0) 276 continue; 277 hpet_intr_single(&sc->t[i]); 278 } 279 return (FILTER_HANDLED); 280 } 281 return (FILTER_STRAY); 282} 283 284static ACPI_STATUS 285hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 286 void **status) 287{ 288 char **ids; 289 uint32_t id = (uint32_t)(uintptr_t)context; 290 uint32_t uid = 0; 291 292 for (ids = hpet_ids; *ids != NULL; ids++) { 293 if (acpi_MatchHid(handle, *ids)) 294 break; 295 } 296 if (*ids == NULL) 297 return (AE_OK); 298 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 299 id == uid) 300 *((int *)status) = 1; 301 return (AE_OK); 302} 303 304/* Discover the HPET via the ACPI table of the same name. */ 305static void 306hpet_identify(driver_t *driver, device_t parent) 307{ 308 ACPI_TABLE_HPET *hpet; 309 ACPI_STATUS status; 310 device_t child; 311 int i, found; 312 313 /* Only one HPET device can be added. */ 314 if (devclass_get_device(hpet_devclass, 0)) 315 return; 316 for (i = 1; ; i++) { 317 /* Search for HPET table. */ 318 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 319 if (ACPI_FAILURE(status)) 320 return; 321 /* Search for HPET device with same ID. */ 322 found = 0; 323 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 324 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found); 325 /* If found - let it be probed in normal way. */ 326 if (found) 327 continue; 328 /* If not - create it from table info. */ 329 child = BUS_ADD_CHILD(parent, ACPI_DEV_BASE_ORDER, "hpet", 0); 330 if (child == NULL) { 331 printf("%s: can't add child\n", __func__); 332 continue; 333 } 334 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 335 HPET_MEM_WIDTH); 336 } 337} 338 339static int 340hpet_probe(device_t dev) 341{ 342 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 343 344 if (acpi_disabled("hpet")) 345 return (ENXIO); 346 if (acpi_get_handle(dev) != NULL && 347 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 348 return (ENXIO); 349 350 device_set_desc(dev, "High Precision Event Timer"); 351 return (0); 352} 353 354static int 355hpet_attach(device_t dev) 356{ 357 struct hpet_softc *sc; 358 struct hpet_timer *t; 359 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 360 int pcpu_master; 361 static int maxhpetet = 0; 362 uint32_t val, val2, cvectors, dvectors; 363 uint16_t vendor, rev; 364 365 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 366 367 sc = device_get_softc(dev); 368 sc->dev = dev; 369 sc->handle = acpi_get_handle(dev); 370 371 sc->mem_rid = 0; 372 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 373 RF_ACTIVE); 374 if (sc->mem_res == NULL) 375 return (ENOMEM); 376 377 /* Validate that we can access the whole region. */ 378 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 379 device_printf(dev, "memory region width %ld too small\n", 380 rman_get_size(sc->mem_res)); 381 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 382 return (ENXIO); 383 } 384 385 /* Be sure timer is enabled. */ 386 hpet_enable(sc); 387 388 /* Read basic statistics about the timer. */ 389 val = bus_read_4(sc->mem_res, HPET_PERIOD); 390 if (val == 0) { 391 device_printf(dev, "invalid period\n"); 392 hpet_disable(sc); 393 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 394 return (ENXIO); 395 } 396 397 sc->freq = (1000000000000000LL + val / 2) / val; 398 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 399 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 400 rev = sc->caps & HPET_CAP_REV_ID; 401 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 402 /* 403 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 404 * Specification and provides an off by one number 405 * of timers/comparators. 406 * Additionally, they use unregistered value in VENDOR_ID field. 407 */ 408 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 409 num_timers--; 410 sc->num_timers = num_timers; 411 if (bootverbose) { 412 device_printf(dev, 413 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 414 vendor, rev, sc->freq, 415 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 416 num_timers, 417 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 418 } 419 for (i = 0; i < num_timers; i++) { 420 t = &sc->t[i]; 421 t->sc = sc; 422 t->num = i; 423 t->mode = 0; 424 t->intr_rid = -1; 425 t->irq = -1; 426 t->pcpu_cpu = -1; 427 t->pcpu_misrouted = 0; 428 t->pcpu_master = -1; 429 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 430 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 431 if (bootverbose) { 432 device_printf(dev, 433 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 434 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 435 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 436 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 437 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 438 } 439 } 440 if (testenv("debug.acpi.hpet_test")) 441 hpet_test(sc); 442 /* 443 * Don't attach if the timer never increments. Since the spec 444 * requires it to be at least 10 MHz, it has to change in 1 us. 445 */ 446 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 447 DELAY(1); 448 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 449 if (val == val2) { 450 device_printf(dev, "HPET never increments, disabling\n"); 451 hpet_disable(sc); 452 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 453 return (ENXIO); 454 } 455 /* Announce first HPET as timecounter. */ 456 if (device_get_unit(dev) == 0) { 457 sc->tc.tc_get_timecount = hpet_get_timecount, 458 sc->tc.tc_counter_mask = ~0u, 459 sc->tc.tc_name = "HPET", 460 sc->tc.tc_quality = 900, 461 sc->tc.tc_frequency = sc->freq; 462 sc->tc.tc_priv = sc; 463 tc_init(&sc->tc); 464 } 465 /* If not disabled - setup and announce event timers. */ 466 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 467 "clock", &i) == 0 && i == 0) 468 return (0); 469 470 /* Check whether we can and want legacy routing. */ 471 sc->legacy_route = 0; 472 resource_int_value(device_get_name(dev), device_get_unit(dev), 473 "legacy_route", &sc->legacy_route); 474 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 475 sc->legacy_route = 0; 476 if (sc->legacy_route) { 477 sc->t[0].vectors = 0; 478 sc->t[1].vectors = 0; 479 } 480 481 /* Check what IRQs we want use. */ 482 /* By default allow any PCI IRQs. */ 483 sc->allowed_irqs = 0xffff0000; 484 /* 485 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 486 * Lower are also not always working for different reasons. 487 * SB800 fixed it, but seems do not implements level triggering 488 * properly, that makes it very unreliable - it freezes after any 489 * interrupt loss. Avoid legacy IRQs for AMD. 490 */ 491 if (vendor == HPET_VENDID_AMD) 492 sc->allowed_irqs = 0x00000000; 493 /* 494 * Neither QEMU nor VirtualBox report supported IRQs correctly. 495 * The only way to use HPET there is to specify IRQs manually 496 * and/or use legacy_route. Legacy_route mode work on both. 497 */ 498 if (vm_guest) 499 sc->allowed_irqs = 0x00000000; 500 /* Let user override. */ 501 resource_int_value(device_get_name(dev), device_get_unit(dev), 502 "allowed_irqs", &sc->allowed_irqs); 503 504 num_msi = 0; 505 sc->useirq = 0; 506 /* Find IRQ vectors for all timers. */ 507 cvectors = sc->allowed_irqs & 0xffff0000; 508 dvectors = sc->allowed_irqs & 0x0000ffff; 509 if (sc->legacy_route) 510 dvectors &= 0x0000fefe; 511 for (i = 0; i < num_timers; i++) { 512 t = &sc->t[i]; 513 if (sc->legacy_route && i < 2) 514 t->irq = (i == 0) ? 0 : 8; 515#ifdef DEV_APIC 516 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 517 if ((j = PCIB_ALLOC_MSIX( 518 device_get_parent(device_get_parent(dev)), dev, 519 &t->irq))) { 520 device_printf(dev, 521 "Can't allocate interrupt for t%d.\n", j); 522 } 523 } 524#endif 525 else if (dvectors & t->vectors) { 526 t->irq = ffs(dvectors & t->vectors) - 1; 527 dvectors &= ~(1 << t->irq); 528 } 529 if (t->irq >= 0) { 530 if (!(t->intr_res = 531 bus_alloc_resource(dev, SYS_RES_IRQ, &t->intr_rid, 532 t->irq, t->irq, 1, RF_ACTIVE))) { 533 t->irq = -1; 534 device_printf(dev, 535 "Can't map interrupt for t%d.\n", i); 536 } else if ((bus_setup_intr(dev, t->intr_res, 537 INTR_MPSAFE | INTR_TYPE_CLK, 538 (driver_filter_t *)hpet_intr_single, NULL, 539 t, &t->intr_handle))) { 540 t->irq = -1; 541 device_printf(dev, 542 "Can't setup interrupt for t%d.\n", i); 543 } else { 544 bus_describe_intr(dev, t->intr_res, 545 t->intr_handle, "t%d", i); 546 num_msi++; 547 } 548 } 549 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 550 cvectors &= t->vectors; 551 sc->useirq |= (1 << i); 552 } 553 } 554 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 555 sc->legacy_route = 0; 556 if (sc->legacy_route) 557 hpet_enable(sc); 558 /* Group timers for per-CPU operation. */ 559 num_percpu_et = min(num_msi / mp_ncpus, 1); 560 num_percpu_t = num_percpu_et * mp_ncpus; 561 pcpu_master = 0; 562 cur_cpu = CPU_FIRST(); 563 for (i = 0; i < num_timers; i++) { 564 t = &sc->t[i]; 565 if (t->irq >= 0 && num_percpu_t > 0) { 566 if (cur_cpu == CPU_FIRST()) 567 pcpu_master = i; 568 t->pcpu_cpu = cur_cpu; 569 t->pcpu_master = pcpu_master; 570 sc->t[pcpu_master]. 571 pcpu_slaves[cur_cpu] = i; 572 bus_bind_intr(dev, t->intr_res, cur_cpu); 573 cur_cpu = CPU_NEXT(cur_cpu); 574 num_percpu_t--; 575 } else if (t->irq >= 0) 576 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 577 } 578 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 579 sc->irq = -1; 580 sc->intr_rid = -1; 581 /* If at least one timer needs legacy IRQ - setup it. */ 582 if (sc->useirq) { 583 j = i = fls(cvectors) - 1; 584 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 585 j--; 586 if (!(sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 587 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE))) 588 device_printf(dev,"Can't map interrupt.\n"); 589 else if ((bus_setup_intr(dev, sc->intr_res, 590 INTR_MPSAFE | INTR_TYPE_CLK, 591 (driver_filter_t *)hpet_intr, NULL, 592 sc, &sc->intr_handle))) { 593 device_printf(dev, "Can't setup interrupt.\n"); 594 } else { 595 sc->irq = rman_get_start(sc->intr_res); 596 /* Bind IRQ to BSP to avoid live migration. */ 597 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 598 } 599 } 600 /* Program and announce event timers. */ 601 for (i = 0; i < num_timers; i++) { 602 t = &sc->t[i]; 603 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 604 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 605 t->caps &= ~(HPET_TCNF_INT_TYPE); 606 t->caps |= HPET_TCNF_32MODE; 607 if (t->irq >= 0 && sc->legacy_route && i < 2) { 608 /* Legacy route doesn't need more configuration. */ 609 } else 610#ifdef DEV_APIC 611 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 612 uint64_t addr; 613 uint32_t data; 614 615 if (PCIB_MAP_MSI( 616 device_get_parent(device_get_parent(dev)), dev, 617 t->irq, &addr, &data) == 0) { 618 bus_write_4(sc->mem_res, 619 HPET_TIMER_FSB_ADDR(i), addr); 620 bus_write_4(sc->mem_res, 621 HPET_TIMER_FSB_VAL(i), data); 622 t->caps |= HPET_TCNF_FSB_EN; 623 } else 624 t->irq = -2; 625 } else 626#endif 627 if (t->irq >= 0) 628 t->caps |= (t->irq << 9); 629 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 630 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 631 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 632 /* Skip event timers without set up IRQ. */ 633 if (t->irq < 0 && 634 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 635 continue; 636 /* Announce the reset. */ 637 if (maxhpetet == 0) 638 t->et.et_name = "HPET"; 639 else { 640 sprintf(t->name, "HPET%d", maxhpetet); 641 t->et.et_name = t->name; 642 } 643 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 644 t->et.et_quality = 450; 645 if (t->pcpu_master >= 0) { 646 t->et.et_flags |= ET_FLAGS_PERCPU; 647 t->et.et_quality += 100; 648 } 649 if ((t->caps & HPET_TCAP_PER_INT) == 0) 650 t->et.et_quality -= 10; 651 t->et.et_frequency = sc->freq; 652 t->et.et_min_period.sec = 0; 653 t->et.et_min_period.frac = 0x00008000LLU << 32; 654 t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq; 655 t->et.et_max_period.frac = 656 ((0xfffffffeLLU << 32) / sc->freq) << 32; 657 t->et.et_start = hpet_start; 658 t->et.et_stop = hpet_stop; 659 t->et.et_priv = &sc->t[i]; 660 if (t->pcpu_master < 0 || t->pcpu_master == i) { 661 et_register(&t->et); 662 maxhpetet++; 663 } 664 } 665 return (0); 666} 667 668static int 669hpet_detach(device_t dev) 670{ 671 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 672 673 /* XXX Without a tc_remove() function, we can't detach. */ 674 return (EBUSY); 675} 676 677static int 678hpet_suspend(device_t dev) 679{ 680 struct hpet_softc *sc; 681 682 /* 683 * Disable the timer during suspend. The timer will not lose 684 * its state in S1 or S2, but we are required to disable 685 * it. 686 */ 687 sc = device_get_softc(dev); 688 hpet_disable(sc); 689 690 return (0); 691} 692 693static int 694hpet_resume(device_t dev) 695{ 696 struct hpet_softc *sc; 697 struct hpet_timer *t; 698 int i; 699 700 /* Re-enable the timer after a resume to keep the clock advancing. */ 701 sc = device_get_softc(dev); 702 hpet_enable(sc); 703 /* Restart event timers that were running on suspend. */ 704 for (i = 0; i < sc->num_timers; i++) { 705 t = &sc->t[i]; 706#ifdef DEV_APIC 707 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 708 uint64_t addr; 709 uint32_t data; 710 711 if (PCIB_MAP_MSI( 712 device_get_parent(device_get_parent(dev)), dev, 713 t->irq, &addr, &data) == 0) { 714 bus_write_4(sc->mem_res, 715 HPET_TIMER_FSB_ADDR(i), addr); 716 bus_write_4(sc->mem_res, 717 HPET_TIMER_FSB_VAL(i), data); 718 } 719 } 720#endif 721 if (t->mode == 0) 722 continue; 723 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 724 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) { 725 t->caps |= HPET_TCNF_TYPE; 726 t->next += t->div; 727 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 728 t->caps | HPET_TCNF_VAL_SET); 729 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 730 t->next); 731 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 732 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 733 t->div); 734 } else { 735 t->next += sc->freq / 1024; 736 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 737 t->next); 738 } 739 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 740 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 741 } 742 return (0); 743} 744 745/* Print some basic latency/rate information to assist in debugging. */ 746static void 747hpet_test(struct hpet_softc *sc) 748{ 749 int i; 750 uint32_t u1, u2; 751 struct bintime b0, b1, b2; 752 struct timespec ts; 753 754 binuptime(&b0); 755 binuptime(&b0); 756 binuptime(&b1); 757 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 758 for (i = 1; i < 1000; i++) 759 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 760 binuptime(&b2); 761 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 762 763 bintime_sub(&b2, &b1); 764 bintime_sub(&b1, &b0); 765 bintime_sub(&b2, &b1); 766 bintime2timespec(&b2, &ts); 767 768 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 769 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 770 771 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 772} 773 774#ifdef DEV_APIC 775static int 776hpet_remap_intr(device_t dev, device_t child, u_int irq) 777{ 778 struct hpet_softc *sc = device_get_softc(dev); 779 struct hpet_timer *t; 780 uint64_t addr; 781 uint32_t data; 782 int error, i; 783 784 for (i = 0; i < sc->num_timers; i++) { 785 t = &sc->t[i]; 786 if (t->irq != irq) 787 continue; 788 error = PCIB_MAP_MSI( 789 device_get_parent(device_get_parent(dev)), dev, 790 irq, &addr, &data); 791 if (error) 792 return (error); 793 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 794 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 795 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 796 hpet_enable(sc); 797 return (0); 798 } 799 return (ENOENT); 800} 801#endif 802 803static device_method_t hpet_methods[] = { 804 /* Device interface */ 805 DEVMETHOD(device_identify, hpet_identify), 806 DEVMETHOD(device_probe, hpet_probe), 807 DEVMETHOD(device_attach, hpet_attach), 808 DEVMETHOD(device_detach, hpet_detach), 809 DEVMETHOD(device_suspend, hpet_suspend), 810 DEVMETHOD(device_resume, hpet_resume), 811 812#ifdef DEV_APIC 813 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 814#endif 815 816 {0, 0} 817}; 818 819static driver_t hpet_driver = { 820 "hpet", 821 hpet_methods, 822 sizeof(struct hpet_softc), 823}; 824 825DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 826MODULE_DEPEND(hpet, acpi, 1, 1, 1); 827