1210284Sjmallett/***********************license start***************
2232812Sjmallett * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
3215990Sjmallett * reserved.
4210284Sjmallett *
5210284Sjmallett *
6215990Sjmallett * Redistribution and use in source and binary forms, with or without
7215990Sjmallett * modification, are permitted provided that the following conditions are
8215990Sjmallett * met:
9210284Sjmallett *
10215990Sjmallett *   * Redistributions of source code must retain the above copyright
11215990Sjmallett *     notice, this list of conditions and the following disclaimer.
12210284Sjmallett *
13215990Sjmallett *   * Redistributions in binary form must reproduce the above
14215990Sjmallett *     copyright notice, this list of conditions and the following
15215990Sjmallett *     disclaimer in the documentation and/or other materials provided
16215990Sjmallett *     with the distribution.
17215990Sjmallett
18232812Sjmallett *   * Neither the name of Cavium Inc. nor the names of
19215990Sjmallett *     its contributors may be used to endorse or promote products
20215990Sjmallett *     derived from this software without specific prior written
21215990Sjmallett *     permission.
22215990Sjmallett
23215990Sjmallett * This Software, including technical data, may be subject to U.S. export  control
24215990Sjmallett * laws, including the U.S. Export Administration Act and its  associated
25215990Sjmallett * regulations, and may be subject to export or import  regulations in other
26215990Sjmallett * countries.
27215990Sjmallett
28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38210284Sjmallett ***********************license end**************************************/
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46215990Sjmallett
47210284Sjmallett#ifndef __OCTEON_PCI_CONSOLE_H__
48210284Sjmallett#define __OCTEON_PCI_CONSOLE_H__
49210284Sjmallett
50215990Sjmallett#ifndef CVMX_BUILD_FOR_LINUX_KERNEL
51210284Sjmallett#include "cvmx-platform.h"
52215990Sjmallett#endif
53210284Sjmallett
54210284Sjmallett/* Current versions */
55210284Sjmallett#define OCTEON_PCI_CONSOLE_MAJOR_VERSION    1
56210284Sjmallett#define OCTEON_PCI_CONSOLE_MINOR_VERSION    0
57210284Sjmallett
58210284Sjmallett#define OCTEON_PCI_CONSOLE_BLOCK_NAME   "__pci_console"
59210284Sjmallett
60210284Sjmallett
61210284Sjmallett/* Structure that defines a single console.
62210284Sjmallett
63210284Sjmallett
64210284Sjmallett* Note: when read_index == write_index, the buffer is empty.  The actual usable size
65210284Sjmallett*       of each console is console_buf_size -1;
66210284Sjmallett*/
67210284Sjmalletttypedef struct {
68210284Sjmallett    uint64_t input_base_addr;
69210284Sjmallett    uint32_t input_read_index;
70210284Sjmallett    uint32_t input_write_index;
71210284Sjmallett    uint64_t output_base_addr;
72210284Sjmallett    uint32_t output_read_index;
73210284Sjmallett    uint32_t output_write_index;
74210284Sjmallett    uint32_t lock;
75210284Sjmallett    uint32_t buf_size;
76210284Sjmallett} octeon_pci_console_t;
77210284Sjmallett
78210284Sjmallett
79210284Sjmallett/* This is the main container structure that contains all the information
80210284Sjmallettabout all PCI consoles.  The address of this structure is passed to various
81210284Sjmallettroutines that operation on PCI consoles.
82210284Sjmallett*/
83210284Sjmalletttypedef struct {
84210284Sjmallett    uint32_t major_version;
85210284Sjmallett    uint32_t minor_version;
86210284Sjmallett    uint32_t lock;
87210284Sjmallett    uint32_t flags;
88210284Sjmallett    uint32_t num_consoles;
89210284Sjmallett    uint32_t pad;
90210284Sjmallett    /* must be 64 bit aligned here... */
91210284Sjmallett    uint64_t console_addr_array[0];  /* Array of addresses of octeon_pci_console_t structures */
92210284Sjmallett    /* Implicit storage for console_addr_array */
93210284Sjmallett} octeon_pci_console_desc_t;
94210284Sjmallett
95210284Sjmallett
96210284Sjmallett/* Flag definitions for octeon_pci_console_desc_t */
97210284Sjmallettenum {
98210284Sjmallett    OCT_PCI_CON_DESC_FLAG_PERCPU = 1 << 0,  /* If set, output from core N will be sent to console N */
99210284Sjmallett};
100210284Sjmallett
101210284Sjmallett#if defined(OCTEON_TARGET) && !defined(__linux__)
102210284Sjmallett/**
103210284Sjmallett * This is an internal-only function that is called from within the simple executive
104210284Sjmallett * C library, and is not intended for any other use.
105210284Sjmallett *
106210284Sjmallett * @param fd
107210284Sjmallett * @param buf
108210284Sjmallett * @param nbytes
109210284Sjmallett *
110210284Sjmallett * @return
111210284Sjmallett */
112210284Sjmallettint  __cvmx_pci_console_write (int fd, char *buf, int nbytes);
113210284Sjmallett#endif
114210284Sjmallett
115210284Sjmallett
116210284Sjmallett#ifdef CVMX_BUILD_FOR_UBOOT
117210284Sjmallettuint64_t octeon_pci_console_init(int num_consoles, int buffer_size);
118210284Sjmallett#endif
119210284Sjmallett
120210284Sjmallett/* Flag definitions for read/write functions */
121210284Sjmallettenum {
122210284Sjmallett    OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0,  /* If set, read/write functions won't block waiting for space or data.
123210284Sjmallett                                          * For reads, 0 bytes may be read, and for writes not all of the
124210284Sjmallett                                          * supplied data may be written.*/
125210284Sjmallett};
126210284Sjmallett
127210284Sjmallett#if !defined(__linux__) || defined(__KERNEL__)
128210284Sjmallettint octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags);
129210284Sjmallettint octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num);
130210284Sjmallett
131210284Sjmallettint octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags);
132210284Sjmallettint octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num);
133210284Sjmallett#endif
134210284Sjmallett
135210284Sjmallett#if !defined(OCTEON_TARGET) && defined(__linux__) && !defined(__KERNEL__)
136210284Sjmallettint octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags);
137210284Sjmallettint octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num);
138210284Sjmallett
139210284Sjmallettint octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags);
140210284Sjmallettint octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num);
141210284Sjmallett#endif
142210284Sjmallett#endif
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