1232809Sjmallett/***********************license start*************** 2232809Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3232809Sjmallett * reserved. 4232809Sjmallett * 5232809Sjmallett * 6232809Sjmallett * Redistribution and use in source and binary forms, with or without 7232809Sjmallett * modification, are permitted provided that the following conditions are 8232809Sjmallett * met: 9232809Sjmallett * 10232809Sjmallett * * Redistributions of source code must retain the above copyright 11232809Sjmallett * notice, this list of conditions and the following disclaimer. 12232809Sjmallett * 13232809Sjmallett * * Redistributions in binary form must reproduce the above 14232809Sjmallett * copyright notice, this list of conditions and the following 15232809Sjmallett * disclaimer in the documentation and/or other materials provided 16232809Sjmallett * with the distribution. 17232809Sjmallett 18232809Sjmallett * * Neither the name of Cavium Inc. nor the names of 19232809Sjmallett * its contributors may be used to endorse or promote products 20232809Sjmallett * derived from this software without specific prior written 21232809Sjmallett * permission. 22232809Sjmallett 23232809Sjmallett * This Software, including technical data, may be subject to U.S. export control 24232809Sjmallett * laws, including the U.S. Export Administration Act and its associated 25232809Sjmallett * regulations, and may be subject to export or import regulations in other 26232809Sjmallett * countries. 27232809Sjmallett 28232809Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232809Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30232809Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31232809Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32232809Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33232809Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34232809Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35232809Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36232809Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37232809Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38232809Sjmallett ***********************license end**************************************/ 39232809Sjmallett 40232809Sjmallett 41232809Sjmallett/** 42232809Sjmallett * cvmx-trax-defs.h 43232809Sjmallett * 44232809Sjmallett * Configuration and status register (CSR) type definitions for 45232809Sjmallett * Octeon trax. 46232809Sjmallett * 47232809Sjmallett * This file is auto generated. Do not edit. 48232809Sjmallett * 49232809Sjmallett * <hr>$Revision$<hr> 50232809Sjmallett * 51232809Sjmallett */ 52232809Sjmallett#ifndef __CVMX_TRAX_DEFS_H__ 53232809Sjmallett#define __CVMX_TRAX_DEFS_H__ 54232809Sjmallett 55232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56232809Sjmallettstatic inline uint64_t CVMX_TRAX_BIST_STATUS(unsigned long block_id) 57232809Sjmallett{ 58232809Sjmallett if (!( 59232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 60232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 61232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 62232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 63232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 64232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 65232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 66232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 67232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 68232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 69232809Sjmallett cvmx_warn("CVMX_TRAX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 70232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000010ull) + ((block_id) & 3) * 0x100000ull; 71232809Sjmallett} 72232809Sjmallett#else 73232809Sjmallett#define CVMX_TRAX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000010ull) + ((block_id) & 3) * 0x100000ull) 74232809Sjmallett#endif 75232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 76232809Sjmallettstatic inline uint64_t CVMX_TRAX_CTL(unsigned long block_id) 77232809Sjmallett{ 78232809Sjmallett if (!( 79232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 80232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 81232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 82232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 83232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 84232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 85232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 86232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 87232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 88232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 89232809Sjmallett cvmx_warn("CVMX_TRAX_CTL(%lu) is invalid on this chip\n", block_id); 90232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000000ull) + ((block_id) & 3) * 0x100000ull; 91232809Sjmallett} 92232809Sjmallett#else 93232809Sjmallett#define CVMX_TRAX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000000ull) + ((block_id) & 3) * 0x100000ull) 94232809Sjmallett#endif 95232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 96232809Sjmallettstatic inline uint64_t CVMX_TRAX_CYCLES_SINCE(unsigned long block_id) 97232809Sjmallett{ 98232809Sjmallett if (!( 99232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 100232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 101232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 102232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 103232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 104232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 105232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 106232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 107232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 108232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 109232809Sjmallett cvmx_warn("CVMX_TRAX_CYCLES_SINCE(%lu) is invalid on this chip\n", block_id); 110232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000018ull) + ((block_id) & 3) * 0x100000ull; 111232809Sjmallett} 112232809Sjmallett#else 113232809Sjmallett#define CVMX_TRAX_CYCLES_SINCE(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000018ull) + ((block_id) & 3) * 0x100000ull) 114232809Sjmallett#endif 115232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116232809Sjmallettstatic inline uint64_t CVMX_TRAX_CYCLES_SINCE1(unsigned long block_id) 117232809Sjmallett{ 118232809Sjmallett if (!( 119232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 120232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 121232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 122232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 123232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 124232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 125232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 126232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 127232809Sjmallett cvmx_warn("CVMX_TRAX_CYCLES_SINCE1(%lu) is invalid on this chip\n", block_id); 128232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000028ull) + ((block_id) & 3) * 0x100000ull; 129232809Sjmallett} 130232809Sjmallett#else 131232809Sjmallett#define CVMX_TRAX_CYCLES_SINCE1(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000028ull) + ((block_id) & 3) * 0x100000ull) 132232809Sjmallett#endif 133232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134232809Sjmallettstatic inline uint64_t CVMX_TRAX_FILT_ADR_ADR(unsigned long block_id) 135232809Sjmallett{ 136232809Sjmallett if (!( 137232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 138232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 139232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 140232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 141232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 142232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 143232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 144232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 145232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 146232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 147232809Sjmallett cvmx_warn("CVMX_TRAX_FILT_ADR_ADR(%lu) is invalid on this chip\n", block_id); 148232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000058ull) + ((block_id) & 3) * 0x100000ull; 149232809Sjmallett} 150232809Sjmallett#else 151232809Sjmallett#define CVMX_TRAX_FILT_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000058ull) + ((block_id) & 3) * 0x100000ull) 152232809Sjmallett#endif 153232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 154232809Sjmallettstatic inline uint64_t CVMX_TRAX_FILT_ADR_MSK(unsigned long block_id) 155232809Sjmallett{ 156232809Sjmallett if (!( 157232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 158232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 159232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 160232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 161232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 162232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 163232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 164232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 165232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 166232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 167232809Sjmallett cvmx_warn("CVMX_TRAX_FILT_ADR_MSK(%lu) is invalid on this chip\n", block_id); 168232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000060ull) + ((block_id) & 3) * 0x100000ull; 169232809Sjmallett} 170232809Sjmallett#else 171232809Sjmallett#define CVMX_TRAX_FILT_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000060ull) + ((block_id) & 3) * 0x100000ull) 172232809Sjmallett#endif 173232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 174232809Sjmallettstatic inline uint64_t CVMX_TRAX_FILT_CMD(unsigned long block_id) 175232809Sjmallett{ 176232809Sjmallett if (!( 177232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 178232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 179232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 180232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 181232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 182232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 183232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 184232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 185232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 186232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 187232809Sjmallett cvmx_warn("CVMX_TRAX_FILT_CMD(%lu) is invalid on this chip\n", block_id); 188232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000040ull) + ((block_id) & 3) * 0x100000ull; 189232809Sjmallett} 190232809Sjmallett#else 191232809Sjmallett#define CVMX_TRAX_FILT_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000040ull) + ((block_id) & 3) * 0x100000ull) 192232809Sjmallett#endif 193232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 194232809Sjmallettstatic inline uint64_t CVMX_TRAX_FILT_DID(unsigned long block_id) 195232809Sjmallett{ 196232809Sjmallett if (!( 197232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 198232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 199232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 200232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 201232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 202232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 203232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 204232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 205232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 206232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 207232809Sjmallett cvmx_warn("CVMX_TRAX_FILT_DID(%lu) is invalid on this chip\n", block_id); 208232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000050ull) + ((block_id) & 3) * 0x100000ull; 209232809Sjmallett} 210232809Sjmallett#else 211232809Sjmallett#define CVMX_TRAX_FILT_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000050ull) + ((block_id) & 3) * 0x100000ull) 212232809Sjmallett#endif 213232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 214232809Sjmallettstatic inline uint64_t CVMX_TRAX_FILT_SID(unsigned long block_id) 215232809Sjmallett{ 216232809Sjmallett if (!( 217232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 218232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 219232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 220232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 221232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 222232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 223232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 224232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 225232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 226232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 227232809Sjmallett cvmx_warn("CVMX_TRAX_FILT_SID(%lu) is invalid on this chip\n", block_id); 228232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000048ull) + ((block_id) & 3) * 0x100000ull; 229232809Sjmallett} 230232809Sjmallett#else 231232809Sjmallett#define CVMX_TRAX_FILT_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000048ull) + ((block_id) & 3) * 0x100000ull) 232232809Sjmallett#endif 233232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 234232809Sjmallettstatic inline uint64_t CVMX_TRAX_INT_STATUS(unsigned long block_id) 235232809Sjmallett{ 236232809Sjmallett if (!( 237232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 238232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 239232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 240232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 241232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 242232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 243232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 244232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 245232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 246232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 247232809Sjmallett cvmx_warn("CVMX_TRAX_INT_STATUS(%lu) is invalid on this chip\n", block_id); 248232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000008ull) + ((block_id) & 3) * 0x100000ull; 249232809Sjmallett} 250232809Sjmallett#else 251232809Sjmallett#define CVMX_TRAX_INT_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000008ull) + ((block_id) & 3) * 0x100000ull) 252232809Sjmallett#endif 253232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254232809Sjmallettstatic inline uint64_t CVMX_TRAX_READ_DAT(unsigned long block_id) 255232809Sjmallett{ 256232809Sjmallett if (!( 257232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 258232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 259232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 260232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 261232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 262232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 263232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 264232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 265232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 266232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 267232809Sjmallett cvmx_warn("CVMX_TRAX_READ_DAT(%lu) is invalid on this chip\n", block_id); 268232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000020ull) + ((block_id) & 3) * 0x100000ull; 269232809Sjmallett} 270232809Sjmallett#else 271232809Sjmallett#define CVMX_TRAX_READ_DAT(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000020ull) + ((block_id) & 3) * 0x100000ull) 272232809Sjmallett#endif 273232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 274232809Sjmallettstatic inline uint64_t CVMX_TRAX_READ_DAT_HI(unsigned long block_id) 275232809Sjmallett{ 276232809Sjmallett if (!( 277232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 278232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 279232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 280232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 281232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 282232809Sjmallett cvmx_warn("CVMX_TRAX_READ_DAT_HI(%lu) is invalid on this chip\n", block_id); 283232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000030ull) + ((block_id) & 3) * 0x100000ull; 284232809Sjmallett} 285232809Sjmallett#else 286232809Sjmallett#define CVMX_TRAX_READ_DAT_HI(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000030ull) + ((block_id) & 3) * 0x100000ull) 287232809Sjmallett#endif 288232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 289232809Sjmallettstatic inline uint64_t CVMX_TRAX_TRIG0_ADR_ADR(unsigned long block_id) 290232809Sjmallett{ 291232809Sjmallett if (!( 292232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 293232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 294232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 295232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 296232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 297232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 298232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 299232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 300232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 301232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 302232809Sjmallett cvmx_warn("CVMX_TRAX_TRIG0_ADR_ADR(%lu) is invalid on this chip\n", block_id); 303232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000098ull) + ((block_id) & 3) * 0x100000ull; 304232809Sjmallett} 305232809Sjmallett#else 306232809Sjmallett#define CVMX_TRAX_TRIG0_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000098ull) + ((block_id) & 3) * 0x100000ull) 307232809Sjmallett#endif 308232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309232809Sjmallettstatic inline uint64_t CVMX_TRAX_TRIG0_ADR_MSK(unsigned long block_id) 310232809Sjmallett{ 311232809Sjmallett if (!( 312232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 313232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 314232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 315232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 316232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 317232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 318232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 319232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 320232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 321232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 322232809Sjmallett cvmx_warn("CVMX_TRAX_TRIG0_ADR_MSK(%lu) is invalid on this chip\n", block_id); 323232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A80000A0ull) + ((block_id) & 3) * 0x100000ull; 324232809Sjmallett} 325232809Sjmallett#else 326232809Sjmallett#define CVMX_TRAX_TRIG0_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000A0ull) + ((block_id) & 3) * 0x100000ull) 327232809Sjmallett#endif 328232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 329232809Sjmallettstatic inline uint64_t CVMX_TRAX_TRIG0_CMD(unsigned long block_id) 330232809Sjmallett{ 331232809Sjmallett if (!( 332232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 333232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 334232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 335232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 336232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 337232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 338232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 339232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 340232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 341232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 342232809Sjmallett cvmx_warn("CVMX_TRAX_TRIG0_CMD(%lu) is invalid on this chip\n", block_id); 343232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000080ull) + ((block_id) & 3) * 0x100000ull; 344232809Sjmallett} 345232809Sjmallett#else 346232809Sjmallett#define CVMX_TRAX_TRIG0_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000080ull) + ((block_id) & 3) * 0x100000ull) 347232809Sjmallett#endif 348232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 349232809Sjmallettstatic inline uint64_t CVMX_TRAX_TRIG0_DID(unsigned long block_id) 350232809Sjmallett{ 351232809Sjmallett if (!( 352232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 353232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 354232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 355232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 356232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 357232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 358232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 359232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 360232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 361232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 362232809Sjmallett cvmx_warn("CVMX_TRAX_TRIG0_DID(%lu) is invalid on this chip\n", block_id); 363232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000090ull) + ((block_id) & 3) * 0x100000ull; 364232809Sjmallett} 365232809Sjmallett#else 366232809Sjmallett#define CVMX_TRAX_TRIG0_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000090ull) + ((block_id) & 3) * 0x100000ull) 367232809Sjmallett#endif 368232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 369232809Sjmallettstatic inline uint64_t CVMX_TRAX_TRIG0_SID(unsigned long block_id) 370232809Sjmallett{ 371232809Sjmallett if (!( 372232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 373232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 374232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 375232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 376232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 377232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 378232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 379232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 380232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 381232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 382232809Sjmallett cvmx_warn("CVMX_TRAX_TRIG0_SID(%lu) is invalid on this chip\n", block_id); 383232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A8000088ull) + ((block_id) & 3) * 0x100000ull; 384232809Sjmallett} 385232809Sjmallett#else 386232809Sjmallett#define CVMX_TRAX_TRIG0_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A8000088ull) + ((block_id) & 3) * 0x100000ull) 387232809Sjmallett#endif 388232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 389232809Sjmallettstatic inline uint64_t CVMX_TRAX_TRIG1_ADR_ADR(unsigned long block_id) 390232809Sjmallett{ 391232809Sjmallett if (!( 392232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 393232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 394232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 395232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 396232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 397232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 398232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 399232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 400232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 401232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 402232809Sjmallett cvmx_warn("CVMX_TRAX_TRIG1_ADR_ADR(%lu) is invalid on this chip\n", block_id); 403232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A80000D8ull) + ((block_id) & 3) * 0x100000ull; 404232809Sjmallett} 405232809Sjmallett#else 406232809Sjmallett#define CVMX_TRAX_TRIG1_ADR_ADR(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000D8ull) + ((block_id) & 3) * 0x100000ull) 407232809Sjmallett#endif 408232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 409232809Sjmallettstatic inline uint64_t CVMX_TRAX_TRIG1_ADR_MSK(unsigned long block_id) 410232809Sjmallett{ 411232809Sjmallett if (!( 412232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 413232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 414232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 415232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 416232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 417232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 418232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 419232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 420232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 421232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 422232809Sjmallett cvmx_warn("CVMX_TRAX_TRIG1_ADR_MSK(%lu) is invalid on this chip\n", block_id); 423232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A80000E0ull) + ((block_id) & 3) * 0x100000ull; 424232809Sjmallett} 425232809Sjmallett#else 426232809Sjmallett#define CVMX_TRAX_TRIG1_ADR_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000E0ull) + ((block_id) & 3) * 0x100000ull) 427232809Sjmallett#endif 428232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 429232809Sjmallettstatic inline uint64_t CVMX_TRAX_TRIG1_CMD(unsigned long block_id) 430232809Sjmallett{ 431232809Sjmallett if (!( 432232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 433232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 434232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 435232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 436232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 437232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 438232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 439232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 440232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 441232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 442232809Sjmallett cvmx_warn("CVMX_TRAX_TRIG1_CMD(%lu) is invalid on this chip\n", block_id); 443232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A80000C0ull) + ((block_id) & 3) * 0x100000ull; 444232809Sjmallett} 445232809Sjmallett#else 446232809Sjmallett#define CVMX_TRAX_TRIG1_CMD(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000C0ull) + ((block_id) & 3) * 0x100000ull) 447232809Sjmallett#endif 448232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 449232809Sjmallettstatic inline uint64_t CVMX_TRAX_TRIG1_DID(unsigned long block_id) 450232809Sjmallett{ 451232809Sjmallett if (!( 452232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 453232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 454232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 455232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 456232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 457232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 458232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 459232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 460232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 461232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 462232809Sjmallett cvmx_warn("CVMX_TRAX_TRIG1_DID(%lu) is invalid on this chip\n", block_id); 463232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A80000D0ull) + ((block_id) & 3) * 0x100000ull; 464232809Sjmallett} 465232809Sjmallett#else 466232809Sjmallett#define CVMX_TRAX_TRIG1_DID(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000D0ull) + ((block_id) & 3) * 0x100000ull) 467232809Sjmallett#endif 468232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 469232809Sjmallettstatic inline uint64_t CVMX_TRAX_TRIG1_SID(unsigned long block_id) 470232809Sjmallett{ 471232809Sjmallett if (!( 472232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 473232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id == 0))) || 474232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id == 0))) || 475232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))) || 476232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id == 0))) || 477232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 478232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 479232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 480232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 3))) || 481232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 482232809Sjmallett cvmx_warn("CVMX_TRAX_TRIG1_SID(%lu) is invalid on this chip\n", block_id); 483232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800A80000C8ull) + ((block_id) & 3) * 0x100000ull; 484232809Sjmallett} 485232809Sjmallett#else 486232809Sjmallett#define CVMX_TRAX_TRIG1_SID(block_id) (CVMX_ADD_IO_SEG(0x00011800A80000C8ull) + ((block_id) & 3) * 0x100000ull) 487232809Sjmallett#endif 488232809Sjmallett 489232809Sjmallett/** 490232809Sjmallett * cvmx_tra#_bist_status 491232809Sjmallett * 492232809Sjmallett * TRA_BIST_STATUS = Trace Buffer BiST Status 493232809Sjmallett * 494232809Sjmallett * Description: 495232809Sjmallett */ 496232809Sjmallettunion cvmx_trax_bist_status { 497232809Sjmallett uint64_t u64; 498232809Sjmallett struct cvmx_trax_bist_status_s { 499232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 500232809Sjmallett uint64_t reserved_3_63 : 61; 501232809Sjmallett uint64_t tcf : 1; /**< Bist Results for TCF memory 502232809Sjmallett - 0: GOOD (or bist in progress/never run) 503232809Sjmallett - 1: BAD */ 504232809Sjmallett uint64_t tdf1 : 1; /**< Bist Results for TDF memory 1 505232809Sjmallett - 0: GOOD (or bist in progress/never run) 506232809Sjmallett - 1: BAD */ 507232809Sjmallett uint64_t reserved_0_0 : 1; 508232809Sjmallett#else 509232809Sjmallett uint64_t reserved_0_0 : 1; 510232809Sjmallett uint64_t tdf1 : 1; 511232809Sjmallett uint64_t tcf : 1; 512232809Sjmallett uint64_t reserved_3_63 : 61; 513232809Sjmallett#endif 514232809Sjmallett } s; 515232809Sjmallett struct cvmx_trax_bist_status_cn31xx { 516232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 517232809Sjmallett uint64_t reserved_3_63 : 61; 518232809Sjmallett uint64_t tcf : 1; /**< Bist Results for TCF memory 519232809Sjmallett - 0: GOOD (or bist in progress/never run) 520232809Sjmallett - 1: BAD */ 521232809Sjmallett uint64_t tdf1 : 1; /**< Bist Results for TDF memory 1 522232809Sjmallett - 0: GOOD (or bist in progress/never run) 523232809Sjmallett - 1: BAD */ 524232809Sjmallett uint64_t tdf0 : 1; /**< Bist Results for TCF memory 0 525232809Sjmallett - 0: GOOD (or bist in progress/never run) 526232809Sjmallett - 1: BAD */ 527232809Sjmallett#else 528232809Sjmallett uint64_t tdf0 : 1; 529232809Sjmallett uint64_t tdf1 : 1; 530232809Sjmallett uint64_t tcf : 1; 531232809Sjmallett uint64_t reserved_3_63 : 61; 532232809Sjmallett#endif 533232809Sjmallett } cn31xx; 534232809Sjmallett struct cvmx_trax_bist_status_cn31xx cn38xx; 535232809Sjmallett struct cvmx_trax_bist_status_cn31xx cn38xxp2; 536232809Sjmallett struct cvmx_trax_bist_status_cn31xx cn52xx; 537232809Sjmallett struct cvmx_trax_bist_status_cn31xx cn52xxp1; 538232809Sjmallett struct cvmx_trax_bist_status_cn31xx cn56xx; 539232809Sjmallett struct cvmx_trax_bist_status_cn31xx cn56xxp1; 540232809Sjmallett struct cvmx_trax_bist_status_cn31xx cn58xx; 541232809Sjmallett struct cvmx_trax_bist_status_cn31xx cn58xxp1; 542232809Sjmallett struct cvmx_trax_bist_status_cn61xx { 543232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 544232809Sjmallett uint64_t reserved_1_63 : 63; 545232809Sjmallett uint64_t tdf : 1; /**< Bist Results for TCF memory 546232809Sjmallett - 0: GOOD (or bist in progress/never run) 547232809Sjmallett - 1: BAD */ 548232809Sjmallett#else 549232809Sjmallett uint64_t tdf : 1; 550232809Sjmallett uint64_t reserved_1_63 : 63; 551232809Sjmallett#endif 552232809Sjmallett } cn61xx; 553232809Sjmallett struct cvmx_trax_bist_status_cn61xx cn63xx; 554232809Sjmallett struct cvmx_trax_bist_status_cn61xx cn63xxp1; 555232809Sjmallett struct cvmx_trax_bist_status_cn61xx cn66xx; 556232809Sjmallett struct cvmx_trax_bist_status_cn61xx cn68xx; 557232809Sjmallett struct cvmx_trax_bist_status_cn61xx cn68xxp1; 558232809Sjmallett struct cvmx_trax_bist_status_cn61xx cnf71xx; 559232809Sjmallett}; 560232809Sjmalletttypedef union cvmx_trax_bist_status cvmx_trax_bist_status_t; 561232809Sjmallett 562232809Sjmallett/** 563232809Sjmallett * cvmx_tra#_ctl 564232809Sjmallett * 565232809Sjmallett * TRA_CTL = Trace Buffer Control 566232809Sjmallett * 567232809Sjmallett * Description: 568232809Sjmallett * 569232809Sjmallett * Notes: 570232809Sjmallett * It is illegal to change the values of WRAP, TRIG_CTL, IGNORE_O while tracing (i.e. when ENA=1). 571232809Sjmallett * Note that the following fields are present only in chip revisions beginning with pass2: IGNORE_O 572232809Sjmallett */ 573232809Sjmallettunion cvmx_trax_ctl { 574232809Sjmallett uint64_t u64; 575232809Sjmallett struct cvmx_trax_ctl_s { 576232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 577232809Sjmallett uint64_t reserved_17_63 : 47; 578232809Sjmallett uint64_t rdat_md : 1; /**< TRA_READ_DAT mode bit 579232809Sjmallett If set, the TRA_READ_DAT reads will return the lower 580232809Sjmallett 64 bits of the TRA entry and the upper bits must be 581232809Sjmallett read through TRA_READ_DAT_HI. If not set the return 582232809Sjmallett value from TRA_READ_DAT accesses will switch between 583232809Sjmallett the lower bits and the upper bits of the TRA entry. */ 584232809Sjmallett uint64_t clkalways : 1; /**< Conditional clock enable 585232809Sjmallett If set, the TRA clock is never disabled. */ 586232809Sjmallett uint64_t ignore_o : 1; /**< Ignore overflow during wrap mode 587232809Sjmallett If set and wrapping mode is enabled, then tracing 588232809Sjmallett will not stop at the overflow condition. Each 589232809Sjmallett write during an overflow will overwrite the 590232809Sjmallett oldest, unread entry and the read pointer is 591232809Sjmallett incremented by one entry. This bit has no effect 592232809Sjmallett if WRAP=0. */ 593232809Sjmallett uint64_t mcd0_ena : 1; /**< MCD0 enable 594232809Sjmallett If set and any PP sends the MCD0 signal, the 595232809Sjmallett tracing is disabled. */ 596232809Sjmallett uint64_t mcd0_thr : 1; /**< MCD0_threshold 597232809Sjmallett At a fill threshold event, sends an MCD0 598232809Sjmallett wire pulse that can cause cores to enter debug 599232809Sjmallett mode, if enabled. This MCD0 wire pulse will not 600232809Sjmallett occur while (TRA_INT_STATUS.MCD0_THR == 1). */ 601232809Sjmallett uint64_t mcd0_trg : 1; /**< MCD0_trigger 602232809Sjmallett At an end trigger event, sends an MCD0 603232809Sjmallett wire pulse that can cause cores to enter debug 604232809Sjmallett mode, if enabled. This MCD0 wire pulse will not 605232809Sjmallett occur while (TRA_INT_STATUS.MCD0_TRG == 1). */ 606232809Sjmallett uint64_t ciu_thr : 1; /**< CIU_threshold 607232809Sjmallett When set during a fill threshold event, 608232809Sjmallett TRA_INT_STATUS[CIU_THR] is set, which can cause 609232809Sjmallett core interrupts, if enabled. */ 610232809Sjmallett uint64_t ciu_trg : 1; /**< CIU_trigger 611232809Sjmallett When set during an end trigger event, 612232809Sjmallett TRA_INT_STATUS[CIU_TRG] is set, which can cause 613232809Sjmallett core interrupts, if enabled. */ 614232809Sjmallett uint64_t full_thr : 2; /**< Full Threshhold 615232809Sjmallett 0=none 616232809Sjmallett 1=1/2 full 617232809Sjmallett 2=3/4 full 618232809Sjmallett 3=4/4 full */ 619232809Sjmallett uint64_t time_grn : 3; /**< Timestamp granularity 620232809Sjmallett granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */ 621232809Sjmallett uint64_t trig_ctl : 2; /**< Trigger Control 622232809Sjmallett Note: trigger events are written to the trace 623232809Sjmallett 0=no triggers 624232809Sjmallett 1=trigger0=start trigger, trigger1=stop trigger 625232809Sjmallett 2=(trigger0 || trigger1)=start trigger 626232809Sjmallett 3=(trigger0 || trigger1)=stop trigger */ 627232809Sjmallett uint64_t wrap : 1; /**< Wrap mode 628232809Sjmallett When WRAP=0, the trace buffer will disable itself 629232809Sjmallett after having logged 1024 entries. When WRAP=1, 630232809Sjmallett the trace buffer will never disable itself. 631232809Sjmallett In this case, tracing may or may not be 632232809Sjmallett temporarily suspended during the overflow 633232809Sjmallett condition (see IGNORE_O above). 634232809Sjmallett 0=do not wrap 635232809Sjmallett 1=wrap */ 636232809Sjmallett uint64_t ena : 1; /**< Enable Trace 637232809Sjmallett Master enable. Tracing only happens when ENA=1. 638232809Sjmallett When ENA changes from 0 to 1, the read and write 639232809Sjmallett pointers are reset to 0x00 to begin a new trace. 640232809Sjmallett The MCD0 event may set ENA=0 (see MCD0_ENA 641232809Sjmallett above). When using triggers, tracing occurs only 642232809Sjmallett between start and stop triggers (including the 643232809Sjmallett triggers themselves). 644232809Sjmallett 0=disable 645232809Sjmallett 1=enable */ 646232809Sjmallett#else 647232809Sjmallett uint64_t ena : 1; 648232809Sjmallett uint64_t wrap : 1; 649232809Sjmallett uint64_t trig_ctl : 2; 650232809Sjmallett uint64_t time_grn : 3; 651232809Sjmallett uint64_t full_thr : 2; 652232809Sjmallett uint64_t ciu_trg : 1; 653232809Sjmallett uint64_t ciu_thr : 1; 654232809Sjmallett uint64_t mcd0_trg : 1; 655232809Sjmallett uint64_t mcd0_thr : 1; 656232809Sjmallett uint64_t mcd0_ena : 1; 657232809Sjmallett uint64_t ignore_o : 1; 658232809Sjmallett uint64_t clkalways : 1; 659232809Sjmallett uint64_t rdat_md : 1; 660232809Sjmallett uint64_t reserved_17_63 : 47; 661232809Sjmallett#endif 662232809Sjmallett } s; 663232809Sjmallett struct cvmx_trax_ctl_cn31xx { 664232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 665232809Sjmallett uint64_t reserved_15_63 : 49; 666232809Sjmallett uint64_t ignore_o : 1; /**< Ignore overflow during wrap mode 667232809Sjmallett If set and wrapping mode is enabled, then tracing 668232809Sjmallett will not stop at the overflow condition. Each 669232809Sjmallett write during an overflow will overwrite the 670232809Sjmallett oldest, unread entry and the read pointer is 671232809Sjmallett incremented by one entry. This bit has no effect 672232809Sjmallett if WRAP=0. */ 673232809Sjmallett uint64_t mcd0_ena : 1; /**< MCD0 enable 674232809Sjmallett If set and any PP sends the MCD0 signal, the 675232809Sjmallett tracing is disabled. */ 676232809Sjmallett uint64_t mcd0_thr : 1; /**< MCD0_threshold 677232809Sjmallett At a fill threshold event, sends an MCD0 678232809Sjmallett wire pulse that can cause cores to enter debug 679232809Sjmallett mode, if enabled. This MCD0 wire pulse will not 680232809Sjmallett occur while (TRA(0..0)_INT_STATUS.MCD0_THR == 1). */ 681232809Sjmallett uint64_t mcd0_trg : 1; /**< MCD0_trigger 682232809Sjmallett At an end trigger event, sends an MCD0 683232809Sjmallett wire pulse that can cause cores to enter debug 684232809Sjmallett mode, if enabled. This MCD0 wire pulse will not 685232809Sjmallett occur while (TRA(0..0)_INT_STATUS.MCD0_TRG == 1). */ 686232809Sjmallett uint64_t ciu_thr : 1; /**< CIU_threshold 687232809Sjmallett When set during a fill threshold event, 688232809Sjmallett TRA(0..0)_INT_STATUS[CIU_THR] is set, which can cause 689232809Sjmallett core interrupts, if enabled. */ 690232809Sjmallett uint64_t ciu_trg : 1; /**< CIU_trigger 691232809Sjmallett When set during an end trigger event, 692232809Sjmallett TRA(0..0)_INT_STATUS[CIU_TRG] is set, which can cause 693232809Sjmallett core interrupts, if enabled. */ 694232809Sjmallett uint64_t full_thr : 2; /**< Full Threshhold 695232809Sjmallett 0=none 696232809Sjmallett 1=1/2 full 697232809Sjmallett 2=3/4 full 698232809Sjmallett 3=4/4 full */ 699232809Sjmallett uint64_t time_grn : 3; /**< Timestamp granularity 700232809Sjmallett granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */ 701232809Sjmallett uint64_t trig_ctl : 2; /**< Trigger Control 702232809Sjmallett Note: trigger events are written to the trace 703232809Sjmallett 0=no triggers 704232809Sjmallett 1=trigger0=start trigger, trigger1=stop trigger 705232809Sjmallett 2=(trigger0 || trigger1)=start trigger 706232809Sjmallett 3=(trigger0 || trigger1)=stop trigger */ 707232809Sjmallett uint64_t wrap : 1; /**< Wrap mode 708232809Sjmallett When WRAP=0, the trace buffer will disable itself 709232809Sjmallett after having logged 256 entries. When WRAP=1, 710232809Sjmallett the trace buffer will never disable itself. 711232809Sjmallett In this case, tracing may or may not be 712232809Sjmallett temporarily suspended during the overflow 713232809Sjmallett condition (see IGNORE_O above). 714232809Sjmallett 0=do not wrap 715232809Sjmallett 1=wrap */ 716232809Sjmallett uint64_t ena : 1; /**< Enable Trace 717232809Sjmallett Master enable. Tracing only happens when ENA=1. 718232809Sjmallett When ENA changes from 0 to 1, the read and write 719232809Sjmallett pointers are reset to 0x00 to begin a new trace. 720232809Sjmallett The MCD0 event may set ENA=0 (see MCD0_ENA 721232809Sjmallett above). When using triggers, tracing occurs only 722232809Sjmallett between start and stop triggers (including the 723232809Sjmallett triggers themselves). 724232809Sjmallett 0=disable 725232809Sjmallett 1=enable */ 726232809Sjmallett#else 727232809Sjmallett uint64_t ena : 1; 728232809Sjmallett uint64_t wrap : 1; 729232809Sjmallett uint64_t trig_ctl : 2; 730232809Sjmallett uint64_t time_grn : 3; 731232809Sjmallett uint64_t full_thr : 2; 732232809Sjmallett uint64_t ciu_trg : 1; 733232809Sjmallett uint64_t ciu_thr : 1; 734232809Sjmallett uint64_t mcd0_trg : 1; 735232809Sjmallett uint64_t mcd0_thr : 1; 736232809Sjmallett uint64_t mcd0_ena : 1; 737232809Sjmallett uint64_t ignore_o : 1; 738232809Sjmallett uint64_t reserved_15_63 : 49; 739232809Sjmallett#endif 740232809Sjmallett } cn31xx; 741232809Sjmallett struct cvmx_trax_ctl_cn31xx cn38xx; 742232809Sjmallett struct cvmx_trax_ctl_cn31xx cn38xxp2; 743232809Sjmallett struct cvmx_trax_ctl_cn31xx cn52xx; 744232809Sjmallett struct cvmx_trax_ctl_cn31xx cn52xxp1; 745232809Sjmallett struct cvmx_trax_ctl_cn31xx cn56xx; 746232809Sjmallett struct cvmx_trax_ctl_cn31xx cn56xxp1; 747232809Sjmallett struct cvmx_trax_ctl_cn31xx cn58xx; 748232809Sjmallett struct cvmx_trax_ctl_cn31xx cn58xxp1; 749232809Sjmallett struct cvmx_trax_ctl_s cn61xx; 750232809Sjmallett struct cvmx_trax_ctl_s cn63xx; 751232809Sjmallett struct cvmx_trax_ctl_cn63xxp1 { 752232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 753232809Sjmallett uint64_t reserved_16_63 : 48; 754232809Sjmallett uint64_t clkalways : 1; /**< Conditional clock enable 755232809Sjmallett If set, the TRA clock is never disabled. */ 756232809Sjmallett uint64_t ignore_o : 1; /**< Ignore overflow during wrap mode 757232809Sjmallett If set and wrapping mode is enabled, then tracing 758232809Sjmallett will not stop at the overflow condition. Each 759232809Sjmallett write during an overflow will overwrite the 760232809Sjmallett oldest, unread entry and the read pointer is 761232809Sjmallett incremented by one entry. This bit has no effect 762232809Sjmallett if WRAP=0. */ 763232809Sjmallett uint64_t mcd0_ena : 1; /**< MCD0 enable 764232809Sjmallett If set and any PP sends the MCD0 signal, the 765232809Sjmallett tracing is disabled. */ 766232809Sjmallett uint64_t mcd0_thr : 1; /**< MCD0_threshold 767232809Sjmallett At a fill threshold event, sends an MCD0 768232809Sjmallett wire pulse that can cause cores to enter debug 769232809Sjmallett mode, if enabled. This MCD0 wire pulse will not 770232809Sjmallett occur while (TRA_INT_STATUS.MCD0_THR == 1). */ 771232809Sjmallett uint64_t mcd0_trg : 1; /**< MCD0_trigger 772232809Sjmallett At an end trigger event, sends an MCD0 773232809Sjmallett wire pulse that can cause cores to enter debug 774232809Sjmallett mode, if enabled. This MCD0 wire pulse will not 775232809Sjmallett occur while (TRA_INT_STATUS.MCD0_TRG == 1). */ 776232809Sjmallett uint64_t ciu_thr : 1; /**< CIU_threshold 777232809Sjmallett When set during a fill threshold event, 778232809Sjmallett TRA_INT_STATUS[CIU_THR] is set, which can cause 779232809Sjmallett core interrupts, if enabled. */ 780232809Sjmallett uint64_t ciu_trg : 1; /**< CIU_trigger 781232809Sjmallett When set during an end trigger event, 782232809Sjmallett TRA_INT_STATUS[CIU_TRG] is set, which can cause 783232809Sjmallett core interrupts, if enabled. */ 784232809Sjmallett uint64_t full_thr : 2; /**< Full Threshhold 785232809Sjmallett 0=none 786232809Sjmallett 1=1/2 full 787232809Sjmallett 2=3/4 full 788232809Sjmallett 3=4/4 full */ 789232809Sjmallett uint64_t time_grn : 3; /**< Timestamp granularity 790232809Sjmallett granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */ 791232809Sjmallett uint64_t trig_ctl : 2; /**< Trigger Control 792232809Sjmallett Note: trigger events are written to the trace 793232809Sjmallett 0=no triggers 794232809Sjmallett 1=trigger0=start trigger, trigger1=stop trigger 795232809Sjmallett 2=(trigger0 || trigger1)=start trigger 796232809Sjmallett 3=(trigger0 || trigger1)=stop trigger */ 797232809Sjmallett uint64_t wrap : 1; /**< Wrap mode 798232809Sjmallett When WRAP=0, the trace buffer will disable itself 799232809Sjmallett after having logged 1024 entries. When WRAP=1, 800232809Sjmallett the trace buffer will never disable itself. 801232809Sjmallett In this case, tracing may or may not be 802232809Sjmallett temporarily suspended during the overflow 803232809Sjmallett condition (see IGNORE_O above). 804232809Sjmallett 0=do not wrap 805232809Sjmallett 1=wrap */ 806232809Sjmallett uint64_t ena : 1; /**< Enable Trace 807232809Sjmallett Master enable. Tracing only happens when ENA=1. 808232809Sjmallett When ENA changes from 0 to 1, the read and write 809232809Sjmallett pointers are reset to 0x00 to begin a new trace. 810232809Sjmallett The MCD0 event may set ENA=0 (see MCD0_ENA 811232809Sjmallett above). When using triggers, tracing occurs only 812232809Sjmallett between start and stop triggers (including the 813232809Sjmallett triggers themselves). 814232809Sjmallett 0=disable 815232809Sjmallett 1=enable */ 816232809Sjmallett#else 817232809Sjmallett uint64_t ena : 1; 818232809Sjmallett uint64_t wrap : 1; 819232809Sjmallett uint64_t trig_ctl : 2; 820232809Sjmallett uint64_t time_grn : 3; 821232809Sjmallett uint64_t full_thr : 2; 822232809Sjmallett uint64_t ciu_trg : 1; 823232809Sjmallett uint64_t ciu_thr : 1; 824232809Sjmallett uint64_t mcd0_trg : 1; 825232809Sjmallett uint64_t mcd0_thr : 1; 826232809Sjmallett uint64_t mcd0_ena : 1; 827232809Sjmallett uint64_t ignore_o : 1; 828232809Sjmallett uint64_t clkalways : 1; 829232809Sjmallett uint64_t reserved_16_63 : 48; 830232809Sjmallett#endif 831232809Sjmallett } cn63xxp1; 832232809Sjmallett struct cvmx_trax_ctl_s cn66xx; 833232809Sjmallett struct cvmx_trax_ctl_s cn68xx; 834232809Sjmallett struct cvmx_trax_ctl_s cn68xxp1; 835232809Sjmallett struct cvmx_trax_ctl_s cnf71xx; 836232809Sjmallett}; 837232809Sjmalletttypedef union cvmx_trax_ctl cvmx_trax_ctl_t; 838232809Sjmallett 839232809Sjmallett/** 840232809Sjmallett * cvmx_tra#_cycles_since 841232809Sjmallett * 842232809Sjmallett * TRA_CYCLES_SINCE = Trace Buffer Cycles Since Last Write, Read/Write pointers 843232809Sjmallett * 844232809Sjmallett * Description: 845232809Sjmallett * 846232809Sjmallett * Notes: 847232809Sjmallett * This CSR is obsolete. Use TRA_CYCLES_SINCE1 instead. 848232809Sjmallett * 849232809Sjmallett */ 850232809Sjmallettunion cvmx_trax_cycles_since { 851232809Sjmallett uint64_t u64; 852232809Sjmallett struct cvmx_trax_cycles_since_s { 853232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 854232809Sjmallett uint64_t cycles : 48; /**< Cycles since the last entry was written */ 855232809Sjmallett uint64_t rptr : 8; /**< Read pointer */ 856232809Sjmallett uint64_t wptr : 8; /**< Write pointer */ 857232809Sjmallett#else 858232809Sjmallett uint64_t wptr : 8; 859232809Sjmallett uint64_t rptr : 8; 860232809Sjmallett uint64_t cycles : 48; 861232809Sjmallett#endif 862232809Sjmallett } s; 863232809Sjmallett struct cvmx_trax_cycles_since_s cn31xx; 864232809Sjmallett struct cvmx_trax_cycles_since_s cn38xx; 865232809Sjmallett struct cvmx_trax_cycles_since_s cn38xxp2; 866232809Sjmallett struct cvmx_trax_cycles_since_s cn52xx; 867232809Sjmallett struct cvmx_trax_cycles_since_s cn52xxp1; 868232809Sjmallett struct cvmx_trax_cycles_since_s cn56xx; 869232809Sjmallett struct cvmx_trax_cycles_since_s cn56xxp1; 870232809Sjmallett struct cvmx_trax_cycles_since_s cn58xx; 871232809Sjmallett struct cvmx_trax_cycles_since_s cn58xxp1; 872232809Sjmallett struct cvmx_trax_cycles_since_s cn61xx; 873232809Sjmallett struct cvmx_trax_cycles_since_s cn63xx; 874232809Sjmallett struct cvmx_trax_cycles_since_s cn63xxp1; 875232809Sjmallett struct cvmx_trax_cycles_since_s cn66xx; 876232809Sjmallett struct cvmx_trax_cycles_since_s cn68xx; 877232809Sjmallett struct cvmx_trax_cycles_since_s cn68xxp1; 878232809Sjmallett struct cvmx_trax_cycles_since_s cnf71xx; 879232809Sjmallett}; 880232809Sjmalletttypedef union cvmx_trax_cycles_since cvmx_trax_cycles_since_t; 881232809Sjmallett 882232809Sjmallett/** 883232809Sjmallett * cvmx_tra#_cycles_since1 884232809Sjmallett * 885232809Sjmallett * TRA_CYCLES_SINCE1 = Trace Buffer Cycles Since Last Write, Read/Write pointers 886232809Sjmallett * 887232809Sjmallett * Description: 888232809Sjmallett */ 889232809Sjmallettunion cvmx_trax_cycles_since1 { 890232809Sjmallett uint64_t u64; 891232809Sjmallett struct cvmx_trax_cycles_since1_s { 892232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 893232809Sjmallett uint64_t cycles : 40; /**< Cycles since the last entry was written */ 894232809Sjmallett uint64_t reserved_22_23 : 2; 895232809Sjmallett uint64_t rptr : 10; /**< Read pointer */ 896232809Sjmallett uint64_t reserved_10_11 : 2; 897232809Sjmallett uint64_t wptr : 10; /**< Write pointer */ 898232809Sjmallett#else 899232809Sjmallett uint64_t wptr : 10; 900232809Sjmallett uint64_t reserved_10_11 : 2; 901232809Sjmallett uint64_t rptr : 10; 902232809Sjmallett uint64_t reserved_22_23 : 2; 903232809Sjmallett uint64_t cycles : 40; 904232809Sjmallett#endif 905232809Sjmallett } s; 906232809Sjmallett struct cvmx_trax_cycles_since1_s cn52xx; 907232809Sjmallett struct cvmx_trax_cycles_since1_s cn52xxp1; 908232809Sjmallett struct cvmx_trax_cycles_since1_s cn56xx; 909232809Sjmallett struct cvmx_trax_cycles_since1_s cn56xxp1; 910232809Sjmallett struct cvmx_trax_cycles_since1_s cn58xx; 911232809Sjmallett struct cvmx_trax_cycles_since1_s cn58xxp1; 912232809Sjmallett struct cvmx_trax_cycles_since1_s cn61xx; 913232809Sjmallett struct cvmx_trax_cycles_since1_s cn63xx; 914232809Sjmallett struct cvmx_trax_cycles_since1_s cn63xxp1; 915232809Sjmallett struct cvmx_trax_cycles_since1_s cn66xx; 916232809Sjmallett struct cvmx_trax_cycles_since1_s cn68xx; 917232809Sjmallett struct cvmx_trax_cycles_since1_s cn68xxp1; 918232809Sjmallett struct cvmx_trax_cycles_since1_s cnf71xx; 919232809Sjmallett}; 920232809Sjmalletttypedef union cvmx_trax_cycles_since1 cvmx_trax_cycles_since1_t; 921232809Sjmallett 922232809Sjmallett/** 923232809Sjmallett * cvmx_tra#_filt_adr_adr 924232809Sjmallett * 925232809Sjmallett * TRA_FILT_ADR_ADR = Trace Buffer Filter Address Address 926232809Sjmallett * 927232809Sjmallett * Description: 928232809Sjmallett */ 929232809Sjmallettunion cvmx_trax_filt_adr_adr { 930232809Sjmallett uint64_t u64; 931232809Sjmallett struct cvmx_trax_filt_adr_adr_s { 932232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 933232809Sjmallett uint64_t reserved_38_63 : 26; 934232809Sjmallett uint64_t adr : 38; /**< Unmasked Address 935232809Sjmallett The combination of TRA_FILT_ADR_ADR and 936232809Sjmallett TRA_FILT_ADR_MSK is a masked address to 937232809Sjmallett enable tracing of only those commands whose 938232809Sjmallett masked address matches */ 939232809Sjmallett#else 940232809Sjmallett uint64_t adr : 38; 941232809Sjmallett uint64_t reserved_38_63 : 26; 942232809Sjmallett#endif 943232809Sjmallett } s; 944232809Sjmallett struct cvmx_trax_filt_adr_adr_cn31xx { 945232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 946232809Sjmallett uint64_t reserved_36_63 : 28; 947232809Sjmallett uint64_t adr : 36; /**< Unmasked Address 948232809Sjmallett The combination of TRA(0..0)_FILT_ADR_ADR and 949232809Sjmallett TRA(0..0)_FILT_ADR_MSK is a masked address to 950232809Sjmallett enable tracing of only those commands whose 951232809Sjmallett masked address matches */ 952232809Sjmallett#else 953232809Sjmallett uint64_t adr : 36; 954232809Sjmallett uint64_t reserved_36_63 : 28; 955232809Sjmallett#endif 956232809Sjmallett } cn31xx; 957232809Sjmallett struct cvmx_trax_filt_adr_adr_cn31xx cn38xx; 958232809Sjmallett struct cvmx_trax_filt_adr_adr_cn31xx cn38xxp2; 959232809Sjmallett struct cvmx_trax_filt_adr_adr_cn31xx cn52xx; 960232809Sjmallett struct cvmx_trax_filt_adr_adr_cn31xx cn52xxp1; 961232809Sjmallett struct cvmx_trax_filt_adr_adr_cn31xx cn56xx; 962232809Sjmallett struct cvmx_trax_filt_adr_adr_cn31xx cn56xxp1; 963232809Sjmallett struct cvmx_trax_filt_adr_adr_cn31xx cn58xx; 964232809Sjmallett struct cvmx_trax_filt_adr_adr_cn31xx cn58xxp1; 965232809Sjmallett struct cvmx_trax_filt_adr_adr_s cn61xx; 966232809Sjmallett struct cvmx_trax_filt_adr_adr_s cn63xx; 967232809Sjmallett struct cvmx_trax_filt_adr_adr_s cn63xxp1; 968232809Sjmallett struct cvmx_trax_filt_adr_adr_s cn66xx; 969232809Sjmallett struct cvmx_trax_filt_adr_adr_s cn68xx; 970232809Sjmallett struct cvmx_trax_filt_adr_adr_s cn68xxp1; 971232809Sjmallett struct cvmx_trax_filt_adr_adr_s cnf71xx; 972232809Sjmallett}; 973232809Sjmalletttypedef union cvmx_trax_filt_adr_adr cvmx_trax_filt_adr_adr_t; 974232809Sjmallett 975232809Sjmallett/** 976232809Sjmallett * cvmx_tra#_filt_adr_msk 977232809Sjmallett * 978232809Sjmallett * TRA_FILT_ADR_MSK = Trace Buffer Filter Address Mask 979232809Sjmallett * 980232809Sjmallett * Description: 981232809Sjmallett */ 982232809Sjmallettunion cvmx_trax_filt_adr_msk { 983232809Sjmallett uint64_t u64; 984232809Sjmallett struct cvmx_trax_filt_adr_msk_s { 985232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 986232809Sjmallett uint64_t reserved_38_63 : 26; 987232809Sjmallett uint64_t adr : 38; /**< Address Mask 988232809Sjmallett The combination of TRA_FILT_ADR_ADR and 989232809Sjmallett TRA_FILT_ADR_MSK is a masked address to 990232809Sjmallett enable tracing of only those commands whose 991232809Sjmallett masked address matches. When a mask bit is not 992232809Sjmallett set, the corresponding address bits are assumed 993232809Sjmallett to match. Also, note that IOBDMAs do not have 994232809Sjmallett proper addresses, so when TRA_FILT_CMD[IOBDMA] 995232809Sjmallett is set, TRA_FILT_ADR_MSK must be zero to 996232809Sjmallett guarantee that any IOBDMAs enter the trace. */ 997232809Sjmallett#else 998232809Sjmallett uint64_t adr : 38; 999232809Sjmallett uint64_t reserved_38_63 : 26; 1000232809Sjmallett#endif 1001232809Sjmallett } s; 1002232809Sjmallett struct cvmx_trax_filt_adr_msk_cn31xx { 1003232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1004232809Sjmallett uint64_t reserved_36_63 : 28; 1005232809Sjmallett uint64_t adr : 36; /**< Address Mask 1006232809Sjmallett The combination of TRA(0..0)_FILT_ADR_ADR and 1007232809Sjmallett TRA(0..0)_FILT_ADR_MSK is a masked address to 1008232809Sjmallett enable tracing of only those commands whose 1009232809Sjmallett masked address matches. When a mask bit is not 1010232809Sjmallett set, the corresponding address bits are assumed 1011232809Sjmallett to match. Also, note that IOBDMAs do not have 1012232809Sjmallett proper addresses, so when TRA(0..0)_FILT_CMD[IOBDMA] 1013232809Sjmallett is set, TRA(0..0)_FILT_ADR_MSK must be zero to 1014232809Sjmallett guarantee that any IOBDMAs enter the trace. */ 1015232809Sjmallett#else 1016232809Sjmallett uint64_t adr : 36; 1017232809Sjmallett uint64_t reserved_36_63 : 28; 1018232809Sjmallett#endif 1019232809Sjmallett } cn31xx; 1020232809Sjmallett struct cvmx_trax_filt_adr_msk_cn31xx cn38xx; 1021232809Sjmallett struct cvmx_trax_filt_adr_msk_cn31xx cn38xxp2; 1022232809Sjmallett struct cvmx_trax_filt_adr_msk_cn31xx cn52xx; 1023232809Sjmallett struct cvmx_trax_filt_adr_msk_cn31xx cn52xxp1; 1024232809Sjmallett struct cvmx_trax_filt_adr_msk_cn31xx cn56xx; 1025232809Sjmallett struct cvmx_trax_filt_adr_msk_cn31xx cn56xxp1; 1026232809Sjmallett struct cvmx_trax_filt_adr_msk_cn31xx cn58xx; 1027232809Sjmallett struct cvmx_trax_filt_adr_msk_cn31xx cn58xxp1; 1028232809Sjmallett struct cvmx_trax_filt_adr_msk_s cn61xx; 1029232809Sjmallett struct cvmx_trax_filt_adr_msk_s cn63xx; 1030232809Sjmallett struct cvmx_trax_filt_adr_msk_s cn63xxp1; 1031232809Sjmallett struct cvmx_trax_filt_adr_msk_s cn66xx; 1032232809Sjmallett struct cvmx_trax_filt_adr_msk_s cn68xx; 1033232809Sjmallett struct cvmx_trax_filt_adr_msk_s cn68xxp1; 1034232809Sjmallett struct cvmx_trax_filt_adr_msk_s cnf71xx; 1035232809Sjmallett}; 1036232809Sjmalletttypedef union cvmx_trax_filt_adr_msk cvmx_trax_filt_adr_msk_t; 1037232809Sjmallett 1038232809Sjmallett/** 1039232809Sjmallett * cvmx_tra#_filt_cmd 1040232809Sjmallett * 1041232809Sjmallett * TRA_FILT_CMD = Trace Buffer Filter Command Mask 1042232809Sjmallett * 1043232809Sjmallett * Description: 1044232809Sjmallett * 1045232809Sjmallett * Notes: 1046232809Sjmallett * Note that the trace buffer does not do proper IOBDMA address compares. Thus, if IOBDMA is set, then 1047232809Sjmallett * the address compare must be disabled (i.e. TRA_FILT_ADR_MSK set to zero) to guarantee that IOBDMAs 1048232809Sjmallett * enter the trace. 1049232809Sjmallett */ 1050232809Sjmallettunion cvmx_trax_filt_cmd { 1051232809Sjmallett uint64_t u64; 1052232809Sjmallett struct cvmx_trax_filt_cmd_s { 1053232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1054232809Sjmallett uint64_t saa64 : 1; /**< Enable SAA64 tracing 1055232809Sjmallett 0=disable, 1=enable */ 1056232809Sjmallett uint64_t saa32 : 1; /**< Enable SAA32 tracing 1057232809Sjmallett 0=disable, 1=enable */ 1058232809Sjmallett uint64_t reserved_60_61 : 2; 1059232809Sjmallett uint64_t faa64 : 1; /**< Enable FAA64 tracing 1060232809Sjmallett 0=disable, 1=enable */ 1061232809Sjmallett uint64_t faa32 : 1; /**< Enable FAA32 tracing 1062232809Sjmallett 0=disable, 1=enable */ 1063232809Sjmallett uint64_t reserved_56_57 : 2; 1064232809Sjmallett uint64_t decr64 : 1; /**< Enable DECR64 tracing 1065232809Sjmallett 0=disable, 1=enable */ 1066232809Sjmallett uint64_t decr32 : 1; /**< Enable DECR32 tracing 1067232809Sjmallett 0=disable, 1=enable */ 1068232809Sjmallett uint64_t decr16 : 1; /**< Enable DECR16 tracing 1069232809Sjmallett 0=disable, 1=enable */ 1070232809Sjmallett uint64_t decr8 : 1; /**< Enable DECR8 tracing 1071232809Sjmallett 0=disable, 1=enable */ 1072232809Sjmallett uint64_t incr64 : 1; /**< Enable INCR64 tracing 1073232809Sjmallett 0=disable, 1=enable */ 1074232809Sjmallett uint64_t incr32 : 1; /**< Enable INCR32 tracing 1075232809Sjmallett 0=disable, 1=enable */ 1076232809Sjmallett uint64_t incr16 : 1; /**< Enable INCR16 tracing 1077232809Sjmallett 0=disable, 1=enable */ 1078232809Sjmallett uint64_t incr8 : 1; /**< Enable INCR8 tracing 1079232809Sjmallett 0=disable, 1=enable */ 1080232809Sjmallett uint64_t clr64 : 1; /**< Enable CLR64 tracing 1081232809Sjmallett 0=disable, 1=enable */ 1082232809Sjmallett uint64_t clr32 : 1; /**< Enable CLR32 tracing 1083232809Sjmallett 0=disable, 1=enable */ 1084232809Sjmallett uint64_t clr16 : 1; /**< Enable CLR16 tracing 1085232809Sjmallett 0=disable, 1=enable */ 1086232809Sjmallett uint64_t clr8 : 1; /**< Enable CLR8 tracing 1087232809Sjmallett 0=disable, 1=enable */ 1088232809Sjmallett uint64_t set64 : 1; /**< Enable SET64 tracing 1089232809Sjmallett 0=disable, 1=enable */ 1090232809Sjmallett uint64_t set32 : 1; /**< Enable SET32 tracing 1091232809Sjmallett 0=disable, 1=enable */ 1092232809Sjmallett uint64_t set16 : 1; /**< Enable SET16 tracing 1093232809Sjmallett 0=disable, 1=enable */ 1094232809Sjmallett uint64_t set8 : 1; /**< Enable SET8 tracing 1095232809Sjmallett 0=disable, 1=enable */ 1096232809Sjmallett uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 1097232809Sjmallett 0=disable, 1=enable */ 1098232809Sjmallett uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 1099232809Sjmallett 0=disable, 1=enable */ 1100232809Sjmallett uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 1101232809Sjmallett 0=disable, 1=enable */ 1102232809Sjmallett uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 1103232809Sjmallett 0=disable, 1=enable */ 1104232809Sjmallett uint64_t reserved_32_35 : 4; 1105232809Sjmallett uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 1106232809Sjmallett 0=disable, 1=enable */ 1107232809Sjmallett uint64_t wbl2 : 1; /**< Enable WBL2 tracing 1108232809Sjmallett 0=disable, 1=enable */ 1109232809Sjmallett uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 1110232809Sjmallett 0=disable, 1=enable */ 1111232809Sjmallett uint64_t invl2 : 1; /**< Enable INVL2 tracing 1112232809Sjmallett 0=disable, 1=enable */ 1113232809Sjmallett uint64_t reserved_27_27 : 1; 1114232809Sjmallett uint64_t stgl2i : 1; /**< Enable STGL2I tracing 1115232809Sjmallett 0=disable, 1=enable */ 1116232809Sjmallett uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 1117232809Sjmallett 0=disable, 1=enable */ 1118232809Sjmallett uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 1119232809Sjmallett 0=disable, 1=enable */ 1120232809Sjmallett uint64_t fas64 : 1; /**< Enable FAS64 tracing 1121232809Sjmallett 0=disable, 1=enable */ 1122232809Sjmallett uint64_t fas32 : 1; /**< Enable FAS32 tracing 1123232809Sjmallett 0=disable, 1=enable */ 1124232809Sjmallett uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 1125232809Sjmallett 0=disable, 1=enable */ 1126232809Sjmallett uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 1127232809Sjmallett 0=disable, 1=enable */ 1128232809Sjmallett uint64_t reserved_16_19 : 4; 1129232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1130232809Sjmallett 0=disable, 1=enable */ 1131232809Sjmallett uint64_t iobst : 1; /**< Enable IOBST tracing 1132232809Sjmallett 0=disable, 1=enable */ 1133232809Sjmallett uint64_t reserved_0_13 : 14; 1134232809Sjmallett#else 1135232809Sjmallett uint64_t reserved_0_13 : 14; 1136232809Sjmallett uint64_t iobst : 1; 1137232809Sjmallett uint64_t iobdma : 1; 1138232809Sjmallett uint64_t reserved_16_19 : 4; 1139232809Sjmallett uint64_t stfil1 : 1; 1140232809Sjmallett uint64_t sttil1 : 1; 1141232809Sjmallett uint64_t fas32 : 1; 1142232809Sjmallett uint64_t fas64 : 1; 1143232809Sjmallett uint64_t wbil2i : 1; 1144232809Sjmallett uint64_t ltgl2i : 1; 1145232809Sjmallett uint64_t stgl2i : 1; 1146232809Sjmallett uint64_t reserved_27_27 : 1; 1147232809Sjmallett uint64_t invl2 : 1; 1148232809Sjmallett uint64_t wbil2 : 1; 1149232809Sjmallett uint64_t wbl2 : 1; 1150232809Sjmallett uint64_t lckl2 : 1; 1151232809Sjmallett uint64_t reserved_32_35 : 4; 1152232809Sjmallett uint64_t iobst8 : 1; 1153232809Sjmallett uint64_t iobst16 : 1; 1154232809Sjmallett uint64_t iobst32 : 1; 1155232809Sjmallett uint64_t iobst64 : 1; 1156232809Sjmallett uint64_t set8 : 1; 1157232809Sjmallett uint64_t set16 : 1; 1158232809Sjmallett uint64_t set32 : 1; 1159232809Sjmallett uint64_t set64 : 1; 1160232809Sjmallett uint64_t clr8 : 1; 1161232809Sjmallett uint64_t clr16 : 1; 1162232809Sjmallett uint64_t clr32 : 1; 1163232809Sjmallett uint64_t clr64 : 1; 1164232809Sjmallett uint64_t incr8 : 1; 1165232809Sjmallett uint64_t incr16 : 1; 1166232809Sjmallett uint64_t incr32 : 1; 1167232809Sjmallett uint64_t incr64 : 1; 1168232809Sjmallett uint64_t decr8 : 1; 1169232809Sjmallett uint64_t decr16 : 1; 1170232809Sjmallett uint64_t decr32 : 1; 1171232809Sjmallett uint64_t decr64 : 1; 1172232809Sjmallett uint64_t reserved_56_57 : 2; 1173232809Sjmallett uint64_t faa32 : 1; 1174232809Sjmallett uint64_t faa64 : 1; 1175232809Sjmallett uint64_t reserved_60_61 : 2; 1176232809Sjmallett uint64_t saa32 : 1; 1177232809Sjmallett uint64_t saa64 : 1; 1178232809Sjmallett#endif 1179232809Sjmallett } s; 1180232809Sjmallett struct cvmx_trax_filt_cmd_cn31xx { 1181232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1182232809Sjmallett uint64_t reserved_16_63 : 48; 1183232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1184232809Sjmallett 0=disable, 1=enable */ 1185232809Sjmallett uint64_t iobst : 1; /**< Enable IOBST tracing 1186232809Sjmallett 0=disable, 1=enable */ 1187232809Sjmallett uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 1188232809Sjmallett 0=disable, 1=enable */ 1189232809Sjmallett uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 1190232809Sjmallett 0=disable, 1=enable */ 1191232809Sjmallett uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 1192232809Sjmallett 0=disable, 1=enable */ 1193232809Sjmallett uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 1194232809Sjmallett 0=disable, 1=enable */ 1195232809Sjmallett uint64_t stt : 1; /**< Enable STT tracing 1196232809Sjmallett 0=disable, 1=enable */ 1197232809Sjmallett uint64_t stp : 1; /**< Enable STP tracing 1198232809Sjmallett 0=disable, 1=enable */ 1199232809Sjmallett uint64_t stc : 1; /**< Enable STC tracing 1200232809Sjmallett 0=disable, 1=enable */ 1201232809Sjmallett uint64_t stf : 1; /**< Enable STF tracing 1202232809Sjmallett 0=disable, 1=enable */ 1203232809Sjmallett uint64_t ldt : 1; /**< Enable LDT tracing 1204232809Sjmallett 0=disable, 1=enable */ 1205232809Sjmallett uint64_t ldi : 1; /**< Enable LDI tracing 1206232809Sjmallett 0=disable, 1=enable */ 1207232809Sjmallett uint64_t ldd : 1; /**< Enable LDD tracing 1208232809Sjmallett 0=disable, 1=enable */ 1209232809Sjmallett uint64_t psl1 : 1; /**< Enable PSL1 tracing 1210232809Sjmallett 0=disable, 1=enable */ 1211232809Sjmallett uint64_t pl2 : 1; /**< Enable PL2 tracing 1212232809Sjmallett 0=disable, 1=enable */ 1213232809Sjmallett uint64_t dwb : 1; /**< Enable DWB tracing 1214232809Sjmallett 0=disable, 1=enable */ 1215232809Sjmallett#else 1216232809Sjmallett uint64_t dwb : 1; 1217232809Sjmallett uint64_t pl2 : 1; 1218232809Sjmallett uint64_t psl1 : 1; 1219232809Sjmallett uint64_t ldd : 1; 1220232809Sjmallett uint64_t ldi : 1; 1221232809Sjmallett uint64_t ldt : 1; 1222232809Sjmallett uint64_t stf : 1; 1223232809Sjmallett uint64_t stc : 1; 1224232809Sjmallett uint64_t stp : 1; 1225232809Sjmallett uint64_t stt : 1; 1226232809Sjmallett uint64_t iobld8 : 1; 1227232809Sjmallett uint64_t iobld16 : 1; 1228232809Sjmallett uint64_t iobld32 : 1; 1229232809Sjmallett uint64_t iobld64 : 1; 1230232809Sjmallett uint64_t iobst : 1; 1231232809Sjmallett uint64_t iobdma : 1; 1232232809Sjmallett uint64_t reserved_16_63 : 48; 1233232809Sjmallett#endif 1234232809Sjmallett } cn31xx; 1235232809Sjmallett struct cvmx_trax_filt_cmd_cn31xx cn38xx; 1236232809Sjmallett struct cvmx_trax_filt_cmd_cn31xx cn38xxp2; 1237232809Sjmallett struct cvmx_trax_filt_cmd_cn52xx { 1238232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1239232809Sjmallett uint64_t reserved_17_63 : 47; 1240232809Sjmallett uint64_t saa : 1; /**< Enable SAA tracing 1241232809Sjmallett 0=disable, 1=enable */ 1242232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1243232809Sjmallett 0=disable, 1=enable */ 1244232809Sjmallett uint64_t iobst : 1; /**< Enable IOBST tracing 1245232809Sjmallett 0=disable, 1=enable */ 1246232809Sjmallett uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 1247232809Sjmallett 0=disable, 1=enable */ 1248232809Sjmallett uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 1249232809Sjmallett 0=disable, 1=enable */ 1250232809Sjmallett uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 1251232809Sjmallett 0=disable, 1=enable */ 1252232809Sjmallett uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 1253232809Sjmallett 0=disable, 1=enable */ 1254232809Sjmallett uint64_t stt : 1; /**< Enable STT tracing 1255232809Sjmallett 0=disable, 1=enable */ 1256232809Sjmallett uint64_t stp : 1; /**< Enable STP tracing 1257232809Sjmallett 0=disable, 1=enable */ 1258232809Sjmallett uint64_t stc : 1; /**< Enable STC tracing 1259232809Sjmallett 0=disable, 1=enable */ 1260232809Sjmallett uint64_t stf : 1; /**< Enable STF tracing 1261232809Sjmallett 0=disable, 1=enable */ 1262232809Sjmallett uint64_t ldt : 1; /**< Enable LDT tracing 1263232809Sjmallett 0=disable, 1=enable */ 1264232809Sjmallett uint64_t ldi : 1; /**< Enable LDI tracing 1265232809Sjmallett 0=disable, 1=enable */ 1266232809Sjmallett uint64_t ldd : 1; /**< Enable LDD tracing 1267232809Sjmallett 0=disable, 1=enable */ 1268232809Sjmallett uint64_t psl1 : 1; /**< Enable PSL1 tracing 1269232809Sjmallett 0=disable, 1=enable */ 1270232809Sjmallett uint64_t pl2 : 1; /**< Enable PL2 tracing 1271232809Sjmallett 0=disable, 1=enable */ 1272232809Sjmallett uint64_t dwb : 1; /**< Enable DWB tracing 1273232809Sjmallett 0=disable, 1=enable */ 1274232809Sjmallett#else 1275232809Sjmallett uint64_t dwb : 1; 1276232809Sjmallett uint64_t pl2 : 1; 1277232809Sjmallett uint64_t psl1 : 1; 1278232809Sjmallett uint64_t ldd : 1; 1279232809Sjmallett uint64_t ldi : 1; 1280232809Sjmallett uint64_t ldt : 1; 1281232809Sjmallett uint64_t stf : 1; 1282232809Sjmallett uint64_t stc : 1; 1283232809Sjmallett uint64_t stp : 1; 1284232809Sjmallett uint64_t stt : 1; 1285232809Sjmallett uint64_t iobld8 : 1; 1286232809Sjmallett uint64_t iobld16 : 1; 1287232809Sjmallett uint64_t iobld32 : 1; 1288232809Sjmallett uint64_t iobld64 : 1; 1289232809Sjmallett uint64_t iobst : 1; 1290232809Sjmallett uint64_t iobdma : 1; 1291232809Sjmallett uint64_t saa : 1; 1292232809Sjmallett uint64_t reserved_17_63 : 47; 1293232809Sjmallett#endif 1294232809Sjmallett } cn52xx; 1295232809Sjmallett struct cvmx_trax_filt_cmd_cn52xx cn52xxp1; 1296232809Sjmallett struct cvmx_trax_filt_cmd_cn52xx cn56xx; 1297232809Sjmallett struct cvmx_trax_filt_cmd_cn52xx cn56xxp1; 1298232809Sjmallett struct cvmx_trax_filt_cmd_cn52xx cn58xx; 1299232809Sjmallett struct cvmx_trax_filt_cmd_cn52xx cn58xxp1; 1300232809Sjmallett struct cvmx_trax_filt_cmd_cn61xx { 1301232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1302232809Sjmallett uint64_t saa64 : 1; /**< Enable SAA64 tracing 1303232809Sjmallett 0=disable, 1=enable */ 1304232809Sjmallett uint64_t saa32 : 1; /**< Enable SAA32 tracing 1305232809Sjmallett 0=disable, 1=enable */ 1306232809Sjmallett uint64_t reserved_60_61 : 2; 1307232809Sjmallett uint64_t faa64 : 1; /**< Enable FAA64 tracing 1308232809Sjmallett 0=disable, 1=enable */ 1309232809Sjmallett uint64_t faa32 : 1; /**< Enable FAA32 tracing 1310232809Sjmallett 0=disable, 1=enable */ 1311232809Sjmallett uint64_t reserved_56_57 : 2; 1312232809Sjmallett uint64_t decr64 : 1; /**< Enable DECR64 tracing 1313232809Sjmallett 0=disable, 1=enable */ 1314232809Sjmallett uint64_t decr32 : 1; /**< Enable DECR32 tracing 1315232809Sjmallett 0=disable, 1=enable */ 1316232809Sjmallett uint64_t decr16 : 1; /**< Enable DECR16 tracing 1317232809Sjmallett 0=disable, 1=enable */ 1318232809Sjmallett uint64_t decr8 : 1; /**< Enable DECR8 tracing 1319232809Sjmallett 0=disable, 1=enable */ 1320232809Sjmallett uint64_t incr64 : 1; /**< Enable INCR64 tracing 1321232809Sjmallett 0=disable, 1=enable */ 1322232809Sjmallett uint64_t incr32 : 1; /**< Enable INCR32 tracing 1323232809Sjmallett 0=disable, 1=enable */ 1324232809Sjmallett uint64_t incr16 : 1; /**< Enable INCR16 tracing 1325232809Sjmallett 0=disable, 1=enable */ 1326232809Sjmallett uint64_t incr8 : 1; /**< Enable INCR8 tracing 1327232809Sjmallett 0=disable, 1=enable */ 1328232809Sjmallett uint64_t clr64 : 1; /**< Enable CLR64 tracing 1329232809Sjmallett 0=disable, 1=enable */ 1330232809Sjmallett uint64_t clr32 : 1; /**< Enable CLR32 tracing 1331232809Sjmallett 0=disable, 1=enable */ 1332232809Sjmallett uint64_t clr16 : 1; /**< Enable CLR16 tracing 1333232809Sjmallett 0=disable, 1=enable */ 1334232809Sjmallett uint64_t clr8 : 1; /**< Enable CLR8 tracing 1335232809Sjmallett 0=disable, 1=enable */ 1336232809Sjmallett uint64_t set64 : 1; /**< Enable SET64 tracing 1337232809Sjmallett 0=disable, 1=enable */ 1338232809Sjmallett uint64_t set32 : 1; /**< Enable SET32 tracing 1339232809Sjmallett 0=disable, 1=enable */ 1340232809Sjmallett uint64_t set16 : 1; /**< Enable SET16 tracing 1341232809Sjmallett 0=disable, 1=enable */ 1342232809Sjmallett uint64_t set8 : 1; /**< Enable SET8 tracing 1343232809Sjmallett 0=disable, 1=enable */ 1344232809Sjmallett uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 1345232809Sjmallett 0=disable, 1=enable */ 1346232809Sjmallett uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 1347232809Sjmallett 0=disable, 1=enable */ 1348232809Sjmallett uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 1349232809Sjmallett 0=disable, 1=enable */ 1350232809Sjmallett uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 1351232809Sjmallett 0=disable, 1=enable */ 1352232809Sjmallett uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 1353232809Sjmallett 0=disable, 1=enable */ 1354232809Sjmallett uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 1355232809Sjmallett 0=disable, 1=enable */ 1356232809Sjmallett uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 1357232809Sjmallett 0=disable, 1=enable */ 1358232809Sjmallett uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 1359232809Sjmallett 0=disable, 1=enable */ 1360232809Sjmallett uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 1361232809Sjmallett 0=disable, 1=enable */ 1362232809Sjmallett uint64_t wbl2 : 1; /**< Enable WBL2 tracing 1363232809Sjmallett 0=disable, 1=enable */ 1364232809Sjmallett uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 1365232809Sjmallett 0=disable, 1=enable */ 1366232809Sjmallett uint64_t invl2 : 1; /**< Enable INVL2 tracing 1367232809Sjmallett 0=disable, 1=enable */ 1368232809Sjmallett uint64_t reserved_27_27 : 1; 1369232809Sjmallett uint64_t stgl2i : 1; /**< Enable STGL2I tracing 1370232809Sjmallett 0=disable, 1=enable */ 1371232809Sjmallett uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 1372232809Sjmallett 0=disable, 1=enable */ 1373232809Sjmallett uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 1374232809Sjmallett 0=disable, 1=enable */ 1375232809Sjmallett uint64_t fas64 : 1; /**< Enable FAS64 tracing 1376232809Sjmallett 0=disable, 1=enable */ 1377232809Sjmallett uint64_t fas32 : 1; /**< Enable FAS32 tracing 1378232809Sjmallett 0=disable, 1=enable */ 1379232809Sjmallett uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 1380232809Sjmallett 0=disable, 1=enable */ 1381232809Sjmallett uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 1382232809Sjmallett 0=disable, 1=enable */ 1383232809Sjmallett uint64_t stc : 1; /**< Enable STC tracing 1384232809Sjmallett 0=disable, 1=enable */ 1385232809Sjmallett uint64_t stp : 1; /**< Enable STP tracing 1386232809Sjmallett 0=disable, 1=enable */ 1387232809Sjmallett uint64_t stt : 1; /**< Enable STT tracing 1388232809Sjmallett 0=disable, 1=enable */ 1389232809Sjmallett uint64_t stf : 1; /**< Enable STF tracing 1390232809Sjmallett 0=disable, 1=enable */ 1391232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1392232809Sjmallett 0=disable, 1=enable */ 1393232809Sjmallett uint64_t reserved_10_14 : 5; 1394232809Sjmallett uint64_t psl1 : 1; /**< Enable PSL1 tracing 1395232809Sjmallett 0=disable, 1=enable */ 1396232809Sjmallett uint64_t ldd : 1; /**< Enable LDD tracing 1397232809Sjmallett 0=disable, 1=enable */ 1398232809Sjmallett uint64_t reserved_6_7 : 2; 1399232809Sjmallett uint64_t dwb : 1; /**< Enable DWB tracing 1400232809Sjmallett 0=disable, 1=enable */ 1401232809Sjmallett uint64_t rpl2 : 1; /**< Enable RPL2 tracing 1402232809Sjmallett 0=disable, 1=enable */ 1403232809Sjmallett uint64_t pl2 : 1; /**< Enable PL2 tracing 1404232809Sjmallett 0=disable, 1=enable */ 1405232809Sjmallett uint64_t ldi : 1; /**< Enable LDI tracing 1406232809Sjmallett 0=disable, 1=enable */ 1407232809Sjmallett uint64_t ldt : 1; /**< Enable LDT tracing 1408232809Sjmallett 0=disable, 1=enable */ 1409232809Sjmallett uint64_t nop : 1; /**< Enable NOP tracing 1410232809Sjmallett 0=disable, 1=enable */ 1411232809Sjmallett#else 1412232809Sjmallett uint64_t nop : 1; 1413232809Sjmallett uint64_t ldt : 1; 1414232809Sjmallett uint64_t ldi : 1; 1415232809Sjmallett uint64_t pl2 : 1; 1416232809Sjmallett uint64_t rpl2 : 1; 1417232809Sjmallett uint64_t dwb : 1; 1418232809Sjmallett uint64_t reserved_6_7 : 2; 1419232809Sjmallett uint64_t ldd : 1; 1420232809Sjmallett uint64_t psl1 : 1; 1421232809Sjmallett uint64_t reserved_10_14 : 5; 1422232809Sjmallett uint64_t iobdma : 1; 1423232809Sjmallett uint64_t stf : 1; 1424232809Sjmallett uint64_t stt : 1; 1425232809Sjmallett uint64_t stp : 1; 1426232809Sjmallett uint64_t stc : 1; 1427232809Sjmallett uint64_t stfil1 : 1; 1428232809Sjmallett uint64_t sttil1 : 1; 1429232809Sjmallett uint64_t fas32 : 1; 1430232809Sjmallett uint64_t fas64 : 1; 1431232809Sjmallett uint64_t wbil2i : 1; 1432232809Sjmallett uint64_t ltgl2i : 1; 1433232809Sjmallett uint64_t stgl2i : 1; 1434232809Sjmallett uint64_t reserved_27_27 : 1; 1435232809Sjmallett uint64_t invl2 : 1; 1436232809Sjmallett uint64_t wbil2 : 1; 1437232809Sjmallett uint64_t wbl2 : 1; 1438232809Sjmallett uint64_t lckl2 : 1; 1439232809Sjmallett uint64_t iobld8 : 1; 1440232809Sjmallett uint64_t iobld16 : 1; 1441232809Sjmallett uint64_t iobld32 : 1; 1442232809Sjmallett uint64_t iobld64 : 1; 1443232809Sjmallett uint64_t iobst8 : 1; 1444232809Sjmallett uint64_t iobst16 : 1; 1445232809Sjmallett uint64_t iobst32 : 1; 1446232809Sjmallett uint64_t iobst64 : 1; 1447232809Sjmallett uint64_t set8 : 1; 1448232809Sjmallett uint64_t set16 : 1; 1449232809Sjmallett uint64_t set32 : 1; 1450232809Sjmallett uint64_t set64 : 1; 1451232809Sjmallett uint64_t clr8 : 1; 1452232809Sjmallett uint64_t clr16 : 1; 1453232809Sjmallett uint64_t clr32 : 1; 1454232809Sjmallett uint64_t clr64 : 1; 1455232809Sjmallett uint64_t incr8 : 1; 1456232809Sjmallett uint64_t incr16 : 1; 1457232809Sjmallett uint64_t incr32 : 1; 1458232809Sjmallett uint64_t incr64 : 1; 1459232809Sjmallett uint64_t decr8 : 1; 1460232809Sjmallett uint64_t decr16 : 1; 1461232809Sjmallett uint64_t decr32 : 1; 1462232809Sjmallett uint64_t decr64 : 1; 1463232809Sjmallett uint64_t reserved_56_57 : 2; 1464232809Sjmallett uint64_t faa32 : 1; 1465232809Sjmallett uint64_t faa64 : 1; 1466232809Sjmallett uint64_t reserved_60_61 : 2; 1467232809Sjmallett uint64_t saa32 : 1; 1468232809Sjmallett uint64_t saa64 : 1; 1469232809Sjmallett#endif 1470232809Sjmallett } cn61xx; 1471232809Sjmallett struct cvmx_trax_filt_cmd_cn61xx cn63xx; 1472232809Sjmallett struct cvmx_trax_filt_cmd_cn61xx cn63xxp1; 1473232809Sjmallett struct cvmx_trax_filt_cmd_cn61xx cn66xx; 1474232809Sjmallett struct cvmx_trax_filt_cmd_cn61xx cn68xx; 1475232809Sjmallett struct cvmx_trax_filt_cmd_cn61xx cn68xxp1; 1476232809Sjmallett struct cvmx_trax_filt_cmd_cn61xx cnf71xx; 1477232809Sjmallett}; 1478232809Sjmalletttypedef union cvmx_trax_filt_cmd cvmx_trax_filt_cmd_t; 1479232809Sjmallett 1480232809Sjmallett/** 1481232809Sjmallett * cvmx_tra#_filt_did 1482232809Sjmallett * 1483232809Sjmallett * TRA_FILT_DID = Trace Buffer Filter DestinationId Mask 1484232809Sjmallett * 1485232809Sjmallett * Description: 1486232809Sjmallett */ 1487232809Sjmallettunion cvmx_trax_filt_did { 1488232809Sjmallett uint64_t u64; 1489232809Sjmallett struct cvmx_trax_filt_did_s { 1490232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1491232809Sjmallett uint64_t reserved_13_63 : 51; 1492232809Sjmallett uint64_t pow : 1; /**< Enable tracing of requests to POW 1493232809Sjmallett (get work, add work, status/memory/index 1494232809Sjmallett loads, NULLRd loads, CSR's) */ 1495232809Sjmallett uint64_t reserved_9_11 : 3; 1496232809Sjmallett uint64_t rng : 1; /**< Enable tracing of requests to RNG 1497232809Sjmallett (loads/IOBDMA's are legal) */ 1498232809Sjmallett uint64_t zip : 1; /**< Enable tracing of requests to ZIP 1499232809Sjmallett (doorbell stores are legal) */ 1500232809Sjmallett uint64_t dfa : 1; /**< Enable tracing of requests to DFA 1501232809Sjmallett (CSR's and operations are legal) */ 1502232809Sjmallett uint64_t fpa : 1; /**< Enable tracing of requests to FPA 1503232809Sjmallett (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 1504232809Sjmallett uint64_t key : 1; /**< Enable tracing of requests to KEY memory 1505232809Sjmallett (loads/IOBDMA's/stores are legal) */ 1506232809Sjmallett uint64_t reserved_3_3 : 1; 1507232809Sjmallett uint64_t illegal3 : 2; /**< Illegal destinations */ 1508232809Sjmallett uint64_t mio : 1; /**< Enable tracing of MIO accesses 1509232809Sjmallett (CIU and GPIO CSR's, boot bus accesses) */ 1510232809Sjmallett#else 1511232809Sjmallett uint64_t mio : 1; 1512232809Sjmallett uint64_t illegal3 : 2; 1513232809Sjmallett uint64_t reserved_3_3 : 1; 1514232809Sjmallett uint64_t key : 1; 1515232809Sjmallett uint64_t fpa : 1; 1516232809Sjmallett uint64_t dfa : 1; 1517232809Sjmallett uint64_t zip : 1; 1518232809Sjmallett uint64_t rng : 1; 1519232809Sjmallett uint64_t reserved_9_11 : 3; 1520232809Sjmallett uint64_t pow : 1; 1521232809Sjmallett uint64_t reserved_13_63 : 51; 1522232809Sjmallett#endif 1523232809Sjmallett } s; 1524232809Sjmallett struct cvmx_trax_filt_did_cn31xx { 1525232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1526232809Sjmallett uint64_t reserved_32_63 : 32; 1527232809Sjmallett uint64_t illegal : 19; /**< Illegal destinations */ 1528232809Sjmallett uint64_t pow : 1; /**< Enable tracing of requests to POW 1529232809Sjmallett (get work, add work, status/memory/index 1530232809Sjmallett loads, NULLRd loads, CSR's) */ 1531232809Sjmallett uint64_t illegal2 : 3; /**< Illegal destinations */ 1532232809Sjmallett uint64_t rng : 1; /**< Enable tracing of requests to RNG 1533232809Sjmallett (loads/IOBDMA's are legal) */ 1534232809Sjmallett uint64_t zip : 1; /**< Enable tracing of requests to ZIP 1535232809Sjmallett (doorbell stores are legal) */ 1536232809Sjmallett uint64_t dfa : 1; /**< Enable tracing of requests to DFA 1537232809Sjmallett (CSR's and operations are legal) */ 1538232809Sjmallett uint64_t fpa : 1; /**< Enable tracing of requests to FPA 1539232809Sjmallett (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 1540232809Sjmallett uint64_t key : 1; /**< Enable tracing of requests to KEY memory 1541232809Sjmallett (loads/IOBDMA's/stores are legal) */ 1542232809Sjmallett uint64_t pci : 1; /**< Enable tracing of requests to PCI and RSL-type 1543232809Sjmallett CSR's (RSL CSR's, PCI bus operations, PCI 1544232809Sjmallett CSR's) */ 1545232809Sjmallett uint64_t illegal3 : 2; /**< Illegal destinations */ 1546232809Sjmallett uint64_t mio : 1; /**< Enable tracing of CIU and GPIO CSR's */ 1547232809Sjmallett#else 1548232809Sjmallett uint64_t mio : 1; 1549232809Sjmallett uint64_t illegal3 : 2; 1550232809Sjmallett uint64_t pci : 1; 1551232809Sjmallett uint64_t key : 1; 1552232809Sjmallett uint64_t fpa : 1; 1553232809Sjmallett uint64_t dfa : 1; 1554232809Sjmallett uint64_t zip : 1; 1555232809Sjmallett uint64_t rng : 1; 1556232809Sjmallett uint64_t illegal2 : 3; 1557232809Sjmallett uint64_t pow : 1; 1558232809Sjmallett uint64_t illegal : 19; 1559232809Sjmallett uint64_t reserved_32_63 : 32; 1560232809Sjmallett#endif 1561232809Sjmallett } cn31xx; 1562232809Sjmallett struct cvmx_trax_filt_did_cn31xx cn38xx; 1563232809Sjmallett struct cvmx_trax_filt_did_cn31xx cn38xxp2; 1564232809Sjmallett struct cvmx_trax_filt_did_cn31xx cn52xx; 1565232809Sjmallett struct cvmx_trax_filt_did_cn31xx cn52xxp1; 1566232809Sjmallett struct cvmx_trax_filt_did_cn31xx cn56xx; 1567232809Sjmallett struct cvmx_trax_filt_did_cn31xx cn56xxp1; 1568232809Sjmallett struct cvmx_trax_filt_did_cn31xx cn58xx; 1569232809Sjmallett struct cvmx_trax_filt_did_cn31xx cn58xxp1; 1570232809Sjmallett struct cvmx_trax_filt_did_cn61xx { 1571232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1572232809Sjmallett uint64_t reserved_32_63 : 32; 1573232809Sjmallett uint64_t illegal5 : 1; /**< Illegal destinations */ 1574232809Sjmallett uint64_t fau : 1; /**< Enable tracing of FAU accesses */ 1575232809Sjmallett uint64_t illegal4 : 2; /**< Illegal destinations */ 1576232809Sjmallett uint64_t dpi : 1; /**< Enable tracing of DPI accesses 1577232809Sjmallett (DPI NCB CSRs) */ 1578232809Sjmallett uint64_t illegal : 12; /**< Illegal destinations */ 1579232809Sjmallett uint64_t rad : 1; /**< Enable tracing of RAD accesses 1580232809Sjmallett (doorbells) */ 1581232809Sjmallett uint64_t usb0 : 1; /**< Enable tracing of USB0 accesses 1582232809Sjmallett (UAHC0 EHCI and OHCI NCB CSRs) */ 1583232809Sjmallett uint64_t pow : 1; /**< Enable tracing of requests to POW 1584232809Sjmallett (get work, add work, status/memory/index 1585232809Sjmallett loads, NULLRd loads, CSR's) */ 1586232809Sjmallett uint64_t illegal2 : 1; /**< Illegal destination */ 1587232809Sjmallett uint64_t pko : 1; /**< Enable tracing of PKO accesses 1588232809Sjmallett (doorbells) */ 1589232809Sjmallett uint64_t ipd : 1; /**< Enable tracing of IPD CSR accesses 1590232809Sjmallett (IPD CSRs) */ 1591232809Sjmallett uint64_t rng : 1; /**< Enable tracing of requests to RNG 1592232809Sjmallett (loads/IOBDMA's are legal) */ 1593232809Sjmallett uint64_t zip : 1; /**< Enable tracing of requests to ZIP 1594232809Sjmallett (doorbell stores are legal) */ 1595232809Sjmallett uint64_t dfa : 1; /**< Enable tracing of requests to DFA 1596232809Sjmallett (CSR's and operations are legal) */ 1597232809Sjmallett uint64_t fpa : 1; /**< Enable tracing of requests to FPA 1598232809Sjmallett (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 1599232809Sjmallett uint64_t key : 1; /**< Enable tracing of requests to KEY memory 1600232809Sjmallett (loads/IOBDMA's/stores are legal) */ 1601232809Sjmallett uint64_t sli : 1; /**< Enable tracing of requests to SLI and RSL-type 1602232809Sjmallett CSR's (RSL CSR's, PCI/sRIO bus operations, SLI 1603232809Sjmallett CSR's) */ 1604232809Sjmallett uint64_t illegal3 : 2; /**< Illegal destinations */ 1605232809Sjmallett uint64_t mio : 1; /**< Enable tracing of MIO accesses 1606232809Sjmallett (CIU and GPIO CSR's, boot bus accesses) */ 1607232809Sjmallett#else 1608232809Sjmallett uint64_t mio : 1; 1609232809Sjmallett uint64_t illegal3 : 2; 1610232809Sjmallett uint64_t sli : 1; 1611232809Sjmallett uint64_t key : 1; 1612232809Sjmallett uint64_t fpa : 1; 1613232809Sjmallett uint64_t dfa : 1; 1614232809Sjmallett uint64_t zip : 1; 1615232809Sjmallett uint64_t rng : 1; 1616232809Sjmallett uint64_t ipd : 1; 1617232809Sjmallett uint64_t pko : 1; 1618232809Sjmallett uint64_t illegal2 : 1; 1619232809Sjmallett uint64_t pow : 1; 1620232809Sjmallett uint64_t usb0 : 1; 1621232809Sjmallett uint64_t rad : 1; 1622232809Sjmallett uint64_t illegal : 12; 1623232809Sjmallett uint64_t dpi : 1; 1624232809Sjmallett uint64_t illegal4 : 2; 1625232809Sjmallett uint64_t fau : 1; 1626232809Sjmallett uint64_t illegal5 : 1; 1627232809Sjmallett uint64_t reserved_32_63 : 32; 1628232809Sjmallett#endif 1629232809Sjmallett } cn61xx; 1630232809Sjmallett struct cvmx_trax_filt_did_cn61xx cn63xx; 1631232809Sjmallett struct cvmx_trax_filt_did_cn61xx cn63xxp1; 1632232809Sjmallett struct cvmx_trax_filt_did_cn61xx cn66xx; 1633232809Sjmallett struct cvmx_trax_filt_did_cn61xx cn68xx; 1634232809Sjmallett struct cvmx_trax_filt_did_cn61xx cn68xxp1; 1635232809Sjmallett struct cvmx_trax_filt_did_cn61xx cnf71xx; 1636232809Sjmallett}; 1637232809Sjmalletttypedef union cvmx_trax_filt_did cvmx_trax_filt_did_t; 1638232809Sjmallett 1639232809Sjmallett/** 1640232809Sjmallett * cvmx_tra#_filt_sid 1641232809Sjmallett * 1642232809Sjmallett * TRA_FILT_SID = Trace Buffer Filter SourceId Mask 1643232809Sjmallett * 1644232809Sjmallett * Description: 1645232809Sjmallett */ 1646232809Sjmallettunion cvmx_trax_filt_sid { 1647232809Sjmallett uint64_t u64; 1648232809Sjmallett struct cvmx_trax_filt_sid_s { 1649232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1650232809Sjmallett uint64_t reserved_20_63 : 44; 1651232809Sjmallett uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1652232809Sjmallett uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1653232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 1654232809Sjmallett uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1655232809Sjmallett uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1656232809Sjmallett uint64_t pp : 16; /**< Enable tracing from PP[N] with matching SourceID 1657232809Sjmallett 0=disable, 1=enable per bit N where 0<=N<=3 */ 1658232809Sjmallett#else 1659232809Sjmallett uint64_t pp : 16; 1660232809Sjmallett uint64_t pki : 1; 1661232809Sjmallett uint64_t pko : 1; 1662232809Sjmallett uint64_t iobreq : 1; 1663232809Sjmallett uint64_t dwb : 1; 1664232809Sjmallett uint64_t reserved_20_63 : 44; 1665232809Sjmallett#endif 1666232809Sjmallett } s; 1667232809Sjmallett struct cvmx_trax_filt_sid_s cn31xx; 1668232809Sjmallett struct cvmx_trax_filt_sid_s cn38xx; 1669232809Sjmallett struct cvmx_trax_filt_sid_s cn38xxp2; 1670232809Sjmallett struct cvmx_trax_filt_sid_s cn52xx; 1671232809Sjmallett struct cvmx_trax_filt_sid_s cn52xxp1; 1672232809Sjmallett struct cvmx_trax_filt_sid_s cn56xx; 1673232809Sjmallett struct cvmx_trax_filt_sid_s cn56xxp1; 1674232809Sjmallett struct cvmx_trax_filt_sid_s cn58xx; 1675232809Sjmallett struct cvmx_trax_filt_sid_s cn58xxp1; 1676232809Sjmallett struct cvmx_trax_filt_sid_cn61xx { 1677232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1678232809Sjmallett uint64_t reserved_20_63 : 44; 1679232809Sjmallett uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1680232809Sjmallett uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1681232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 1682232809Sjmallett uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1683232809Sjmallett uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1684232809Sjmallett uint64_t reserved_4_15 : 12; 1685232809Sjmallett uint64_t pp : 4; /**< Enable tracing from PP[N] with matching SourceID 1686232809Sjmallett 0=disable, 1=enable per bit N where 0<=N<=3 */ 1687232809Sjmallett#else 1688232809Sjmallett uint64_t pp : 4; 1689232809Sjmallett uint64_t reserved_4_15 : 12; 1690232809Sjmallett uint64_t pki : 1; 1691232809Sjmallett uint64_t pko : 1; 1692232809Sjmallett uint64_t iobreq : 1; 1693232809Sjmallett uint64_t dwb : 1; 1694232809Sjmallett uint64_t reserved_20_63 : 44; 1695232809Sjmallett#endif 1696232809Sjmallett } cn61xx; 1697232809Sjmallett struct cvmx_trax_filt_sid_cn63xx { 1698232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1699232809Sjmallett uint64_t reserved_20_63 : 44; 1700232809Sjmallett uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1701232809Sjmallett uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1702232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 1703232809Sjmallett uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1704232809Sjmallett uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1705232809Sjmallett uint64_t reserved_8_15 : 8; 1706232809Sjmallett uint64_t pp : 8; /**< Enable tracing from PP[N] with matching SourceID 1707232809Sjmallett 0=disable, 1=enableper bit N where 0<=N<=15 */ 1708232809Sjmallett#else 1709232809Sjmallett uint64_t pp : 8; 1710232809Sjmallett uint64_t reserved_8_15 : 8; 1711232809Sjmallett uint64_t pki : 1; 1712232809Sjmallett uint64_t pko : 1; 1713232809Sjmallett uint64_t iobreq : 1; 1714232809Sjmallett uint64_t dwb : 1; 1715232809Sjmallett uint64_t reserved_20_63 : 44; 1716232809Sjmallett#endif 1717232809Sjmallett } cn63xx; 1718232809Sjmallett struct cvmx_trax_filt_sid_cn63xxp1 { 1719232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1720232809Sjmallett uint64_t reserved_20_63 : 44; 1721232809Sjmallett uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1722232809Sjmallett uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1723232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 1724232809Sjmallett uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1725232809Sjmallett uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1726232809Sjmallett uint64_t reserved_6_15 : 10; 1727232809Sjmallett uint64_t pp : 6; /**< Enable tracing from PP[N] with matching SourceID 1728232809Sjmallett 0=disable, 1=enable per bit N where 0<=N<=5 */ 1729232809Sjmallett#else 1730232809Sjmallett uint64_t pp : 6; 1731232809Sjmallett uint64_t reserved_6_15 : 10; 1732232809Sjmallett uint64_t pki : 1; 1733232809Sjmallett uint64_t pko : 1; 1734232809Sjmallett uint64_t iobreq : 1; 1735232809Sjmallett uint64_t dwb : 1; 1736232809Sjmallett uint64_t reserved_20_63 : 44; 1737232809Sjmallett#endif 1738232809Sjmallett } cn63xxp1; 1739232809Sjmallett struct cvmx_trax_filt_sid_cn66xx { 1740232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1741232809Sjmallett uint64_t reserved_20_63 : 44; 1742232809Sjmallett uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1743232809Sjmallett uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1744232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 1745232809Sjmallett uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1746232809Sjmallett uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1747232809Sjmallett uint64_t reserved_10_15 : 6; 1748232809Sjmallett uint64_t pp : 10; /**< Enable tracing from PP[N] with matching SourceID 1749232809Sjmallett 0=disable, 1=enableper bit N where 0<=N<=15 */ 1750232809Sjmallett#else 1751232809Sjmallett uint64_t pp : 10; 1752232809Sjmallett uint64_t reserved_10_15 : 6; 1753232809Sjmallett uint64_t pki : 1; 1754232809Sjmallett uint64_t pko : 1; 1755232809Sjmallett uint64_t iobreq : 1; 1756232809Sjmallett uint64_t dwb : 1; 1757232809Sjmallett uint64_t reserved_20_63 : 44; 1758232809Sjmallett#endif 1759232809Sjmallett } cn66xx; 1760232809Sjmallett struct cvmx_trax_filt_sid_cn63xx cn68xx; 1761232809Sjmallett struct cvmx_trax_filt_sid_cn63xx cn68xxp1; 1762232809Sjmallett struct cvmx_trax_filt_sid_cn61xx cnf71xx; 1763232809Sjmallett}; 1764232809Sjmalletttypedef union cvmx_trax_filt_sid cvmx_trax_filt_sid_t; 1765232809Sjmallett 1766232809Sjmallett/** 1767232809Sjmallett * cvmx_tra#_int_status 1768232809Sjmallett * 1769232809Sjmallett * TRA_INT_STATUS = Trace Buffer Interrupt Status 1770232809Sjmallett * 1771232809Sjmallett * Description: 1772232809Sjmallett * 1773232809Sjmallett * Notes: 1774232809Sjmallett * During a CSR write to this register, the write data is used as a mask to clear the selected status 1775232809Sjmallett * bits (status'[3:0] = status[3:0] & ~write_data[3:0]). 1776232809Sjmallett */ 1777232809Sjmallettunion cvmx_trax_int_status { 1778232809Sjmallett uint64_t u64; 1779232809Sjmallett struct cvmx_trax_int_status_s { 1780232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1781232809Sjmallett uint64_t reserved_4_63 : 60; 1782232809Sjmallett uint64_t mcd0_thr : 1; /**< MCD0 full threshold interrupt status 1783232809Sjmallett 0=trace buffer did not generate MCD0 wire pulse 1784232809Sjmallett 1=trace buffer did generate MCD0 wire pulse 1785232809Sjmallett and prevents additional MCD0_THR MCD0 wire pulses */ 1786232809Sjmallett uint64_t mcd0_trg : 1; /**< MCD0 end trigger interrupt status 1787232809Sjmallett 0=trace buffer did not generate interrupt 1788232809Sjmallett 1=trace buffer did generate interrupt 1789232809Sjmallett and prevents additional MCD0_TRG MCD0 wire pulses */ 1790232809Sjmallett uint64_t ciu_thr : 1; /**< CIU full threshold interrupt status 1791232809Sjmallett 0=trace buffer did not generate interrupt 1792232809Sjmallett 1=trace buffer did generate interrupt */ 1793232809Sjmallett uint64_t ciu_trg : 1; /**< CIU end trigger interrupt status 1794232809Sjmallett 0=trace buffer did not generate interrupt 1795232809Sjmallett 1=trace buffer did generate interrupt */ 1796232809Sjmallett#else 1797232809Sjmallett uint64_t ciu_trg : 1; 1798232809Sjmallett uint64_t ciu_thr : 1; 1799232809Sjmallett uint64_t mcd0_trg : 1; 1800232809Sjmallett uint64_t mcd0_thr : 1; 1801232809Sjmallett uint64_t reserved_4_63 : 60; 1802232809Sjmallett#endif 1803232809Sjmallett } s; 1804232809Sjmallett struct cvmx_trax_int_status_s cn31xx; 1805232809Sjmallett struct cvmx_trax_int_status_s cn38xx; 1806232809Sjmallett struct cvmx_trax_int_status_s cn38xxp2; 1807232809Sjmallett struct cvmx_trax_int_status_s cn52xx; 1808232809Sjmallett struct cvmx_trax_int_status_s cn52xxp1; 1809232809Sjmallett struct cvmx_trax_int_status_s cn56xx; 1810232809Sjmallett struct cvmx_trax_int_status_s cn56xxp1; 1811232809Sjmallett struct cvmx_trax_int_status_s cn58xx; 1812232809Sjmallett struct cvmx_trax_int_status_s cn58xxp1; 1813232809Sjmallett struct cvmx_trax_int_status_s cn61xx; 1814232809Sjmallett struct cvmx_trax_int_status_s cn63xx; 1815232809Sjmallett struct cvmx_trax_int_status_s cn63xxp1; 1816232809Sjmallett struct cvmx_trax_int_status_s cn66xx; 1817232809Sjmallett struct cvmx_trax_int_status_s cn68xx; 1818232809Sjmallett struct cvmx_trax_int_status_s cn68xxp1; 1819232809Sjmallett struct cvmx_trax_int_status_s cnf71xx; 1820232809Sjmallett}; 1821232809Sjmalletttypedef union cvmx_trax_int_status cvmx_trax_int_status_t; 1822232809Sjmallett 1823232809Sjmallett/** 1824232809Sjmallett * cvmx_tra#_read_dat 1825232809Sjmallett * 1826232809Sjmallett * TRA_READ_DAT = Trace Buffer Read Data 1827232809Sjmallett * 1828232809Sjmallett * Description: 1829232809Sjmallett * 1830232809Sjmallett * Notes: 1831232809Sjmallett * This CSR is a memory of 1024 entries. When the trace was enabled, the read pointer was set to entry 1832232809Sjmallett * 0 by hardware. Each read to this address increments the read pointer. 1833232809Sjmallett */ 1834232809Sjmallettunion cvmx_trax_read_dat { 1835232809Sjmallett uint64_t u64; 1836232809Sjmallett struct cvmx_trax_read_dat_s { 1837232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1838232809Sjmallett uint64_t data : 64; /**< Trace buffer data for current entry 1839232809Sjmallett if TRA_CTL[16]== 1; returns lower 64 bits of entry 1840232809Sjmallett else two access are necessary to get all of 69bits 1841232809Sjmallett first access of a pair is the lower 64 bits and 1842232809Sjmallett second access is the upper 5 bits. */ 1843232809Sjmallett#else 1844232809Sjmallett uint64_t data : 64; 1845232809Sjmallett#endif 1846232809Sjmallett } s; 1847232809Sjmallett struct cvmx_trax_read_dat_s cn31xx; 1848232809Sjmallett struct cvmx_trax_read_dat_s cn38xx; 1849232809Sjmallett struct cvmx_trax_read_dat_s cn38xxp2; 1850232809Sjmallett struct cvmx_trax_read_dat_s cn52xx; 1851232809Sjmallett struct cvmx_trax_read_dat_s cn52xxp1; 1852232809Sjmallett struct cvmx_trax_read_dat_s cn56xx; 1853232809Sjmallett struct cvmx_trax_read_dat_s cn56xxp1; 1854232809Sjmallett struct cvmx_trax_read_dat_s cn58xx; 1855232809Sjmallett struct cvmx_trax_read_dat_s cn58xxp1; 1856232809Sjmallett struct cvmx_trax_read_dat_s cn61xx; 1857232809Sjmallett struct cvmx_trax_read_dat_s cn63xx; 1858232809Sjmallett struct cvmx_trax_read_dat_s cn63xxp1; 1859232809Sjmallett struct cvmx_trax_read_dat_s cn66xx; 1860232809Sjmallett struct cvmx_trax_read_dat_s cn68xx; 1861232809Sjmallett struct cvmx_trax_read_dat_s cn68xxp1; 1862232809Sjmallett struct cvmx_trax_read_dat_s cnf71xx; 1863232809Sjmallett}; 1864232809Sjmalletttypedef union cvmx_trax_read_dat cvmx_trax_read_dat_t; 1865232809Sjmallett 1866232809Sjmallett/** 1867232809Sjmallett * cvmx_tra#_read_dat_hi 1868232809Sjmallett * 1869232809Sjmallett * TRA_READ_DAT_HI = Trace Buffer Read Data- upper 5 bits do not use if TRA_CTL[16]==0 1870232809Sjmallett * 1871232809Sjmallett * Description: 1872232809Sjmallett * 1873232809Sjmallett * Notes: 1874232809Sjmallett * This CSR is a memory of 1024 entries. Reads to this address do not increment the read pointer. The 1875232809Sjmallett * 5 bits read are the upper 5 bits of the TRA entry last read by the TRA_READ_DAT reg. 1876232809Sjmallett */ 1877232809Sjmallettunion cvmx_trax_read_dat_hi { 1878232809Sjmallett uint64_t u64; 1879232809Sjmallett struct cvmx_trax_read_dat_hi_s { 1880232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1881232809Sjmallett uint64_t reserved_5_63 : 59; 1882232809Sjmallett uint64_t data : 5; /**< Trace buffer data[68:64] for current entry */ 1883232809Sjmallett#else 1884232809Sjmallett uint64_t data : 5; 1885232809Sjmallett uint64_t reserved_5_63 : 59; 1886232809Sjmallett#endif 1887232809Sjmallett } s; 1888232809Sjmallett struct cvmx_trax_read_dat_hi_s cn61xx; 1889232809Sjmallett struct cvmx_trax_read_dat_hi_s cn63xx; 1890232809Sjmallett struct cvmx_trax_read_dat_hi_s cn66xx; 1891232809Sjmallett struct cvmx_trax_read_dat_hi_s cn68xx; 1892232809Sjmallett struct cvmx_trax_read_dat_hi_s cn68xxp1; 1893232809Sjmallett struct cvmx_trax_read_dat_hi_s cnf71xx; 1894232809Sjmallett}; 1895232809Sjmalletttypedef union cvmx_trax_read_dat_hi cvmx_trax_read_dat_hi_t; 1896232809Sjmallett 1897232809Sjmallett/** 1898232809Sjmallett * cvmx_tra#_trig0_adr_adr 1899232809Sjmallett * 1900232809Sjmallett * TRA_TRIG0_ADR_ADR = Trace Buffer Filter Address Address 1901232809Sjmallett * 1902232809Sjmallett * Description: 1903232809Sjmallett */ 1904232809Sjmallettunion cvmx_trax_trig0_adr_adr { 1905232809Sjmallett uint64_t u64; 1906232809Sjmallett struct cvmx_trax_trig0_adr_adr_s { 1907232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1908232809Sjmallett uint64_t reserved_38_63 : 26; 1909232809Sjmallett uint64_t adr : 38; /**< Unmasked Address 1910232809Sjmallett The combination of TRA_TRIG0_ADR_ADR and 1911232809Sjmallett TRA_TRIG0_ADR_MSK is a masked address to 1912232809Sjmallett enable tracing of only those commands whose 1913232809Sjmallett masked address matches */ 1914232809Sjmallett#else 1915232809Sjmallett uint64_t adr : 38; 1916232809Sjmallett uint64_t reserved_38_63 : 26; 1917232809Sjmallett#endif 1918232809Sjmallett } s; 1919232809Sjmallett struct cvmx_trax_trig0_adr_adr_cn31xx { 1920232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1921232809Sjmallett uint64_t reserved_36_63 : 28; 1922232809Sjmallett uint64_t adr : 36; /**< Unmasked Address 1923232809Sjmallett The combination of TRA(0..0)_TRIG0_ADR_ADR and 1924232809Sjmallett TRA(0..0)_TRIG0_ADR_MSK is a masked address to 1925232809Sjmallett enable tracing of only those commands whose 1926232809Sjmallett masked address matches */ 1927232809Sjmallett#else 1928232809Sjmallett uint64_t adr : 36; 1929232809Sjmallett uint64_t reserved_36_63 : 28; 1930232809Sjmallett#endif 1931232809Sjmallett } cn31xx; 1932232809Sjmallett struct cvmx_trax_trig0_adr_adr_cn31xx cn38xx; 1933232809Sjmallett struct cvmx_trax_trig0_adr_adr_cn31xx cn38xxp2; 1934232809Sjmallett struct cvmx_trax_trig0_adr_adr_cn31xx cn52xx; 1935232809Sjmallett struct cvmx_trax_trig0_adr_adr_cn31xx cn52xxp1; 1936232809Sjmallett struct cvmx_trax_trig0_adr_adr_cn31xx cn56xx; 1937232809Sjmallett struct cvmx_trax_trig0_adr_adr_cn31xx cn56xxp1; 1938232809Sjmallett struct cvmx_trax_trig0_adr_adr_cn31xx cn58xx; 1939232809Sjmallett struct cvmx_trax_trig0_adr_adr_cn31xx cn58xxp1; 1940232809Sjmallett struct cvmx_trax_trig0_adr_adr_s cn61xx; 1941232809Sjmallett struct cvmx_trax_trig0_adr_adr_s cn63xx; 1942232809Sjmallett struct cvmx_trax_trig0_adr_adr_s cn63xxp1; 1943232809Sjmallett struct cvmx_trax_trig0_adr_adr_s cn66xx; 1944232809Sjmallett struct cvmx_trax_trig0_adr_adr_s cn68xx; 1945232809Sjmallett struct cvmx_trax_trig0_adr_adr_s cn68xxp1; 1946232809Sjmallett struct cvmx_trax_trig0_adr_adr_s cnf71xx; 1947232809Sjmallett}; 1948232809Sjmalletttypedef union cvmx_trax_trig0_adr_adr cvmx_trax_trig0_adr_adr_t; 1949232809Sjmallett 1950232809Sjmallett/** 1951232809Sjmallett * cvmx_tra#_trig0_adr_msk 1952232809Sjmallett * 1953232809Sjmallett * TRA_TRIG0_ADR_MSK = Trace Buffer Filter Address Mask 1954232809Sjmallett * 1955232809Sjmallett * Description: 1956232809Sjmallett */ 1957232809Sjmallettunion cvmx_trax_trig0_adr_msk { 1958232809Sjmallett uint64_t u64; 1959232809Sjmallett struct cvmx_trax_trig0_adr_msk_s { 1960232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1961232809Sjmallett uint64_t reserved_38_63 : 26; 1962232809Sjmallett uint64_t adr : 38; /**< Address Mask 1963232809Sjmallett The combination of TRA_TRIG0_ADR_ADR and 1964232809Sjmallett TRA_TRIG0_ADR_MSK is a masked address to 1965232809Sjmallett enable tracing of only those commands whose 1966232809Sjmallett masked address matches. When a mask bit is not 1967232809Sjmallett set, the corresponding address bits are assumed 1968232809Sjmallett to match. Also, note that IOBDMAs do not have 1969232809Sjmallett proper addresses, so when TRA_TRIG0_CMD[IOBDMA] 1970232809Sjmallett is set, TRA_FILT_TRIG0_MSK must be zero to 1971232809Sjmallett guarantee that any IOBDMAs are recognized as 1972232809Sjmallett triggers. */ 1973232809Sjmallett#else 1974232809Sjmallett uint64_t adr : 38; 1975232809Sjmallett uint64_t reserved_38_63 : 26; 1976232809Sjmallett#endif 1977232809Sjmallett } s; 1978232809Sjmallett struct cvmx_trax_trig0_adr_msk_cn31xx { 1979232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1980232809Sjmallett uint64_t reserved_36_63 : 28; 1981232809Sjmallett uint64_t adr : 36; /**< Address Mask 1982232809Sjmallett The combination of TRA(0..0)_TRIG0_ADR_ADR and 1983232809Sjmallett TRA(0..0)_TRIG0_ADR_MSK is a masked address to 1984232809Sjmallett enable tracing of only those commands whose 1985232809Sjmallett masked address matches. When a mask bit is not 1986232809Sjmallett set, the corresponding address bits are assumed 1987232809Sjmallett to match. Also, note that IOBDMAs do not have 1988232809Sjmallett proper addresses, so when TRA(0..0)_TRIG0_CMD[IOBDMA] 1989232809Sjmallett is set, TRA(0..0)_FILT_TRIG0_MSK must be zero to 1990232809Sjmallett guarantee that any IOBDMAs are recognized as 1991232809Sjmallett triggers. */ 1992232809Sjmallett#else 1993232809Sjmallett uint64_t adr : 36; 1994232809Sjmallett uint64_t reserved_36_63 : 28; 1995232809Sjmallett#endif 1996232809Sjmallett } cn31xx; 1997232809Sjmallett struct cvmx_trax_trig0_adr_msk_cn31xx cn38xx; 1998232809Sjmallett struct cvmx_trax_trig0_adr_msk_cn31xx cn38xxp2; 1999232809Sjmallett struct cvmx_trax_trig0_adr_msk_cn31xx cn52xx; 2000232809Sjmallett struct cvmx_trax_trig0_adr_msk_cn31xx cn52xxp1; 2001232809Sjmallett struct cvmx_trax_trig0_adr_msk_cn31xx cn56xx; 2002232809Sjmallett struct cvmx_trax_trig0_adr_msk_cn31xx cn56xxp1; 2003232809Sjmallett struct cvmx_trax_trig0_adr_msk_cn31xx cn58xx; 2004232809Sjmallett struct cvmx_trax_trig0_adr_msk_cn31xx cn58xxp1; 2005232809Sjmallett struct cvmx_trax_trig0_adr_msk_s cn61xx; 2006232809Sjmallett struct cvmx_trax_trig0_adr_msk_s cn63xx; 2007232809Sjmallett struct cvmx_trax_trig0_adr_msk_s cn63xxp1; 2008232809Sjmallett struct cvmx_trax_trig0_adr_msk_s cn66xx; 2009232809Sjmallett struct cvmx_trax_trig0_adr_msk_s cn68xx; 2010232809Sjmallett struct cvmx_trax_trig0_adr_msk_s cn68xxp1; 2011232809Sjmallett struct cvmx_trax_trig0_adr_msk_s cnf71xx; 2012232809Sjmallett}; 2013232809Sjmalletttypedef union cvmx_trax_trig0_adr_msk cvmx_trax_trig0_adr_msk_t; 2014232809Sjmallett 2015232809Sjmallett/** 2016232809Sjmallett * cvmx_tra#_trig0_cmd 2017232809Sjmallett * 2018232809Sjmallett * TRA_TRIG0_CMD = Trace Buffer Filter Command Mask 2019232809Sjmallett * 2020232809Sjmallett * Description: 2021232809Sjmallett * 2022232809Sjmallett * Notes: 2023232809Sjmallett * Note that the trace buffer does not do proper IOBDMA address compares. Thus, if IOBDMA is set, then 2024232809Sjmallett * the address compare must be disabled (i.e. TRA_TRIG0_ADR_MSK set to zero) to guarantee that IOBDMAs 2025232809Sjmallett * are recognized as triggers. 2026232809Sjmallett */ 2027232809Sjmallettunion cvmx_trax_trig0_cmd { 2028232809Sjmallett uint64_t u64; 2029232809Sjmallett struct cvmx_trax_trig0_cmd_s { 2030232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2031232809Sjmallett uint64_t saa64 : 1; /**< Enable SAA64 tracing 2032232809Sjmallett 0=disable, 1=enable */ 2033232809Sjmallett uint64_t saa32 : 1; /**< Enable SAA32 tracing 2034232809Sjmallett 0=disable, 1=enable */ 2035232809Sjmallett uint64_t reserved_60_61 : 2; 2036232809Sjmallett uint64_t faa64 : 1; /**< Enable FAA64 tracing 2037232809Sjmallett 0=disable, 1=enable */ 2038232809Sjmallett uint64_t faa32 : 1; /**< Enable FAA32 tracing 2039232809Sjmallett 0=disable, 1=enable */ 2040232809Sjmallett uint64_t reserved_56_57 : 2; 2041232809Sjmallett uint64_t decr64 : 1; /**< Enable DECR64 tracing 2042232809Sjmallett 0=disable, 1=enable */ 2043232809Sjmallett uint64_t decr32 : 1; /**< Enable DECR32 tracing 2044232809Sjmallett 0=disable, 1=enable */ 2045232809Sjmallett uint64_t decr16 : 1; /**< Enable DECR16 tracing 2046232809Sjmallett 0=disable, 1=enable */ 2047232809Sjmallett uint64_t decr8 : 1; /**< Enable DECR8 tracing 2048232809Sjmallett 0=disable, 1=enable */ 2049232809Sjmallett uint64_t incr64 : 1; /**< Enable INCR64 tracing 2050232809Sjmallett 0=disable, 1=enable */ 2051232809Sjmallett uint64_t incr32 : 1; /**< Enable INCR32 tracing 2052232809Sjmallett 0=disable, 1=enable */ 2053232809Sjmallett uint64_t incr16 : 1; /**< Enable INCR16 tracing 2054232809Sjmallett 0=disable, 1=enable */ 2055232809Sjmallett uint64_t incr8 : 1; /**< Enable INCR8 tracing 2056232809Sjmallett 0=disable, 1=enable */ 2057232809Sjmallett uint64_t clr64 : 1; /**< Enable CLR64 tracing 2058232809Sjmallett 0=disable, 1=enable */ 2059232809Sjmallett uint64_t clr32 : 1; /**< Enable CLR32 tracing 2060232809Sjmallett 0=disable, 1=enable */ 2061232809Sjmallett uint64_t clr16 : 1; /**< Enable CLR16 tracing 2062232809Sjmallett 0=disable, 1=enable */ 2063232809Sjmallett uint64_t clr8 : 1; /**< Enable CLR8 tracing 2064232809Sjmallett 0=disable, 1=enable */ 2065232809Sjmallett uint64_t set64 : 1; /**< Enable SET64 tracing 2066232809Sjmallett 0=disable, 1=enable */ 2067232809Sjmallett uint64_t set32 : 1; /**< Enable SET32 tracing 2068232809Sjmallett 0=disable, 1=enable */ 2069232809Sjmallett uint64_t set16 : 1; /**< Enable SET16 tracing 2070232809Sjmallett 0=disable, 1=enable */ 2071232809Sjmallett uint64_t set8 : 1; /**< Enable SET8 tracing 2072232809Sjmallett 0=disable, 1=enable */ 2073232809Sjmallett uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 2074232809Sjmallett 0=disable, 1=enable */ 2075232809Sjmallett uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 2076232809Sjmallett 0=disable, 1=enable */ 2077232809Sjmallett uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 2078232809Sjmallett 0=disable, 1=enable */ 2079232809Sjmallett uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 2080232809Sjmallett 0=disable, 1=enable */ 2081232809Sjmallett uint64_t reserved_32_35 : 4; 2082232809Sjmallett uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 2083232809Sjmallett 0=disable, 1=enable */ 2084232809Sjmallett uint64_t wbl2 : 1; /**< Enable WBL2 tracing 2085232809Sjmallett 0=disable, 1=enable */ 2086232809Sjmallett uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 2087232809Sjmallett 0=disable, 1=enable */ 2088232809Sjmallett uint64_t invl2 : 1; /**< Enable INVL2 tracing 2089232809Sjmallett 0=disable, 1=enable */ 2090232809Sjmallett uint64_t reserved_27_27 : 1; 2091232809Sjmallett uint64_t stgl2i : 1; /**< Enable STGL2I tracing 2092232809Sjmallett 0=disable, 1=enable */ 2093232809Sjmallett uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 2094232809Sjmallett 0=disable, 1=enable */ 2095232809Sjmallett uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 2096232809Sjmallett 0=disable, 1=enable */ 2097232809Sjmallett uint64_t fas64 : 1; /**< Enable FAS64 tracing 2098232809Sjmallett 0=disable, 1=enable */ 2099232809Sjmallett uint64_t fas32 : 1; /**< Enable FAS32 tracing 2100232809Sjmallett 0=disable, 1=enable */ 2101232809Sjmallett uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 2102232809Sjmallett 0=disable, 1=enable */ 2103232809Sjmallett uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 2104232809Sjmallett 0=disable, 1=enable */ 2105232809Sjmallett uint64_t reserved_16_19 : 4; 2106232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2107232809Sjmallett 0=disable, 1=enable */ 2108232809Sjmallett uint64_t iobst : 1; /**< Enable IOBST tracing 2109232809Sjmallett 0=disable, 1=enable */ 2110232809Sjmallett uint64_t reserved_0_13 : 14; 2111232809Sjmallett#else 2112232809Sjmallett uint64_t reserved_0_13 : 14; 2113232809Sjmallett uint64_t iobst : 1; 2114232809Sjmallett uint64_t iobdma : 1; 2115232809Sjmallett uint64_t reserved_16_19 : 4; 2116232809Sjmallett uint64_t stfil1 : 1; 2117232809Sjmallett uint64_t sttil1 : 1; 2118232809Sjmallett uint64_t fas32 : 1; 2119232809Sjmallett uint64_t fas64 : 1; 2120232809Sjmallett uint64_t wbil2i : 1; 2121232809Sjmallett uint64_t ltgl2i : 1; 2122232809Sjmallett uint64_t stgl2i : 1; 2123232809Sjmallett uint64_t reserved_27_27 : 1; 2124232809Sjmallett uint64_t invl2 : 1; 2125232809Sjmallett uint64_t wbil2 : 1; 2126232809Sjmallett uint64_t wbl2 : 1; 2127232809Sjmallett uint64_t lckl2 : 1; 2128232809Sjmallett uint64_t reserved_32_35 : 4; 2129232809Sjmallett uint64_t iobst8 : 1; 2130232809Sjmallett uint64_t iobst16 : 1; 2131232809Sjmallett uint64_t iobst32 : 1; 2132232809Sjmallett uint64_t iobst64 : 1; 2133232809Sjmallett uint64_t set8 : 1; 2134232809Sjmallett uint64_t set16 : 1; 2135232809Sjmallett uint64_t set32 : 1; 2136232809Sjmallett uint64_t set64 : 1; 2137232809Sjmallett uint64_t clr8 : 1; 2138232809Sjmallett uint64_t clr16 : 1; 2139232809Sjmallett uint64_t clr32 : 1; 2140232809Sjmallett uint64_t clr64 : 1; 2141232809Sjmallett uint64_t incr8 : 1; 2142232809Sjmallett uint64_t incr16 : 1; 2143232809Sjmallett uint64_t incr32 : 1; 2144232809Sjmallett uint64_t incr64 : 1; 2145232809Sjmallett uint64_t decr8 : 1; 2146232809Sjmallett uint64_t decr16 : 1; 2147232809Sjmallett uint64_t decr32 : 1; 2148232809Sjmallett uint64_t decr64 : 1; 2149232809Sjmallett uint64_t reserved_56_57 : 2; 2150232809Sjmallett uint64_t faa32 : 1; 2151232809Sjmallett uint64_t faa64 : 1; 2152232809Sjmallett uint64_t reserved_60_61 : 2; 2153232809Sjmallett uint64_t saa32 : 1; 2154232809Sjmallett uint64_t saa64 : 1; 2155232809Sjmallett#endif 2156232809Sjmallett } s; 2157232809Sjmallett struct cvmx_trax_trig0_cmd_cn31xx { 2158232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2159232809Sjmallett uint64_t reserved_16_63 : 48; 2160232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2161232809Sjmallett 0=disable, 1=enable */ 2162232809Sjmallett uint64_t iobst : 1; /**< Enable IOBST tracing 2163232809Sjmallett 0=disable, 1=enable */ 2164232809Sjmallett uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 2165232809Sjmallett 0=disable, 1=enable */ 2166232809Sjmallett uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 2167232809Sjmallett 0=disable, 1=enable */ 2168232809Sjmallett uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 2169232809Sjmallett 0=disable, 1=enable */ 2170232809Sjmallett uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 2171232809Sjmallett 0=disable, 1=enable */ 2172232809Sjmallett uint64_t stt : 1; /**< Enable STT tracing 2173232809Sjmallett 0=disable, 1=enable */ 2174232809Sjmallett uint64_t stp : 1; /**< Enable STP tracing 2175232809Sjmallett 0=disable, 1=enable */ 2176232809Sjmallett uint64_t stc : 1; /**< Enable STC tracing 2177232809Sjmallett 0=disable, 1=enable */ 2178232809Sjmallett uint64_t stf : 1; /**< Enable STF tracing 2179232809Sjmallett 0=disable, 1=enable */ 2180232809Sjmallett uint64_t ldt : 1; /**< Enable LDT tracing 2181232809Sjmallett 0=disable, 1=enable */ 2182232809Sjmallett uint64_t ldi : 1; /**< Enable LDI tracing 2183232809Sjmallett 0=disable, 1=enable */ 2184232809Sjmallett uint64_t ldd : 1; /**< Enable LDD tracing 2185232809Sjmallett 0=disable, 1=enable */ 2186232809Sjmallett uint64_t psl1 : 1; /**< Enable PSL1 tracing 2187232809Sjmallett 0=disable, 1=enable */ 2188232809Sjmallett uint64_t pl2 : 1; /**< Enable PL2 tracing 2189232809Sjmallett 0=disable, 1=enable */ 2190232809Sjmallett uint64_t dwb : 1; /**< Enable DWB tracing 2191232809Sjmallett 0=disable, 1=enable */ 2192232809Sjmallett#else 2193232809Sjmallett uint64_t dwb : 1; 2194232809Sjmallett uint64_t pl2 : 1; 2195232809Sjmallett uint64_t psl1 : 1; 2196232809Sjmallett uint64_t ldd : 1; 2197232809Sjmallett uint64_t ldi : 1; 2198232809Sjmallett uint64_t ldt : 1; 2199232809Sjmallett uint64_t stf : 1; 2200232809Sjmallett uint64_t stc : 1; 2201232809Sjmallett uint64_t stp : 1; 2202232809Sjmallett uint64_t stt : 1; 2203232809Sjmallett uint64_t iobld8 : 1; 2204232809Sjmallett uint64_t iobld16 : 1; 2205232809Sjmallett uint64_t iobld32 : 1; 2206232809Sjmallett uint64_t iobld64 : 1; 2207232809Sjmallett uint64_t iobst : 1; 2208232809Sjmallett uint64_t iobdma : 1; 2209232809Sjmallett uint64_t reserved_16_63 : 48; 2210232809Sjmallett#endif 2211232809Sjmallett } cn31xx; 2212232809Sjmallett struct cvmx_trax_trig0_cmd_cn31xx cn38xx; 2213232809Sjmallett struct cvmx_trax_trig0_cmd_cn31xx cn38xxp2; 2214232809Sjmallett struct cvmx_trax_trig0_cmd_cn52xx { 2215232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2216232809Sjmallett uint64_t reserved_17_63 : 47; 2217232809Sjmallett uint64_t saa : 1; /**< Enable SAA tracing 2218232809Sjmallett 0=disable, 1=enable */ 2219232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2220232809Sjmallett 0=disable, 1=enable */ 2221232809Sjmallett uint64_t iobst : 1; /**< Enable IOBST tracing 2222232809Sjmallett 0=disable, 1=enable */ 2223232809Sjmallett uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 2224232809Sjmallett 0=disable, 1=enable */ 2225232809Sjmallett uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 2226232809Sjmallett 0=disable, 1=enable */ 2227232809Sjmallett uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 2228232809Sjmallett 0=disable, 1=enable */ 2229232809Sjmallett uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 2230232809Sjmallett 0=disable, 1=enable */ 2231232809Sjmallett uint64_t stt : 1; /**< Enable STT tracing 2232232809Sjmallett 0=disable, 1=enable */ 2233232809Sjmallett uint64_t stp : 1; /**< Enable STP tracing 2234232809Sjmallett 0=disable, 1=enable */ 2235232809Sjmallett uint64_t stc : 1; /**< Enable STC tracing 2236232809Sjmallett 0=disable, 1=enable */ 2237232809Sjmallett uint64_t stf : 1; /**< Enable STF tracing 2238232809Sjmallett 0=disable, 1=enable */ 2239232809Sjmallett uint64_t ldt : 1; /**< Enable LDT tracing 2240232809Sjmallett 0=disable, 1=enable */ 2241232809Sjmallett uint64_t ldi : 1; /**< Enable LDI tracing 2242232809Sjmallett 0=disable, 1=enable */ 2243232809Sjmallett uint64_t ldd : 1; /**< Enable LDD tracing 2244232809Sjmallett 0=disable, 1=enable */ 2245232809Sjmallett uint64_t psl1 : 1; /**< Enable PSL1 tracing 2246232809Sjmallett 0=disable, 1=enable */ 2247232809Sjmallett uint64_t pl2 : 1; /**< Enable PL2 tracing 2248232809Sjmallett 0=disable, 1=enable */ 2249232809Sjmallett uint64_t dwb : 1; /**< Enable DWB tracing 2250232809Sjmallett 0=disable, 1=enable */ 2251232809Sjmallett#else 2252232809Sjmallett uint64_t dwb : 1; 2253232809Sjmallett uint64_t pl2 : 1; 2254232809Sjmallett uint64_t psl1 : 1; 2255232809Sjmallett uint64_t ldd : 1; 2256232809Sjmallett uint64_t ldi : 1; 2257232809Sjmallett uint64_t ldt : 1; 2258232809Sjmallett uint64_t stf : 1; 2259232809Sjmallett uint64_t stc : 1; 2260232809Sjmallett uint64_t stp : 1; 2261232809Sjmallett uint64_t stt : 1; 2262232809Sjmallett uint64_t iobld8 : 1; 2263232809Sjmallett uint64_t iobld16 : 1; 2264232809Sjmallett uint64_t iobld32 : 1; 2265232809Sjmallett uint64_t iobld64 : 1; 2266232809Sjmallett uint64_t iobst : 1; 2267232809Sjmallett uint64_t iobdma : 1; 2268232809Sjmallett uint64_t saa : 1; 2269232809Sjmallett uint64_t reserved_17_63 : 47; 2270232809Sjmallett#endif 2271232809Sjmallett } cn52xx; 2272232809Sjmallett struct cvmx_trax_trig0_cmd_cn52xx cn52xxp1; 2273232809Sjmallett struct cvmx_trax_trig0_cmd_cn52xx cn56xx; 2274232809Sjmallett struct cvmx_trax_trig0_cmd_cn52xx cn56xxp1; 2275232809Sjmallett struct cvmx_trax_trig0_cmd_cn52xx cn58xx; 2276232809Sjmallett struct cvmx_trax_trig0_cmd_cn52xx cn58xxp1; 2277232809Sjmallett struct cvmx_trax_trig0_cmd_cn61xx { 2278232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2279232809Sjmallett uint64_t saa64 : 1; /**< Enable SAA64 tracing 2280232809Sjmallett 0=disable, 1=enable */ 2281232809Sjmallett uint64_t saa32 : 1; /**< Enable SAA32 tracing 2282232809Sjmallett 0=disable, 1=enable */ 2283232809Sjmallett uint64_t reserved_60_61 : 2; 2284232809Sjmallett uint64_t faa64 : 1; /**< Enable FAA64 tracing 2285232809Sjmallett 0=disable, 1=enable */ 2286232809Sjmallett uint64_t faa32 : 1; /**< Enable FAA32 tracing 2287232809Sjmallett 0=disable, 1=enable */ 2288232809Sjmallett uint64_t reserved_56_57 : 2; 2289232809Sjmallett uint64_t decr64 : 1; /**< Enable DECR64 tracing 2290232809Sjmallett 0=disable, 1=enable */ 2291232809Sjmallett uint64_t decr32 : 1; /**< Enable DECR32 tracing 2292232809Sjmallett 0=disable, 1=enable */ 2293232809Sjmallett uint64_t decr16 : 1; /**< Enable DECR16 tracing 2294232809Sjmallett 0=disable, 1=enable */ 2295232809Sjmallett uint64_t decr8 : 1; /**< Enable DECR8 tracing 2296232809Sjmallett 0=disable, 1=enable */ 2297232809Sjmallett uint64_t incr64 : 1; /**< Enable INCR64 tracing 2298232809Sjmallett 0=disable, 1=enable */ 2299232809Sjmallett uint64_t incr32 : 1; /**< Enable INCR32 tracing 2300232809Sjmallett 0=disable, 1=enable */ 2301232809Sjmallett uint64_t incr16 : 1; /**< Enable INCR16 tracing 2302232809Sjmallett 0=disable, 1=enable */ 2303232809Sjmallett uint64_t incr8 : 1; /**< Enable INCR8 tracing 2304232809Sjmallett 0=disable, 1=enable */ 2305232809Sjmallett uint64_t clr64 : 1; /**< Enable CLR64 tracing 2306232809Sjmallett 0=disable, 1=enable */ 2307232809Sjmallett uint64_t clr32 : 1; /**< Enable CLR32 tracing 2308232809Sjmallett 0=disable, 1=enable */ 2309232809Sjmallett uint64_t clr16 : 1; /**< Enable CLR16 tracing 2310232809Sjmallett 0=disable, 1=enable */ 2311232809Sjmallett uint64_t clr8 : 1; /**< Enable CLR8 tracing 2312232809Sjmallett 0=disable, 1=enable */ 2313232809Sjmallett uint64_t set64 : 1; /**< Enable SET64 tracing 2314232809Sjmallett 0=disable, 1=enable */ 2315232809Sjmallett uint64_t set32 : 1; /**< Enable SET32 tracing 2316232809Sjmallett 0=disable, 1=enable */ 2317232809Sjmallett uint64_t set16 : 1; /**< Enable SET16 tracing 2318232809Sjmallett 0=disable, 1=enable */ 2319232809Sjmallett uint64_t set8 : 1; /**< Enable SET8 tracing 2320232809Sjmallett 0=disable, 1=enable */ 2321232809Sjmallett uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 2322232809Sjmallett 0=disable, 1=enable */ 2323232809Sjmallett uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 2324232809Sjmallett 0=disable, 1=enable */ 2325232809Sjmallett uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 2326232809Sjmallett 0=disable, 1=enable */ 2327232809Sjmallett uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 2328232809Sjmallett 0=disable, 1=enable */ 2329232809Sjmallett uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 2330232809Sjmallett 0=disable, 1=enable */ 2331232809Sjmallett uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 2332232809Sjmallett 0=disable, 1=enable */ 2333232809Sjmallett uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 2334232809Sjmallett 0=disable, 1=enable */ 2335232809Sjmallett uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 2336232809Sjmallett 0=disable, 1=enable */ 2337232809Sjmallett uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 2338232809Sjmallett 0=disable, 1=enable */ 2339232809Sjmallett uint64_t wbl2 : 1; /**< Enable WBL2 tracing 2340232809Sjmallett 0=disable, 1=enable */ 2341232809Sjmallett uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 2342232809Sjmallett 0=disable, 1=enable */ 2343232809Sjmallett uint64_t invl2 : 1; /**< Enable INVL2 tracing 2344232809Sjmallett 0=disable, 1=enable */ 2345232809Sjmallett uint64_t reserved_27_27 : 1; 2346232809Sjmallett uint64_t stgl2i : 1; /**< Enable STGL2I tracing 2347232809Sjmallett 0=disable, 1=enable */ 2348232809Sjmallett uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 2349232809Sjmallett 0=disable, 1=enable */ 2350232809Sjmallett uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 2351232809Sjmallett 0=disable, 1=enable */ 2352232809Sjmallett uint64_t fas64 : 1; /**< Enable FAS64 tracing 2353232809Sjmallett 0=disable, 1=enable */ 2354232809Sjmallett uint64_t fas32 : 1; /**< Enable FAS32 tracing 2355232809Sjmallett 0=disable, 1=enable */ 2356232809Sjmallett uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 2357232809Sjmallett 0=disable, 1=enable */ 2358232809Sjmallett uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 2359232809Sjmallett 0=disable, 1=enable */ 2360232809Sjmallett uint64_t stc : 1; /**< Enable STC tracing 2361232809Sjmallett 0=disable, 1=enable */ 2362232809Sjmallett uint64_t stp : 1; /**< Enable STP tracing 2363232809Sjmallett 0=disable, 1=enable */ 2364232809Sjmallett uint64_t stt : 1; /**< Enable STT tracing 2365232809Sjmallett 0=disable, 1=enable */ 2366232809Sjmallett uint64_t stf : 1; /**< Enable STF tracing 2367232809Sjmallett 0=disable, 1=enable */ 2368232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2369232809Sjmallett 0=disable, 1=enable */ 2370232809Sjmallett uint64_t reserved_10_14 : 5; 2371232809Sjmallett uint64_t psl1 : 1; /**< Enable PSL1 tracing 2372232809Sjmallett 0=disable, 1=enable */ 2373232809Sjmallett uint64_t ldd : 1; /**< Enable LDD tracing 2374232809Sjmallett 0=disable, 1=enable */ 2375232809Sjmallett uint64_t reserved_6_7 : 2; 2376232809Sjmallett uint64_t dwb : 1; /**< Enable DWB tracing 2377232809Sjmallett 0=disable, 1=enable */ 2378232809Sjmallett uint64_t rpl2 : 1; /**< Enable RPL2 tracing 2379232809Sjmallett 0=disable, 1=enable */ 2380232809Sjmallett uint64_t pl2 : 1; /**< Enable PL2 tracing 2381232809Sjmallett 0=disable, 1=enable */ 2382232809Sjmallett uint64_t ldi : 1; /**< Enable LDI tracing 2383232809Sjmallett 0=disable, 1=enable */ 2384232809Sjmallett uint64_t ldt : 1; /**< Enable LDT tracing 2385232809Sjmallett 0=disable, 1=enable */ 2386232809Sjmallett uint64_t nop : 1; /**< Enable NOP tracing 2387232809Sjmallett 0=disable, 1=enable */ 2388232809Sjmallett#else 2389232809Sjmallett uint64_t nop : 1; 2390232809Sjmallett uint64_t ldt : 1; 2391232809Sjmallett uint64_t ldi : 1; 2392232809Sjmallett uint64_t pl2 : 1; 2393232809Sjmallett uint64_t rpl2 : 1; 2394232809Sjmallett uint64_t dwb : 1; 2395232809Sjmallett uint64_t reserved_6_7 : 2; 2396232809Sjmallett uint64_t ldd : 1; 2397232809Sjmallett uint64_t psl1 : 1; 2398232809Sjmallett uint64_t reserved_10_14 : 5; 2399232809Sjmallett uint64_t iobdma : 1; 2400232809Sjmallett uint64_t stf : 1; 2401232809Sjmallett uint64_t stt : 1; 2402232809Sjmallett uint64_t stp : 1; 2403232809Sjmallett uint64_t stc : 1; 2404232809Sjmallett uint64_t stfil1 : 1; 2405232809Sjmallett uint64_t sttil1 : 1; 2406232809Sjmallett uint64_t fas32 : 1; 2407232809Sjmallett uint64_t fas64 : 1; 2408232809Sjmallett uint64_t wbil2i : 1; 2409232809Sjmallett uint64_t ltgl2i : 1; 2410232809Sjmallett uint64_t stgl2i : 1; 2411232809Sjmallett uint64_t reserved_27_27 : 1; 2412232809Sjmallett uint64_t invl2 : 1; 2413232809Sjmallett uint64_t wbil2 : 1; 2414232809Sjmallett uint64_t wbl2 : 1; 2415232809Sjmallett uint64_t lckl2 : 1; 2416232809Sjmallett uint64_t iobld8 : 1; 2417232809Sjmallett uint64_t iobld16 : 1; 2418232809Sjmallett uint64_t iobld32 : 1; 2419232809Sjmallett uint64_t iobld64 : 1; 2420232809Sjmallett uint64_t iobst8 : 1; 2421232809Sjmallett uint64_t iobst16 : 1; 2422232809Sjmallett uint64_t iobst32 : 1; 2423232809Sjmallett uint64_t iobst64 : 1; 2424232809Sjmallett uint64_t set8 : 1; 2425232809Sjmallett uint64_t set16 : 1; 2426232809Sjmallett uint64_t set32 : 1; 2427232809Sjmallett uint64_t set64 : 1; 2428232809Sjmallett uint64_t clr8 : 1; 2429232809Sjmallett uint64_t clr16 : 1; 2430232809Sjmallett uint64_t clr32 : 1; 2431232809Sjmallett uint64_t clr64 : 1; 2432232809Sjmallett uint64_t incr8 : 1; 2433232809Sjmallett uint64_t incr16 : 1; 2434232809Sjmallett uint64_t incr32 : 1; 2435232809Sjmallett uint64_t incr64 : 1; 2436232809Sjmallett uint64_t decr8 : 1; 2437232809Sjmallett uint64_t decr16 : 1; 2438232809Sjmallett uint64_t decr32 : 1; 2439232809Sjmallett uint64_t decr64 : 1; 2440232809Sjmallett uint64_t reserved_56_57 : 2; 2441232809Sjmallett uint64_t faa32 : 1; 2442232809Sjmallett uint64_t faa64 : 1; 2443232809Sjmallett uint64_t reserved_60_61 : 2; 2444232809Sjmallett uint64_t saa32 : 1; 2445232809Sjmallett uint64_t saa64 : 1; 2446232809Sjmallett#endif 2447232809Sjmallett } cn61xx; 2448232809Sjmallett struct cvmx_trax_trig0_cmd_cn61xx cn63xx; 2449232809Sjmallett struct cvmx_trax_trig0_cmd_cn61xx cn63xxp1; 2450232809Sjmallett struct cvmx_trax_trig0_cmd_cn61xx cn66xx; 2451232809Sjmallett struct cvmx_trax_trig0_cmd_cn61xx cn68xx; 2452232809Sjmallett struct cvmx_trax_trig0_cmd_cn61xx cn68xxp1; 2453232809Sjmallett struct cvmx_trax_trig0_cmd_cn61xx cnf71xx; 2454232809Sjmallett}; 2455232809Sjmalletttypedef union cvmx_trax_trig0_cmd cvmx_trax_trig0_cmd_t; 2456232809Sjmallett 2457232809Sjmallett/** 2458232809Sjmallett * cvmx_tra#_trig0_did 2459232809Sjmallett * 2460232809Sjmallett * TRA_TRIG0_DID = Trace Buffer Filter DestinationId Mask 2461232809Sjmallett * 2462232809Sjmallett * Description: 2463232809Sjmallett */ 2464232809Sjmallettunion cvmx_trax_trig0_did { 2465232809Sjmallett uint64_t u64; 2466232809Sjmallett struct cvmx_trax_trig0_did_s { 2467232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2468232809Sjmallett uint64_t reserved_13_63 : 51; 2469232809Sjmallett uint64_t pow : 1; /**< Enable triggering on requests to POW 2470232809Sjmallett (get work, add work, status/memory/index 2471232809Sjmallett loads, NULLRd loads, CSR's) */ 2472232809Sjmallett uint64_t reserved_9_11 : 3; 2473232809Sjmallett uint64_t rng : 1; /**< Enable triggering on requests to RNG 2474232809Sjmallett (loads/IOBDMA's are legal) */ 2475232809Sjmallett uint64_t zip : 1; /**< Enable triggering on requests to ZIP 2476232809Sjmallett (doorbell stores are legal) */ 2477232809Sjmallett uint64_t dfa : 1; /**< Enable triggering on requests to DFA 2478232809Sjmallett (CSR's and operations are legal) */ 2479232809Sjmallett uint64_t fpa : 1; /**< Enable triggering on requests to FPA 2480232809Sjmallett (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 2481232809Sjmallett uint64_t key : 1; /**< Enable triggering on requests to KEY memory 2482232809Sjmallett (loads/IOBDMA's/stores are legal) */ 2483232809Sjmallett uint64_t reserved_3_3 : 1; 2484232809Sjmallett uint64_t illegal3 : 2; /**< Illegal destinations */ 2485232809Sjmallett uint64_t mio : 1; /**< Enable triggering on MIO accesses 2486232809Sjmallett (CIU and GPIO CSR's, boot bus accesses) */ 2487232809Sjmallett#else 2488232809Sjmallett uint64_t mio : 1; 2489232809Sjmallett uint64_t illegal3 : 2; 2490232809Sjmallett uint64_t reserved_3_3 : 1; 2491232809Sjmallett uint64_t key : 1; 2492232809Sjmallett uint64_t fpa : 1; 2493232809Sjmallett uint64_t dfa : 1; 2494232809Sjmallett uint64_t zip : 1; 2495232809Sjmallett uint64_t rng : 1; 2496232809Sjmallett uint64_t reserved_9_11 : 3; 2497232809Sjmallett uint64_t pow : 1; 2498232809Sjmallett uint64_t reserved_13_63 : 51; 2499232809Sjmallett#endif 2500232809Sjmallett } s; 2501232809Sjmallett struct cvmx_trax_trig0_did_cn31xx { 2502232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2503232809Sjmallett uint64_t reserved_32_63 : 32; 2504232809Sjmallett uint64_t illegal : 19; /**< Illegal destinations */ 2505232809Sjmallett uint64_t pow : 1; /**< Enable triggering on requests to POW 2506232809Sjmallett (get work, add work, status/memory/index 2507232809Sjmallett loads, NULLRd loads, CSR's) */ 2508232809Sjmallett uint64_t illegal2 : 3; /**< Illegal destinations */ 2509232809Sjmallett uint64_t rng : 1; /**< Enable triggering on requests to RNG 2510232809Sjmallett (loads/IOBDMA's are legal) */ 2511232809Sjmallett uint64_t zip : 1; /**< Enable triggering on requests to ZIP 2512232809Sjmallett (doorbell stores are legal) */ 2513232809Sjmallett uint64_t dfa : 1; /**< Enable triggering on requests to DFA 2514232809Sjmallett (CSR's and operations are legal) */ 2515232809Sjmallett uint64_t fpa : 1; /**< Enable triggering on requests to FPA 2516232809Sjmallett (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 2517232809Sjmallett uint64_t key : 1; /**< Enable triggering on requests to KEY memory 2518232809Sjmallett (loads/IOBDMA's/stores are legal) */ 2519232809Sjmallett uint64_t pci : 1; /**< Enable triggering on requests to PCI and RSL-type 2520232809Sjmallett CSR's (RSL CSR's, PCI bus operations, PCI 2521232809Sjmallett CSR's) */ 2522232809Sjmallett uint64_t illegal3 : 2; /**< Illegal destinations */ 2523232809Sjmallett uint64_t mio : 1; /**< Enable triggering on CIU and GPIO CSR's */ 2524232809Sjmallett#else 2525232809Sjmallett uint64_t mio : 1; 2526232809Sjmallett uint64_t illegal3 : 2; 2527232809Sjmallett uint64_t pci : 1; 2528232809Sjmallett uint64_t key : 1; 2529232809Sjmallett uint64_t fpa : 1; 2530232809Sjmallett uint64_t dfa : 1; 2531232809Sjmallett uint64_t zip : 1; 2532232809Sjmallett uint64_t rng : 1; 2533232809Sjmallett uint64_t illegal2 : 3; 2534232809Sjmallett uint64_t pow : 1; 2535232809Sjmallett uint64_t illegal : 19; 2536232809Sjmallett uint64_t reserved_32_63 : 32; 2537232809Sjmallett#endif 2538232809Sjmallett } cn31xx; 2539232809Sjmallett struct cvmx_trax_trig0_did_cn31xx cn38xx; 2540232809Sjmallett struct cvmx_trax_trig0_did_cn31xx cn38xxp2; 2541232809Sjmallett struct cvmx_trax_trig0_did_cn31xx cn52xx; 2542232809Sjmallett struct cvmx_trax_trig0_did_cn31xx cn52xxp1; 2543232809Sjmallett struct cvmx_trax_trig0_did_cn31xx cn56xx; 2544232809Sjmallett struct cvmx_trax_trig0_did_cn31xx cn56xxp1; 2545232809Sjmallett struct cvmx_trax_trig0_did_cn31xx cn58xx; 2546232809Sjmallett struct cvmx_trax_trig0_did_cn31xx cn58xxp1; 2547232809Sjmallett struct cvmx_trax_trig0_did_cn61xx { 2548232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2549232809Sjmallett uint64_t reserved_32_63 : 32; 2550232809Sjmallett uint64_t illegal5 : 1; /**< Illegal destinations */ 2551232809Sjmallett uint64_t fau : 1; /**< Enable triggering on FAU accesses */ 2552232809Sjmallett uint64_t illegal4 : 2; /**< Illegal destinations */ 2553232809Sjmallett uint64_t dpi : 1; /**< Enable triggering on DPI accesses 2554232809Sjmallett (DPI NCB CSRs) */ 2555232809Sjmallett uint64_t illegal : 12; /**< Illegal destinations */ 2556232809Sjmallett uint64_t rad : 1; /**< Enable triggering on RAD accesses 2557232809Sjmallett (doorbells) */ 2558232809Sjmallett uint64_t usb0 : 1; /**< Enable triggering on USB0 accesses 2559232809Sjmallett (UAHC0 EHCI and OHCI NCB CSRs) */ 2560232809Sjmallett uint64_t pow : 1; /**< Enable triggering on requests to POW 2561232809Sjmallett (get work, add work, status/memory/index 2562232809Sjmallett loads, NULLRd loads, CSR's) */ 2563232809Sjmallett uint64_t illegal2 : 1; /**< Illegal destination */ 2564232809Sjmallett uint64_t pko : 1; /**< Enable triggering on PKO accesses 2565232809Sjmallett (doorbells) */ 2566232809Sjmallett uint64_t ipd : 1; /**< Enable triggering on IPD CSR accesses 2567232809Sjmallett (IPD CSRs) */ 2568232809Sjmallett uint64_t rng : 1; /**< Enable triggering on requests to RNG 2569232809Sjmallett (loads/IOBDMA's are legal) */ 2570232809Sjmallett uint64_t zip : 1; /**< Enable triggering on requests to ZIP 2571232809Sjmallett (doorbell stores are legal) */ 2572232809Sjmallett uint64_t dfa : 1; /**< Enable triggering on requests to DFA 2573232809Sjmallett (CSR's and operations are legal) */ 2574232809Sjmallett uint64_t fpa : 1; /**< Enable triggering on requests to FPA 2575232809Sjmallett (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 2576232809Sjmallett uint64_t key : 1; /**< Enable triggering on requests to KEY memory 2577232809Sjmallett (loads/IOBDMA's/stores are legal) */ 2578232809Sjmallett uint64_t sli : 1; /**< Enable triggering on requests to SLI and RSL-type 2579232809Sjmallett CSR's (RSL CSR's, PCI/sRIO bus operations, SLI 2580232809Sjmallett CSR's) */ 2581232809Sjmallett uint64_t illegal3 : 2; /**< Illegal destinations */ 2582232809Sjmallett uint64_t mio : 1; /**< Enable triggering on MIO accesses 2583232809Sjmallett (CIU and GPIO CSR's, boot bus accesses) */ 2584232809Sjmallett#else 2585232809Sjmallett uint64_t mio : 1; 2586232809Sjmallett uint64_t illegal3 : 2; 2587232809Sjmallett uint64_t sli : 1; 2588232809Sjmallett uint64_t key : 1; 2589232809Sjmallett uint64_t fpa : 1; 2590232809Sjmallett uint64_t dfa : 1; 2591232809Sjmallett uint64_t zip : 1; 2592232809Sjmallett uint64_t rng : 1; 2593232809Sjmallett uint64_t ipd : 1; 2594232809Sjmallett uint64_t pko : 1; 2595232809Sjmallett uint64_t illegal2 : 1; 2596232809Sjmallett uint64_t pow : 1; 2597232809Sjmallett uint64_t usb0 : 1; 2598232809Sjmallett uint64_t rad : 1; 2599232809Sjmallett uint64_t illegal : 12; 2600232809Sjmallett uint64_t dpi : 1; 2601232809Sjmallett uint64_t illegal4 : 2; 2602232809Sjmallett uint64_t fau : 1; 2603232809Sjmallett uint64_t illegal5 : 1; 2604232809Sjmallett uint64_t reserved_32_63 : 32; 2605232809Sjmallett#endif 2606232809Sjmallett } cn61xx; 2607232809Sjmallett struct cvmx_trax_trig0_did_cn61xx cn63xx; 2608232809Sjmallett struct cvmx_trax_trig0_did_cn61xx cn63xxp1; 2609232809Sjmallett struct cvmx_trax_trig0_did_cn61xx cn66xx; 2610232809Sjmallett struct cvmx_trax_trig0_did_cn61xx cn68xx; 2611232809Sjmallett struct cvmx_trax_trig0_did_cn61xx cn68xxp1; 2612232809Sjmallett struct cvmx_trax_trig0_did_cn61xx cnf71xx; 2613232809Sjmallett}; 2614232809Sjmalletttypedef union cvmx_trax_trig0_did cvmx_trax_trig0_did_t; 2615232809Sjmallett 2616232809Sjmallett/** 2617232809Sjmallett * cvmx_tra#_trig0_sid 2618232809Sjmallett * 2619232809Sjmallett * TRA_TRIG0_SID = Trace Buffer Filter SourceId Mask 2620232809Sjmallett * 2621232809Sjmallett * Description: 2622232809Sjmallett */ 2623232809Sjmallettunion cvmx_trax_trig0_sid { 2624232809Sjmallett uint64_t u64; 2625232809Sjmallett struct cvmx_trax_trig0_sid_s { 2626232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2627232809Sjmallett uint64_t reserved_20_63 : 44; 2628232809Sjmallett uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2629232809Sjmallett uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2630232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 2631232809Sjmallett uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2632232809Sjmallett uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2633232809Sjmallett uint64_t pp : 16; /**< Enable triggering from PP[N] with matching SourceID 2634232809Sjmallett 0=disable, 1=enable per bit N where 0<=N<=3 */ 2635232809Sjmallett#else 2636232809Sjmallett uint64_t pp : 16; 2637232809Sjmallett uint64_t pki : 1; 2638232809Sjmallett uint64_t pko : 1; 2639232809Sjmallett uint64_t iobreq : 1; 2640232809Sjmallett uint64_t dwb : 1; 2641232809Sjmallett uint64_t reserved_20_63 : 44; 2642232809Sjmallett#endif 2643232809Sjmallett } s; 2644232809Sjmallett struct cvmx_trax_trig0_sid_s cn31xx; 2645232809Sjmallett struct cvmx_trax_trig0_sid_s cn38xx; 2646232809Sjmallett struct cvmx_trax_trig0_sid_s cn38xxp2; 2647232809Sjmallett struct cvmx_trax_trig0_sid_s cn52xx; 2648232809Sjmallett struct cvmx_trax_trig0_sid_s cn52xxp1; 2649232809Sjmallett struct cvmx_trax_trig0_sid_s cn56xx; 2650232809Sjmallett struct cvmx_trax_trig0_sid_s cn56xxp1; 2651232809Sjmallett struct cvmx_trax_trig0_sid_s cn58xx; 2652232809Sjmallett struct cvmx_trax_trig0_sid_s cn58xxp1; 2653232809Sjmallett struct cvmx_trax_trig0_sid_cn61xx { 2654232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2655232809Sjmallett uint64_t reserved_20_63 : 44; 2656232809Sjmallett uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2657232809Sjmallett uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2658232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 2659232809Sjmallett uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2660232809Sjmallett uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2661232809Sjmallett uint64_t reserved_4_15 : 12; 2662232809Sjmallett uint64_t pp : 4; /**< Enable triggering from PP[N] with matching SourceID 2663232809Sjmallett 0=disable, 1=enable per bit N where 0<=N<=3 */ 2664232809Sjmallett#else 2665232809Sjmallett uint64_t pp : 4; 2666232809Sjmallett uint64_t reserved_4_15 : 12; 2667232809Sjmallett uint64_t pki : 1; 2668232809Sjmallett uint64_t pko : 1; 2669232809Sjmallett uint64_t iobreq : 1; 2670232809Sjmallett uint64_t dwb : 1; 2671232809Sjmallett uint64_t reserved_20_63 : 44; 2672232809Sjmallett#endif 2673232809Sjmallett } cn61xx; 2674232809Sjmallett struct cvmx_trax_trig0_sid_cn63xx { 2675232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2676232809Sjmallett uint64_t reserved_20_63 : 44; 2677232809Sjmallett uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2678232809Sjmallett uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2679232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 2680232809Sjmallett uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2681232809Sjmallett uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2682232809Sjmallett uint64_t reserved_8_15 : 8; 2683232809Sjmallett uint64_t pp : 8; /**< Enable triggering from PP[N] with matching SourceID 2684232809Sjmallett 0=disable, 1=enableper bit N where 0<=N<=15 */ 2685232809Sjmallett#else 2686232809Sjmallett uint64_t pp : 8; 2687232809Sjmallett uint64_t reserved_8_15 : 8; 2688232809Sjmallett uint64_t pki : 1; 2689232809Sjmallett uint64_t pko : 1; 2690232809Sjmallett uint64_t iobreq : 1; 2691232809Sjmallett uint64_t dwb : 1; 2692232809Sjmallett uint64_t reserved_20_63 : 44; 2693232809Sjmallett#endif 2694232809Sjmallett } cn63xx; 2695232809Sjmallett struct cvmx_trax_trig0_sid_cn63xxp1 { 2696232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2697232809Sjmallett uint64_t reserved_20_63 : 44; 2698232809Sjmallett uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2699232809Sjmallett uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2700232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 2701232809Sjmallett uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2702232809Sjmallett uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2703232809Sjmallett uint64_t reserved_6_15 : 10; 2704232809Sjmallett uint64_t pp : 6; /**< Enable triggering from PP[N] with matching SourceID 2705232809Sjmallett 0=disable, 1=enable per bit N where 0<=N<=5 */ 2706232809Sjmallett#else 2707232809Sjmallett uint64_t pp : 6; 2708232809Sjmallett uint64_t reserved_6_15 : 10; 2709232809Sjmallett uint64_t pki : 1; 2710232809Sjmallett uint64_t pko : 1; 2711232809Sjmallett uint64_t iobreq : 1; 2712232809Sjmallett uint64_t dwb : 1; 2713232809Sjmallett uint64_t reserved_20_63 : 44; 2714232809Sjmallett#endif 2715232809Sjmallett } cn63xxp1; 2716232809Sjmallett struct cvmx_trax_trig0_sid_cn66xx { 2717232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2718232809Sjmallett uint64_t reserved_20_63 : 44; 2719232809Sjmallett uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2720232809Sjmallett uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2721232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 2722232809Sjmallett uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2723232809Sjmallett uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2724232809Sjmallett uint64_t reserved_10_15 : 6; 2725232809Sjmallett uint64_t pp : 10; /**< Enable triggering from PP[N] with matching SourceID 2726232809Sjmallett 0=disable, 1=enableper bit N where 0<=N<=15 */ 2727232809Sjmallett#else 2728232809Sjmallett uint64_t pp : 10; 2729232809Sjmallett uint64_t reserved_10_15 : 6; 2730232809Sjmallett uint64_t pki : 1; 2731232809Sjmallett uint64_t pko : 1; 2732232809Sjmallett uint64_t iobreq : 1; 2733232809Sjmallett uint64_t dwb : 1; 2734232809Sjmallett uint64_t reserved_20_63 : 44; 2735232809Sjmallett#endif 2736232809Sjmallett } cn66xx; 2737232809Sjmallett struct cvmx_trax_trig0_sid_cn63xx cn68xx; 2738232809Sjmallett struct cvmx_trax_trig0_sid_cn63xx cn68xxp1; 2739232809Sjmallett struct cvmx_trax_trig0_sid_cn61xx cnf71xx; 2740232809Sjmallett}; 2741232809Sjmalletttypedef union cvmx_trax_trig0_sid cvmx_trax_trig0_sid_t; 2742232809Sjmallett 2743232809Sjmallett/** 2744232809Sjmallett * cvmx_tra#_trig1_adr_adr 2745232809Sjmallett * 2746232809Sjmallett * TRA_TRIG1_ADR_ADR = Trace Buffer Filter Address Address 2747232809Sjmallett * 2748232809Sjmallett * Description: 2749232809Sjmallett */ 2750232809Sjmallettunion cvmx_trax_trig1_adr_adr { 2751232809Sjmallett uint64_t u64; 2752232809Sjmallett struct cvmx_trax_trig1_adr_adr_s { 2753232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2754232809Sjmallett uint64_t reserved_38_63 : 26; 2755232809Sjmallett uint64_t adr : 38; /**< Unmasked Address 2756232809Sjmallett The combination of TRA_TRIG1_ADR_ADR and 2757232809Sjmallett TRA_TRIG1_ADR_MSK is a masked address to 2758232809Sjmallett enable tracing of only those commands whose 2759232809Sjmallett masked address matches */ 2760232809Sjmallett#else 2761232809Sjmallett uint64_t adr : 38; 2762232809Sjmallett uint64_t reserved_38_63 : 26; 2763232809Sjmallett#endif 2764232809Sjmallett } s; 2765232809Sjmallett struct cvmx_trax_trig1_adr_adr_cn31xx { 2766232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2767232809Sjmallett uint64_t reserved_36_63 : 28; 2768232809Sjmallett uint64_t adr : 36; /**< Unmasked Address 2769232809Sjmallett The combination of TRA(0..0)_TRIG1_ADR_ADR and 2770232809Sjmallett TRA(0..0)_TRIG1_ADR_MSK is a masked address to 2771232809Sjmallett enable tracing of only those commands whose 2772232809Sjmallett masked address matches */ 2773232809Sjmallett#else 2774232809Sjmallett uint64_t adr : 36; 2775232809Sjmallett uint64_t reserved_36_63 : 28; 2776232809Sjmallett#endif 2777232809Sjmallett } cn31xx; 2778232809Sjmallett struct cvmx_trax_trig1_adr_adr_cn31xx cn38xx; 2779232809Sjmallett struct cvmx_trax_trig1_adr_adr_cn31xx cn38xxp2; 2780232809Sjmallett struct cvmx_trax_trig1_adr_adr_cn31xx cn52xx; 2781232809Sjmallett struct cvmx_trax_trig1_adr_adr_cn31xx cn52xxp1; 2782232809Sjmallett struct cvmx_trax_trig1_adr_adr_cn31xx cn56xx; 2783232809Sjmallett struct cvmx_trax_trig1_adr_adr_cn31xx cn56xxp1; 2784232809Sjmallett struct cvmx_trax_trig1_adr_adr_cn31xx cn58xx; 2785232809Sjmallett struct cvmx_trax_trig1_adr_adr_cn31xx cn58xxp1; 2786232809Sjmallett struct cvmx_trax_trig1_adr_adr_s cn61xx; 2787232809Sjmallett struct cvmx_trax_trig1_adr_adr_s cn63xx; 2788232809Sjmallett struct cvmx_trax_trig1_adr_adr_s cn63xxp1; 2789232809Sjmallett struct cvmx_trax_trig1_adr_adr_s cn66xx; 2790232809Sjmallett struct cvmx_trax_trig1_adr_adr_s cn68xx; 2791232809Sjmallett struct cvmx_trax_trig1_adr_adr_s cn68xxp1; 2792232809Sjmallett struct cvmx_trax_trig1_adr_adr_s cnf71xx; 2793232809Sjmallett}; 2794232809Sjmalletttypedef union cvmx_trax_trig1_adr_adr cvmx_trax_trig1_adr_adr_t; 2795232809Sjmallett 2796232809Sjmallett/** 2797232809Sjmallett * cvmx_tra#_trig1_adr_msk 2798232809Sjmallett * 2799232809Sjmallett * TRA_TRIG1_ADR_MSK = Trace Buffer Filter Address Mask 2800232809Sjmallett * 2801232809Sjmallett * Description: 2802232809Sjmallett */ 2803232809Sjmallettunion cvmx_trax_trig1_adr_msk { 2804232809Sjmallett uint64_t u64; 2805232809Sjmallett struct cvmx_trax_trig1_adr_msk_s { 2806232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2807232809Sjmallett uint64_t reserved_38_63 : 26; 2808232809Sjmallett uint64_t adr : 38; /**< Address Mask 2809232809Sjmallett The combination of TRA_TRIG1_ADR_ADR and 2810232809Sjmallett TRA_TRIG1_ADR_MSK is a masked address to 2811232809Sjmallett enable tracing of only those commands whose 2812232809Sjmallett masked address matches. When a mask bit is not 2813232809Sjmallett set, the corresponding address bits are assumed 2814232809Sjmallett to match. Also, note that IOBDMAs do not have 2815232809Sjmallett proper addresses, so when TRA_TRIG1_CMD[IOBDMA] 2816232809Sjmallett is set, TRA_FILT_TRIG1_MSK must be zero to 2817232809Sjmallett guarantee that any IOBDMAs are recognized as 2818232809Sjmallett triggers. */ 2819232809Sjmallett#else 2820232809Sjmallett uint64_t adr : 38; 2821232809Sjmallett uint64_t reserved_38_63 : 26; 2822232809Sjmallett#endif 2823232809Sjmallett } s; 2824232809Sjmallett struct cvmx_trax_trig1_adr_msk_cn31xx { 2825232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2826232809Sjmallett uint64_t reserved_36_63 : 28; 2827232809Sjmallett uint64_t adr : 36; /**< Address Mask 2828232809Sjmallett The combination of TRA(0..0)_TRIG1_ADR_ADR and 2829232809Sjmallett TRA(0..0)_TRIG1_ADR_MSK is a masked address to 2830232809Sjmallett enable tracing of only those commands whose 2831232809Sjmallett masked address matches. When a mask bit is not 2832232809Sjmallett set, the corresponding address bits are assumed 2833232809Sjmallett to match. Also, note that IOBDMAs do not have 2834232809Sjmallett proper addresses, so when TRA(0..0)_TRIG1_CMD[IOBDMA] 2835232809Sjmallett is set, TRA(0..0)_FILT_TRIG1_MSK must be zero to 2836232809Sjmallett guarantee that any IOBDMAs are recognized as 2837232809Sjmallett triggers. */ 2838232809Sjmallett#else 2839232809Sjmallett uint64_t adr : 36; 2840232809Sjmallett uint64_t reserved_36_63 : 28; 2841232809Sjmallett#endif 2842232809Sjmallett } cn31xx; 2843232809Sjmallett struct cvmx_trax_trig1_adr_msk_cn31xx cn38xx; 2844232809Sjmallett struct cvmx_trax_trig1_adr_msk_cn31xx cn38xxp2; 2845232809Sjmallett struct cvmx_trax_trig1_adr_msk_cn31xx cn52xx; 2846232809Sjmallett struct cvmx_trax_trig1_adr_msk_cn31xx cn52xxp1; 2847232809Sjmallett struct cvmx_trax_trig1_adr_msk_cn31xx cn56xx; 2848232809Sjmallett struct cvmx_trax_trig1_adr_msk_cn31xx cn56xxp1; 2849232809Sjmallett struct cvmx_trax_trig1_adr_msk_cn31xx cn58xx; 2850232809Sjmallett struct cvmx_trax_trig1_adr_msk_cn31xx cn58xxp1; 2851232809Sjmallett struct cvmx_trax_trig1_adr_msk_s cn61xx; 2852232809Sjmallett struct cvmx_trax_trig1_adr_msk_s cn63xx; 2853232809Sjmallett struct cvmx_trax_trig1_adr_msk_s cn63xxp1; 2854232809Sjmallett struct cvmx_trax_trig1_adr_msk_s cn66xx; 2855232809Sjmallett struct cvmx_trax_trig1_adr_msk_s cn68xx; 2856232809Sjmallett struct cvmx_trax_trig1_adr_msk_s cn68xxp1; 2857232809Sjmallett struct cvmx_trax_trig1_adr_msk_s cnf71xx; 2858232809Sjmallett}; 2859232809Sjmalletttypedef union cvmx_trax_trig1_adr_msk cvmx_trax_trig1_adr_msk_t; 2860232809Sjmallett 2861232809Sjmallett/** 2862232809Sjmallett * cvmx_tra#_trig1_cmd 2863232809Sjmallett * 2864232809Sjmallett * TRA_TRIG1_CMD = Trace Buffer Filter Command Mask 2865232809Sjmallett * 2866232809Sjmallett * Description: 2867232809Sjmallett * 2868232809Sjmallett * Notes: 2869232809Sjmallett * Note that the trace buffer does not do proper IOBDMA address compares. Thus, if IOBDMA is set, then 2870232809Sjmallett * the address compare must be disabled (i.e. TRA_TRIG1_ADR_MSK set to zero) to guarantee that IOBDMAs 2871232809Sjmallett * are recognized as triggers. 2872232809Sjmallett */ 2873232809Sjmallettunion cvmx_trax_trig1_cmd { 2874232809Sjmallett uint64_t u64; 2875232809Sjmallett struct cvmx_trax_trig1_cmd_s { 2876232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2877232809Sjmallett uint64_t saa64 : 1; /**< Enable SAA64 tracing 2878232809Sjmallett 0=disable, 1=enable */ 2879232809Sjmallett uint64_t saa32 : 1; /**< Enable SAA32 tracing 2880232809Sjmallett 0=disable, 1=enable */ 2881232809Sjmallett uint64_t reserved_60_61 : 2; 2882232809Sjmallett uint64_t faa64 : 1; /**< Enable FAA64 tracing 2883232809Sjmallett 0=disable, 1=enable */ 2884232809Sjmallett uint64_t faa32 : 1; /**< Enable FAA32 tracing 2885232809Sjmallett 0=disable, 1=enable */ 2886232809Sjmallett uint64_t reserved_56_57 : 2; 2887232809Sjmallett uint64_t decr64 : 1; /**< Enable DECR64 tracing 2888232809Sjmallett 0=disable, 1=enable */ 2889232809Sjmallett uint64_t decr32 : 1; /**< Enable DECR32 tracing 2890232809Sjmallett 0=disable, 1=enable */ 2891232809Sjmallett uint64_t decr16 : 1; /**< Enable DECR16 tracing 2892232809Sjmallett 0=disable, 1=enable */ 2893232809Sjmallett uint64_t decr8 : 1; /**< Enable DECR8 tracing 2894232809Sjmallett 0=disable, 1=enable */ 2895232809Sjmallett uint64_t incr64 : 1; /**< Enable INCR64 tracing 2896232809Sjmallett 0=disable, 1=enable */ 2897232809Sjmallett uint64_t incr32 : 1; /**< Enable INCR32 tracing 2898232809Sjmallett 0=disable, 1=enable */ 2899232809Sjmallett uint64_t incr16 : 1; /**< Enable INCR16 tracing 2900232809Sjmallett 0=disable, 1=enable */ 2901232809Sjmallett uint64_t incr8 : 1; /**< Enable INCR8 tracing 2902232809Sjmallett 0=disable, 1=enable */ 2903232809Sjmallett uint64_t clr64 : 1; /**< Enable CLR64 tracing 2904232809Sjmallett 0=disable, 1=enable */ 2905232809Sjmallett uint64_t clr32 : 1; /**< Enable CLR32 tracing 2906232809Sjmallett 0=disable, 1=enable */ 2907232809Sjmallett uint64_t clr16 : 1; /**< Enable CLR16 tracing 2908232809Sjmallett 0=disable, 1=enable */ 2909232809Sjmallett uint64_t clr8 : 1; /**< Enable CLR8 tracing 2910232809Sjmallett 0=disable, 1=enable */ 2911232809Sjmallett uint64_t set64 : 1; /**< Enable SET64 tracing 2912232809Sjmallett 0=disable, 1=enable */ 2913232809Sjmallett uint64_t set32 : 1; /**< Enable SET32 tracing 2914232809Sjmallett 0=disable, 1=enable */ 2915232809Sjmallett uint64_t set16 : 1; /**< Enable SET16 tracing 2916232809Sjmallett 0=disable, 1=enable */ 2917232809Sjmallett uint64_t set8 : 1; /**< Enable SET8 tracing 2918232809Sjmallett 0=disable, 1=enable */ 2919232809Sjmallett uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 2920232809Sjmallett 0=disable, 1=enable */ 2921232809Sjmallett uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 2922232809Sjmallett 0=disable, 1=enable */ 2923232809Sjmallett uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 2924232809Sjmallett 0=disable, 1=enable */ 2925232809Sjmallett uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 2926232809Sjmallett 0=disable, 1=enable */ 2927232809Sjmallett uint64_t reserved_32_35 : 4; 2928232809Sjmallett uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 2929232809Sjmallett 0=disable, 1=enable */ 2930232809Sjmallett uint64_t wbl2 : 1; /**< Enable WBL2 tracing 2931232809Sjmallett 0=disable, 1=enable */ 2932232809Sjmallett uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 2933232809Sjmallett 0=disable, 1=enable */ 2934232809Sjmallett uint64_t invl2 : 1; /**< Enable INVL2 tracing 2935232809Sjmallett 0=disable, 1=enable */ 2936232809Sjmallett uint64_t reserved_27_27 : 1; 2937232809Sjmallett uint64_t stgl2i : 1; /**< Enable STGL2I tracing 2938232809Sjmallett 0=disable, 1=enable */ 2939232809Sjmallett uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 2940232809Sjmallett 0=disable, 1=enable */ 2941232809Sjmallett uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 2942232809Sjmallett 0=disable, 1=enable */ 2943232809Sjmallett uint64_t fas64 : 1; /**< Enable FAS64 tracing 2944232809Sjmallett 0=disable, 1=enable */ 2945232809Sjmallett uint64_t fas32 : 1; /**< Enable FAS32 tracing 2946232809Sjmallett 0=disable, 1=enable */ 2947232809Sjmallett uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 2948232809Sjmallett 0=disable, 1=enable */ 2949232809Sjmallett uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 2950232809Sjmallett 0=disable, 1=enable */ 2951232809Sjmallett uint64_t reserved_16_19 : 4; 2952232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2953232809Sjmallett 0=disable, 1=enable */ 2954232809Sjmallett uint64_t iobst : 1; /**< Enable IOBST tracing 2955232809Sjmallett 0=disable, 1=enable */ 2956232809Sjmallett uint64_t reserved_0_13 : 14; 2957232809Sjmallett#else 2958232809Sjmallett uint64_t reserved_0_13 : 14; 2959232809Sjmallett uint64_t iobst : 1; 2960232809Sjmallett uint64_t iobdma : 1; 2961232809Sjmallett uint64_t reserved_16_19 : 4; 2962232809Sjmallett uint64_t stfil1 : 1; 2963232809Sjmallett uint64_t sttil1 : 1; 2964232809Sjmallett uint64_t fas32 : 1; 2965232809Sjmallett uint64_t fas64 : 1; 2966232809Sjmallett uint64_t wbil2i : 1; 2967232809Sjmallett uint64_t ltgl2i : 1; 2968232809Sjmallett uint64_t stgl2i : 1; 2969232809Sjmallett uint64_t reserved_27_27 : 1; 2970232809Sjmallett uint64_t invl2 : 1; 2971232809Sjmallett uint64_t wbil2 : 1; 2972232809Sjmallett uint64_t wbl2 : 1; 2973232809Sjmallett uint64_t lckl2 : 1; 2974232809Sjmallett uint64_t reserved_32_35 : 4; 2975232809Sjmallett uint64_t iobst8 : 1; 2976232809Sjmallett uint64_t iobst16 : 1; 2977232809Sjmallett uint64_t iobst32 : 1; 2978232809Sjmallett uint64_t iobst64 : 1; 2979232809Sjmallett uint64_t set8 : 1; 2980232809Sjmallett uint64_t set16 : 1; 2981232809Sjmallett uint64_t set32 : 1; 2982232809Sjmallett uint64_t set64 : 1; 2983232809Sjmallett uint64_t clr8 : 1; 2984232809Sjmallett uint64_t clr16 : 1; 2985232809Sjmallett uint64_t clr32 : 1; 2986232809Sjmallett uint64_t clr64 : 1; 2987232809Sjmallett uint64_t incr8 : 1; 2988232809Sjmallett uint64_t incr16 : 1; 2989232809Sjmallett uint64_t incr32 : 1; 2990232809Sjmallett uint64_t incr64 : 1; 2991232809Sjmallett uint64_t decr8 : 1; 2992232809Sjmallett uint64_t decr16 : 1; 2993232809Sjmallett uint64_t decr32 : 1; 2994232809Sjmallett uint64_t decr64 : 1; 2995232809Sjmallett uint64_t reserved_56_57 : 2; 2996232809Sjmallett uint64_t faa32 : 1; 2997232809Sjmallett uint64_t faa64 : 1; 2998232809Sjmallett uint64_t reserved_60_61 : 2; 2999232809Sjmallett uint64_t saa32 : 1; 3000232809Sjmallett uint64_t saa64 : 1; 3001232809Sjmallett#endif 3002232809Sjmallett } s; 3003232809Sjmallett struct cvmx_trax_trig1_cmd_cn31xx { 3004232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3005232809Sjmallett uint64_t reserved_16_63 : 48; 3006232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 3007232809Sjmallett 0=disable, 1=enable */ 3008232809Sjmallett uint64_t iobst : 1; /**< Enable IOBST tracing 3009232809Sjmallett 0=disable, 1=enable */ 3010232809Sjmallett uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 3011232809Sjmallett 0=disable, 1=enable */ 3012232809Sjmallett uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 3013232809Sjmallett 0=disable, 1=enable */ 3014232809Sjmallett uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 3015232809Sjmallett 0=disable, 1=enable */ 3016232809Sjmallett uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 3017232809Sjmallett 0=disable, 1=enable */ 3018232809Sjmallett uint64_t stt : 1; /**< Enable STT tracing 3019232809Sjmallett 0=disable, 1=enable */ 3020232809Sjmallett uint64_t stp : 1; /**< Enable STP tracing 3021232809Sjmallett 0=disable, 1=enable */ 3022232809Sjmallett uint64_t stc : 1; /**< Enable STC tracing 3023232809Sjmallett 0=disable, 1=enable */ 3024232809Sjmallett uint64_t stf : 1; /**< Enable STF tracing 3025232809Sjmallett 0=disable, 1=enable */ 3026232809Sjmallett uint64_t ldt : 1; /**< Enable LDT tracing 3027232809Sjmallett 0=disable, 1=enable */ 3028232809Sjmallett uint64_t ldi : 1; /**< Enable LDI tracing 3029232809Sjmallett 0=disable, 1=enable */ 3030232809Sjmallett uint64_t ldd : 1; /**< Enable LDD tracing 3031232809Sjmallett 0=disable, 1=enable */ 3032232809Sjmallett uint64_t psl1 : 1; /**< Enable PSL1 tracing 3033232809Sjmallett 0=disable, 1=enable */ 3034232809Sjmallett uint64_t pl2 : 1; /**< Enable PL2 tracing 3035232809Sjmallett 0=disable, 1=enable */ 3036232809Sjmallett uint64_t dwb : 1; /**< Enable DWB tracing 3037232809Sjmallett 0=disable, 1=enable */ 3038232809Sjmallett#else 3039232809Sjmallett uint64_t dwb : 1; 3040232809Sjmallett uint64_t pl2 : 1; 3041232809Sjmallett uint64_t psl1 : 1; 3042232809Sjmallett uint64_t ldd : 1; 3043232809Sjmallett uint64_t ldi : 1; 3044232809Sjmallett uint64_t ldt : 1; 3045232809Sjmallett uint64_t stf : 1; 3046232809Sjmallett uint64_t stc : 1; 3047232809Sjmallett uint64_t stp : 1; 3048232809Sjmallett uint64_t stt : 1; 3049232809Sjmallett uint64_t iobld8 : 1; 3050232809Sjmallett uint64_t iobld16 : 1; 3051232809Sjmallett uint64_t iobld32 : 1; 3052232809Sjmallett uint64_t iobld64 : 1; 3053232809Sjmallett uint64_t iobst : 1; 3054232809Sjmallett uint64_t iobdma : 1; 3055232809Sjmallett uint64_t reserved_16_63 : 48; 3056232809Sjmallett#endif 3057232809Sjmallett } cn31xx; 3058232809Sjmallett struct cvmx_trax_trig1_cmd_cn31xx cn38xx; 3059232809Sjmallett struct cvmx_trax_trig1_cmd_cn31xx cn38xxp2; 3060232809Sjmallett struct cvmx_trax_trig1_cmd_cn52xx { 3061232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3062232809Sjmallett uint64_t reserved_17_63 : 47; 3063232809Sjmallett uint64_t saa : 1; /**< Enable SAA tracing 3064232809Sjmallett 0=disable, 1=enable */ 3065232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 3066232809Sjmallett 0=disable, 1=enable */ 3067232809Sjmallett uint64_t iobst : 1; /**< Enable IOBST tracing 3068232809Sjmallett 0=disable, 1=enable */ 3069232809Sjmallett uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 3070232809Sjmallett 0=disable, 1=enable */ 3071232809Sjmallett uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 3072232809Sjmallett 0=disable, 1=enable */ 3073232809Sjmallett uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 3074232809Sjmallett 0=disable, 1=enable */ 3075232809Sjmallett uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 3076232809Sjmallett 0=disable, 1=enable */ 3077232809Sjmallett uint64_t stt : 1; /**< Enable STT tracing 3078232809Sjmallett 0=disable, 1=enable */ 3079232809Sjmallett uint64_t stp : 1; /**< Enable STP tracing 3080232809Sjmallett 0=disable, 1=enable */ 3081232809Sjmallett uint64_t stc : 1; /**< Enable STC tracing 3082232809Sjmallett 0=disable, 1=enable */ 3083232809Sjmallett uint64_t stf : 1; /**< Enable STF tracing 3084232809Sjmallett 0=disable, 1=enable */ 3085232809Sjmallett uint64_t ldt : 1; /**< Enable LDT tracing 3086232809Sjmallett 0=disable, 1=enable */ 3087232809Sjmallett uint64_t ldi : 1; /**< Enable LDI tracing 3088232809Sjmallett 0=disable, 1=enable */ 3089232809Sjmallett uint64_t ldd : 1; /**< Enable LDD tracing 3090232809Sjmallett 0=disable, 1=enable */ 3091232809Sjmallett uint64_t psl1 : 1; /**< Enable PSL1 tracing 3092232809Sjmallett 0=disable, 1=enable */ 3093232809Sjmallett uint64_t pl2 : 1; /**< Enable PL2 tracing 3094232809Sjmallett 0=disable, 1=enable */ 3095232809Sjmallett uint64_t dwb : 1; /**< Enable DWB tracing 3096232809Sjmallett 0=disable, 1=enable */ 3097232809Sjmallett#else 3098232809Sjmallett uint64_t dwb : 1; 3099232809Sjmallett uint64_t pl2 : 1; 3100232809Sjmallett uint64_t psl1 : 1; 3101232809Sjmallett uint64_t ldd : 1; 3102232809Sjmallett uint64_t ldi : 1; 3103232809Sjmallett uint64_t ldt : 1; 3104232809Sjmallett uint64_t stf : 1; 3105232809Sjmallett uint64_t stc : 1; 3106232809Sjmallett uint64_t stp : 1; 3107232809Sjmallett uint64_t stt : 1; 3108232809Sjmallett uint64_t iobld8 : 1; 3109232809Sjmallett uint64_t iobld16 : 1; 3110232809Sjmallett uint64_t iobld32 : 1; 3111232809Sjmallett uint64_t iobld64 : 1; 3112232809Sjmallett uint64_t iobst : 1; 3113232809Sjmallett uint64_t iobdma : 1; 3114232809Sjmallett uint64_t saa : 1; 3115232809Sjmallett uint64_t reserved_17_63 : 47; 3116232809Sjmallett#endif 3117232809Sjmallett } cn52xx; 3118232809Sjmallett struct cvmx_trax_trig1_cmd_cn52xx cn52xxp1; 3119232809Sjmallett struct cvmx_trax_trig1_cmd_cn52xx cn56xx; 3120232809Sjmallett struct cvmx_trax_trig1_cmd_cn52xx cn56xxp1; 3121232809Sjmallett struct cvmx_trax_trig1_cmd_cn52xx cn58xx; 3122232809Sjmallett struct cvmx_trax_trig1_cmd_cn52xx cn58xxp1; 3123232809Sjmallett struct cvmx_trax_trig1_cmd_cn61xx { 3124232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3125232809Sjmallett uint64_t saa64 : 1; /**< Enable SAA64 tracing 3126232809Sjmallett 0=disable, 1=enable */ 3127232809Sjmallett uint64_t saa32 : 1; /**< Enable SAA32 tracing 3128232809Sjmallett 0=disable, 1=enable */ 3129232809Sjmallett uint64_t reserved_60_61 : 2; 3130232809Sjmallett uint64_t faa64 : 1; /**< Enable FAA64 tracing 3131232809Sjmallett 0=disable, 1=enable */ 3132232809Sjmallett uint64_t faa32 : 1; /**< Enable FAA32 tracing 3133232809Sjmallett 0=disable, 1=enable */ 3134232809Sjmallett uint64_t reserved_56_57 : 2; 3135232809Sjmallett uint64_t decr64 : 1; /**< Enable DECR64 tracing 3136232809Sjmallett 0=disable, 1=enable */ 3137232809Sjmallett uint64_t decr32 : 1; /**< Enable DECR32 tracing 3138232809Sjmallett 0=disable, 1=enable */ 3139232809Sjmallett uint64_t decr16 : 1; /**< Enable DECR16 tracing 3140232809Sjmallett 0=disable, 1=enable */ 3141232809Sjmallett uint64_t decr8 : 1; /**< Enable DECR8 tracing 3142232809Sjmallett 0=disable, 1=enable */ 3143232809Sjmallett uint64_t incr64 : 1; /**< Enable INCR64 tracing 3144232809Sjmallett 0=disable, 1=enable */ 3145232809Sjmallett uint64_t incr32 : 1; /**< Enable INCR32 tracing 3146232809Sjmallett 0=disable, 1=enable */ 3147232809Sjmallett uint64_t incr16 : 1; /**< Enable INCR16 tracing 3148232809Sjmallett 0=disable, 1=enable */ 3149232809Sjmallett uint64_t incr8 : 1; /**< Enable INCR8 tracing 3150232809Sjmallett 0=disable, 1=enable */ 3151232809Sjmallett uint64_t clr64 : 1; /**< Enable CLR64 tracing 3152232809Sjmallett 0=disable, 1=enable */ 3153232809Sjmallett uint64_t clr32 : 1; /**< Enable CLR32 tracing 3154232809Sjmallett 0=disable, 1=enable */ 3155232809Sjmallett uint64_t clr16 : 1; /**< Enable CLR16 tracing 3156232809Sjmallett 0=disable, 1=enable */ 3157232809Sjmallett uint64_t clr8 : 1; /**< Enable CLR8 tracing 3158232809Sjmallett 0=disable, 1=enable */ 3159232809Sjmallett uint64_t set64 : 1; /**< Enable SET64 tracing 3160232809Sjmallett 0=disable, 1=enable */ 3161232809Sjmallett uint64_t set32 : 1; /**< Enable SET32 tracing 3162232809Sjmallett 0=disable, 1=enable */ 3163232809Sjmallett uint64_t set16 : 1; /**< Enable SET16 tracing 3164232809Sjmallett 0=disable, 1=enable */ 3165232809Sjmallett uint64_t set8 : 1; /**< Enable SET8 tracing 3166232809Sjmallett 0=disable, 1=enable */ 3167232809Sjmallett uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 3168232809Sjmallett 0=disable, 1=enable */ 3169232809Sjmallett uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 3170232809Sjmallett 0=disable, 1=enable */ 3171232809Sjmallett uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 3172232809Sjmallett 0=disable, 1=enable */ 3173232809Sjmallett uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 3174232809Sjmallett 0=disable, 1=enable */ 3175232809Sjmallett uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 3176232809Sjmallett 0=disable, 1=enable */ 3177232809Sjmallett uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 3178232809Sjmallett 0=disable, 1=enable */ 3179232809Sjmallett uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 3180232809Sjmallett 0=disable, 1=enable */ 3181232809Sjmallett uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 3182232809Sjmallett 0=disable, 1=enable */ 3183232809Sjmallett uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 3184232809Sjmallett 0=disable, 1=enable */ 3185232809Sjmallett uint64_t wbl2 : 1; /**< Enable WBL2 tracing 3186232809Sjmallett 0=disable, 1=enable */ 3187232809Sjmallett uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 3188232809Sjmallett 0=disable, 1=enable */ 3189232809Sjmallett uint64_t invl2 : 1; /**< Enable INVL2 tracing 3190232809Sjmallett 0=disable, 1=enable */ 3191232809Sjmallett uint64_t reserved_27_27 : 1; 3192232809Sjmallett uint64_t stgl2i : 1; /**< Enable STGL2I tracing 3193232809Sjmallett 0=disable, 1=enable */ 3194232809Sjmallett uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 3195232809Sjmallett 0=disable, 1=enable */ 3196232809Sjmallett uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 3197232809Sjmallett 0=disable, 1=enable */ 3198232809Sjmallett uint64_t fas64 : 1; /**< Enable FAS64 tracing 3199232809Sjmallett 0=disable, 1=enable */ 3200232809Sjmallett uint64_t fas32 : 1; /**< Enable FAS32 tracing 3201232809Sjmallett 0=disable, 1=enable */ 3202232809Sjmallett uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 3203232809Sjmallett 0=disable, 1=enable */ 3204232809Sjmallett uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 3205232809Sjmallett 0=disable, 1=enable */ 3206232809Sjmallett uint64_t stc : 1; /**< Enable STC tracing 3207232809Sjmallett 0=disable, 1=enable */ 3208232809Sjmallett uint64_t stp : 1; /**< Enable STP tracing 3209232809Sjmallett 0=disable, 1=enable */ 3210232809Sjmallett uint64_t stt : 1; /**< Enable STT tracing 3211232809Sjmallett 0=disable, 1=enable */ 3212232809Sjmallett uint64_t stf : 1; /**< Enable STF tracing 3213232809Sjmallett 0=disable, 1=enable */ 3214232809Sjmallett uint64_t iobdma : 1; /**< Enable IOBDMA tracing 3215232809Sjmallett 0=disable, 1=enable */ 3216232809Sjmallett uint64_t reserved_10_14 : 5; 3217232809Sjmallett uint64_t psl1 : 1; /**< Enable PSL1 tracing 3218232809Sjmallett 0=disable, 1=enable */ 3219232809Sjmallett uint64_t ldd : 1; /**< Enable LDD tracing 3220232809Sjmallett 0=disable, 1=enable */ 3221232809Sjmallett uint64_t reserved_6_7 : 2; 3222232809Sjmallett uint64_t dwb : 1; /**< Enable DWB tracing 3223232809Sjmallett 0=disable, 1=enable */ 3224232809Sjmallett uint64_t rpl2 : 1; /**< Enable RPL2 tracing 3225232809Sjmallett 0=disable, 1=enable */ 3226232809Sjmallett uint64_t pl2 : 1; /**< Enable PL2 tracing 3227232809Sjmallett 0=disable, 1=enable */ 3228232809Sjmallett uint64_t ldi : 1; /**< Enable LDI tracing 3229232809Sjmallett 0=disable, 1=enable */ 3230232809Sjmallett uint64_t ldt : 1; /**< Enable LDT tracing 3231232809Sjmallett 0=disable, 1=enable */ 3232232809Sjmallett uint64_t nop : 1; /**< Enable NOP tracing 3233232809Sjmallett 0=disable, 1=enable */ 3234232809Sjmallett#else 3235232809Sjmallett uint64_t nop : 1; 3236232809Sjmallett uint64_t ldt : 1; 3237232809Sjmallett uint64_t ldi : 1; 3238232809Sjmallett uint64_t pl2 : 1; 3239232809Sjmallett uint64_t rpl2 : 1; 3240232809Sjmallett uint64_t dwb : 1; 3241232809Sjmallett uint64_t reserved_6_7 : 2; 3242232809Sjmallett uint64_t ldd : 1; 3243232809Sjmallett uint64_t psl1 : 1; 3244232809Sjmallett uint64_t reserved_10_14 : 5; 3245232809Sjmallett uint64_t iobdma : 1; 3246232809Sjmallett uint64_t stf : 1; 3247232809Sjmallett uint64_t stt : 1; 3248232809Sjmallett uint64_t stp : 1; 3249232809Sjmallett uint64_t stc : 1; 3250232809Sjmallett uint64_t stfil1 : 1; 3251232809Sjmallett uint64_t sttil1 : 1; 3252232809Sjmallett uint64_t fas32 : 1; 3253232809Sjmallett uint64_t fas64 : 1; 3254232809Sjmallett uint64_t wbil2i : 1; 3255232809Sjmallett uint64_t ltgl2i : 1; 3256232809Sjmallett uint64_t stgl2i : 1; 3257232809Sjmallett uint64_t reserved_27_27 : 1; 3258232809Sjmallett uint64_t invl2 : 1; 3259232809Sjmallett uint64_t wbil2 : 1; 3260232809Sjmallett uint64_t wbl2 : 1; 3261232809Sjmallett uint64_t lckl2 : 1; 3262232809Sjmallett uint64_t iobld8 : 1; 3263232809Sjmallett uint64_t iobld16 : 1; 3264232809Sjmallett uint64_t iobld32 : 1; 3265232809Sjmallett uint64_t iobld64 : 1; 3266232809Sjmallett uint64_t iobst8 : 1; 3267232809Sjmallett uint64_t iobst16 : 1; 3268232809Sjmallett uint64_t iobst32 : 1; 3269232809Sjmallett uint64_t iobst64 : 1; 3270232809Sjmallett uint64_t set8 : 1; 3271232809Sjmallett uint64_t set16 : 1; 3272232809Sjmallett uint64_t set32 : 1; 3273232809Sjmallett uint64_t set64 : 1; 3274232809Sjmallett uint64_t clr8 : 1; 3275232809Sjmallett uint64_t clr16 : 1; 3276232809Sjmallett uint64_t clr32 : 1; 3277232809Sjmallett uint64_t clr64 : 1; 3278232809Sjmallett uint64_t incr8 : 1; 3279232809Sjmallett uint64_t incr16 : 1; 3280232809Sjmallett uint64_t incr32 : 1; 3281232809Sjmallett uint64_t incr64 : 1; 3282232809Sjmallett uint64_t decr8 : 1; 3283232809Sjmallett uint64_t decr16 : 1; 3284232809Sjmallett uint64_t decr32 : 1; 3285232809Sjmallett uint64_t decr64 : 1; 3286232809Sjmallett uint64_t reserved_56_57 : 2; 3287232809Sjmallett uint64_t faa32 : 1; 3288232809Sjmallett uint64_t faa64 : 1; 3289232809Sjmallett uint64_t reserved_60_61 : 2; 3290232809Sjmallett uint64_t saa32 : 1; 3291232809Sjmallett uint64_t saa64 : 1; 3292232809Sjmallett#endif 3293232809Sjmallett } cn61xx; 3294232809Sjmallett struct cvmx_trax_trig1_cmd_cn61xx cn63xx; 3295232809Sjmallett struct cvmx_trax_trig1_cmd_cn61xx cn63xxp1; 3296232809Sjmallett struct cvmx_trax_trig1_cmd_cn61xx cn66xx; 3297232809Sjmallett struct cvmx_trax_trig1_cmd_cn61xx cn68xx; 3298232809Sjmallett struct cvmx_trax_trig1_cmd_cn61xx cn68xxp1; 3299232809Sjmallett struct cvmx_trax_trig1_cmd_cn61xx cnf71xx; 3300232809Sjmallett}; 3301232809Sjmalletttypedef union cvmx_trax_trig1_cmd cvmx_trax_trig1_cmd_t; 3302232809Sjmallett 3303232809Sjmallett/** 3304232809Sjmallett * cvmx_tra#_trig1_did 3305232809Sjmallett * 3306232809Sjmallett * TRA_TRIG1_DID = Trace Buffer Filter DestinationId Mask 3307232809Sjmallett * 3308232809Sjmallett * Description: 3309232809Sjmallett */ 3310232809Sjmallettunion cvmx_trax_trig1_did { 3311232809Sjmallett uint64_t u64; 3312232809Sjmallett struct cvmx_trax_trig1_did_s { 3313232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3314232809Sjmallett uint64_t reserved_13_63 : 51; 3315232809Sjmallett uint64_t pow : 1; /**< Enable triggering on requests to POW 3316232809Sjmallett (get work, add work, status/memory/index 3317232809Sjmallett loads, NULLRd loads, CSR's) */ 3318232809Sjmallett uint64_t reserved_9_11 : 3; 3319232809Sjmallett uint64_t rng : 1; /**< Enable triggering on requests to RNG 3320232809Sjmallett (loads/IOBDMA's are legal) */ 3321232809Sjmallett uint64_t zip : 1; /**< Enable triggering on requests to ZIP 3322232809Sjmallett (doorbell stores are legal) */ 3323232809Sjmallett uint64_t dfa : 1; /**< Enable triggering on requests to DFA 3324232809Sjmallett (CSR's and operations are legal) */ 3325232809Sjmallett uint64_t fpa : 1; /**< Enable triggering on requests to FPA 3326232809Sjmallett (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 3327232809Sjmallett uint64_t key : 1; /**< Enable triggering on requests to KEY memory 3328232809Sjmallett (loads/IOBDMA's/stores are legal) */ 3329232809Sjmallett uint64_t reserved_3_3 : 1; 3330232809Sjmallett uint64_t illegal3 : 2; /**< Illegal destinations */ 3331232809Sjmallett uint64_t mio : 1; /**< Enable triggering on MIO accesses 3332232809Sjmallett (CIU and GPIO CSR's, boot bus accesses) */ 3333232809Sjmallett#else 3334232809Sjmallett uint64_t mio : 1; 3335232809Sjmallett uint64_t illegal3 : 2; 3336232809Sjmallett uint64_t reserved_3_3 : 1; 3337232809Sjmallett uint64_t key : 1; 3338232809Sjmallett uint64_t fpa : 1; 3339232809Sjmallett uint64_t dfa : 1; 3340232809Sjmallett uint64_t zip : 1; 3341232809Sjmallett uint64_t rng : 1; 3342232809Sjmallett uint64_t reserved_9_11 : 3; 3343232809Sjmallett uint64_t pow : 1; 3344232809Sjmallett uint64_t reserved_13_63 : 51; 3345232809Sjmallett#endif 3346232809Sjmallett } s; 3347232809Sjmallett struct cvmx_trax_trig1_did_cn31xx { 3348232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3349232809Sjmallett uint64_t reserved_32_63 : 32; 3350232809Sjmallett uint64_t illegal : 19; /**< Illegal destinations */ 3351232809Sjmallett uint64_t pow : 1; /**< Enable triggering on requests to POW 3352232809Sjmallett (get work, add work, status/memory/index 3353232809Sjmallett loads, NULLRd loads, CSR's) */ 3354232809Sjmallett uint64_t illegal2 : 3; /**< Illegal destinations */ 3355232809Sjmallett uint64_t rng : 1; /**< Enable triggering on requests to RNG 3356232809Sjmallett (loads/IOBDMA's are legal) */ 3357232809Sjmallett uint64_t zip : 1; /**< Enable triggering on requests to ZIP 3358232809Sjmallett (doorbell stores are legal) */ 3359232809Sjmallett uint64_t dfa : 1; /**< Enable triggering on requests to DFA 3360232809Sjmallett (CSR's and operations are legal) */ 3361232809Sjmallett uint64_t fpa : 1; /**< Enable triggering on requests to FPA 3362232809Sjmallett (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 3363232809Sjmallett uint64_t key : 1; /**< Enable triggering on requests to KEY memory 3364232809Sjmallett (loads/IOBDMA's/stores are legal) */ 3365232809Sjmallett uint64_t pci : 1; /**< Enable triggering on requests to PCI and RSL-type 3366232809Sjmallett CSR's (RSL CSR's, PCI bus operations, PCI 3367232809Sjmallett CSR's) */ 3368232809Sjmallett uint64_t illegal3 : 2; /**< Illegal destinations */ 3369232809Sjmallett uint64_t mio : 1; /**< Enable triggering on CIU and GPIO CSR's */ 3370232809Sjmallett#else 3371232809Sjmallett uint64_t mio : 1; 3372232809Sjmallett uint64_t illegal3 : 2; 3373232809Sjmallett uint64_t pci : 1; 3374232809Sjmallett uint64_t key : 1; 3375232809Sjmallett uint64_t fpa : 1; 3376232809Sjmallett uint64_t dfa : 1; 3377232809Sjmallett uint64_t zip : 1; 3378232809Sjmallett uint64_t rng : 1; 3379232809Sjmallett uint64_t illegal2 : 3; 3380232809Sjmallett uint64_t pow : 1; 3381232809Sjmallett uint64_t illegal : 19; 3382232809Sjmallett uint64_t reserved_32_63 : 32; 3383232809Sjmallett#endif 3384232809Sjmallett } cn31xx; 3385232809Sjmallett struct cvmx_trax_trig1_did_cn31xx cn38xx; 3386232809Sjmallett struct cvmx_trax_trig1_did_cn31xx cn38xxp2; 3387232809Sjmallett struct cvmx_trax_trig1_did_cn31xx cn52xx; 3388232809Sjmallett struct cvmx_trax_trig1_did_cn31xx cn52xxp1; 3389232809Sjmallett struct cvmx_trax_trig1_did_cn31xx cn56xx; 3390232809Sjmallett struct cvmx_trax_trig1_did_cn31xx cn56xxp1; 3391232809Sjmallett struct cvmx_trax_trig1_did_cn31xx cn58xx; 3392232809Sjmallett struct cvmx_trax_trig1_did_cn31xx cn58xxp1; 3393232809Sjmallett struct cvmx_trax_trig1_did_cn61xx { 3394232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3395232809Sjmallett uint64_t reserved_32_63 : 32; 3396232809Sjmallett uint64_t illegal5 : 1; /**< Illegal destinations */ 3397232809Sjmallett uint64_t fau : 1; /**< Enable triggering on FAU accesses */ 3398232809Sjmallett uint64_t illegal4 : 2; /**< Illegal destinations */ 3399232809Sjmallett uint64_t dpi : 1; /**< Enable triggering on DPI accesses 3400232809Sjmallett (DPI NCB CSRs) */ 3401232809Sjmallett uint64_t illegal : 12; /**< Illegal destinations */ 3402232809Sjmallett uint64_t rad : 1; /**< Enable triggering on RAD accesses 3403232809Sjmallett (doorbells) */ 3404232809Sjmallett uint64_t usb0 : 1; /**< Enable triggering on USB0 accesses 3405232809Sjmallett (UAHC0 EHCI and OHCI NCB CSRs) */ 3406232809Sjmallett uint64_t pow : 1; /**< Enable triggering on requests to POW 3407232809Sjmallett (get work, add work, status/memory/index 3408232809Sjmallett loads, NULLRd loads, CSR's) */ 3409232809Sjmallett uint64_t illegal2 : 1; /**< Illegal destination */ 3410232809Sjmallett uint64_t pko : 1; /**< Enable triggering on PKO accesses 3411232809Sjmallett (doorbells) */ 3412232809Sjmallett uint64_t ipd : 1; /**< Enable triggering on IPD CSR accesses 3413232809Sjmallett (IPD CSRs) */ 3414232809Sjmallett uint64_t rng : 1; /**< Enable triggering on requests to RNG 3415232809Sjmallett (loads/IOBDMA's are legal) */ 3416232809Sjmallett uint64_t zip : 1; /**< Enable triggering on requests to ZIP 3417232809Sjmallett (doorbell stores are legal) */ 3418232809Sjmallett uint64_t dfa : 1; /**< Enable triggering on requests to DFA 3419232809Sjmallett (CSR's and operations are legal) */ 3420232809Sjmallett uint64_t fpa : 1; /**< Enable triggering on requests to FPA 3421232809Sjmallett (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 3422232809Sjmallett uint64_t key : 1; /**< Enable triggering on requests to KEY memory 3423232809Sjmallett (loads/IOBDMA's/stores are legal) */ 3424232809Sjmallett uint64_t sli : 1; /**< Enable triggering on requests to SLI and RSL-type 3425232809Sjmallett CSR's (RSL CSR's, PCI/sRIO bus operations, SLI 3426232809Sjmallett CSR's) */ 3427232809Sjmallett uint64_t illegal3 : 2; /**< Illegal destinations */ 3428232809Sjmallett uint64_t mio : 1; /**< Enable triggering on MIO accesses 3429232809Sjmallett (CIU and GPIO CSR's, boot bus accesses) */ 3430232809Sjmallett#else 3431232809Sjmallett uint64_t mio : 1; 3432232809Sjmallett uint64_t illegal3 : 2; 3433232809Sjmallett uint64_t sli : 1; 3434232809Sjmallett uint64_t key : 1; 3435232809Sjmallett uint64_t fpa : 1; 3436232809Sjmallett uint64_t dfa : 1; 3437232809Sjmallett uint64_t zip : 1; 3438232809Sjmallett uint64_t rng : 1; 3439232809Sjmallett uint64_t ipd : 1; 3440232809Sjmallett uint64_t pko : 1; 3441232809Sjmallett uint64_t illegal2 : 1; 3442232809Sjmallett uint64_t pow : 1; 3443232809Sjmallett uint64_t usb0 : 1; 3444232809Sjmallett uint64_t rad : 1; 3445232809Sjmallett uint64_t illegal : 12; 3446232809Sjmallett uint64_t dpi : 1; 3447232809Sjmallett uint64_t illegal4 : 2; 3448232809Sjmallett uint64_t fau : 1; 3449232809Sjmallett uint64_t illegal5 : 1; 3450232809Sjmallett uint64_t reserved_32_63 : 32; 3451232809Sjmallett#endif 3452232809Sjmallett } cn61xx; 3453232809Sjmallett struct cvmx_trax_trig1_did_cn61xx cn63xx; 3454232809Sjmallett struct cvmx_trax_trig1_did_cn61xx cn63xxp1; 3455232809Sjmallett struct cvmx_trax_trig1_did_cn61xx cn66xx; 3456232809Sjmallett struct cvmx_trax_trig1_did_cn61xx cn68xx; 3457232809Sjmallett struct cvmx_trax_trig1_did_cn61xx cn68xxp1; 3458232809Sjmallett struct cvmx_trax_trig1_did_cn61xx cnf71xx; 3459232809Sjmallett}; 3460232809Sjmalletttypedef union cvmx_trax_trig1_did cvmx_trax_trig1_did_t; 3461232809Sjmallett 3462232809Sjmallett/** 3463232809Sjmallett * cvmx_tra#_trig1_sid 3464232809Sjmallett * 3465232809Sjmallett * TRA_TRIG1_SID = Trace Buffer Filter SourceId Mask 3466232809Sjmallett * 3467232809Sjmallett * Description: 3468232809Sjmallett */ 3469232809Sjmallettunion cvmx_trax_trig1_sid { 3470232809Sjmallett uint64_t u64; 3471232809Sjmallett struct cvmx_trax_trig1_sid_s { 3472232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3473232809Sjmallett uint64_t reserved_20_63 : 44; 3474232809Sjmallett uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3475232809Sjmallett uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3476232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 3477232809Sjmallett uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3478232809Sjmallett uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3479232809Sjmallett uint64_t pp : 16; /**< Enable trigering from PP[N] with matching SourceID 3480232809Sjmallett 0=disable, 1=enable per bit N where 0<=N<=3 */ 3481232809Sjmallett#else 3482232809Sjmallett uint64_t pp : 16; 3483232809Sjmallett uint64_t pki : 1; 3484232809Sjmallett uint64_t pko : 1; 3485232809Sjmallett uint64_t iobreq : 1; 3486232809Sjmallett uint64_t dwb : 1; 3487232809Sjmallett uint64_t reserved_20_63 : 44; 3488232809Sjmallett#endif 3489232809Sjmallett } s; 3490232809Sjmallett struct cvmx_trax_trig1_sid_s cn31xx; 3491232809Sjmallett struct cvmx_trax_trig1_sid_s cn38xx; 3492232809Sjmallett struct cvmx_trax_trig1_sid_s cn38xxp2; 3493232809Sjmallett struct cvmx_trax_trig1_sid_s cn52xx; 3494232809Sjmallett struct cvmx_trax_trig1_sid_s cn52xxp1; 3495232809Sjmallett struct cvmx_trax_trig1_sid_s cn56xx; 3496232809Sjmallett struct cvmx_trax_trig1_sid_s cn56xxp1; 3497232809Sjmallett struct cvmx_trax_trig1_sid_s cn58xx; 3498232809Sjmallett struct cvmx_trax_trig1_sid_s cn58xxp1; 3499232809Sjmallett struct cvmx_trax_trig1_sid_cn61xx { 3500232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3501232809Sjmallett uint64_t reserved_20_63 : 44; 3502232809Sjmallett uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3503232809Sjmallett uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3504232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 3505232809Sjmallett uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3506232809Sjmallett uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3507232809Sjmallett uint64_t reserved_4_15 : 12; 3508232809Sjmallett uint64_t pp : 4; /**< Enable trigering from PP[N] with matching SourceID 3509232809Sjmallett 0=disable, 1=enable per bit N where 0<=N<=3 */ 3510232809Sjmallett#else 3511232809Sjmallett uint64_t pp : 4; 3512232809Sjmallett uint64_t reserved_4_15 : 12; 3513232809Sjmallett uint64_t pki : 1; 3514232809Sjmallett uint64_t pko : 1; 3515232809Sjmallett uint64_t iobreq : 1; 3516232809Sjmallett uint64_t dwb : 1; 3517232809Sjmallett uint64_t reserved_20_63 : 44; 3518232809Sjmallett#endif 3519232809Sjmallett } cn61xx; 3520232809Sjmallett struct cvmx_trax_trig1_sid_cn63xx { 3521232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3522232809Sjmallett uint64_t reserved_20_63 : 44; 3523232809Sjmallett uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3524232809Sjmallett uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3525232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 3526232809Sjmallett uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3527232809Sjmallett uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3528232809Sjmallett uint64_t reserved_8_15 : 8; 3529232809Sjmallett uint64_t pp : 8; /**< Enable trigering from PP[N] with matching SourceID 3530232809Sjmallett 0=disable, 1=enableper bit N where 0<=N<=15 */ 3531232809Sjmallett#else 3532232809Sjmallett uint64_t pp : 8; 3533232809Sjmallett uint64_t reserved_8_15 : 8; 3534232809Sjmallett uint64_t pki : 1; 3535232809Sjmallett uint64_t pko : 1; 3536232809Sjmallett uint64_t iobreq : 1; 3537232809Sjmallett uint64_t dwb : 1; 3538232809Sjmallett uint64_t reserved_20_63 : 44; 3539232809Sjmallett#endif 3540232809Sjmallett } cn63xx; 3541232809Sjmallett struct cvmx_trax_trig1_sid_cn63xxp1 { 3542232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3543232809Sjmallett uint64_t reserved_20_63 : 44; 3544232809Sjmallett uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3545232809Sjmallett uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3546232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 3547232809Sjmallett uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3548232809Sjmallett uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3549232809Sjmallett uint64_t reserved_6_15 : 10; 3550232809Sjmallett uint64_t pp : 6; /**< Enable trigering from PP[N] with matching SourceID 3551232809Sjmallett 0=disable, 1=enable per bit N where 0<=N<=5 */ 3552232809Sjmallett#else 3553232809Sjmallett uint64_t pp : 6; 3554232809Sjmallett uint64_t reserved_6_15 : 10; 3555232809Sjmallett uint64_t pki : 1; 3556232809Sjmallett uint64_t pko : 1; 3557232809Sjmallett uint64_t iobreq : 1; 3558232809Sjmallett uint64_t dwb : 1; 3559232809Sjmallett uint64_t reserved_20_63 : 44; 3560232809Sjmallett#endif 3561232809Sjmallett } cn63xxp1; 3562232809Sjmallett struct cvmx_trax_trig1_sid_cn66xx { 3563232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3564232809Sjmallett uint64_t reserved_20_63 : 44; 3565232809Sjmallett uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3566232809Sjmallett uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3567232809Sjmallett PCI,ZIP,POW, and PKO (writes) */ 3568232809Sjmallett uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3569232809Sjmallett uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3570232809Sjmallett uint64_t reserved_10_15 : 6; 3571232809Sjmallett uint64_t pp : 10; /**< Enable trigering from PP[N] with matching SourceID 3572232809Sjmallett 0=disable, 1=enableper bit N where 0<=N<=15 */ 3573232809Sjmallett#else 3574232809Sjmallett uint64_t pp : 10; 3575232809Sjmallett uint64_t reserved_10_15 : 6; 3576232809Sjmallett uint64_t pki : 1; 3577232809Sjmallett uint64_t pko : 1; 3578232809Sjmallett uint64_t iobreq : 1; 3579232809Sjmallett uint64_t dwb : 1; 3580232809Sjmallett uint64_t reserved_20_63 : 44; 3581232809Sjmallett#endif 3582232809Sjmallett } cn66xx; 3583232809Sjmallett struct cvmx_trax_trig1_sid_cn63xx cn68xx; 3584232809Sjmallett struct cvmx_trax_trig1_sid_cn63xx cn68xxp1; 3585232809Sjmallett struct cvmx_trax_trig1_sid_cn61xx cnf71xx; 3586232809Sjmallett}; 3587232809Sjmalletttypedef union cvmx_trax_trig1_sid cvmx_trax_trig1_sid_t; 3588232809Sjmallett 3589232809Sjmallett#include "cvmx-tra-defs.h" 3590232809Sjmallett#endif 3591