cvmx-tra-defs.h revision 215990
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-tra-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon tra. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_TRA_TYPEDEFS_H__ 53#define __CVMX_TRA_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_TRA_BIST_STATUS CVMX_TRA_BIST_STATUS_FUNC() 57static inline uint64_t CVMX_TRA_BIST_STATUS_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 60 cvmx_warn("CVMX_TRA_BIST_STATUS not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x00011800A8000010ull); 62} 63#else 64#define CVMX_TRA_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A8000010ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_TRA_CTL CVMX_TRA_CTL_FUNC() 68static inline uint64_t CVMX_TRA_CTL_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 71 cvmx_warn("CVMX_TRA_CTL not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x00011800A8000000ull); 73} 74#else 75#define CVMX_TRA_CTL (CVMX_ADD_IO_SEG(0x00011800A8000000ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_TRA_CYCLES_SINCE CVMX_TRA_CYCLES_SINCE_FUNC() 79static inline uint64_t CVMX_TRA_CYCLES_SINCE_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 82 cvmx_warn("CVMX_TRA_CYCLES_SINCE not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x00011800A8000018ull); 84} 85#else 86#define CVMX_TRA_CYCLES_SINCE (CVMX_ADD_IO_SEG(0x00011800A8000018ull)) 87#endif 88#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89#define CVMX_TRA_CYCLES_SINCE1 CVMX_TRA_CYCLES_SINCE1_FUNC() 90static inline uint64_t CVMX_TRA_CYCLES_SINCE1_FUNC(void) 91{ 92 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 93 cvmx_warn("CVMX_TRA_CYCLES_SINCE1 not supported on this chip\n"); 94 return CVMX_ADD_IO_SEG(0x00011800A8000028ull); 95} 96#else 97#define CVMX_TRA_CYCLES_SINCE1 (CVMX_ADD_IO_SEG(0x00011800A8000028ull)) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100#define CVMX_TRA_FILT_ADR_ADR CVMX_TRA_FILT_ADR_ADR_FUNC() 101static inline uint64_t CVMX_TRA_FILT_ADR_ADR_FUNC(void) 102{ 103 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 104 cvmx_warn("CVMX_TRA_FILT_ADR_ADR not supported on this chip\n"); 105 return CVMX_ADD_IO_SEG(0x00011800A8000058ull); 106} 107#else 108#define CVMX_TRA_FILT_ADR_ADR (CVMX_ADD_IO_SEG(0x00011800A8000058ull)) 109#endif 110#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111#define CVMX_TRA_FILT_ADR_MSK CVMX_TRA_FILT_ADR_MSK_FUNC() 112static inline uint64_t CVMX_TRA_FILT_ADR_MSK_FUNC(void) 113{ 114 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 115 cvmx_warn("CVMX_TRA_FILT_ADR_MSK not supported on this chip\n"); 116 return CVMX_ADD_IO_SEG(0x00011800A8000060ull); 117} 118#else 119#define CVMX_TRA_FILT_ADR_MSK (CVMX_ADD_IO_SEG(0x00011800A8000060ull)) 120#endif 121#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122#define CVMX_TRA_FILT_CMD CVMX_TRA_FILT_CMD_FUNC() 123static inline uint64_t CVMX_TRA_FILT_CMD_FUNC(void) 124{ 125 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 126 cvmx_warn("CVMX_TRA_FILT_CMD not supported on this chip\n"); 127 return CVMX_ADD_IO_SEG(0x00011800A8000040ull); 128} 129#else 130#define CVMX_TRA_FILT_CMD (CVMX_ADD_IO_SEG(0x00011800A8000040ull)) 131#endif 132#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133#define CVMX_TRA_FILT_DID CVMX_TRA_FILT_DID_FUNC() 134static inline uint64_t CVMX_TRA_FILT_DID_FUNC(void) 135{ 136 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 137 cvmx_warn("CVMX_TRA_FILT_DID not supported on this chip\n"); 138 return CVMX_ADD_IO_SEG(0x00011800A8000050ull); 139} 140#else 141#define CVMX_TRA_FILT_DID (CVMX_ADD_IO_SEG(0x00011800A8000050ull)) 142#endif 143#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144#define CVMX_TRA_FILT_SID CVMX_TRA_FILT_SID_FUNC() 145static inline uint64_t CVMX_TRA_FILT_SID_FUNC(void) 146{ 147 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 148 cvmx_warn("CVMX_TRA_FILT_SID not supported on this chip\n"); 149 return CVMX_ADD_IO_SEG(0x00011800A8000048ull); 150} 151#else 152#define CVMX_TRA_FILT_SID (CVMX_ADD_IO_SEG(0x00011800A8000048ull)) 153#endif 154#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155#define CVMX_TRA_INT_STATUS CVMX_TRA_INT_STATUS_FUNC() 156static inline uint64_t CVMX_TRA_INT_STATUS_FUNC(void) 157{ 158 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 159 cvmx_warn("CVMX_TRA_INT_STATUS not supported on this chip\n"); 160 return CVMX_ADD_IO_SEG(0x00011800A8000008ull); 161} 162#else 163#define CVMX_TRA_INT_STATUS (CVMX_ADD_IO_SEG(0x00011800A8000008ull)) 164#endif 165#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166#define CVMX_TRA_READ_DAT CVMX_TRA_READ_DAT_FUNC() 167static inline uint64_t CVMX_TRA_READ_DAT_FUNC(void) 168{ 169 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 170 cvmx_warn("CVMX_TRA_READ_DAT not supported on this chip\n"); 171 return CVMX_ADD_IO_SEG(0x00011800A8000020ull); 172} 173#else 174#define CVMX_TRA_READ_DAT (CVMX_ADD_IO_SEG(0x00011800A8000020ull)) 175#endif 176#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177#define CVMX_TRA_READ_DAT_HI CVMX_TRA_READ_DAT_HI_FUNC() 178static inline uint64_t CVMX_TRA_READ_DAT_HI_FUNC(void) 179{ 180 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 181 cvmx_warn("CVMX_TRA_READ_DAT_HI not supported on this chip\n"); 182 return CVMX_ADD_IO_SEG(0x00011800A8000030ull); 183} 184#else 185#define CVMX_TRA_READ_DAT_HI (CVMX_ADD_IO_SEG(0x00011800A8000030ull)) 186#endif 187#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188#define CVMX_TRA_TRIG0_ADR_ADR CVMX_TRA_TRIG0_ADR_ADR_FUNC() 189static inline uint64_t CVMX_TRA_TRIG0_ADR_ADR_FUNC(void) 190{ 191 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 192 cvmx_warn("CVMX_TRA_TRIG0_ADR_ADR not supported on this chip\n"); 193 return CVMX_ADD_IO_SEG(0x00011800A8000098ull); 194} 195#else 196#define CVMX_TRA_TRIG0_ADR_ADR (CVMX_ADD_IO_SEG(0x00011800A8000098ull)) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199#define CVMX_TRA_TRIG0_ADR_MSK CVMX_TRA_TRIG0_ADR_MSK_FUNC() 200static inline uint64_t CVMX_TRA_TRIG0_ADR_MSK_FUNC(void) 201{ 202 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 203 cvmx_warn("CVMX_TRA_TRIG0_ADR_MSK not supported on this chip\n"); 204 return CVMX_ADD_IO_SEG(0x00011800A80000A0ull); 205} 206#else 207#define CVMX_TRA_TRIG0_ADR_MSK (CVMX_ADD_IO_SEG(0x00011800A80000A0ull)) 208#endif 209#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210#define CVMX_TRA_TRIG0_CMD CVMX_TRA_TRIG0_CMD_FUNC() 211static inline uint64_t CVMX_TRA_TRIG0_CMD_FUNC(void) 212{ 213 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 214 cvmx_warn("CVMX_TRA_TRIG0_CMD not supported on this chip\n"); 215 return CVMX_ADD_IO_SEG(0x00011800A8000080ull); 216} 217#else 218#define CVMX_TRA_TRIG0_CMD (CVMX_ADD_IO_SEG(0x00011800A8000080ull)) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221#define CVMX_TRA_TRIG0_DID CVMX_TRA_TRIG0_DID_FUNC() 222static inline uint64_t CVMX_TRA_TRIG0_DID_FUNC(void) 223{ 224 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 225 cvmx_warn("CVMX_TRA_TRIG0_DID not supported on this chip\n"); 226 return CVMX_ADD_IO_SEG(0x00011800A8000090ull); 227} 228#else 229#define CVMX_TRA_TRIG0_DID (CVMX_ADD_IO_SEG(0x00011800A8000090ull)) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232#define CVMX_TRA_TRIG0_SID CVMX_TRA_TRIG0_SID_FUNC() 233static inline uint64_t CVMX_TRA_TRIG0_SID_FUNC(void) 234{ 235 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 236 cvmx_warn("CVMX_TRA_TRIG0_SID not supported on this chip\n"); 237 return CVMX_ADD_IO_SEG(0x00011800A8000088ull); 238} 239#else 240#define CVMX_TRA_TRIG0_SID (CVMX_ADD_IO_SEG(0x00011800A8000088ull)) 241#endif 242#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243#define CVMX_TRA_TRIG1_ADR_ADR CVMX_TRA_TRIG1_ADR_ADR_FUNC() 244static inline uint64_t CVMX_TRA_TRIG1_ADR_ADR_FUNC(void) 245{ 246 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 247 cvmx_warn("CVMX_TRA_TRIG1_ADR_ADR not supported on this chip\n"); 248 return CVMX_ADD_IO_SEG(0x00011800A80000D8ull); 249} 250#else 251#define CVMX_TRA_TRIG1_ADR_ADR (CVMX_ADD_IO_SEG(0x00011800A80000D8ull)) 252#endif 253#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254#define CVMX_TRA_TRIG1_ADR_MSK CVMX_TRA_TRIG1_ADR_MSK_FUNC() 255static inline uint64_t CVMX_TRA_TRIG1_ADR_MSK_FUNC(void) 256{ 257 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 258 cvmx_warn("CVMX_TRA_TRIG1_ADR_MSK not supported on this chip\n"); 259 return CVMX_ADD_IO_SEG(0x00011800A80000E0ull); 260} 261#else 262#define CVMX_TRA_TRIG1_ADR_MSK (CVMX_ADD_IO_SEG(0x00011800A80000E0ull)) 263#endif 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265#define CVMX_TRA_TRIG1_CMD CVMX_TRA_TRIG1_CMD_FUNC() 266static inline uint64_t CVMX_TRA_TRIG1_CMD_FUNC(void) 267{ 268 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 269 cvmx_warn("CVMX_TRA_TRIG1_CMD not supported on this chip\n"); 270 return CVMX_ADD_IO_SEG(0x00011800A80000C0ull); 271} 272#else 273#define CVMX_TRA_TRIG1_CMD (CVMX_ADD_IO_SEG(0x00011800A80000C0ull)) 274#endif 275#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276#define CVMX_TRA_TRIG1_DID CVMX_TRA_TRIG1_DID_FUNC() 277static inline uint64_t CVMX_TRA_TRIG1_DID_FUNC(void) 278{ 279 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 280 cvmx_warn("CVMX_TRA_TRIG1_DID not supported on this chip\n"); 281 return CVMX_ADD_IO_SEG(0x00011800A80000D0ull); 282} 283#else 284#define CVMX_TRA_TRIG1_DID (CVMX_ADD_IO_SEG(0x00011800A80000D0ull)) 285#endif 286#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287#define CVMX_TRA_TRIG1_SID CVMX_TRA_TRIG1_SID_FUNC() 288static inline uint64_t CVMX_TRA_TRIG1_SID_FUNC(void) 289{ 290 if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 291 cvmx_warn("CVMX_TRA_TRIG1_SID not supported on this chip\n"); 292 return CVMX_ADD_IO_SEG(0x00011800A80000C8ull); 293} 294#else 295#define CVMX_TRA_TRIG1_SID (CVMX_ADD_IO_SEG(0x00011800A80000C8ull)) 296#endif 297 298/** 299 * cvmx_tra_bist_status 300 * 301 * TRA_BIST_STATUS = Trace Buffer BiST Status 302 * 303 * Description: 304 */ 305union cvmx_tra_bist_status 306{ 307 uint64_t u64; 308 struct cvmx_tra_bist_status_s 309 { 310#if __BYTE_ORDER == __BIG_ENDIAN 311 uint64_t reserved_3_63 : 61; 312 uint64_t tcf : 1; /**< Bist Results for TCF memory 313 - 0: GOOD (or bist in progress/never run) 314 - 1: BAD */ 315 uint64_t tdf1 : 1; /**< Bist Results for TDF memory 1 316 - 0: GOOD (or bist in progress/never run) 317 - 1: BAD */ 318 uint64_t reserved_0_0 : 1; 319#else 320 uint64_t reserved_0_0 : 1; 321 uint64_t tdf1 : 1; 322 uint64_t tcf : 1; 323 uint64_t reserved_3_63 : 61; 324#endif 325 } s; 326 struct cvmx_tra_bist_status_cn31xx 327 { 328#if __BYTE_ORDER == __BIG_ENDIAN 329 uint64_t reserved_3_63 : 61; 330 uint64_t tcf : 1; /**< Bist Results for TCF memory 331 - 0: GOOD (or bist in progress/never run) 332 - 1: BAD */ 333 uint64_t tdf1 : 1; /**< Bist Results for TDF memory 1 334 - 0: GOOD (or bist in progress/never run) 335 - 1: BAD */ 336 uint64_t tdf0 : 1; /**< Bist Results for TCF memory 0 337 - 0: GOOD (or bist in progress/never run) 338 - 1: BAD */ 339#else 340 uint64_t tdf0 : 1; 341 uint64_t tdf1 : 1; 342 uint64_t tcf : 1; 343 uint64_t reserved_3_63 : 61; 344#endif 345 } cn31xx; 346 struct cvmx_tra_bist_status_cn31xx cn38xx; 347 struct cvmx_tra_bist_status_cn31xx cn38xxp2; 348 struct cvmx_tra_bist_status_cn31xx cn52xx; 349 struct cvmx_tra_bist_status_cn31xx cn52xxp1; 350 struct cvmx_tra_bist_status_cn31xx cn56xx; 351 struct cvmx_tra_bist_status_cn31xx cn56xxp1; 352 struct cvmx_tra_bist_status_cn31xx cn58xx; 353 struct cvmx_tra_bist_status_cn31xx cn58xxp1; 354 struct cvmx_tra_bist_status_cn63xx 355 { 356#if __BYTE_ORDER == __BIG_ENDIAN 357 uint64_t reserved_1_63 : 63; 358 uint64_t tdf : 1; /**< Bist Results for TCF memory 359 - 0: GOOD (or bist in progress/never run) 360 - 1: BAD */ 361#else 362 uint64_t tdf : 1; 363 uint64_t reserved_1_63 : 63; 364#endif 365 } cn63xx; 366 struct cvmx_tra_bist_status_cn63xx cn63xxp1; 367}; 368typedef union cvmx_tra_bist_status cvmx_tra_bist_status_t; 369 370/** 371 * cvmx_tra_ctl 372 * 373 * TRA_CTL = Trace Buffer Control 374 * 375 * Description: 376 * 377 * Notes: 378 * It is illegal to change the values of WRAP, TRIG_CTL, IGNORE_O while tracing (i.e. when ENA=1). 379 * Note that the following fields are present only in chip revisions beginning with pass2: IGNORE_O 380 */ 381union cvmx_tra_ctl 382{ 383 uint64_t u64; 384 struct cvmx_tra_ctl_s 385 { 386#if __BYTE_ORDER == __BIG_ENDIAN 387 uint64_t reserved_17_63 : 47; 388 uint64_t rdat_md : 1; /**< TRA_READ_DAT mode bit 389 If set, the TRA_READ_DAT reads will return the lower 390 64 bits of the TRA entry and the upper bits must be 391 read through TRA_READ_DAT_HI. If not set the return 392 value from TRA_READ_DAT accesses will switch between 393 the lower bits and the upper bits of the TRA entry. */ 394 uint64_t clkalways : 1; /**< Conditional clock enable 395 If set, the TRA clock is never disabled. */ 396 uint64_t ignore_o : 1; /**< Ignore overflow during wrap mode 397 If set and wrapping mode is enabled, then tracing 398 will not stop at the overflow condition. Each 399 write during an overflow will overwrite the 400 oldest, unread entry and the read pointer is 401 incremented by one entry. This bit has no effect 402 if WRAP=0. */ 403 uint64_t mcd0_ena : 1; /**< MCD0 enable 404 If set and any PP sends the MCD0 signal, the 405 tracing is disabled. */ 406 uint64_t mcd0_thr : 1; /**< MCD0_threshold 407 At a fill threshold event, sends an MCD0 408 wire pulse that can cause cores to enter debug 409 mode, if enabled. This MCD0 wire pulse will not 410 occur while (TRA_INT_STATUS.MCD0_THR == 1). */ 411 uint64_t mcd0_trg : 1; /**< MCD0_trigger 412 At an end trigger event, sends an MCD0 413 wire pulse that can cause cores to enter debug 414 mode, if enabled. This MCD0 wire pulse will not 415 occur while (TRA_INT_STATUS.MCD0_TRG == 1). */ 416 uint64_t ciu_thr : 1; /**< CIU_threshold 417 When set during a fill threshold event, 418 TRA_INT_STATUS[CIU_THR] is set, which can cause 419 core interrupts, if enabled. */ 420 uint64_t ciu_trg : 1; /**< CIU_trigger 421 When set during an end trigger event, 422 TRA_INT_STATUS[CIU_TRG] is set, which can cause 423 core interrupts, if enabled. */ 424 uint64_t full_thr : 2; /**< Full Threshhold 425 0=none 426 1=1/2 full 427 2=3/4 full 428 3=4/4 full */ 429 uint64_t time_grn : 3; /**< Timestamp granularity 430 granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */ 431 uint64_t trig_ctl : 2; /**< Trigger Control 432 Note: trigger events are written to the trace 433 0=no triggers 434 1=trigger0=start trigger, trigger1=stop trigger 435 2=(trigger0 || trigger1)=start trigger 436 3=(trigger0 || trigger1)=stop trigger */ 437 uint64_t wrap : 1; /**< Wrap mode 438 When WRAP=0, the trace buffer will disable itself 439 after having logged 1024 entries. When WRAP=1, 440 the trace buffer will never disable itself. 441 In this case, tracing may or may not be 442 temporarily suspended during the overflow 443 condition (see IGNORE_O above). 444 0=do not wrap 445 1=wrap */ 446 uint64_t ena : 1; /**< Enable Trace 447 Master enable. Tracing only happens when ENA=1. 448 When ENA changes from 0 to 1, the read and write 449 pointers are reset to 0x00 to begin a new trace. 450 The MCD0 event may set ENA=0 (see MCD0_ENA 451 above). When using triggers, tracing occurs only 452 between start and stop triggers (including the 453 triggers themselves). 454 0=disable 455 1=enable */ 456#else 457 uint64_t ena : 1; 458 uint64_t wrap : 1; 459 uint64_t trig_ctl : 2; 460 uint64_t time_grn : 3; 461 uint64_t full_thr : 2; 462 uint64_t ciu_trg : 1; 463 uint64_t ciu_thr : 1; 464 uint64_t mcd0_trg : 1; 465 uint64_t mcd0_thr : 1; 466 uint64_t mcd0_ena : 1; 467 uint64_t ignore_o : 1; 468 uint64_t clkalways : 1; 469 uint64_t rdat_md : 1; 470 uint64_t reserved_17_63 : 47; 471#endif 472 } s; 473 struct cvmx_tra_ctl_cn31xx 474 { 475#if __BYTE_ORDER == __BIG_ENDIAN 476 uint64_t reserved_15_63 : 49; 477 uint64_t ignore_o : 1; /**< Ignore overflow during wrap mode 478 If set and wrapping mode is enabled, then tracing 479 will not stop at the overflow condition. Each 480 write during an overflow will overwrite the 481 oldest, unread entry and the read pointer is 482 incremented by one entry. This bit has no effect 483 if WRAP=0. */ 484 uint64_t mcd0_ena : 1; /**< MCD0 enable 485 If set and any PP sends the MCD0 signal, the 486 tracing is disabled. */ 487 uint64_t mcd0_thr : 1; /**< MCD0_threshold 488 At a fill threshold event, sends an MCD0 489 wire pulse that can cause cores to enter debug 490 mode, if enabled. This MCD0 wire pulse will not 491 occur while (TRA_INT_STATUS.MCD0_THR == 1). */ 492 uint64_t mcd0_trg : 1; /**< MCD0_trigger 493 At an end trigger event, sends an MCD0 494 wire pulse that can cause cores to enter debug 495 mode, if enabled. This MCD0 wire pulse will not 496 occur while (TRA_INT_STATUS.MCD0_TRG == 1). */ 497 uint64_t ciu_thr : 1; /**< CIU_threshold 498 When set during a fill threshold event, 499 TRA_INT_STATUS[CIU_THR] is set, which can cause 500 core interrupts, if enabled. */ 501 uint64_t ciu_trg : 1; /**< CIU_trigger 502 When set during an end trigger event, 503 TRA_INT_STATUS[CIU_TRG] is set, which can cause 504 core interrupts, if enabled. */ 505 uint64_t full_thr : 2; /**< Full Threshhold 506 0=none 507 1=1/2 full 508 2=3/4 full 509 3=4/4 full */ 510 uint64_t time_grn : 3; /**< Timestamp granularity 511 granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */ 512 uint64_t trig_ctl : 2; /**< Trigger Control 513 Note: trigger events are written to the trace 514 0=no triggers 515 1=trigger0=start trigger, trigger1=stop trigger 516 2=(trigger0 || trigger1)=start trigger 517 3=(trigger0 || trigger1)=stop trigger */ 518 uint64_t wrap : 1; /**< Wrap mode 519 When WRAP=0, the trace buffer will disable itself 520 after having logged 256 entries. When WRAP=1, 521 the trace buffer will never disable itself. 522 In this case, tracing may or may not be 523 temporarily suspended during the overflow 524 condition (see IGNORE_O above). 525 0=do not wrap 526 1=wrap */ 527 uint64_t ena : 1; /**< Enable Trace 528 Master enable. Tracing only happens when ENA=1. 529 When ENA changes from 0 to 1, the read and write 530 pointers are reset to 0x00 to begin a new trace. 531 The MCD0 event may set ENA=0 (see MCD0_ENA 532 above). When using triggers, tracing occurs only 533 between start and stop triggers (including the 534 triggers themselves). 535 0=disable 536 1=enable */ 537#else 538 uint64_t ena : 1; 539 uint64_t wrap : 1; 540 uint64_t trig_ctl : 2; 541 uint64_t time_grn : 3; 542 uint64_t full_thr : 2; 543 uint64_t ciu_trg : 1; 544 uint64_t ciu_thr : 1; 545 uint64_t mcd0_trg : 1; 546 uint64_t mcd0_thr : 1; 547 uint64_t mcd0_ena : 1; 548 uint64_t ignore_o : 1; 549 uint64_t reserved_15_63 : 49; 550#endif 551 } cn31xx; 552 struct cvmx_tra_ctl_cn31xx cn38xx; 553 struct cvmx_tra_ctl_cn31xx cn38xxp2; 554 struct cvmx_tra_ctl_cn31xx cn52xx; 555 struct cvmx_tra_ctl_cn31xx cn52xxp1; 556 struct cvmx_tra_ctl_cn31xx cn56xx; 557 struct cvmx_tra_ctl_cn31xx cn56xxp1; 558 struct cvmx_tra_ctl_cn31xx cn58xx; 559 struct cvmx_tra_ctl_cn31xx cn58xxp1; 560 struct cvmx_tra_ctl_s cn63xx; 561 struct cvmx_tra_ctl_cn63xxp1 562 { 563#if __BYTE_ORDER == __BIG_ENDIAN 564 uint64_t reserved_16_63 : 48; 565 uint64_t clkalways : 1; /**< Conditional clock enable 566 If set, the TRA clock is never disabled. */ 567 uint64_t ignore_o : 1; /**< Ignore overflow during wrap mode 568 If set and wrapping mode is enabled, then tracing 569 will not stop at the overflow condition. Each 570 write during an overflow will overwrite the 571 oldest, unread entry and the read pointer is 572 incremented by one entry. This bit has no effect 573 if WRAP=0. */ 574 uint64_t mcd0_ena : 1; /**< MCD0 enable 575 If set and any PP sends the MCD0 signal, the 576 tracing is disabled. */ 577 uint64_t mcd0_thr : 1; /**< MCD0_threshold 578 At a fill threshold event, sends an MCD0 579 wire pulse that can cause cores to enter debug 580 mode, if enabled. This MCD0 wire pulse will not 581 occur while (TRA_INT_STATUS.MCD0_THR == 1). */ 582 uint64_t mcd0_trg : 1; /**< MCD0_trigger 583 At an end trigger event, sends an MCD0 584 wire pulse that can cause cores to enter debug 585 mode, if enabled. This MCD0 wire pulse will not 586 occur while (TRA_INT_STATUS.MCD0_TRG == 1). */ 587 uint64_t ciu_thr : 1; /**< CIU_threshold 588 When set during a fill threshold event, 589 TRA_INT_STATUS[CIU_THR] is set, which can cause 590 core interrupts, if enabled. */ 591 uint64_t ciu_trg : 1; /**< CIU_trigger 592 When set during an end trigger event, 593 TRA_INT_STATUS[CIU_TRG] is set, which can cause 594 core interrupts, if enabled. */ 595 uint64_t full_thr : 2; /**< Full Threshhold 596 0=none 597 1=1/2 full 598 2=3/4 full 599 3=4/4 full */ 600 uint64_t time_grn : 3; /**< Timestamp granularity 601 granularity=8^n cycles, n=0,1,2,3,4,5,6,7 */ 602 uint64_t trig_ctl : 2; /**< Trigger Control 603 Note: trigger events are written to the trace 604 0=no triggers 605 1=trigger0=start trigger, trigger1=stop trigger 606 2=(trigger0 || trigger1)=start trigger 607 3=(trigger0 || trigger1)=stop trigger */ 608 uint64_t wrap : 1; /**< Wrap mode 609 When WRAP=0, the trace buffer will disable itself 610 after having logged 1024 entries. When WRAP=1, 611 the trace buffer will never disable itself. 612 In this case, tracing may or may not be 613 temporarily suspended during the overflow 614 condition (see IGNORE_O above). 615 0=do not wrap 616 1=wrap */ 617 uint64_t ena : 1; /**< Enable Trace 618 Master enable. Tracing only happens when ENA=1. 619 When ENA changes from 0 to 1, the read and write 620 pointers are reset to 0x00 to begin a new trace. 621 The MCD0 event may set ENA=0 (see MCD0_ENA 622 above). When using triggers, tracing occurs only 623 between start and stop triggers (including the 624 triggers themselves). 625 0=disable 626 1=enable */ 627#else 628 uint64_t ena : 1; 629 uint64_t wrap : 1; 630 uint64_t trig_ctl : 2; 631 uint64_t time_grn : 3; 632 uint64_t full_thr : 2; 633 uint64_t ciu_trg : 1; 634 uint64_t ciu_thr : 1; 635 uint64_t mcd0_trg : 1; 636 uint64_t mcd0_thr : 1; 637 uint64_t mcd0_ena : 1; 638 uint64_t ignore_o : 1; 639 uint64_t clkalways : 1; 640 uint64_t reserved_16_63 : 48; 641#endif 642 } cn63xxp1; 643}; 644typedef union cvmx_tra_ctl cvmx_tra_ctl_t; 645 646/** 647 * cvmx_tra_cycles_since 648 * 649 * TRA_CYCLES_SINCE = Trace Buffer Cycles Since Last Write, Read/Write pointers 650 * 651 * Description: 652 * 653 * Notes: 654 * This CSR is obsolete. Use TRA_CYCLES_SINCE1 instead. 655 * 656 */ 657union cvmx_tra_cycles_since 658{ 659 uint64_t u64; 660 struct cvmx_tra_cycles_since_s 661 { 662#if __BYTE_ORDER == __BIG_ENDIAN 663 uint64_t cycles : 48; /**< Cycles since the last entry was written */ 664 uint64_t rptr : 8; /**< Read pointer */ 665 uint64_t wptr : 8; /**< Write pointer */ 666#else 667 uint64_t wptr : 8; 668 uint64_t rptr : 8; 669 uint64_t cycles : 48; 670#endif 671 } s; 672 struct cvmx_tra_cycles_since_s cn31xx; 673 struct cvmx_tra_cycles_since_s cn38xx; 674 struct cvmx_tra_cycles_since_s cn38xxp2; 675 struct cvmx_tra_cycles_since_s cn52xx; 676 struct cvmx_tra_cycles_since_s cn52xxp1; 677 struct cvmx_tra_cycles_since_s cn56xx; 678 struct cvmx_tra_cycles_since_s cn56xxp1; 679 struct cvmx_tra_cycles_since_s cn58xx; 680 struct cvmx_tra_cycles_since_s cn58xxp1; 681 struct cvmx_tra_cycles_since_s cn63xx; 682 struct cvmx_tra_cycles_since_s cn63xxp1; 683}; 684typedef union cvmx_tra_cycles_since cvmx_tra_cycles_since_t; 685 686/** 687 * cvmx_tra_cycles_since1 688 * 689 * TRA_CYCLES_SINCE1 = Trace Buffer Cycles Since Last Write, Read/Write pointers 690 * 691 * Description: 692 */ 693union cvmx_tra_cycles_since1 694{ 695 uint64_t u64; 696 struct cvmx_tra_cycles_since1_s 697 { 698#if __BYTE_ORDER == __BIG_ENDIAN 699 uint64_t cycles : 40; /**< Cycles since the last entry was written */ 700 uint64_t reserved_22_23 : 2; 701 uint64_t rptr : 10; /**< Read pointer */ 702 uint64_t reserved_10_11 : 2; 703 uint64_t wptr : 10; /**< Write pointer */ 704#else 705 uint64_t wptr : 10; 706 uint64_t reserved_10_11 : 2; 707 uint64_t rptr : 10; 708 uint64_t reserved_22_23 : 2; 709 uint64_t cycles : 40; 710#endif 711 } s; 712 struct cvmx_tra_cycles_since1_s cn52xx; 713 struct cvmx_tra_cycles_since1_s cn52xxp1; 714 struct cvmx_tra_cycles_since1_s cn56xx; 715 struct cvmx_tra_cycles_since1_s cn56xxp1; 716 struct cvmx_tra_cycles_since1_s cn58xx; 717 struct cvmx_tra_cycles_since1_s cn58xxp1; 718 struct cvmx_tra_cycles_since1_s cn63xx; 719 struct cvmx_tra_cycles_since1_s cn63xxp1; 720}; 721typedef union cvmx_tra_cycles_since1 cvmx_tra_cycles_since1_t; 722 723/** 724 * cvmx_tra_filt_adr_adr 725 * 726 * TRA_FILT_ADR_ADR = Trace Buffer Filter Address Address 727 * 728 * Description: 729 */ 730union cvmx_tra_filt_adr_adr 731{ 732 uint64_t u64; 733 struct cvmx_tra_filt_adr_adr_s 734 { 735#if __BYTE_ORDER == __BIG_ENDIAN 736 uint64_t reserved_38_63 : 26; 737 uint64_t adr : 38; /**< Unmasked Address 738 The combination of TRA_FILT_ADR_ADR and 739 TRA_FILT_ADR_MSK is a masked address to 740 enable tracing of only those commands whose 741 masked address matches */ 742#else 743 uint64_t adr : 38; 744 uint64_t reserved_38_63 : 26; 745#endif 746 } s; 747 struct cvmx_tra_filt_adr_adr_cn31xx 748 { 749#if __BYTE_ORDER == __BIG_ENDIAN 750 uint64_t reserved_36_63 : 28; 751 uint64_t adr : 36; /**< Unmasked Address 752 The combination of TRA_FILT_ADR_ADR and 753 TRA_FILT_ADR_MSK is a masked address to 754 enable tracing of only those commands whose 755 masked address matches */ 756#else 757 uint64_t adr : 36; 758 uint64_t reserved_36_63 : 28; 759#endif 760 } cn31xx; 761 struct cvmx_tra_filt_adr_adr_cn31xx cn38xx; 762 struct cvmx_tra_filt_adr_adr_cn31xx cn38xxp2; 763 struct cvmx_tra_filt_adr_adr_cn31xx cn52xx; 764 struct cvmx_tra_filt_adr_adr_cn31xx cn52xxp1; 765 struct cvmx_tra_filt_adr_adr_cn31xx cn56xx; 766 struct cvmx_tra_filt_adr_adr_cn31xx cn56xxp1; 767 struct cvmx_tra_filt_adr_adr_cn31xx cn58xx; 768 struct cvmx_tra_filt_adr_adr_cn31xx cn58xxp1; 769 struct cvmx_tra_filt_adr_adr_s cn63xx; 770 struct cvmx_tra_filt_adr_adr_s cn63xxp1; 771}; 772typedef union cvmx_tra_filt_adr_adr cvmx_tra_filt_adr_adr_t; 773 774/** 775 * cvmx_tra_filt_adr_msk 776 * 777 * TRA_FILT_ADR_MSK = Trace Buffer Filter Address Mask 778 * 779 * Description: 780 */ 781union cvmx_tra_filt_adr_msk 782{ 783 uint64_t u64; 784 struct cvmx_tra_filt_adr_msk_s 785 { 786#if __BYTE_ORDER == __BIG_ENDIAN 787 uint64_t reserved_38_63 : 26; 788 uint64_t adr : 38; /**< Address Mask 789 The combination of TRA_FILT_ADR_ADR and 790 TRA_FILT_ADR_MSK is a masked address to 791 enable tracing of only those commands whose 792 masked address matches. When a mask bit is not 793 set, the corresponding address bits are assumed 794 to match. Also, note that IOBDMAs do not have 795 proper addresses, so when TRA_FILT_CMD[IOBDMA] 796 is set, TRA_FILT_ADR_MSK must be zero to 797 guarantee that any IOBDMAs enter the trace. */ 798#else 799 uint64_t adr : 38; 800 uint64_t reserved_38_63 : 26; 801#endif 802 } s; 803 struct cvmx_tra_filt_adr_msk_cn31xx 804 { 805#if __BYTE_ORDER == __BIG_ENDIAN 806 uint64_t reserved_36_63 : 28; 807 uint64_t adr : 36; /**< Address Mask 808 The combination of TRA_FILT_ADR_ADR and 809 TRA_FILT_ADR_MSK is a masked address to 810 enable tracing of only those commands whose 811 masked address matches. When a mask bit is not 812 set, the corresponding address bits are assumed 813 to match. Also, note that IOBDMAs do not have 814 proper addresses, so when TRA_FILT_CMD[IOBDMA] 815 is set, TRA_FILT_ADR_MSK must be zero to 816 guarantee that any IOBDMAs enter the trace. */ 817#else 818 uint64_t adr : 36; 819 uint64_t reserved_36_63 : 28; 820#endif 821 } cn31xx; 822 struct cvmx_tra_filt_adr_msk_cn31xx cn38xx; 823 struct cvmx_tra_filt_adr_msk_cn31xx cn38xxp2; 824 struct cvmx_tra_filt_adr_msk_cn31xx cn52xx; 825 struct cvmx_tra_filt_adr_msk_cn31xx cn52xxp1; 826 struct cvmx_tra_filt_adr_msk_cn31xx cn56xx; 827 struct cvmx_tra_filt_adr_msk_cn31xx cn56xxp1; 828 struct cvmx_tra_filt_adr_msk_cn31xx cn58xx; 829 struct cvmx_tra_filt_adr_msk_cn31xx cn58xxp1; 830 struct cvmx_tra_filt_adr_msk_s cn63xx; 831 struct cvmx_tra_filt_adr_msk_s cn63xxp1; 832}; 833typedef union cvmx_tra_filt_adr_msk cvmx_tra_filt_adr_msk_t; 834 835/** 836 * cvmx_tra_filt_cmd 837 * 838 * TRA_FILT_CMD = Trace Buffer Filter Command Mask 839 * 840 * Description: 841 * 842 * Notes: 843 * Note that the trace buffer does not do proper IOBDMA address compares. Thus, if IOBDMA is set, then 844 * the address compare must be disabled (i.e. TRA_FILT_ADR_MSK set to zero) to guarantee that IOBDMAs 845 * enter the trace. 846 */ 847union cvmx_tra_filt_cmd 848{ 849 uint64_t u64; 850 struct cvmx_tra_filt_cmd_s 851 { 852#if __BYTE_ORDER == __BIG_ENDIAN 853 uint64_t saa64 : 1; /**< Enable SAA64 tracing 854 0=disable, 1=enable */ 855 uint64_t saa32 : 1; /**< Enable SAA32 tracing 856 0=disable, 1=enable */ 857 uint64_t reserved_60_61 : 2; 858 uint64_t faa64 : 1; /**< Enable FAA64 tracing 859 0=disable, 1=enable */ 860 uint64_t faa32 : 1; /**< Enable FAA32 tracing 861 0=disable, 1=enable */ 862 uint64_t reserved_56_57 : 2; 863 uint64_t decr64 : 1; /**< Enable DECR64 tracing 864 0=disable, 1=enable */ 865 uint64_t decr32 : 1; /**< Enable DECR32 tracing 866 0=disable, 1=enable */ 867 uint64_t decr16 : 1; /**< Enable DECR16 tracing 868 0=disable, 1=enable */ 869 uint64_t decr8 : 1; /**< Enable DECR8 tracing 870 0=disable, 1=enable */ 871 uint64_t incr64 : 1; /**< Enable INCR64 tracing 872 0=disable, 1=enable */ 873 uint64_t incr32 : 1; /**< Enable INCR32 tracing 874 0=disable, 1=enable */ 875 uint64_t incr16 : 1; /**< Enable INCR16 tracing 876 0=disable, 1=enable */ 877 uint64_t incr8 : 1; /**< Enable INCR8 tracing 878 0=disable, 1=enable */ 879 uint64_t clr64 : 1; /**< Enable CLR64 tracing 880 0=disable, 1=enable */ 881 uint64_t clr32 : 1; /**< Enable CLR32 tracing 882 0=disable, 1=enable */ 883 uint64_t clr16 : 1; /**< Enable CLR16 tracing 884 0=disable, 1=enable */ 885 uint64_t clr8 : 1; /**< Enable CLR8 tracing 886 0=disable, 1=enable */ 887 uint64_t set64 : 1; /**< Enable SET64 tracing 888 0=disable, 1=enable */ 889 uint64_t set32 : 1; /**< Enable SET32 tracing 890 0=disable, 1=enable */ 891 uint64_t set16 : 1; /**< Enable SET16 tracing 892 0=disable, 1=enable */ 893 uint64_t set8 : 1; /**< Enable SET8 tracing 894 0=disable, 1=enable */ 895 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 896 0=disable, 1=enable */ 897 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 898 0=disable, 1=enable */ 899 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 900 0=disable, 1=enable */ 901 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 902 0=disable, 1=enable */ 903 uint64_t reserved_32_35 : 4; 904 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 905 0=disable, 1=enable */ 906 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 907 0=disable, 1=enable */ 908 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 909 0=disable, 1=enable */ 910 uint64_t invl2 : 1; /**< Enable INVL2 tracing 911 0=disable, 1=enable */ 912 uint64_t reserved_27_27 : 1; 913 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 914 0=disable, 1=enable */ 915 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 916 0=disable, 1=enable */ 917 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 918 0=disable, 1=enable */ 919 uint64_t fas64 : 1; /**< Enable FAS64 tracing 920 0=disable, 1=enable */ 921 uint64_t fas32 : 1; /**< Enable FAS32 tracing 922 0=disable, 1=enable */ 923 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 924 0=disable, 1=enable */ 925 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 926 0=disable, 1=enable */ 927 uint64_t reserved_16_19 : 4; 928 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 929 0=disable, 1=enable */ 930 uint64_t iobst : 1; /**< Enable IOBST tracing 931 0=disable, 1=enable */ 932 uint64_t reserved_0_13 : 14; 933#else 934 uint64_t reserved_0_13 : 14; 935 uint64_t iobst : 1; 936 uint64_t iobdma : 1; 937 uint64_t reserved_16_19 : 4; 938 uint64_t stfil1 : 1; 939 uint64_t sttil1 : 1; 940 uint64_t fas32 : 1; 941 uint64_t fas64 : 1; 942 uint64_t wbil2i : 1; 943 uint64_t ltgl2i : 1; 944 uint64_t stgl2i : 1; 945 uint64_t reserved_27_27 : 1; 946 uint64_t invl2 : 1; 947 uint64_t wbil2 : 1; 948 uint64_t wbl2 : 1; 949 uint64_t lckl2 : 1; 950 uint64_t reserved_32_35 : 4; 951 uint64_t iobst8 : 1; 952 uint64_t iobst16 : 1; 953 uint64_t iobst32 : 1; 954 uint64_t iobst64 : 1; 955 uint64_t set8 : 1; 956 uint64_t set16 : 1; 957 uint64_t set32 : 1; 958 uint64_t set64 : 1; 959 uint64_t clr8 : 1; 960 uint64_t clr16 : 1; 961 uint64_t clr32 : 1; 962 uint64_t clr64 : 1; 963 uint64_t incr8 : 1; 964 uint64_t incr16 : 1; 965 uint64_t incr32 : 1; 966 uint64_t incr64 : 1; 967 uint64_t decr8 : 1; 968 uint64_t decr16 : 1; 969 uint64_t decr32 : 1; 970 uint64_t decr64 : 1; 971 uint64_t reserved_56_57 : 2; 972 uint64_t faa32 : 1; 973 uint64_t faa64 : 1; 974 uint64_t reserved_60_61 : 2; 975 uint64_t saa32 : 1; 976 uint64_t saa64 : 1; 977#endif 978 } s; 979 struct cvmx_tra_filt_cmd_cn31xx 980 { 981#if __BYTE_ORDER == __BIG_ENDIAN 982 uint64_t reserved_16_63 : 48; 983 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 984 0=disable, 1=enable */ 985 uint64_t iobst : 1; /**< Enable IOBST tracing 986 0=disable, 1=enable */ 987 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 988 0=disable, 1=enable */ 989 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 990 0=disable, 1=enable */ 991 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 992 0=disable, 1=enable */ 993 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 994 0=disable, 1=enable */ 995 uint64_t stt : 1; /**< Enable STT tracing 996 0=disable, 1=enable */ 997 uint64_t stp : 1; /**< Enable STP tracing 998 0=disable, 1=enable */ 999 uint64_t stc : 1; /**< Enable STC tracing 1000 0=disable, 1=enable */ 1001 uint64_t stf : 1; /**< Enable STF tracing 1002 0=disable, 1=enable */ 1003 uint64_t ldt : 1; /**< Enable LDT tracing 1004 0=disable, 1=enable */ 1005 uint64_t ldi : 1; /**< Enable LDI tracing 1006 0=disable, 1=enable */ 1007 uint64_t ldd : 1; /**< Enable LDD tracing 1008 0=disable, 1=enable */ 1009 uint64_t psl1 : 1; /**< Enable PSL1 tracing 1010 0=disable, 1=enable */ 1011 uint64_t pl2 : 1; /**< Enable PL2 tracing 1012 0=disable, 1=enable */ 1013 uint64_t dwb : 1; /**< Enable DWB tracing 1014 0=disable, 1=enable */ 1015#else 1016 uint64_t dwb : 1; 1017 uint64_t pl2 : 1; 1018 uint64_t psl1 : 1; 1019 uint64_t ldd : 1; 1020 uint64_t ldi : 1; 1021 uint64_t ldt : 1; 1022 uint64_t stf : 1; 1023 uint64_t stc : 1; 1024 uint64_t stp : 1; 1025 uint64_t stt : 1; 1026 uint64_t iobld8 : 1; 1027 uint64_t iobld16 : 1; 1028 uint64_t iobld32 : 1; 1029 uint64_t iobld64 : 1; 1030 uint64_t iobst : 1; 1031 uint64_t iobdma : 1; 1032 uint64_t reserved_16_63 : 48; 1033#endif 1034 } cn31xx; 1035 struct cvmx_tra_filt_cmd_cn31xx cn38xx; 1036 struct cvmx_tra_filt_cmd_cn31xx cn38xxp2; 1037 struct cvmx_tra_filt_cmd_cn52xx 1038 { 1039#if __BYTE_ORDER == __BIG_ENDIAN 1040 uint64_t reserved_17_63 : 47; 1041 uint64_t saa : 1; /**< Enable SAA tracing 1042 0=disable, 1=enable */ 1043 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1044 0=disable, 1=enable */ 1045 uint64_t iobst : 1; /**< Enable IOBST tracing 1046 0=disable, 1=enable */ 1047 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 1048 0=disable, 1=enable */ 1049 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 1050 0=disable, 1=enable */ 1051 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 1052 0=disable, 1=enable */ 1053 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 1054 0=disable, 1=enable */ 1055 uint64_t stt : 1; /**< Enable STT tracing 1056 0=disable, 1=enable */ 1057 uint64_t stp : 1; /**< Enable STP tracing 1058 0=disable, 1=enable */ 1059 uint64_t stc : 1; /**< Enable STC tracing 1060 0=disable, 1=enable */ 1061 uint64_t stf : 1; /**< Enable STF tracing 1062 0=disable, 1=enable */ 1063 uint64_t ldt : 1; /**< Enable LDT tracing 1064 0=disable, 1=enable */ 1065 uint64_t ldi : 1; /**< Enable LDI tracing 1066 0=disable, 1=enable */ 1067 uint64_t ldd : 1; /**< Enable LDD tracing 1068 0=disable, 1=enable */ 1069 uint64_t psl1 : 1; /**< Enable PSL1 tracing 1070 0=disable, 1=enable */ 1071 uint64_t pl2 : 1; /**< Enable PL2 tracing 1072 0=disable, 1=enable */ 1073 uint64_t dwb : 1; /**< Enable DWB tracing 1074 0=disable, 1=enable */ 1075#else 1076 uint64_t dwb : 1; 1077 uint64_t pl2 : 1; 1078 uint64_t psl1 : 1; 1079 uint64_t ldd : 1; 1080 uint64_t ldi : 1; 1081 uint64_t ldt : 1; 1082 uint64_t stf : 1; 1083 uint64_t stc : 1; 1084 uint64_t stp : 1; 1085 uint64_t stt : 1; 1086 uint64_t iobld8 : 1; 1087 uint64_t iobld16 : 1; 1088 uint64_t iobld32 : 1; 1089 uint64_t iobld64 : 1; 1090 uint64_t iobst : 1; 1091 uint64_t iobdma : 1; 1092 uint64_t saa : 1; 1093 uint64_t reserved_17_63 : 47; 1094#endif 1095 } cn52xx; 1096 struct cvmx_tra_filt_cmd_cn52xx cn52xxp1; 1097 struct cvmx_tra_filt_cmd_cn52xx cn56xx; 1098 struct cvmx_tra_filt_cmd_cn52xx cn56xxp1; 1099 struct cvmx_tra_filt_cmd_cn52xx cn58xx; 1100 struct cvmx_tra_filt_cmd_cn52xx cn58xxp1; 1101 struct cvmx_tra_filt_cmd_cn63xx 1102 { 1103#if __BYTE_ORDER == __BIG_ENDIAN 1104 uint64_t saa64 : 1; /**< Enable SAA64 tracing 1105 0=disable, 1=enable */ 1106 uint64_t saa32 : 1; /**< Enable SAA32 tracing 1107 0=disable, 1=enable */ 1108 uint64_t reserved_60_61 : 2; 1109 uint64_t faa64 : 1; /**< Enable FAA64 tracing 1110 0=disable, 1=enable */ 1111 uint64_t faa32 : 1; /**< Enable FAA32 tracing 1112 0=disable, 1=enable */ 1113 uint64_t reserved_56_57 : 2; 1114 uint64_t decr64 : 1; /**< Enable DECR64 tracing 1115 0=disable, 1=enable */ 1116 uint64_t decr32 : 1; /**< Enable DECR32 tracing 1117 0=disable, 1=enable */ 1118 uint64_t decr16 : 1; /**< Enable DECR16 tracing 1119 0=disable, 1=enable */ 1120 uint64_t decr8 : 1; /**< Enable DECR8 tracing 1121 0=disable, 1=enable */ 1122 uint64_t incr64 : 1; /**< Enable INCR64 tracing 1123 0=disable, 1=enable */ 1124 uint64_t incr32 : 1; /**< Enable INCR32 tracing 1125 0=disable, 1=enable */ 1126 uint64_t incr16 : 1; /**< Enable INCR16 tracing 1127 0=disable, 1=enable */ 1128 uint64_t incr8 : 1; /**< Enable INCR8 tracing 1129 0=disable, 1=enable */ 1130 uint64_t clr64 : 1; /**< Enable CLR64 tracing 1131 0=disable, 1=enable */ 1132 uint64_t clr32 : 1; /**< Enable CLR32 tracing 1133 0=disable, 1=enable */ 1134 uint64_t clr16 : 1; /**< Enable CLR16 tracing 1135 0=disable, 1=enable */ 1136 uint64_t clr8 : 1; /**< Enable CLR8 tracing 1137 0=disable, 1=enable */ 1138 uint64_t set64 : 1; /**< Enable SET64 tracing 1139 0=disable, 1=enable */ 1140 uint64_t set32 : 1; /**< Enable SET32 tracing 1141 0=disable, 1=enable */ 1142 uint64_t set16 : 1; /**< Enable SET16 tracing 1143 0=disable, 1=enable */ 1144 uint64_t set8 : 1; /**< Enable SET8 tracing 1145 0=disable, 1=enable */ 1146 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 1147 0=disable, 1=enable */ 1148 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 1149 0=disable, 1=enable */ 1150 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 1151 0=disable, 1=enable */ 1152 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 1153 0=disable, 1=enable */ 1154 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 1155 0=disable, 1=enable */ 1156 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 1157 0=disable, 1=enable */ 1158 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 1159 0=disable, 1=enable */ 1160 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 1161 0=disable, 1=enable */ 1162 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 1163 0=disable, 1=enable */ 1164 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 1165 0=disable, 1=enable */ 1166 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 1167 0=disable, 1=enable */ 1168 uint64_t invl2 : 1; /**< Enable INVL2 tracing 1169 0=disable, 1=enable */ 1170 uint64_t reserved_27_27 : 1; 1171 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 1172 0=disable, 1=enable */ 1173 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 1174 0=disable, 1=enable */ 1175 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 1176 0=disable, 1=enable */ 1177 uint64_t fas64 : 1; /**< Enable FAS64 tracing 1178 0=disable, 1=enable */ 1179 uint64_t fas32 : 1; /**< Enable FAS32 tracing 1180 0=disable, 1=enable */ 1181 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 1182 0=disable, 1=enable */ 1183 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 1184 0=disable, 1=enable */ 1185 uint64_t stc : 1; /**< Enable STC tracing 1186 0=disable, 1=enable */ 1187 uint64_t stp : 1; /**< Enable STP tracing 1188 0=disable, 1=enable */ 1189 uint64_t stt : 1; /**< Enable STT tracing 1190 0=disable, 1=enable */ 1191 uint64_t stf : 1; /**< Enable STF tracing 1192 0=disable, 1=enable */ 1193 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1194 0=disable, 1=enable */ 1195 uint64_t reserved_10_14 : 5; 1196 uint64_t psl1 : 1; /**< Enable PSL1 tracing 1197 0=disable, 1=enable */ 1198 uint64_t ldd : 1; /**< Enable LDD tracing 1199 0=disable, 1=enable */ 1200 uint64_t reserved_6_7 : 2; 1201 uint64_t dwb : 1; /**< Enable DWB tracing 1202 0=disable, 1=enable */ 1203 uint64_t rpl2 : 1; /**< Enable RPL2 tracing 1204 0=disable, 1=enable */ 1205 uint64_t pl2 : 1; /**< Enable PL2 tracing 1206 0=disable, 1=enable */ 1207 uint64_t ldi : 1; /**< Enable LDI tracing 1208 0=disable, 1=enable */ 1209 uint64_t ldt : 1; /**< Enable LDT tracing 1210 0=disable, 1=enable */ 1211 uint64_t nop : 1; /**< Enable NOP tracing 1212 0=disable, 1=enable */ 1213#else 1214 uint64_t nop : 1; 1215 uint64_t ldt : 1; 1216 uint64_t ldi : 1; 1217 uint64_t pl2 : 1; 1218 uint64_t rpl2 : 1; 1219 uint64_t dwb : 1; 1220 uint64_t reserved_6_7 : 2; 1221 uint64_t ldd : 1; 1222 uint64_t psl1 : 1; 1223 uint64_t reserved_10_14 : 5; 1224 uint64_t iobdma : 1; 1225 uint64_t stf : 1; 1226 uint64_t stt : 1; 1227 uint64_t stp : 1; 1228 uint64_t stc : 1; 1229 uint64_t stfil1 : 1; 1230 uint64_t sttil1 : 1; 1231 uint64_t fas32 : 1; 1232 uint64_t fas64 : 1; 1233 uint64_t wbil2i : 1; 1234 uint64_t ltgl2i : 1; 1235 uint64_t stgl2i : 1; 1236 uint64_t reserved_27_27 : 1; 1237 uint64_t invl2 : 1; 1238 uint64_t wbil2 : 1; 1239 uint64_t wbl2 : 1; 1240 uint64_t lckl2 : 1; 1241 uint64_t iobld8 : 1; 1242 uint64_t iobld16 : 1; 1243 uint64_t iobld32 : 1; 1244 uint64_t iobld64 : 1; 1245 uint64_t iobst8 : 1; 1246 uint64_t iobst16 : 1; 1247 uint64_t iobst32 : 1; 1248 uint64_t iobst64 : 1; 1249 uint64_t set8 : 1; 1250 uint64_t set16 : 1; 1251 uint64_t set32 : 1; 1252 uint64_t set64 : 1; 1253 uint64_t clr8 : 1; 1254 uint64_t clr16 : 1; 1255 uint64_t clr32 : 1; 1256 uint64_t clr64 : 1; 1257 uint64_t incr8 : 1; 1258 uint64_t incr16 : 1; 1259 uint64_t incr32 : 1; 1260 uint64_t incr64 : 1; 1261 uint64_t decr8 : 1; 1262 uint64_t decr16 : 1; 1263 uint64_t decr32 : 1; 1264 uint64_t decr64 : 1; 1265 uint64_t reserved_56_57 : 2; 1266 uint64_t faa32 : 1; 1267 uint64_t faa64 : 1; 1268 uint64_t reserved_60_61 : 2; 1269 uint64_t saa32 : 1; 1270 uint64_t saa64 : 1; 1271#endif 1272 } cn63xx; 1273 struct cvmx_tra_filt_cmd_cn63xx cn63xxp1; 1274}; 1275typedef union cvmx_tra_filt_cmd cvmx_tra_filt_cmd_t; 1276 1277/** 1278 * cvmx_tra_filt_did 1279 * 1280 * TRA_FILT_DID = Trace Buffer Filter DestinationId Mask 1281 * 1282 * Description: 1283 */ 1284union cvmx_tra_filt_did 1285{ 1286 uint64_t u64; 1287 struct cvmx_tra_filt_did_s 1288 { 1289#if __BYTE_ORDER == __BIG_ENDIAN 1290 uint64_t reserved_13_63 : 51; 1291 uint64_t pow : 1; /**< Enable tracing of requests to POW 1292 (get work, add work, status/memory/index 1293 loads, NULLRd loads, CSR's) */ 1294 uint64_t reserved_9_11 : 3; 1295 uint64_t rng : 1; /**< Enable tracing of requests to RNG 1296 (loads/IOBDMA's are legal) */ 1297 uint64_t zip : 1; /**< Enable tracing of requests to ZIP 1298 (doorbell stores are legal) */ 1299 uint64_t dfa : 1; /**< Enable tracing of requests to DFA 1300 (CSR's and operations are legal) */ 1301 uint64_t fpa : 1; /**< Enable tracing of requests to FPA 1302 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 1303 uint64_t key : 1; /**< Enable tracing of requests to KEY memory 1304 (loads/IOBDMA's/stores are legal) */ 1305 uint64_t reserved_3_3 : 1; 1306 uint64_t illegal3 : 2; /**< Illegal destinations */ 1307 uint64_t mio : 1; /**< Enable tracing of MIO accesses 1308 (CIU and GPIO CSR's, boot bus accesses) */ 1309#else 1310 uint64_t mio : 1; 1311 uint64_t illegal3 : 2; 1312 uint64_t reserved_3_3 : 1; 1313 uint64_t key : 1; 1314 uint64_t fpa : 1; 1315 uint64_t dfa : 1; 1316 uint64_t zip : 1; 1317 uint64_t rng : 1; 1318 uint64_t reserved_9_11 : 3; 1319 uint64_t pow : 1; 1320 uint64_t reserved_13_63 : 51; 1321#endif 1322 } s; 1323 struct cvmx_tra_filt_did_cn31xx 1324 { 1325#if __BYTE_ORDER == __BIG_ENDIAN 1326 uint64_t reserved_32_63 : 32; 1327 uint64_t illegal : 19; /**< Illegal destinations */ 1328 uint64_t pow : 1; /**< Enable tracing of requests to POW 1329 (get work, add work, status/memory/index 1330 loads, NULLRd loads, CSR's) */ 1331 uint64_t illegal2 : 3; /**< Illegal destinations */ 1332 uint64_t rng : 1; /**< Enable tracing of requests to RNG 1333 (loads/IOBDMA's are legal) */ 1334 uint64_t zip : 1; /**< Enable tracing of requests to ZIP 1335 (doorbell stores are legal) */ 1336 uint64_t dfa : 1; /**< Enable tracing of requests to DFA 1337 (CSR's and operations are legal) */ 1338 uint64_t fpa : 1; /**< Enable tracing of requests to FPA 1339 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 1340 uint64_t key : 1; /**< Enable tracing of requests to KEY memory 1341 (loads/IOBDMA's/stores are legal) */ 1342 uint64_t pci : 1; /**< Enable tracing of requests to PCI and RSL-type 1343 CSR's (RSL CSR's, PCI bus operations, PCI 1344 CSR's) */ 1345 uint64_t illegal3 : 2; /**< Illegal destinations */ 1346 uint64_t mio : 1; /**< Enable tracing of CIU and GPIO CSR's */ 1347#else 1348 uint64_t mio : 1; 1349 uint64_t illegal3 : 2; 1350 uint64_t pci : 1; 1351 uint64_t key : 1; 1352 uint64_t fpa : 1; 1353 uint64_t dfa : 1; 1354 uint64_t zip : 1; 1355 uint64_t rng : 1; 1356 uint64_t illegal2 : 3; 1357 uint64_t pow : 1; 1358 uint64_t illegal : 19; 1359 uint64_t reserved_32_63 : 32; 1360#endif 1361 } cn31xx; 1362 struct cvmx_tra_filt_did_cn31xx cn38xx; 1363 struct cvmx_tra_filt_did_cn31xx cn38xxp2; 1364 struct cvmx_tra_filt_did_cn31xx cn52xx; 1365 struct cvmx_tra_filt_did_cn31xx cn52xxp1; 1366 struct cvmx_tra_filt_did_cn31xx cn56xx; 1367 struct cvmx_tra_filt_did_cn31xx cn56xxp1; 1368 struct cvmx_tra_filt_did_cn31xx cn58xx; 1369 struct cvmx_tra_filt_did_cn31xx cn58xxp1; 1370 struct cvmx_tra_filt_did_cn63xx 1371 { 1372#if __BYTE_ORDER == __BIG_ENDIAN 1373 uint64_t reserved_32_63 : 32; 1374 uint64_t illegal5 : 1; /**< Illegal destinations */ 1375 uint64_t fau : 1; /**< Enable tracing of FAU accesses */ 1376 uint64_t illegal4 : 2; /**< Illegal destinations */ 1377 uint64_t dpi : 1; /**< Enable tracing of DPI accesses 1378 (DPI NCB CSRs) */ 1379 uint64_t illegal : 12; /**< Illegal destinations */ 1380 uint64_t rad : 1; /**< Enable tracing of RAD accesses 1381 (doorbells) */ 1382 uint64_t usb0 : 1; /**< Enable tracing of USB0 accesses 1383 (UAHC0 EHCI and OHCI NCB CSRs) */ 1384 uint64_t pow : 1; /**< Enable tracing of requests to POW 1385 (get work, add work, status/memory/index 1386 loads, NULLRd loads, CSR's) */ 1387 uint64_t illegal2 : 1; /**< Illegal destination */ 1388 uint64_t pko : 1; /**< Enable tracing of PKO accesses 1389 (doorbells) */ 1390 uint64_t ipd : 1; /**< Enable tracing of IPD CSR accesses 1391 (IPD CSRs) */ 1392 uint64_t rng : 1; /**< Enable tracing of requests to RNG 1393 (loads/IOBDMA's are legal) */ 1394 uint64_t zip : 1; /**< Enable tracing of requests to ZIP 1395 (doorbell stores are legal) */ 1396 uint64_t dfa : 1; /**< Enable tracing of requests to DFA 1397 (CSR's and operations are legal) */ 1398 uint64_t fpa : 1; /**< Enable tracing of requests to FPA 1399 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 1400 uint64_t key : 1; /**< Enable tracing of requests to KEY memory 1401 (loads/IOBDMA's/stores are legal) */ 1402 uint64_t sli : 1; /**< Enable tracing of requests to SLI and RSL-type 1403 CSR's (RSL CSR's, PCI/sRIO bus operations, SLI 1404 CSR's) */ 1405 uint64_t illegal3 : 2; /**< Illegal destinations */ 1406 uint64_t mio : 1; /**< Enable tracing of MIO accesses 1407 (CIU and GPIO CSR's, boot bus accesses) */ 1408#else 1409 uint64_t mio : 1; 1410 uint64_t illegal3 : 2; 1411 uint64_t sli : 1; 1412 uint64_t key : 1; 1413 uint64_t fpa : 1; 1414 uint64_t dfa : 1; 1415 uint64_t zip : 1; 1416 uint64_t rng : 1; 1417 uint64_t ipd : 1; 1418 uint64_t pko : 1; 1419 uint64_t illegal2 : 1; 1420 uint64_t pow : 1; 1421 uint64_t usb0 : 1; 1422 uint64_t rad : 1; 1423 uint64_t illegal : 12; 1424 uint64_t dpi : 1; 1425 uint64_t illegal4 : 2; 1426 uint64_t fau : 1; 1427 uint64_t illegal5 : 1; 1428 uint64_t reserved_32_63 : 32; 1429#endif 1430 } cn63xx; 1431 struct cvmx_tra_filt_did_cn63xx cn63xxp1; 1432}; 1433typedef union cvmx_tra_filt_did cvmx_tra_filt_did_t; 1434 1435/** 1436 * cvmx_tra_filt_sid 1437 * 1438 * TRA_FILT_SID = Trace Buffer Filter SourceId Mask 1439 * 1440 * Description: 1441 */ 1442union cvmx_tra_filt_sid 1443{ 1444 uint64_t u64; 1445 struct cvmx_tra_filt_sid_s 1446 { 1447#if __BYTE_ORDER == __BIG_ENDIAN 1448 uint64_t reserved_20_63 : 44; 1449 uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1450 uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1451 PCI,ZIP,POW, and PKO (writes) */ 1452 uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1453 uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1454 uint64_t pp : 16; /**< Enable tracing from PP[N] with matching SourceID 1455 0=disable, 1=enableper bit N where 0<=N<=15 */ 1456#else 1457 uint64_t pp : 16; 1458 uint64_t pki : 1; 1459 uint64_t pko : 1; 1460 uint64_t iobreq : 1; 1461 uint64_t dwb : 1; 1462 uint64_t reserved_20_63 : 44; 1463#endif 1464 } s; 1465 struct cvmx_tra_filt_sid_s cn31xx; 1466 struct cvmx_tra_filt_sid_s cn38xx; 1467 struct cvmx_tra_filt_sid_s cn38xxp2; 1468 struct cvmx_tra_filt_sid_s cn52xx; 1469 struct cvmx_tra_filt_sid_s cn52xxp1; 1470 struct cvmx_tra_filt_sid_s cn56xx; 1471 struct cvmx_tra_filt_sid_s cn56xxp1; 1472 struct cvmx_tra_filt_sid_s cn58xx; 1473 struct cvmx_tra_filt_sid_s cn58xxp1; 1474 struct cvmx_tra_filt_sid_cn63xx 1475 { 1476#if __BYTE_ORDER == __BIG_ENDIAN 1477 uint64_t reserved_20_63 : 44; 1478 uint64_t dwb : 1; /**< Enable tracing of requests from the IOB DWB engine */ 1479 uint64_t iobreq : 1; /**< Enable tracing of requests from FPA,TIM,DFA, 1480 PCI,ZIP,POW, and PKO (writes) */ 1481 uint64_t pko : 1; /**< Enable tracing of read requests from PKO */ 1482 uint64_t pki : 1; /**< Enable tracing of write requests from PIP/IPD */ 1483 uint64_t reserved_8_15 : 8; 1484 uint64_t pp : 8; /**< Enable tracing from PP[N] with matching SourceID 1485 0=disable, 1=enableper bit N where 0<=N<=15 */ 1486#else 1487 uint64_t pp : 8; 1488 uint64_t reserved_8_15 : 8; 1489 uint64_t pki : 1; 1490 uint64_t pko : 1; 1491 uint64_t iobreq : 1; 1492 uint64_t dwb : 1; 1493 uint64_t reserved_20_63 : 44; 1494#endif 1495 } cn63xx; 1496 struct cvmx_tra_filt_sid_cn63xx cn63xxp1; 1497}; 1498typedef union cvmx_tra_filt_sid cvmx_tra_filt_sid_t; 1499 1500/** 1501 * cvmx_tra_int_status 1502 * 1503 * TRA_INT_STATUS = Trace Buffer Interrupt Status 1504 * 1505 * Description: 1506 * 1507 * Notes: 1508 * During a CSR write to this register, the write data is used as a mask to clear the selected status 1509 * bits (status'[3:0] = status[3:0] & ~write_data[3:0]). 1510 */ 1511union cvmx_tra_int_status 1512{ 1513 uint64_t u64; 1514 struct cvmx_tra_int_status_s 1515 { 1516#if __BYTE_ORDER == __BIG_ENDIAN 1517 uint64_t reserved_4_63 : 60; 1518 uint64_t mcd0_thr : 1; /**< MCD0 full threshold interrupt status 1519 0=trace buffer did not generate MCD0 wire pulse 1520 1=trace buffer did generate MCD0 wire pulse 1521 and prevents additional MCD0_THR MCD0 wire pulses */ 1522 uint64_t mcd0_trg : 1; /**< MCD0 end trigger interrupt status 1523 0=trace buffer did not generate interrupt 1524 1=trace buffer did generate interrupt 1525 and prevents additional MCD0_TRG MCD0 wire pulses */ 1526 uint64_t ciu_thr : 1; /**< CIU full threshold interrupt status 1527 0=trace buffer did not generate interrupt 1528 1=trace buffer did generate interrupt */ 1529 uint64_t ciu_trg : 1; /**< CIU end trigger interrupt status 1530 0=trace buffer did not generate interrupt 1531 1=trace buffer did generate interrupt */ 1532#else 1533 uint64_t ciu_trg : 1; 1534 uint64_t ciu_thr : 1; 1535 uint64_t mcd0_trg : 1; 1536 uint64_t mcd0_thr : 1; 1537 uint64_t reserved_4_63 : 60; 1538#endif 1539 } s; 1540 struct cvmx_tra_int_status_s cn31xx; 1541 struct cvmx_tra_int_status_s cn38xx; 1542 struct cvmx_tra_int_status_s cn38xxp2; 1543 struct cvmx_tra_int_status_s cn52xx; 1544 struct cvmx_tra_int_status_s cn52xxp1; 1545 struct cvmx_tra_int_status_s cn56xx; 1546 struct cvmx_tra_int_status_s cn56xxp1; 1547 struct cvmx_tra_int_status_s cn58xx; 1548 struct cvmx_tra_int_status_s cn58xxp1; 1549 struct cvmx_tra_int_status_s cn63xx; 1550 struct cvmx_tra_int_status_s cn63xxp1; 1551}; 1552typedef union cvmx_tra_int_status cvmx_tra_int_status_t; 1553 1554/** 1555 * cvmx_tra_read_dat 1556 * 1557 * TRA_READ_DAT = Trace Buffer Read Data 1558 * 1559 * Description: 1560 * 1561 * Notes: 1562 * This CSR is a memory of 1024 entries. When the trace was enabled, the read pointer was set to entry 1563 * 0 by hardware. Each read to this address increments the read pointer. 1564 */ 1565union cvmx_tra_read_dat 1566{ 1567 uint64_t u64; 1568 struct cvmx_tra_read_dat_s 1569 { 1570#if __BYTE_ORDER == __BIG_ENDIAN 1571 uint64_t data : 64; /**< Trace buffer data for current entry */ 1572#else 1573 uint64_t data : 64; 1574#endif 1575 } s; 1576 struct cvmx_tra_read_dat_s cn31xx; 1577 struct cvmx_tra_read_dat_s cn38xx; 1578 struct cvmx_tra_read_dat_s cn38xxp2; 1579 struct cvmx_tra_read_dat_s cn52xx; 1580 struct cvmx_tra_read_dat_s cn52xxp1; 1581 struct cvmx_tra_read_dat_s cn56xx; 1582 struct cvmx_tra_read_dat_s cn56xxp1; 1583 struct cvmx_tra_read_dat_s cn58xx; 1584 struct cvmx_tra_read_dat_s cn58xxp1; 1585 struct cvmx_tra_read_dat_s cn63xx; 1586 struct cvmx_tra_read_dat_s cn63xxp1; 1587}; 1588typedef union cvmx_tra_read_dat cvmx_tra_read_dat_t; 1589 1590/** 1591 * cvmx_tra_read_dat_hi 1592 * 1593 * TRA_READ_DAT_HI = Trace Buffer Read Data- upper 5 bits do not use if TRA_CTL[16]==0 1594 * 1595 * Description: 1596 * 1597 * Notes: 1598 * This CSR is a memory of 1024 entries. Reads to this address do not increment the read pointer. The 1599 * 5 bits read are the upper 5 bits of the TRA entry last read by the TRA_READ_DAT reg. 1600 */ 1601union cvmx_tra_read_dat_hi 1602{ 1603 uint64_t u64; 1604 struct cvmx_tra_read_dat_hi_s 1605 { 1606#if __BYTE_ORDER == __BIG_ENDIAN 1607 uint64_t reserved_5_63 : 59; 1608 uint64_t data : 5; /**< Trace buffer data[68:64] for current entry */ 1609#else 1610 uint64_t data : 5; 1611 uint64_t reserved_5_63 : 59; 1612#endif 1613 } s; 1614 struct cvmx_tra_read_dat_hi_s cn63xx; 1615}; 1616typedef union cvmx_tra_read_dat_hi cvmx_tra_read_dat_hi_t; 1617 1618/** 1619 * cvmx_tra_trig0_adr_adr 1620 * 1621 * TRA_TRIG0_ADR_ADR = Trace Buffer Filter Address Address 1622 * 1623 * Description: 1624 */ 1625union cvmx_tra_trig0_adr_adr 1626{ 1627 uint64_t u64; 1628 struct cvmx_tra_trig0_adr_adr_s 1629 { 1630#if __BYTE_ORDER == __BIG_ENDIAN 1631 uint64_t reserved_38_63 : 26; 1632 uint64_t adr : 38; /**< Unmasked Address 1633 The combination of TRA_TRIG0_ADR_ADR and 1634 TRA_TRIG0_ADR_MSK is a masked address to 1635 enable tracing of only those commands whose 1636 masked address matches */ 1637#else 1638 uint64_t adr : 38; 1639 uint64_t reserved_38_63 : 26; 1640#endif 1641 } s; 1642 struct cvmx_tra_trig0_adr_adr_cn31xx 1643 { 1644#if __BYTE_ORDER == __BIG_ENDIAN 1645 uint64_t reserved_36_63 : 28; 1646 uint64_t adr : 36; /**< Unmasked Address 1647 The combination of TRA_TRIG0_ADR_ADR and 1648 TRA_TRIG0_ADR_MSK is a masked address to 1649 enable tracing of only those commands whose 1650 masked address matches */ 1651#else 1652 uint64_t adr : 36; 1653 uint64_t reserved_36_63 : 28; 1654#endif 1655 } cn31xx; 1656 struct cvmx_tra_trig0_adr_adr_cn31xx cn38xx; 1657 struct cvmx_tra_trig0_adr_adr_cn31xx cn38xxp2; 1658 struct cvmx_tra_trig0_adr_adr_cn31xx cn52xx; 1659 struct cvmx_tra_trig0_adr_adr_cn31xx cn52xxp1; 1660 struct cvmx_tra_trig0_adr_adr_cn31xx cn56xx; 1661 struct cvmx_tra_trig0_adr_adr_cn31xx cn56xxp1; 1662 struct cvmx_tra_trig0_adr_adr_cn31xx cn58xx; 1663 struct cvmx_tra_trig0_adr_adr_cn31xx cn58xxp1; 1664 struct cvmx_tra_trig0_adr_adr_s cn63xx; 1665 struct cvmx_tra_trig0_adr_adr_s cn63xxp1; 1666}; 1667typedef union cvmx_tra_trig0_adr_adr cvmx_tra_trig0_adr_adr_t; 1668 1669/** 1670 * cvmx_tra_trig0_adr_msk 1671 * 1672 * TRA_TRIG0_ADR_MSK = Trace Buffer Filter Address Mask 1673 * 1674 * Description: 1675 */ 1676union cvmx_tra_trig0_adr_msk 1677{ 1678 uint64_t u64; 1679 struct cvmx_tra_trig0_adr_msk_s 1680 { 1681#if __BYTE_ORDER == __BIG_ENDIAN 1682 uint64_t reserved_38_63 : 26; 1683 uint64_t adr : 38; /**< Address Mask 1684 The combination of TRA_TRIG0_ADR_ADR and 1685 TRA_TRIG0_ADR_MSK is a masked address to 1686 enable tracing of only those commands whose 1687 masked address matches. When a mask bit is not 1688 set, the corresponding address bits are assumed 1689 to match. Also, note that IOBDMAs do not have 1690 proper addresses, so when TRA_TRIG0_CMD[IOBDMA] 1691 is set, TRA_FILT_TRIG0_MSK must be zero to 1692 guarantee that any IOBDMAs are recognized as 1693 triggers. */ 1694#else 1695 uint64_t adr : 38; 1696 uint64_t reserved_38_63 : 26; 1697#endif 1698 } s; 1699 struct cvmx_tra_trig0_adr_msk_cn31xx 1700 { 1701#if __BYTE_ORDER == __BIG_ENDIAN 1702 uint64_t reserved_36_63 : 28; 1703 uint64_t adr : 36; /**< Address Mask 1704 The combination of TRA_TRIG0_ADR_ADR and 1705 TRA_TRIG0_ADR_MSK is a masked address to 1706 enable tracing of only those commands whose 1707 masked address matches. When a mask bit is not 1708 set, the corresponding address bits are assumed 1709 to match. Also, note that IOBDMAs do not have 1710 proper addresses, so when TRA_TRIG0_CMD[IOBDMA] 1711 is set, TRA_FILT_TRIG0_MSK must be zero to 1712 guarantee that any IOBDMAs are recognized as 1713 triggers. */ 1714#else 1715 uint64_t adr : 36; 1716 uint64_t reserved_36_63 : 28; 1717#endif 1718 } cn31xx; 1719 struct cvmx_tra_trig0_adr_msk_cn31xx cn38xx; 1720 struct cvmx_tra_trig0_adr_msk_cn31xx cn38xxp2; 1721 struct cvmx_tra_trig0_adr_msk_cn31xx cn52xx; 1722 struct cvmx_tra_trig0_adr_msk_cn31xx cn52xxp1; 1723 struct cvmx_tra_trig0_adr_msk_cn31xx cn56xx; 1724 struct cvmx_tra_trig0_adr_msk_cn31xx cn56xxp1; 1725 struct cvmx_tra_trig0_adr_msk_cn31xx cn58xx; 1726 struct cvmx_tra_trig0_adr_msk_cn31xx cn58xxp1; 1727 struct cvmx_tra_trig0_adr_msk_s cn63xx; 1728 struct cvmx_tra_trig0_adr_msk_s cn63xxp1; 1729}; 1730typedef union cvmx_tra_trig0_adr_msk cvmx_tra_trig0_adr_msk_t; 1731 1732/** 1733 * cvmx_tra_trig0_cmd 1734 * 1735 * TRA_TRIG0_CMD = Trace Buffer Filter Command Mask 1736 * 1737 * Description: 1738 * 1739 * Notes: 1740 * Note that the trace buffer does not do proper IOBDMA address compares. Thus, if IOBDMA is set, then 1741 * the address compare must be disabled (i.e. TRA_TRIG0_ADR_MSK set to zero) to guarantee that IOBDMAs 1742 * are recognized as triggers. 1743 */ 1744union cvmx_tra_trig0_cmd 1745{ 1746 uint64_t u64; 1747 struct cvmx_tra_trig0_cmd_s 1748 { 1749#if __BYTE_ORDER == __BIG_ENDIAN 1750 uint64_t saa64 : 1; /**< Enable SAA64 tracing 1751 0=disable, 1=enable */ 1752 uint64_t saa32 : 1; /**< Enable SAA32 tracing 1753 0=disable, 1=enable */ 1754 uint64_t reserved_60_61 : 2; 1755 uint64_t faa64 : 1; /**< Enable FAA64 tracing 1756 0=disable, 1=enable */ 1757 uint64_t faa32 : 1; /**< Enable FAA32 tracing 1758 0=disable, 1=enable */ 1759 uint64_t reserved_56_57 : 2; 1760 uint64_t decr64 : 1; /**< Enable DECR64 tracing 1761 0=disable, 1=enable */ 1762 uint64_t decr32 : 1; /**< Enable DECR32 tracing 1763 0=disable, 1=enable */ 1764 uint64_t decr16 : 1; /**< Enable DECR16 tracing 1765 0=disable, 1=enable */ 1766 uint64_t decr8 : 1; /**< Enable DECR8 tracing 1767 0=disable, 1=enable */ 1768 uint64_t incr64 : 1; /**< Enable INCR64 tracing 1769 0=disable, 1=enable */ 1770 uint64_t incr32 : 1; /**< Enable INCR32 tracing 1771 0=disable, 1=enable */ 1772 uint64_t incr16 : 1; /**< Enable INCR16 tracing 1773 0=disable, 1=enable */ 1774 uint64_t incr8 : 1; /**< Enable INCR8 tracing 1775 0=disable, 1=enable */ 1776 uint64_t clr64 : 1; /**< Enable CLR64 tracing 1777 0=disable, 1=enable */ 1778 uint64_t clr32 : 1; /**< Enable CLR32 tracing 1779 0=disable, 1=enable */ 1780 uint64_t clr16 : 1; /**< Enable CLR16 tracing 1781 0=disable, 1=enable */ 1782 uint64_t clr8 : 1; /**< Enable CLR8 tracing 1783 0=disable, 1=enable */ 1784 uint64_t set64 : 1; /**< Enable SET64 tracing 1785 0=disable, 1=enable */ 1786 uint64_t set32 : 1; /**< Enable SET32 tracing 1787 0=disable, 1=enable */ 1788 uint64_t set16 : 1; /**< Enable SET16 tracing 1789 0=disable, 1=enable */ 1790 uint64_t set8 : 1; /**< Enable SET8 tracing 1791 0=disable, 1=enable */ 1792 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 1793 0=disable, 1=enable */ 1794 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 1795 0=disable, 1=enable */ 1796 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 1797 0=disable, 1=enable */ 1798 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 1799 0=disable, 1=enable */ 1800 uint64_t reserved_32_35 : 4; 1801 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 1802 0=disable, 1=enable */ 1803 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 1804 0=disable, 1=enable */ 1805 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 1806 0=disable, 1=enable */ 1807 uint64_t invl2 : 1; /**< Enable INVL2 tracing 1808 0=disable, 1=enable */ 1809 uint64_t reserved_27_27 : 1; 1810 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 1811 0=disable, 1=enable */ 1812 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 1813 0=disable, 1=enable */ 1814 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 1815 0=disable, 1=enable */ 1816 uint64_t fas64 : 1; /**< Enable FAS64 tracing 1817 0=disable, 1=enable */ 1818 uint64_t fas32 : 1; /**< Enable FAS32 tracing 1819 0=disable, 1=enable */ 1820 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 1821 0=disable, 1=enable */ 1822 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 1823 0=disable, 1=enable */ 1824 uint64_t reserved_16_19 : 4; 1825 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1826 0=disable, 1=enable */ 1827 uint64_t iobst : 1; /**< Enable IOBST tracing 1828 0=disable, 1=enable */ 1829 uint64_t reserved_0_13 : 14; 1830#else 1831 uint64_t reserved_0_13 : 14; 1832 uint64_t iobst : 1; 1833 uint64_t iobdma : 1; 1834 uint64_t reserved_16_19 : 4; 1835 uint64_t stfil1 : 1; 1836 uint64_t sttil1 : 1; 1837 uint64_t fas32 : 1; 1838 uint64_t fas64 : 1; 1839 uint64_t wbil2i : 1; 1840 uint64_t ltgl2i : 1; 1841 uint64_t stgl2i : 1; 1842 uint64_t reserved_27_27 : 1; 1843 uint64_t invl2 : 1; 1844 uint64_t wbil2 : 1; 1845 uint64_t wbl2 : 1; 1846 uint64_t lckl2 : 1; 1847 uint64_t reserved_32_35 : 4; 1848 uint64_t iobst8 : 1; 1849 uint64_t iobst16 : 1; 1850 uint64_t iobst32 : 1; 1851 uint64_t iobst64 : 1; 1852 uint64_t set8 : 1; 1853 uint64_t set16 : 1; 1854 uint64_t set32 : 1; 1855 uint64_t set64 : 1; 1856 uint64_t clr8 : 1; 1857 uint64_t clr16 : 1; 1858 uint64_t clr32 : 1; 1859 uint64_t clr64 : 1; 1860 uint64_t incr8 : 1; 1861 uint64_t incr16 : 1; 1862 uint64_t incr32 : 1; 1863 uint64_t incr64 : 1; 1864 uint64_t decr8 : 1; 1865 uint64_t decr16 : 1; 1866 uint64_t decr32 : 1; 1867 uint64_t decr64 : 1; 1868 uint64_t reserved_56_57 : 2; 1869 uint64_t faa32 : 1; 1870 uint64_t faa64 : 1; 1871 uint64_t reserved_60_61 : 2; 1872 uint64_t saa32 : 1; 1873 uint64_t saa64 : 1; 1874#endif 1875 } s; 1876 struct cvmx_tra_trig0_cmd_cn31xx 1877 { 1878#if __BYTE_ORDER == __BIG_ENDIAN 1879 uint64_t reserved_16_63 : 48; 1880 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1881 0=disable, 1=enable */ 1882 uint64_t iobst : 1; /**< Enable IOBST tracing 1883 0=disable, 1=enable */ 1884 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 1885 0=disable, 1=enable */ 1886 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 1887 0=disable, 1=enable */ 1888 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 1889 0=disable, 1=enable */ 1890 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 1891 0=disable, 1=enable */ 1892 uint64_t stt : 1; /**< Enable STT tracing 1893 0=disable, 1=enable */ 1894 uint64_t stp : 1; /**< Enable STP tracing 1895 0=disable, 1=enable */ 1896 uint64_t stc : 1; /**< Enable STC tracing 1897 0=disable, 1=enable */ 1898 uint64_t stf : 1; /**< Enable STF tracing 1899 0=disable, 1=enable */ 1900 uint64_t ldt : 1; /**< Enable LDT tracing 1901 0=disable, 1=enable */ 1902 uint64_t ldi : 1; /**< Enable LDI tracing 1903 0=disable, 1=enable */ 1904 uint64_t ldd : 1; /**< Enable LDD tracing 1905 0=disable, 1=enable */ 1906 uint64_t psl1 : 1; /**< Enable PSL1 tracing 1907 0=disable, 1=enable */ 1908 uint64_t pl2 : 1; /**< Enable PL2 tracing 1909 0=disable, 1=enable */ 1910 uint64_t dwb : 1; /**< Enable DWB tracing 1911 0=disable, 1=enable */ 1912#else 1913 uint64_t dwb : 1; 1914 uint64_t pl2 : 1; 1915 uint64_t psl1 : 1; 1916 uint64_t ldd : 1; 1917 uint64_t ldi : 1; 1918 uint64_t ldt : 1; 1919 uint64_t stf : 1; 1920 uint64_t stc : 1; 1921 uint64_t stp : 1; 1922 uint64_t stt : 1; 1923 uint64_t iobld8 : 1; 1924 uint64_t iobld16 : 1; 1925 uint64_t iobld32 : 1; 1926 uint64_t iobld64 : 1; 1927 uint64_t iobst : 1; 1928 uint64_t iobdma : 1; 1929 uint64_t reserved_16_63 : 48; 1930#endif 1931 } cn31xx; 1932 struct cvmx_tra_trig0_cmd_cn31xx cn38xx; 1933 struct cvmx_tra_trig0_cmd_cn31xx cn38xxp2; 1934 struct cvmx_tra_trig0_cmd_cn52xx 1935 { 1936#if __BYTE_ORDER == __BIG_ENDIAN 1937 uint64_t reserved_17_63 : 47; 1938 uint64_t saa : 1; /**< Enable SAA tracing 1939 0=disable, 1=enable */ 1940 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 1941 0=disable, 1=enable */ 1942 uint64_t iobst : 1; /**< Enable IOBST tracing 1943 0=disable, 1=enable */ 1944 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 1945 0=disable, 1=enable */ 1946 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 1947 0=disable, 1=enable */ 1948 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 1949 0=disable, 1=enable */ 1950 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 1951 0=disable, 1=enable */ 1952 uint64_t stt : 1; /**< Enable STT tracing 1953 0=disable, 1=enable */ 1954 uint64_t stp : 1; /**< Enable STP tracing 1955 0=disable, 1=enable */ 1956 uint64_t stc : 1; /**< Enable STC tracing 1957 0=disable, 1=enable */ 1958 uint64_t stf : 1; /**< Enable STF tracing 1959 0=disable, 1=enable */ 1960 uint64_t ldt : 1; /**< Enable LDT tracing 1961 0=disable, 1=enable */ 1962 uint64_t ldi : 1; /**< Enable LDI tracing 1963 0=disable, 1=enable */ 1964 uint64_t ldd : 1; /**< Enable LDD tracing 1965 0=disable, 1=enable */ 1966 uint64_t psl1 : 1; /**< Enable PSL1 tracing 1967 0=disable, 1=enable */ 1968 uint64_t pl2 : 1; /**< Enable PL2 tracing 1969 0=disable, 1=enable */ 1970 uint64_t dwb : 1; /**< Enable DWB tracing 1971 0=disable, 1=enable */ 1972#else 1973 uint64_t dwb : 1; 1974 uint64_t pl2 : 1; 1975 uint64_t psl1 : 1; 1976 uint64_t ldd : 1; 1977 uint64_t ldi : 1; 1978 uint64_t ldt : 1; 1979 uint64_t stf : 1; 1980 uint64_t stc : 1; 1981 uint64_t stp : 1; 1982 uint64_t stt : 1; 1983 uint64_t iobld8 : 1; 1984 uint64_t iobld16 : 1; 1985 uint64_t iobld32 : 1; 1986 uint64_t iobld64 : 1; 1987 uint64_t iobst : 1; 1988 uint64_t iobdma : 1; 1989 uint64_t saa : 1; 1990 uint64_t reserved_17_63 : 47; 1991#endif 1992 } cn52xx; 1993 struct cvmx_tra_trig0_cmd_cn52xx cn52xxp1; 1994 struct cvmx_tra_trig0_cmd_cn52xx cn56xx; 1995 struct cvmx_tra_trig0_cmd_cn52xx cn56xxp1; 1996 struct cvmx_tra_trig0_cmd_cn52xx cn58xx; 1997 struct cvmx_tra_trig0_cmd_cn52xx cn58xxp1; 1998 struct cvmx_tra_trig0_cmd_cn63xx 1999 { 2000#if __BYTE_ORDER == __BIG_ENDIAN 2001 uint64_t saa64 : 1; /**< Enable SAA64 tracing 2002 0=disable, 1=enable */ 2003 uint64_t saa32 : 1; /**< Enable SAA32 tracing 2004 0=disable, 1=enable */ 2005 uint64_t reserved_60_61 : 2; 2006 uint64_t faa64 : 1; /**< Enable FAA64 tracing 2007 0=disable, 1=enable */ 2008 uint64_t faa32 : 1; /**< Enable FAA32 tracing 2009 0=disable, 1=enable */ 2010 uint64_t reserved_56_57 : 2; 2011 uint64_t decr64 : 1; /**< Enable DECR64 tracing 2012 0=disable, 1=enable */ 2013 uint64_t decr32 : 1; /**< Enable DECR32 tracing 2014 0=disable, 1=enable */ 2015 uint64_t decr16 : 1; /**< Enable DECR16 tracing 2016 0=disable, 1=enable */ 2017 uint64_t decr8 : 1; /**< Enable DECR8 tracing 2018 0=disable, 1=enable */ 2019 uint64_t incr64 : 1; /**< Enable INCR64 tracing 2020 0=disable, 1=enable */ 2021 uint64_t incr32 : 1; /**< Enable INCR32 tracing 2022 0=disable, 1=enable */ 2023 uint64_t incr16 : 1; /**< Enable INCR16 tracing 2024 0=disable, 1=enable */ 2025 uint64_t incr8 : 1; /**< Enable INCR8 tracing 2026 0=disable, 1=enable */ 2027 uint64_t clr64 : 1; /**< Enable CLR64 tracing 2028 0=disable, 1=enable */ 2029 uint64_t clr32 : 1; /**< Enable CLR32 tracing 2030 0=disable, 1=enable */ 2031 uint64_t clr16 : 1; /**< Enable CLR16 tracing 2032 0=disable, 1=enable */ 2033 uint64_t clr8 : 1; /**< Enable CLR8 tracing 2034 0=disable, 1=enable */ 2035 uint64_t set64 : 1; /**< Enable SET64 tracing 2036 0=disable, 1=enable */ 2037 uint64_t set32 : 1; /**< Enable SET32 tracing 2038 0=disable, 1=enable */ 2039 uint64_t set16 : 1; /**< Enable SET16 tracing 2040 0=disable, 1=enable */ 2041 uint64_t set8 : 1; /**< Enable SET8 tracing 2042 0=disable, 1=enable */ 2043 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 2044 0=disable, 1=enable */ 2045 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 2046 0=disable, 1=enable */ 2047 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 2048 0=disable, 1=enable */ 2049 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 2050 0=disable, 1=enable */ 2051 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 2052 0=disable, 1=enable */ 2053 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 2054 0=disable, 1=enable */ 2055 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 2056 0=disable, 1=enable */ 2057 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 2058 0=disable, 1=enable */ 2059 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 2060 0=disable, 1=enable */ 2061 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 2062 0=disable, 1=enable */ 2063 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 2064 0=disable, 1=enable */ 2065 uint64_t invl2 : 1; /**< Enable INVL2 tracing 2066 0=disable, 1=enable */ 2067 uint64_t reserved_27_27 : 1; 2068 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 2069 0=disable, 1=enable */ 2070 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 2071 0=disable, 1=enable */ 2072 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 2073 0=disable, 1=enable */ 2074 uint64_t fas64 : 1; /**< Enable FAS64 tracing 2075 0=disable, 1=enable */ 2076 uint64_t fas32 : 1; /**< Enable FAS32 tracing 2077 0=disable, 1=enable */ 2078 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 2079 0=disable, 1=enable */ 2080 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 2081 0=disable, 1=enable */ 2082 uint64_t stc : 1; /**< Enable STC tracing 2083 0=disable, 1=enable */ 2084 uint64_t stp : 1; /**< Enable STP tracing 2085 0=disable, 1=enable */ 2086 uint64_t stt : 1; /**< Enable STT tracing 2087 0=disable, 1=enable */ 2088 uint64_t stf : 1; /**< Enable STF tracing 2089 0=disable, 1=enable */ 2090 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2091 0=disable, 1=enable */ 2092 uint64_t reserved_10_14 : 5; 2093 uint64_t psl1 : 1; /**< Enable PSL1 tracing 2094 0=disable, 1=enable */ 2095 uint64_t ldd : 1; /**< Enable LDD tracing 2096 0=disable, 1=enable */ 2097 uint64_t reserved_6_7 : 2; 2098 uint64_t dwb : 1; /**< Enable DWB tracing 2099 0=disable, 1=enable */ 2100 uint64_t rpl2 : 1; /**< Enable RPL2 tracing 2101 0=disable, 1=enable */ 2102 uint64_t pl2 : 1; /**< Enable PL2 tracing 2103 0=disable, 1=enable */ 2104 uint64_t ldi : 1; /**< Enable LDI tracing 2105 0=disable, 1=enable */ 2106 uint64_t ldt : 1; /**< Enable LDT tracing 2107 0=disable, 1=enable */ 2108 uint64_t nop : 1; /**< Enable NOP tracing 2109 0=disable, 1=enable */ 2110#else 2111 uint64_t nop : 1; 2112 uint64_t ldt : 1; 2113 uint64_t ldi : 1; 2114 uint64_t pl2 : 1; 2115 uint64_t rpl2 : 1; 2116 uint64_t dwb : 1; 2117 uint64_t reserved_6_7 : 2; 2118 uint64_t ldd : 1; 2119 uint64_t psl1 : 1; 2120 uint64_t reserved_10_14 : 5; 2121 uint64_t iobdma : 1; 2122 uint64_t stf : 1; 2123 uint64_t stt : 1; 2124 uint64_t stp : 1; 2125 uint64_t stc : 1; 2126 uint64_t stfil1 : 1; 2127 uint64_t sttil1 : 1; 2128 uint64_t fas32 : 1; 2129 uint64_t fas64 : 1; 2130 uint64_t wbil2i : 1; 2131 uint64_t ltgl2i : 1; 2132 uint64_t stgl2i : 1; 2133 uint64_t reserved_27_27 : 1; 2134 uint64_t invl2 : 1; 2135 uint64_t wbil2 : 1; 2136 uint64_t wbl2 : 1; 2137 uint64_t lckl2 : 1; 2138 uint64_t iobld8 : 1; 2139 uint64_t iobld16 : 1; 2140 uint64_t iobld32 : 1; 2141 uint64_t iobld64 : 1; 2142 uint64_t iobst8 : 1; 2143 uint64_t iobst16 : 1; 2144 uint64_t iobst32 : 1; 2145 uint64_t iobst64 : 1; 2146 uint64_t set8 : 1; 2147 uint64_t set16 : 1; 2148 uint64_t set32 : 1; 2149 uint64_t set64 : 1; 2150 uint64_t clr8 : 1; 2151 uint64_t clr16 : 1; 2152 uint64_t clr32 : 1; 2153 uint64_t clr64 : 1; 2154 uint64_t incr8 : 1; 2155 uint64_t incr16 : 1; 2156 uint64_t incr32 : 1; 2157 uint64_t incr64 : 1; 2158 uint64_t decr8 : 1; 2159 uint64_t decr16 : 1; 2160 uint64_t decr32 : 1; 2161 uint64_t decr64 : 1; 2162 uint64_t reserved_56_57 : 2; 2163 uint64_t faa32 : 1; 2164 uint64_t faa64 : 1; 2165 uint64_t reserved_60_61 : 2; 2166 uint64_t saa32 : 1; 2167 uint64_t saa64 : 1; 2168#endif 2169 } cn63xx; 2170 struct cvmx_tra_trig0_cmd_cn63xx cn63xxp1; 2171}; 2172typedef union cvmx_tra_trig0_cmd cvmx_tra_trig0_cmd_t; 2173 2174/** 2175 * cvmx_tra_trig0_did 2176 * 2177 * TRA_TRIG0_DID = Trace Buffer Filter DestinationId Mask 2178 * 2179 * Description: 2180 */ 2181union cvmx_tra_trig0_did 2182{ 2183 uint64_t u64; 2184 struct cvmx_tra_trig0_did_s 2185 { 2186#if __BYTE_ORDER == __BIG_ENDIAN 2187 uint64_t reserved_13_63 : 51; 2188 uint64_t pow : 1; /**< Enable triggering on requests to POW 2189 (get work, add work, status/memory/index 2190 loads, NULLRd loads, CSR's) */ 2191 uint64_t reserved_9_11 : 3; 2192 uint64_t rng : 1; /**< Enable triggering on requests to RNG 2193 (loads/IOBDMA's are legal) */ 2194 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 2195 (doorbell stores are legal) */ 2196 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 2197 (CSR's and operations are legal) */ 2198 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 2199 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 2200 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 2201 (loads/IOBDMA's/stores are legal) */ 2202 uint64_t reserved_3_3 : 1; 2203 uint64_t illegal3 : 2; /**< Illegal destinations */ 2204 uint64_t mio : 1; /**< Enable triggering on MIO accesses 2205 (CIU and GPIO CSR's, boot bus accesses) */ 2206#else 2207 uint64_t mio : 1; 2208 uint64_t illegal3 : 2; 2209 uint64_t reserved_3_3 : 1; 2210 uint64_t key : 1; 2211 uint64_t fpa : 1; 2212 uint64_t dfa : 1; 2213 uint64_t zip : 1; 2214 uint64_t rng : 1; 2215 uint64_t reserved_9_11 : 3; 2216 uint64_t pow : 1; 2217 uint64_t reserved_13_63 : 51; 2218#endif 2219 } s; 2220 struct cvmx_tra_trig0_did_cn31xx 2221 { 2222#if __BYTE_ORDER == __BIG_ENDIAN 2223 uint64_t reserved_32_63 : 32; 2224 uint64_t illegal : 19; /**< Illegal destinations */ 2225 uint64_t pow : 1; /**< Enable triggering on requests to POW 2226 (get work, add work, status/memory/index 2227 loads, NULLRd loads, CSR's) */ 2228 uint64_t illegal2 : 3; /**< Illegal destinations */ 2229 uint64_t rng : 1; /**< Enable triggering on requests to RNG 2230 (loads/IOBDMA's are legal) */ 2231 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 2232 (doorbell stores are legal) */ 2233 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 2234 (CSR's and operations are legal) */ 2235 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 2236 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 2237 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 2238 (loads/IOBDMA's/stores are legal) */ 2239 uint64_t pci : 1; /**< Enable triggering on requests to PCI and RSL-type 2240 CSR's (RSL CSR's, PCI bus operations, PCI 2241 CSR's) */ 2242 uint64_t illegal3 : 2; /**< Illegal destinations */ 2243 uint64_t mio : 1; /**< Enable triggering on CIU and GPIO CSR's */ 2244#else 2245 uint64_t mio : 1; 2246 uint64_t illegal3 : 2; 2247 uint64_t pci : 1; 2248 uint64_t key : 1; 2249 uint64_t fpa : 1; 2250 uint64_t dfa : 1; 2251 uint64_t zip : 1; 2252 uint64_t rng : 1; 2253 uint64_t illegal2 : 3; 2254 uint64_t pow : 1; 2255 uint64_t illegal : 19; 2256 uint64_t reserved_32_63 : 32; 2257#endif 2258 } cn31xx; 2259 struct cvmx_tra_trig0_did_cn31xx cn38xx; 2260 struct cvmx_tra_trig0_did_cn31xx cn38xxp2; 2261 struct cvmx_tra_trig0_did_cn31xx cn52xx; 2262 struct cvmx_tra_trig0_did_cn31xx cn52xxp1; 2263 struct cvmx_tra_trig0_did_cn31xx cn56xx; 2264 struct cvmx_tra_trig0_did_cn31xx cn56xxp1; 2265 struct cvmx_tra_trig0_did_cn31xx cn58xx; 2266 struct cvmx_tra_trig0_did_cn31xx cn58xxp1; 2267 struct cvmx_tra_trig0_did_cn63xx 2268 { 2269#if __BYTE_ORDER == __BIG_ENDIAN 2270 uint64_t reserved_32_63 : 32; 2271 uint64_t illegal5 : 1; /**< Illegal destinations */ 2272 uint64_t fau : 1; /**< Enable triggering on FAU accesses */ 2273 uint64_t illegal4 : 2; /**< Illegal destinations */ 2274 uint64_t dpi : 1; /**< Enable triggering on DPI accesses 2275 (DPI NCB CSRs) */ 2276 uint64_t illegal : 12; /**< Illegal destinations */ 2277 uint64_t rad : 1; /**< Enable triggering on RAD accesses 2278 (doorbells) */ 2279 uint64_t usb0 : 1; /**< Enable triggering on USB0 accesses 2280 (UAHC0 EHCI and OHCI NCB CSRs) */ 2281 uint64_t pow : 1; /**< Enable triggering on requests to POW 2282 (get work, add work, status/memory/index 2283 loads, NULLRd loads, CSR's) */ 2284 uint64_t illegal2 : 1; /**< Illegal destination */ 2285 uint64_t pko : 1; /**< Enable triggering on PKO accesses 2286 (doorbells) */ 2287 uint64_t ipd : 1; /**< Enable triggering on IPD CSR accesses 2288 (IPD CSRs) */ 2289 uint64_t rng : 1; /**< Enable triggering on requests to RNG 2290 (loads/IOBDMA's are legal) */ 2291 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 2292 (doorbell stores are legal) */ 2293 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 2294 (CSR's and operations are legal) */ 2295 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 2296 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 2297 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 2298 (loads/IOBDMA's/stores are legal) */ 2299 uint64_t sli : 1; /**< Enable triggering on requests to SLI and RSL-type 2300 CSR's (RSL CSR's, PCI/sRIO bus operations, SLI 2301 CSR's) */ 2302 uint64_t illegal3 : 2; /**< Illegal destinations */ 2303 uint64_t mio : 1; /**< Enable triggering on MIO accesses 2304 (CIU and GPIO CSR's, boot bus accesses) */ 2305#else 2306 uint64_t mio : 1; 2307 uint64_t illegal3 : 2; 2308 uint64_t sli : 1; 2309 uint64_t key : 1; 2310 uint64_t fpa : 1; 2311 uint64_t dfa : 1; 2312 uint64_t zip : 1; 2313 uint64_t rng : 1; 2314 uint64_t ipd : 1; 2315 uint64_t pko : 1; 2316 uint64_t illegal2 : 1; 2317 uint64_t pow : 1; 2318 uint64_t usb0 : 1; 2319 uint64_t rad : 1; 2320 uint64_t illegal : 12; 2321 uint64_t dpi : 1; 2322 uint64_t illegal4 : 2; 2323 uint64_t fau : 1; 2324 uint64_t illegal5 : 1; 2325 uint64_t reserved_32_63 : 32; 2326#endif 2327 } cn63xx; 2328 struct cvmx_tra_trig0_did_cn63xx cn63xxp1; 2329}; 2330typedef union cvmx_tra_trig0_did cvmx_tra_trig0_did_t; 2331 2332/** 2333 * cvmx_tra_trig0_sid 2334 * 2335 * TRA_TRIG0_SID = Trace Buffer Filter SourceId Mask 2336 * 2337 * Description: 2338 */ 2339union cvmx_tra_trig0_sid 2340{ 2341 uint64_t u64; 2342 struct cvmx_tra_trig0_sid_s 2343 { 2344#if __BYTE_ORDER == __BIG_ENDIAN 2345 uint64_t reserved_20_63 : 44; 2346 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2347 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2348 PCI,ZIP,POW, and PKO (writes) */ 2349 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2350 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2351 uint64_t pp : 16; /**< Enable triggering from PP[N] with matching SourceID 2352 0=disable, 1=enableper bit N where 0<=N<=15 */ 2353#else 2354 uint64_t pp : 16; 2355 uint64_t pki : 1; 2356 uint64_t pko : 1; 2357 uint64_t iobreq : 1; 2358 uint64_t dwb : 1; 2359 uint64_t reserved_20_63 : 44; 2360#endif 2361 } s; 2362 struct cvmx_tra_trig0_sid_s cn31xx; 2363 struct cvmx_tra_trig0_sid_s cn38xx; 2364 struct cvmx_tra_trig0_sid_s cn38xxp2; 2365 struct cvmx_tra_trig0_sid_s cn52xx; 2366 struct cvmx_tra_trig0_sid_s cn52xxp1; 2367 struct cvmx_tra_trig0_sid_s cn56xx; 2368 struct cvmx_tra_trig0_sid_s cn56xxp1; 2369 struct cvmx_tra_trig0_sid_s cn58xx; 2370 struct cvmx_tra_trig0_sid_s cn58xxp1; 2371 struct cvmx_tra_trig0_sid_cn63xx 2372 { 2373#if __BYTE_ORDER == __BIG_ENDIAN 2374 uint64_t reserved_20_63 : 44; 2375 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 2376 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 2377 PCI,ZIP,POW, and PKO (writes) */ 2378 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 2379 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 2380 uint64_t reserved_8_15 : 8; 2381 uint64_t pp : 8; /**< Enable triggering from PP[N] with matching SourceID 2382 0=disable, 1=enableper bit N where 0<=N<=15 */ 2383#else 2384 uint64_t pp : 8; 2385 uint64_t reserved_8_15 : 8; 2386 uint64_t pki : 1; 2387 uint64_t pko : 1; 2388 uint64_t iobreq : 1; 2389 uint64_t dwb : 1; 2390 uint64_t reserved_20_63 : 44; 2391#endif 2392 } cn63xx; 2393 struct cvmx_tra_trig0_sid_cn63xx cn63xxp1; 2394}; 2395typedef union cvmx_tra_trig0_sid cvmx_tra_trig0_sid_t; 2396 2397/** 2398 * cvmx_tra_trig1_adr_adr 2399 * 2400 * TRA_TRIG1_ADR_ADR = Trace Buffer Filter Address Address 2401 * 2402 * Description: 2403 */ 2404union cvmx_tra_trig1_adr_adr 2405{ 2406 uint64_t u64; 2407 struct cvmx_tra_trig1_adr_adr_s 2408 { 2409#if __BYTE_ORDER == __BIG_ENDIAN 2410 uint64_t reserved_38_63 : 26; 2411 uint64_t adr : 38; /**< Unmasked Address 2412 The combination of TRA_TRIG1_ADR_ADR and 2413 TRA_TRIG1_ADR_MSK is a masked address to 2414 enable tracing of only those commands whose 2415 masked address matches */ 2416#else 2417 uint64_t adr : 38; 2418 uint64_t reserved_38_63 : 26; 2419#endif 2420 } s; 2421 struct cvmx_tra_trig1_adr_adr_cn31xx 2422 { 2423#if __BYTE_ORDER == __BIG_ENDIAN 2424 uint64_t reserved_36_63 : 28; 2425 uint64_t adr : 36; /**< Unmasked Address 2426 The combination of TRA_TRIG1_ADR_ADR and 2427 TRA_TRIG1_ADR_MSK is a masked address to 2428 enable tracing of only those commands whose 2429 masked address matches */ 2430#else 2431 uint64_t adr : 36; 2432 uint64_t reserved_36_63 : 28; 2433#endif 2434 } cn31xx; 2435 struct cvmx_tra_trig1_adr_adr_cn31xx cn38xx; 2436 struct cvmx_tra_trig1_adr_adr_cn31xx cn38xxp2; 2437 struct cvmx_tra_trig1_adr_adr_cn31xx cn52xx; 2438 struct cvmx_tra_trig1_adr_adr_cn31xx cn52xxp1; 2439 struct cvmx_tra_trig1_adr_adr_cn31xx cn56xx; 2440 struct cvmx_tra_trig1_adr_adr_cn31xx cn56xxp1; 2441 struct cvmx_tra_trig1_adr_adr_cn31xx cn58xx; 2442 struct cvmx_tra_trig1_adr_adr_cn31xx cn58xxp1; 2443 struct cvmx_tra_trig1_adr_adr_s cn63xx; 2444 struct cvmx_tra_trig1_adr_adr_s cn63xxp1; 2445}; 2446typedef union cvmx_tra_trig1_adr_adr cvmx_tra_trig1_adr_adr_t; 2447 2448/** 2449 * cvmx_tra_trig1_adr_msk 2450 * 2451 * TRA_TRIG1_ADR_MSK = Trace Buffer Filter Address Mask 2452 * 2453 * Description: 2454 */ 2455union cvmx_tra_trig1_adr_msk 2456{ 2457 uint64_t u64; 2458 struct cvmx_tra_trig1_adr_msk_s 2459 { 2460#if __BYTE_ORDER == __BIG_ENDIAN 2461 uint64_t reserved_38_63 : 26; 2462 uint64_t adr : 38; /**< Address Mask 2463 The combination of TRA_TRIG1_ADR_ADR and 2464 TRA_TRIG1_ADR_MSK is a masked address to 2465 enable tracing of only those commands whose 2466 masked address matches. When a mask bit is not 2467 set, the corresponding address bits are assumed 2468 to match. Also, note that IOBDMAs do not have 2469 proper addresses, so when TRA_TRIG1_CMD[IOBDMA] 2470 is set, TRA_FILT_TRIG1_MSK must be zero to 2471 guarantee that any IOBDMAs are recognized as 2472 triggers. */ 2473#else 2474 uint64_t adr : 38; 2475 uint64_t reserved_38_63 : 26; 2476#endif 2477 } s; 2478 struct cvmx_tra_trig1_adr_msk_cn31xx 2479 { 2480#if __BYTE_ORDER == __BIG_ENDIAN 2481 uint64_t reserved_36_63 : 28; 2482 uint64_t adr : 36; /**< Address Mask 2483 The combination of TRA_TRIG1_ADR_ADR and 2484 TRA_TRIG1_ADR_MSK is a masked address to 2485 enable tracing of only those commands whose 2486 masked address matches. When a mask bit is not 2487 set, the corresponding address bits are assumed 2488 to match. Also, note that IOBDMAs do not have 2489 proper addresses, so when TRA_TRIG1_CMD[IOBDMA] 2490 is set, TRA_FILT_TRIG1_MSK must be zero to 2491 guarantee that any IOBDMAs are recognized as 2492 triggers. */ 2493#else 2494 uint64_t adr : 36; 2495 uint64_t reserved_36_63 : 28; 2496#endif 2497 } cn31xx; 2498 struct cvmx_tra_trig1_adr_msk_cn31xx cn38xx; 2499 struct cvmx_tra_trig1_adr_msk_cn31xx cn38xxp2; 2500 struct cvmx_tra_trig1_adr_msk_cn31xx cn52xx; 2501 struct cvmx_tra_trig1_adr_msk_cn31xx cn52xxp1; 2502 struct cvmx_tra_trig1_adr_msk_cn31xx cn56xx; 2503 struct cvmx_tra_trig1_adr_msk_cn31xx cn56xxp1; 2504 struct cvmx_tra_trig1_adr_msk_cn31xx cn58xx; 2505 struct cvmx_tra_trig1_adr_msk_cn31xx cn58xxp1; 2506 struct cvmx_tra_trig1_adr_msk_s cn63xx; 2507 struct cvmx_tra_trig1_adr_msk_s cn63xxp1; 2508}; 2509typedef union cvmx_tra_trig1_adr_msk cvmx_tra_trig1_adr_msk_t; 2510 2511/** 2512 * cvmx_tra_trig1_cmd 2513 * 2514 * TRA_TRIG1_CMD = Trace Buffer Filter Command Mask 2515 * 2516 * Description: 2517 * 2518 * Notes: 2519 * Note that the trace buffer does not do proper IOBDMA address compares. Thus, if IOBDMA is set, then 2520 * the address compare must be disabled (i.e. TRA_TRIG1_ADR_MSK set to zero) to guarantee that IOBDMAs 2521 * are recognized as triggers. 2522 */ 2523union cvmx_tra_trig1_cmd 2524{ 2525 uint64_t u64; 2526 struct cvmx_tra_trig1_cmd_s 2527 { 2528#if __BYTE_ORDER == __BIG_ENDIAN 2529 uint64_t saa64 : 1; /**< Enable SAA64 tracing 2530 0=disable, 1=enable */ 2531 uint64_t saa32 : 1; /**< Enable SAA32 tracing 2532 0=disable, 1=enable */ 2533 uint64_t reserved_60_61 : 2; 2534 uint64_t faa64 : 1; /**< Enable FAA64 tracing 2535 0=disable, 1=enable */ 2536 uint64_t faa32 : 1; /**< Enable FAA32 tracing 2537 0=disable, 1=enable */ 2538 uint64_t reserved_56_57 : 2; 2539 uint64_t decr64 : 1; /**< Enable DECR64 tracing 2540 0=disable, 1=enable */ 2541 uint64_t decr32 : 1; /**< Enable DECR32 tracing 2542 0=disable, 1=enable */ 2543 uint64_t decr16 : 1; /**< Enable DECR16 tracing 2544 0=disable, 1=enable */ 2545 uint64_t decr8 : 1; /**< Enable DECR8 tracing 2546 0=disable, 1=enable */ 2547 uint64_t incr64 : 1; /**< Enable INCR64 tracing 2548 0=disable, 1=enable */ 2549 uint64_t incr32 : 1; /**< Enable INCR32 tracing 2550 0=disable, 1=enable */ 2551 uint64_t incr16 : 1; /**< Enable INCR16 tracing 2552 0=disable, 1=enable */ 2553 uint64_t incr8 : 1; /**< Enable INCR8 tracing 2554 0=disable, 1=enable */ 2555 uint64_t clr64 : 1; /**< Enable CLR64 tracing 2556 0=disable, 1=enable */ 2557 uint64_t clr32 : 1; /**< Enable CLR32 tracing 2558 0=disable, 1=enable */ 2559 uint64_t clr16 : 1; /**< Enable CLR16 tracing 2560 0=disable, 1=enable */ 2561 uint64_t clr8 : 1; /**< Enable CLR8 tracing 2562 0=disable, 1=enable */ 2563 uint64_t set64 : 1; /**< Enable SET64 tracing 2564 0=disable, 1=enable */ 2565 uint64_t set32 : 1; /**< Enable SET32 tracing 2566 0=disable, 1=enable */ 2567 uint64_t set16 : 1; /**< Enable SET16 tracing 2568 0=disable, 1=enable */ 2569 uint64_t set8 : 1; /**< Enable SET8 tracing 2570 0=disable, 1=enable */ 2571 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 2572 0=disable, 1=enable */ 2573 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 2574 0=disable, 1=enable */ 2575 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 2576 0=disable, 1=enable */ 2577 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 2578 0=disable, 1=enable */ 2579 uint64_t reserved_32_35 : 4; 2580 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 2581 0=disable, 1=enable */ 2582 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 2583 0=disable, 1=enable */ 2584 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 2585 0=disable, 1=enable */ 2586 uint64_t invl2 : 1; /**< Enable INVL2 tracing 2587 0=disable, 1=enable */ 2588 uint64_t reserved_27_27 : 1; 2589 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 2590 0=disable, 1=enable */ 2591 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 2592 0=disable, 1=enable */ 2593 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 2594 0=disable, 1=enable */ 2595 uint64_t fas64 : 1; /**< Enable FAS64 tracing 2596 0=disable, 1=enable */ 2597 uint64_t fas32 : 1; /**< Enable FAS32 tracing 2598 0=disable, 1=enable */ 2599 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 2600 0=disable, 1=enable */ 2601 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 2602 0=disable, 1=enable */ 2603 uint64_t reserved_16_19 : 4; 2604 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2605 0=disable, 1=enable */ 2606 uint64_t iobst : 1; /**< Enable IOBST tracing 2607 0=disable, 1=enable */ 2608 uint64_t reserved_0_13 : 14; 2609#else 2610 uint64_t reserved_0_13 : 14; 2611 uint64_t iobst : 1; 2612 uint64_t iobdma : 1; 2613 uint64_t reserved_16_19 : 4; 2614 uint64_t stfil1 : 1; 2615 uint64_t sttil1 : 1; 2616 uint64_t fas32 : 1; 2617 uint64_t fas64 : 1; 2618 uint64_t wbil2i : 1; 2619 uint64_t ltgl2i : 1; 2620 uint64_t stgl2i : 1; 2621 uint64_t reserved_27_27 : 1; 2622 uint64_t invl2 : 1; 2623 uint64_t wbil2 : 1; 2624 uint64_t wbl2 : 1; 2625 uint64_t lckl2 : 1; 2626 uint64_t reserved_32_35 : 4; 2627 uint64_t iobst8 : 1; 2628 uint64_t iobst16 : 1; 2629 uint64_t iobst32 : 1; 2630 uint64_t iobst64 : 1; 2631 uint64_t set8 : 1; 2632 uint64_t set16 : 1; 2633 uint64_t set32 : 1; 2634 uint64_t set64 : 1; 2635 uint64_t clr8 : 1; 2636 uint64_t clr16 : 1; 2637 uint64_t clr32 : 1; 2638 uint64_t clr64 : 1; 2639 uint64_t incr8 : 1; 2640 uint64_t incr16 : 1; 2641 uint64_t incr32 : 1; 2642 uint64_t incr64 : 1; 2643 uint64_t decr8 : 1; 2644 uint64_t decr16 : 1; 2645 uint64_t decr32 : 1; 2646 uint64_t decr64 : 1; 2647 uint64_t reserved_56_57 : 2; 2648 uint64_t faa32 : 1; 2649 uint64_t faa64 : 1; 2650 uint64_t reserved_60_61 : 2; 2651 uint64_t saa32 : 1; 2652 uint64_t saa64 : 1; 2653#endif 2654 } s; 2655 struct cvmx_tra_trig1_cmd_cn31xx 2656 { 2657#if __BYTE_ORDER == __BIG_ENDIAN 2658 uint64_t reserved_16_63 : 48; 2659 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2660 0=disable, 1=enable */ 2661 uint64_t iobst : 1; /**< Enable IOBST tracing 2662 0=disable, 1=enable */ 2663 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 2664 0=disable, 1=enable */ 2665 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 2666 0=disable, 1=enable */ 2667 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 2668 0=disable, 1=enable */ 2669 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 2670 0=disable, 1=enable */ 2671 uint64_t stt : 1; /**< Enable STT tracing 2672 0=disable, 1=enable */ 2673 uint64_t stp : 1; /**< Enable STP tracing 2674 0=disable, 1=enable */ 2675 uint64_t stc : 1; /**< Enable STC tracing 2676 0=disable, 1=enable */ 2677 uint64_t stf : 1; /**< Enable STF tracing 2678 0=disable, 1=enable */ 2679 uint64_t ldt : 1; /**< Enable LDT tracing 2680 0=disable, 1=enable */ 2681 uint64_t ldi : 1; /**< Enable LDI tracing 2682 0=disable, 1=enable */ 2683 uint64_t ldd : 1; /**< Enable LDD tracing 2684 0=disable, 1=enable */ 2685 uint64_t psl1 : 1; /**< Enable PSL1 tracing 2686 0=disable, 1=enable */ 2687 uint64_t pl2 : 1; /**< Enable PL2 tracing 2688 0=disable, 1=enable */ 2689 uint64_t dwb : 1; /**< Enable DWB tracing 2690 0=disable, 1=enable */ 2691#else 2692 uint64_t dwb : 1; 2693 uint64_t pl2 : 1; 2694 uint64_t psl1 : 1; 2695 uint64_t ldd : 1; 2696 uint64_t ldi : 1; 2697 uint64_t ldt : 1; 2698 uint64_t stf : 1; 2699 uint64_t stc : 1; 2700 uint64_t stp : 1; 2701 uint64_t stt : 1; 2702 uint64_t iobld8 : 1; 2703 uint64_t iobld16 : 1; 2704 uint64_t iobld32 : 1; 2705 uint64_t iobld64 : 1; 2706 uint64_t iobst : 1; 2707 uint64_t iobdma : 1; 2708 uint64_t reserved_16_63 : 48; 2709#endif 2710 } cn31xx; 2711 struct cvmx_tra_trig1_cmd_cn31xx cn38xx; 2712 struct cvmx_tra_trig1_cmd_cn31xx cn38xxp2; 2713 struct cvmx_tra_trig1_cmd_cn52xx 2714 { 2715#if __BYTE_ORDER == __BIG_ENDIAN 2716 uint64_t reserved_17_63 : 47; 2717 uint64_t saa : 1; /**< Enable SAA tracing 2718 0=disable, 1=enable */ 2719 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2720 0=disable, 1=enable */ 2721 uint64_t iobst : 1; /**< Enable IOBST tracing 2722 0=disable, 1=enable */ 2723 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 2724 0=disable, 1=enable */ 2725 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 2726 0=disable, 1=enable */ 2727 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 2728 0=disable, 1=enable */ 2729 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 2730 0=disable, 1=enable */ 2731 uint64_t stt : 1; /**< Enable STT tracing 2732 0=disable, 1=enable */ 2733 uint64_t stp : 1; /**< Enable STP tracing 2734 0=disable, 1=enable */ 2735 uint64_t stc : 1; /**< Enable STC tracing 2736 0=disable, 1=enable */ 2737 uint64_t stf : 1; /**< Enable STF tracing 2738 0=disable, 1=enable */ 2739 uint64_t ldt : 1; /**< Enable LDT tracing 2740 0=disable, 1=enable */ 2741 uint64_t ldi : 1; /**< Enable LDI tracing 2742 0=disable, 1=enable */ 2743 uint64_t ldd : 1; /**< Enable LDD tracing 2744 0=disable, 1=enable */ 2745 uint64_t psl1 : 1; /**< Enable PSL1 tracing 2746 0=disable, 1=enable */ 2747 uint64_t pl2 : 1; /**< Enable PL2 tracing 2748 0=disable, 1=enable */ 2749 uint64_t dwb : 1; /**< Enable DWB tracing 2750 0=disable, 1=enable */ 2751#else 2752 uint64_t dwb : 1; 2753 uint64_t pl2 : 1; 2754 uint64_t psl1 : 1; 2755 uint64_t ldd : 1; 2756 uint64_t ldi : 1; 2757 uint64_t ldt : 1; 2758 uint64_t stf : 1; 2759 uint64_t stc : 1; 2760 uint64_t stp : 1; 2761 uint64_t stt : 1; 2762 uint64_t iobld8 : 1; 2763 uint64_t iobld16 : 1; 2764 uint64_t iobld32 : 1; 2765 uint64_t iobld64 : 1; 2766 uint64_t iobst : 1; 2767 uint64_t iobdma : 1; 2768 uint64_t saa : 1; 2769 uint64_t reserved_17_63 : 47; 2770#endif 2771 } cn52xx; 2772 struct cvmx_tra_trig1_cmd_cn52xx cn52xxp1; 2773 struct cvmx_tra_trig1_cmd_cn52xx cn56xx; 2774 struct cvmx_tra_trig1_cmd_cn52xx cn56xxp1; 2775 struct cvmx_tra_trig1_cmd_cn52xx cn58xx; 2776 struct cvmx_tra_trig1_cmd_cn52xx cn58xxp1; 2777 struct cvmx_tra_trig1_cmd_cn63xx 2778 { 2779#if __BYTE_ORDER == __BIG_ENDIAN 2780 uint64_t saa64 : 1; /**< Enable SAA64 tracing 2781 0=disable, 1=enable */ 2782 uint64_t saa32 : 1; /**< Enable SAA32 tracing 2783 0=disable, 1=enable */ 2784 uint64_t reserved_60_61 : 2; 2785 uint64_t faa64 : 1; /**< Enable FAA64 tracing 2786 0=disable, 1=enable */ 2787 uint64_t faa32 : 1; /**< Enable FAA32 tracing 2788 0=disable, 1=enable */ 2789 uint64_t reserved_56_57 : 2; 2790 uint64_t decr64 : 1; /**< Enable DECR64 tracing 2791 0=disable, 1=enable */ 2792 uint64_t decr32 : 1; /**< Enable DECR32 tracing 2793 0=disable, 1=enable */ 2794 uint64_t decr16 : 1; /**< Enable DECR16 tracing 2795 0=disable, 1=enable */ 2796 uint64_t decr8 : 1; /**< Enable DECR8 tracing 2797 0=disable, 1=enable */ 2798 uint64_t incr64 : 1; /**< Enable INCR64 tracing 2799 0=disable, 1=enable */ 2800 uint64_t incr32 : 1; /**< Enable INCR32 tracing 2801 0=disable, 1=enable */ 2802 uint64_t incr16 : 1; /**< Enable INCR16 tracing 2803 0=disable, 1=enable */ 2804 uint64_t incr8 : 1; /**< Enable INCR8 tracing 2805 0=disable, 1=enable */ 2806 uint64_t clr64 : 1; /**< Enable CLR64 tracing 2807 0=disable, 1=enable */ 2808 uint64_t clr32 : 1; /**< Enable CLR32 tracing 2809 0=disable, 1=enable */ 2810 uint64_t clr16 : 1; /**< Enable CLR16 tracing 2811 0=disable, 1=enable */ 2812 uint64_t clr8 : 1; /**< Enable CLR8 tracing 2813 0=disable, 1=enable */ 2814 uint64_t set64 : 1; /**< Enable SET64 tracing 2815 0=disable, 1=enable */ 2816 uint64_t set32 : 1; /**< Enable SET32 tracing 2817 0=disable, 1=enable */ 2818 uint64_t set16 : 1; /**< Enable SET16 tracing 2819 0=disable, 1=enable */ 2820 uint64_t set8 : 1; /**< Enable SET8 tracing 2821 0=disable, 1=enable */ 2822 uint64_t iobst64 : 1; /**< Enable IOBST64 tracing 2823 0=disable, 1=enable */ 2824 uint64_t iobst32 : 1; /**< Enable IOBST32 tracing 2825 0=disable, 1=enable */ 2826 uint64_t iobst16 : 1; /**< Enable IOBST16 tracing 2827 0=disable, 1=enable */ 2828 uint64_t iobst8 : 1; /**< Enable IOBST8 tracing 2829 0=disable, 1=enable */ 2830 uint64_t iobld64 : 1; /**< Enable IOBLD64 tracing 2831 0=disable, 1=enable */ 2832 uint64_t iobld32 : 1; /**< Enable IOBLD32 tracing 2833 0=disable, 1=enable */ 2834 uint64_t iobld16 : 1; /**< Enable IOBLD16 tracing 2835 0=disable, 1=enable */ 2836 uint64_t iobld8 : 1; /**< Enable IOBLD8 tracing 2837 0=disable, 1=enable */ 2838 uint64_t lckl2 : 1; /**< Enable LCKL2 tracing 2839 0=disable, 1=enable */ 2840 uint64_t wbl2 : 1; /**< Enable WBL2 tracing 2841 0=disable, 1=enable */ 2842 uint64_t wbil2 : 1; /**< Enable WBIL2 tracing 2843 0=disable, 1=enable */ 2844 uint64_t invl2 : 1; /**< Enable INVL2 tracing 2845 0=disable, 1=enable */ 2846 uint64_t reserved_27_27 : 1; 2847 uint64_t stgl2i : 1; /**< Enable STGL2I tracing 2848 0=disable, 1=enable */ 2849 uint64_t ltgl2i : 1; /**< Enable LTGL2I tracing 2850 0=disable, 1=enable */ 2851 uint64_t wbil2i : 1; /**< Enable WBIL2I tracing 2852 0=disable, 1=enable */ 2853 uint64_t fas64 : 1; /**< Enable FAS64 tracing 2854 0=disable, 1=enable */ 2855 uint64_t fas32 : 1; /**< Enable FAS32 tracing 2856 0=disable, 1=enable */ 2857 uint64_t sttil1 : 1; /**< Enable STTIL1 tracing 2858 0=disable, 1=enable */ 2859 uint64_t stfil1 : 1; /**< Enable STFIL1 tracing 2860 0=disable, 1=enable */ 2861 uint64_t stc : 1; /**< Enable STC tracing 2862 0=disable, 1=enable */ 2863 uint64_t stp : 1; /**< Enable STP tracing 2864 0=disable, 1=enable */ 2865 uint64_t stt : 1; /**< Enable STT tracing 2866 0=disable, 1=enable */ 2867 uint64_t stf : 1; /**< Enable STF tracing 2868 0=disable, 1=enable */ 2869 uint64_t iobdma : 1; /**< Enable IOBDMA tracing 2870 0=disable, 1=enable */ 2871 uint64_t reserved_10_14 : 5; 2872 uint64_t psl1 : 1; /**< Enable PSL1 tracing 2873 0=disable, 1=enable */ 2874 uint64_t ldd : 1; /**< Enable LDD tracing 2875 0=disable, 1=enable */ 2876 uint64_t reserved_6_7 : 2; 2877 uint64_t dwb : 1; /**< Enable DWB tracing 2878 0=disable, 1=enable */ 2879 uint64_t rpl2 : 1; /**< Enable RPL2 tracing 2880 0=disable, 1=enable */ 2881 uint64_t pl2 : 1; /**< Enable PL2 tracing 2882 0=disable, 1=enable */ 2883 uint64_t ldi : 1; /**< Enable LDI tracing 2884 0=disable, 1=enable */ 2885 uint64_t ldt : 1; /**< Enable LDT tracing 2886 0=disable, 1=enable */ 2887 uint64_t nop : 1; /**< Enable NOP tracing 2888 0=disable, 1=enable */ 2889#else 2890 uint64_t nop : 1; 2891 uint64_t ldt : 1; 2892 uint64_t ldi : 1; 2893 uint64_t pl2 : 1; 2894 uint64_t rpl2 : 1; 2895 uint64_t dwb : 1; 2896 uint64_t reserved_6_7 : 2; 2897 uint64_t ldd : 1; 2898 uint64_t psl1 : 1; 2899 uint64_t reserved_10_14 : 5; 2900 uint64_t iobdma : 1; 2901 uint64_t stf : 1; 2902 uint64_t stt : 1; 2903 uint64_t stp : 1; 2904 uint64_t stc : 1; 2905 uint64_t stfil1 : 1; 2906 uint64_t sttil1 : 1; 2907 uint64_t fas32 : 1; 2908 uint64_t fas64 : 1; 2909 uint64_t wbil2i : 1; 2910 uint64_t ltgl2i : 1; 2911 uint64_t stgl2i : 1; 2912 uint64_t reserved_27_27 : 1; 2913 uint64_t invl2 : 1; 2914 uint64_t wbil2 : 1; 2915 uint64_t wbl2 : 1; 2916 uint64_t lckl2 : 1; 2917 uint64_t iobld8 : 1; 2918 uint64_t iobld16 : 1; 2919 uint64_t iobld32 : 1; 2920 uint64_t iobld64 : 1; 2921 uint64_t iobst8 : 1; 2922 uint64_t iobst16 : 1; 2923 uint64_t iobst32 : 1; 2924 uint64_t iobst64 : 1; 2925 uint64_t set8 : 1; 2926 uint64_t set16 : 1; 2927 uint64_t set32 : 1; 2928 uint64_t set64 : 1; 2929 uint64_t clr8 : 1; 2930 uint64_t clr16 : 1; 2931 uint64_t clr32 : 1; 2932 uint64_t clr64 : 1; 2933 uint64_t incr8 : 1; 2934 uint64_t incr16 : 1; 2935 uint64_t incr32 : 1; 2936 uint64_t incr64 : 1; 2937 uint64_t decr8 : 1; 2938 uint64_t decr16 : 1; 2939 uint64_t decr32 : 1; 2940 uint64_t decr64 : 1; 2941 uint64_t reserved_56_57 : 2; 2942 uint64_t faa32 : 1; 2943 uint64_t faa64 : 1; 2944 uint64_t reserved_60_61 : 2; 2945 uint64_t saa32 : 1; 2946 uint64_t saa64 : 1; 2947#endif 2948 } cn63xx; 2949 struct cvmx_tra_trig1_cmd_cn63xx cn63xxp1; 2950}; 2951typedef union cvmx_tra_trig1_cmd cvmx_tra_trig1_cmd_t; 2952 2953/** 2954 * cvmx_tra_trig1_did 2955 * 2956 * TRA_TRIG1_DID = Trace Buffer Filter DestinationId Mask 2957 * 2958 * Description: 2959 */ 2960union cvmx_tra_trig1_did 2961{ 2962 uint64_t u64; 2963 struct cvmx_tra_trig1_did_s 2964 { 2965#if __BYTE_ORDER == __BIG_ENDIAN 2966 uint64_t reserved_13_63 : 51; 2967 uint64_t pow : 1; /**< Enable triggering on requests to POW 2968 (get work, add work, status/memory/index 2969 loads, NULLRd loads, CSR's) */ 2970 uint64_t reserved_9_11 : 3; 2971 uint64_t rng : 1; /**< Enable triggering on requests to RNG 2972 (loads/IOBDMA's are legal) */ 2973 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 2974 (doorbell stores are legal) */ 2975 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 2976 (CSR's and operations are legal) */ 2977 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 2978 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 2979 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 2980 (loads/IOBDMA's/stores are legal) */ 2981 uint64_t reserved_3_3 : 1; 2982 uint64_t illegal3 : 2; /**< Illegal destinations */ 2983 uint64_t mio : 1; /**< Enable triggering on MIO accesses 2984 (CIU and GPIO CSR's, boot bus accesses) */ 2985#else 2986 uint64_t mio : 1; 2987 uint64_t illegal3 : 2; 2988 uint64_t reserved_3_3 : 1; 2989 uint64_t key : 1; 2990 uint64_t fpa : 1; 2991 uint64_t dfa : 1; 2992 uint64_t zip : 1; 2993 uint64_t rng : 1; 2994 uint64_t reserved_9_11 : 3; 2995 uint64_t pow : 1; 2996 uint64_t reserved_13_63 : 51; 2997#endif 2998 } s; 2999 struct cvmx_tra_trig1_did_cn31xx 3000 { 3001#if __BYTE_ORDER == __BIG_ENDIAN 3002 uint64_t reserved_32_63 : 32; 3003 uint64_t illegal : 19; /**< Illegal destinations */ 3004 uint64_t pow : 1; /**< Enable triggering on requests to POW 3005 (get work, add work, status/memory/index 3006 loads, NULLRd loads, CSR's) */ 3007 uint64_t illegal2 : 3; /**< Illegal destinations */ 3008 uint64_t rng : 1; /**< Enable triggering on requests to RNG 3009 (loads/IOBDMA's are legal) */ 3010 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 3011 (doorbell stores are legal) */ 3012 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 3013 (CSR's and operations are legal) */ 3014 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 3015 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 3016 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 3017 (loads/IOBDMA's/stores are legal) */ 3018 uint64_t pci : 1; /**< Enable triggering on requests to PCI and RSL-type 3019 CSR's (RSL CSR's, PCI bus operations, PCI 3020 CSR's) */ 3021 uint64_t illegal3 : 2; /**< Illegal destinations */ 3022 uint64_t mio : 1; /**< Enable triggering on CIU and GPIO CSR's */ 3023#else 3024 uint64_t mio : 1; 3025 uint64_t illegal3 : 2; 3026 uint64_t pci : 1; 3027 uint64_t key : 1; 3028 uint64_t fpa : 1; 3029 uint64_t dfa : 1; 3030 uint64_t zip : 1; 3031 uint64_t rng : 1; 3032 uint64_t illegal2 : 3; 3033 uint64_t pow : 1; 3034 uint64_t illegal : 19; 3035 uint64_t reserved_32_63 : 32; 3036#endif 3037 } cn31xx; 3038 struct cvmx_tra_trig1_did_cn31xx cn38xx; 3039 struct cvmx_tra_trig1_did_cn31xx cn38xxp2; 3040 struct cvmx_tra_trig1_did_cn31xx cn52xx; 3041 struct cvmx_tra_trig1_did_cn31xx cn52xxp1; 3042 struct cvmx_tra_trig1_did_cn31xx cn56xx; 3043 struct cvmx_tra_trig1_did_cn31xx cn56xxp1; 3044 struct cvmx_tra_trig1_did_cn31xx cn58xx; 3045 struct cvmx_tra_trig1_did_cn31xx cn58xxp1; 3046 struct cvmx_tra_trig1_did_cn63xx 3047 { 3048#if __BYTE_ORDER == __BIG_ENDIAN 3049 uint64_t reserved_32_63 : 32; 3050 uint64_t illegal5 : 1; /**< Illegal destinations */ 3051 uint64_t fau : 1; /**< Enable triggering on FAU accesses */ 3052 uint64_t illegal4 : 2; /**< Illegal destinations */ 3053 uint64_t dpi : 1; /**< Enable triggering on DPI accesses 3054 (DPI NCB CSRs) */ 3055 uint64_t illegal : 12; /**< Illegal destinations */ 3056 uint64_t rad : 1; /**< Enable triggering on RAD accesses 3057 (doorbells) */ 3058 uint64_t usb0 : 1; /**< Enable triggering on USB0 accesses 3059 (UAHC0 EHCI and OHCI NCB CSRs) */ 3060 uint64_t pow : 1; /**< Enable triggering on requests to POW 3061 (get work, add work, status/memory/index 3062 loads, NULLRd loads, CSR's) */ 3063 uint64_t illegal2 : 1; /**< Illegal destination */ 3064 uint64_t pko : 1; /**< Enable triggering on PKO accesses 3065 (doorbells) */ 3066 uint64_t ipd : 1; /**< Enable triggering on IPD CSR accesses 3067 (IPD CSRs) */ 3068 uint64_t rng : 1; /**< Enable triggering on requests to RNG 3069 (loads/IOBDMA's are legal) */ 3070 uint64_t zip : 1; /**< Enable triggering on requests to ZIP 3071 (doorbell stores are legal) */ 3072 uint64_t dfa : 1; /**< Enable triggering on requests to DFA 3073 (CSR's and operations are legal) */ 3074 uint64_t fpa : 1; /**< Enable triggering on requests to FPA 3075 (alloc's (loads/IOBDMA's), frees (stores) are legal) */ 3076 uint64_t key : 1; /**< Enable triggering on requests to KEY memory 3077 (loads/IOBDMA's/stores are legal) */ 3078 uint64_t sli : 1; /**< Enable triggering on requests to SLI and RSL-type 3079 CSR's (RSL CSR's, PCI/sRIO bus operations, SLI 3080 CSR's) */ 3081 uint64_t illegal3 : 2; /**< Illegal destinations */ 3082 uint64_t mio : 1; /**< Enable triggering on MIO accesses 3083 (CIU and GPIO CSR's, boot bus accesses) */ 3084#else 3085 uint64_t mio : 1; 3086 uint64_t illegal3 : 2; 3087 uint64_t sli : 1; 3088 uint64_t key : 1; 3089 uint64_t fpa : 1; 3090 uint64_t dfa : 1; 3091 uint64_t zip : 1; 3092 uint64_t rng : 1; 3093 uint64_t ipd : 1; 3094 uint64_t pko : 1; 3095 uint64_t illegal2 : 1; 3096 uint64_t pow : 1; 3097 uint64_t usb0 : 1; 3098 uint64_t rad : 1; 3099 uint64_t illegal : 12; 3100 uint64_t dpi : 1; 3101 uint64_t illegal4 : 2; 3102 uint64_t fau : 1; 3103 uint64_t illegal5 : 1; 3104 uint64_t reserved_32_63 : 32; 3105#endif 3106 } cn63xx; 3107 struct cvmx_tra_trig1_did_cn63xx cn63xxp1; 3108}; 3109typedef union cvmx_tra_trig1_did cvmx_tra_trig1_did_t; 3110 3111/** 3112 * cvmx_tra_trig1_sid 3113 * 3114 * TRA_TRIG1_SID = Trace Buffer Filter SourceId Mask 3115 * 3116 * Description: 3117 */ 3118union cvmx_tra_trig1_sid 3119{ 3120 uint64_t u64; 3121 struct cvmx_tra_trig1_sid_s 3122 { 3123#if __BYTE_ORDER == __BIG_ENDIAN 3124 uint64_t reserved_20_63 : 44; 3125 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3126 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3127 PCI,ZIP,POW, and PKO (writes) */ 3128 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3129 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3130 uint64_t pp : 16; /**< Enable trigering from PP[N] with matching SourceID 3131 0=disable, 1=enableper bit N where 0<=N<=15 */ 3132#else 3133 uint64_t pp : 16; 3134 uint64_t pki : 1; 3135 uint64_t pko : 1; 3136 uint64_t iobreq : 1; 3137 uint64_t dwb : 1; 3138 uint64_t reserved_20_63 : 44; 3139#endif 3140 } s; 3141 struct cvmx_tra_trig1_sid_s cn31xx; 3142 struct cvmx_tra_trig1_sid_s cn38xx; 3143 struct cvmx_tra_trig1_sid_s cn38xxp2; 3144 struct cvmx_tra_trig1_sid_s cn52xx; 3145 struct cvmx_tra_trig1_sid_s cn52xxp1; 3146 struct cvmx_tra_trig1_sid_s cn56xx; 3147 struct cvmx_tra_trig1_sid_s cn56xxp1; 3148 struct cvmx_tra_trig1_sid_s cn58xx; 3149 struct cvmx_tra_trig1_sid_s cn58xxp1; 3150 struct cvmx_tra_trig1_sid_cn63xx 3151 { 3152#if __BYTE_ORDER == __BIG_ENDIAN 3153 uint64_t reserved_20_63 : 44; 3154 uint64_t dwb : 1; /**< Enable triggering on requests from the IOB DWB engine */ 3155 uint64_t iobreq : 1; /**< Enable triggering on requests from FPA,TIM,DFA, 3156 PCI,ZIP,POW, and PKO (writes) */ 3157 uint64_t pko : 1; /**< Enable triggering on read requests from PKO */ 3158 uint64_t pki : 1; /**< Enable triggering on write requests from PIP/IPD */ 3159 uint64_t reserved_8_15 : 8; 3160 uint64_t pp : 8; /**< Enable trigering from PP[N] with matching SourceID 3161 0=disable, 1=enableper bit N where 0<=N<=15 */ 3162#else 3163 uint64_t pp : 8; 3164 uint64_t reserved_8_15 : 8; 3165 uint64_t pki : 1; 3166 uint64_t pko : 1; 3167 uint64_t iobreq : 1; 3168 uint64_t dwb : 1; 3169 uint64_t reserved_20_63 : 44; 3170#endif 3171 } cn63xx; 3172 struct cvmx_tra_trig1_sid_cn63xx cn63xxp1; 3173}; 3174typedef union cvmx_tra_trig1_sid cvmx_tra_trig1_sid_t; 3175 3176#endif 3177