cvmx-sriomaintx-defs.h revision 215976
1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-sriomaintx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon sriomaintx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52215976Sjmallett#ifndef __CVMX_SRIOMAINTX_TYPEDEFS_H__ 53215976Sjmallett#define __CVMX_SRIOMAINTX_TYPEDEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 60215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); 61215976Sjmallett return 0x0000000000000008ull; 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_SRIOMAINTX_ASMBLY_ID(block_id) (0x0000000000000008ull) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id) 68215976Sjmallett{ 69215976Sjmallett if (!( 70215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 71215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id); 72215976Sjmallett return 0x000000000000000Cull; 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_SRIOMAINTX_ASMBLY_INFO(block_id) (0x000000000000000Cull) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_BAR1_IDXX(unsigned long offset, unsigned long block_id) 79215976Sjmallett{ 80215976Sjmallett if (!( 81215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))))) 82215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_BAR1_IDXX(%lu,%lu) is invalid on this chip\n", offset, block_id); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4; 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_SRIOMAINTX_BAR1_IDXX(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000200010ull) + (((offset) & 15) + ((block_id) & 1) * 0x0ull) * 4) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_BELL_STATUS(unsigned long block_id) 90215976Sjmallett{ 91215976Sjmallett if (!( 92215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 93215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_BELL_STATUS(%lu) is invalid on this chip\n", block_id); 94215976Sjmallett return 0x0000000000200080ull; 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_SRIOMAINTX_BELL_STATUS(block_id) (0x0000000000200080ull) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_COMP_TAG(unsigned long block_id) 101215976Sjmallett{ 102215976Sjmallett if (!( 103215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 104215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_COMP_TAG(%lu) is invalid on this chip\n", block_id); 105215976Sjmallett return 0x000000000000006Cull; 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_SRIOMAINTX_COMP_TAG(block_id) (0x000000000000006Cull) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_CORE_ENABLES(unsigned long block_id) 112215976Sjmallett{ 113215976Sjmallett if (!( 114215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 115215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_CORE_ENABLES(%lu) is invalid on this chip\n", block_id); 116215976Sjmallett return 0x0000000000200070ull; 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_SRIOMAINTX_CORE_ENABLES(block_id) (0x0000000000200070ull) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_DEV_ID(unsigned long block_id) 123215976Sjmallett{ 124215976Sjmallett if (!( 125215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 126215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_DEV_ID(%lu) is invalid on this chip\n", block_id); 127215976Sjmallett return 0x0000000000000000ull; 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_SRIOMAINTX_DEV_ID(block_id) (0x0000000000000000ull) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_DEV_REV(unsigned long block_id) 134215976Sjmallett{ 135215976Sjmallett if (!( 136215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 137215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_DEV_REV(%lu) is invalid on this chip\n", block_id); 138215976Sjmallett return 0x0000000000000004ull; 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_SRIOMAINTX_DEV_REV(block_id) (0x0000000000000004ull) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_DST_OPS(unsigned long block_id) 145215976Sjmallett{ 146215976Sjmallett if (!( 147215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 148215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_DST_OPS(%lu) is invalid on this chip\n", block_id); 149215976Sjmallett return 0x000000000000001Cull; 150215976Sjmallett} 151215976Sjmallett#else 152215976Sjmallett#define CVMX_SRIOMAINTX_DST_OPS(block_id) (0x000000000000001Cull) 153215976Sjmallett#endif 154215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_ATTR_CAPT(unsigned long block_id) 156215976Sjmallett{ 157215976Sjmallett if (!( 158215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 159215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_ATTR_CAPT(%lu) is invalid on this chip\n", block_id); 160215976Sjmallett return 0x0000000000002048ull; 161215976Sjmallett} 162215976Sjmallett#else 163215976Sjmallett#define CVMX_SRIOMAINTX_ERB_ATTR_CAPT(block_id) (0x0000000000002048ull) 164215976Sjmallett#endif 165215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_DET(unsigned long block_id) 167215976Sjmallett{ 168215976Sjmallett if (!( 169215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 170215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_DET(%lu) is invalid on this chip\n", block_id); 171215976Sjmallett return 0x0000000000002040ull; 172215976Sjmallett} 173215976Sjmallett#else 174215976Sjmallett#define CVMX_SRIOMAINTX_ERB_ERR_DET(block_id) (0x0000000000002040ull) 175215976Sjmallett#endif 176215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE(unsigned long block_id) 178215976Sjmallett{ 179215976Sjmallett if (!( 180215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 181215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE(%lu) is invalid on this chip\n", block_id); 182215976Sjmallett return 0x0000000000002068ull; 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_SRIOMAINTX_ERB_ERR_RATE(block_id) (0x0000000000002068ull) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(unsigned long block_id) 189215976Sjmallett{ 190215976Sjmallett if (!( 191215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 192215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(%lu) is invalid on this chip\n", block_id); 193215976Sjmallett return 0x0000000000002044ull; 194215976Sjmallett} 195215976Sjmallett#else 196215976Sjmallett#define CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(block_id) (0x0000000000002044ull) 197215976Sjmallett#endif 198215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(unsigned long block_id) 200215976Sjmallett{ 201215976Sjmallett if (!( 202215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 203215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(%lu) is invalid on this chip\n", block_id); 204215976Sjmallett return 0x000000000000206Cull; 205215976Sjmallett} 206215976Sjmallett#else 207215976Sjmallett#define CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(block_id) (0x000000000000206Cull) 208215976Sjmallett#endif 209215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_HDR(unsigned long block_id) 211215976Sjmallett{ 212215976Sjmallett if (!( 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 214215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_HDR(%lu) is invalid on this chip\n", block_id); 215215976Sjmallett return 0x0000000000002000ull; 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_SRIOMAINTX_ERB_HDR(block_id) (0x0000000000002000ull) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(unsigned long block_id) 222215976Sjmallett{ 223215976Sjmallett if (!( 224215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 225215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(%lu) is invalid on this chip\n", block_id); 226215976Sjmallett return 0x0000000000002010ull; 227215976Sjmallett} 228215976Sjmallett#else 229215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(block_id) (0x0000000000002010ull) 230215976Sjmallett#endif 231215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(unsigned long block_id) 233215976Sjmallett{ 234215976Sjmallett if (!( 235215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 236215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(%lu) is invalid on this chip\n", block_id); 237215976Sjmallett return 0x0000000000002014ull; 238215976Sjmallett} 239215976Sjmallett#else 240215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(block_id) (0x0000000000002014ull) 241215976Sjmallett#endif 242215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(unsigned long block_id) 244215976Sjmallett{ 245215976Sjmallett if (!( 246215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 247215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(%lu) is invalid on this chip\n", block_id); 248215976Sjmallett return 0x000000000000201Cull; 249215976Sjmallett} 250215976Sjmallett#else 251215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(block_id) (0x000000000000201Cull) 252215976Sjmallett#endif 253215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID(unsigned long block_id) 255215976Sjmallett{ 256215976Sjmallett if (!( 257215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 258215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID(%lu) is invalid on this chip\n", block_id); 259215976Sjmallett return 0x0000000000002028ull; 260215976Sjmallett} 261215976Sjmallett#else 262215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_DEV_ID(block_id) (0x0000000000002028ull) 263215976Sjmallett#endif 264215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(unsigned long block_id) 266215976Sjmallett{ 267215976Sjmallett if (!( 268215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 269215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(%lu) is invalid on this chip\n", block_id); 270215976Sjmallett return 0x0000000000002018ull; 271215976Sjmallett} 272215976Sjmallett#else 273215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(block_id) (0x0000000000002018ull) 274215976Sjmallett#endif 275215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_DET(unsigned long block_id) 277215976Sjmallett{ 278215976Sjmallett if (!( 279215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 280215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_DET(%lu) is invalid on this chip\n", block_id); 281215976Sjmallett return 0x0000000000002008ull; 282215976Sjmallett} 283215976Sjmallett#else 284215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_ERR_DET(block_id) (0x0000000000002008ull) 285215976Sjmallett#endif 286215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_EN(unsigned long block_id) 288215976Sjmallett{ 289215976Sjmallett if (!( 290215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 291215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_EN(%lu) is invalid on this chip\n", block_id); 292215976Sjmallett return 0x000000000000200Cull; 293215976Sjmallett} 294215976Sjmallett#else 295215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_ERR_EN(block_id) (0x000000000000200Cull) 296215976Sjmallett#endif 297215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(unsigned long block_id) 299215976Sjmallett{ 300215976Sjmallett if (!( 301215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 302215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(%lu) is invalid on this chip\n", block_id); 303215976Sjmallett return 0x0000000000002050ull; 304215976Sjmallett} 305215976Sjmallett#else 306215976Sjmallett#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(block_id) (0x0000000000002050ull) 307215976Sjmallett#endif 308215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(unsigned long block_id) 310215976Sjmallett{ 311215976Sjmallett if (!( 312215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 313215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(%lu) is invalid on this chip\n", block_id); 314215976Sjmallett return 0x0000000000002054ull; 315215976Sjmallett} 316215976Sjmallett#else 317215976Sjmallett#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(block_id) (0x0000000000002054ull) 318215976Sjmallett#endif 319215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(unsigned long block_id) 321215976Sjmallett{ 322215976Sjmallett if (!( 323215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 324215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(%lu) is invalid on this chip\n", block_id); 325215976Sjmallett return 0x0000000000002058ull; 326215976Sjmallett} 327215976Sjmallett#else 328215976Sjmallett#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(block_id) (0x0000000000002058ull) 329215976Sjmallett#endif 330215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(unsigned long block_id) 332215976Sjmallett{ 333215976Sjmallett if (!( 334215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 335215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(%lu) is invalid on this chip\n", block_id); 336215976Sjmallett return 0x000000000000204Cull; 337215976Sjmallett} 338215976Sjmallett#else 339215976Sjmallett#define CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(block_id) (0x000000000000204Cull) 340215976Sjmallett#endif 341215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(unsigned long block_id) 343215976Sjmallett{ 344215976Sjmallett if (!( 345215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 346215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(%lu) is invalid on this chip\n", block_id); 347215976Sjmallett return 0x0000000000000068ull; 348215976Sjmallett} 349215976Sjmallett#else 350215976Sjmallett#define CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(block_id) (0x0000000000000068ull) 351215976Sjmallett#endif 352215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(unsigned long block_id) 354215976Sjmallett{ 355215976Sjmallett if (!( 356215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 357215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(%lu) is invalid on this chip\n", block_id); 358215976Sjmallett return 0x0000000000102000ull; 359215976Sjmallett} 360215976Sjmallett#else 361215976Sjmallett#define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(block_id) (0x0000000000102000ull) 362215976Sjmallett#endif 363215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(unsigned long block_id) 365215976Sjmallett{ 366215976Sjmallett if (!( 367215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 368215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(%lu) is invalid on this chip\n", block_id); 369215976Sjmallett return 0x0000000000102004ull; 370215976Sjmallett} 371215976Sjmallett#else 372215976Sjmallett#define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(block_id) (0x0000000000102004ull) 373215976Sjmallett#endif 374215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(unsigned long block_id) 376215976Sjmallett{ 377215976Sjmallett if (!( 378215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 379215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(%lu) is invalid on this chip\n", block_id); 380215976Sjmallett return 0x0000000000107028ull; 381215976Sjmallett} 382215976Sjmallett#else 383215976Sjmallett#define CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(block_id) (0x0000000000107028ull) 384215976Sjmallett#endif 385215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_STAT(unsigned long block_id) 387215976Sjmallett{ 388215976Sjmallett if (!( 389215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 390215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_STAT(%lu) is invalid on this chip\n", block_id); 391215976Sjmallett return 0x000000000010702Cull; 392215976Sjmallett} 393215976Sjmallett#else 394215976Sjmallett#define CVMX_SRIOMAINTX_IR_PD_PHY_STAT(block_id) (0x000000000010702Cull) 395215976Sjmallett#endif 396215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(unsigned long block_id) 398215976Sjmallett{ 399215976Sjmallett if (!( 400215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 401215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(%lu) is invalid on this chip\n", block_id); 402215976Sjmallett return 0x0000000000107020ull; 403215976Sjmallett} 404215976Sjmallett#else 405215976Sjmallett#define CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(block_id) (0x0000000000107020ull) 406215976Sjmallett#endif 407215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_STAT(unsigned long block_id) 409215976Sjmallett{ 410215976Sjmallett if (!( 411215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 412215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_STAT(%lu) is invalid on this chip\n", block_id); 413215976Sjmallett return 0x0000000000107024ull; 414215976Sjmallett} 415215976Sjmallett#else 416215976Sjmallett#define CVMX_SRIOMAINTX_IR_PI_PHY_STAT(block_id) (0x0000000000107024ull) 417215976Sjmallett#endif 418215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_CTRL(unsigned long block_id) 420215976Sjmallett{ 421215976Sjmallett if (!( 422215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 423215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_CTRL(%lu) is invalid on this chip\n", block_id); 424215976Sjmallett return 0x000000000010700Cull; 425215976Sjmallett} 426215976Sjmallett#else 427215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_RX_CTRL(block_id) (0x000000000010700Cull) 428215976Sjmallett#endif 429215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_DATA(unsigned long block_id) 431215976Sjmallett{ 432215976Sjmallett if (!( 433215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 434215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_DATA(%lu) is invalid on this chip\n", block_id); 435215976Sjmallett return 0x0000000000107014ull; 436215976Sjmallett} 437215976Sjmallett#else 438215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_RX_DATA(block_id) (0x0000000000107014ull) 439215976Sjmallett#endif 440215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_STAT(unsigned long block_id) 442215976Sjmallett{ 443215976Sjmallett if (!( 444215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 445215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_STAT(%lu) is invalid on this chip\n", block_id); 446215976Sjmallett return 0x0000000000107010ull; 447215976Sjmallett} 448215976Sjmallett#else 449215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_RX_STAT(block_id) (0x0000000000107010ull) 450215976Sjmallett#endif 451215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_CTRL(unsigned long block_id) 453215976Sjmallett{ 454215976Sjmallett if (!( 455215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 456215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_CTRL(%lu) is invalid on this chip\n", block_id); 457215976Sjmallett return 0x0000000000107000ull; 458215976Sjmallett} 459215976Sjmallett#else 460215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_TX_CTRL(block_id) (0x0000000000107000ull) 461215976Sjmallett#endif 462215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_DATA(unsigned long block_id) 464215976Sjmallett{ 465215976Sjmallett if (!( 466215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 467215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_DATA(%lu) is invalid on this chip\n", block_id); 468215976Sjmallett return 0x0000000000107008ull; 469215976Sjmallett} 470215976Sjmallett#else 471215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_TX_DATA(block_id) (0x0000000000107008ull) 472215976Sjmallett#endif 473215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_STAT(unsigned long block_id) 475215976Sjmallett{ 476215976Sjmallett if (!( 477215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 478215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_STAT(%lu) is invalid on this chip\n", block_id); 479215976Sjmallett return 0x0000000000107004ull; 480215976Sjmallett} 481215976Sjmallett#else 482215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_TX_STAT(block_id) (0x0000000000107004ull) 483215976Sjmallett#endif 484215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_LANE_X_STATUS_0(unsigned long offset, unsigned long block_id) 486215976Sjmallett{ 487215976Sjmallett if (!( 488215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))))) 489215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_LANE_X_STATUS_0(%lu,%lu) is invalid on this chip\n", offset, block_id); 490215976Sjmallett return CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32; 491215976Sjmallett} 492215976Sjmallett#else 493215976Sjmallett#define CVMX_SRIOMAINTX_LANE_X_STATUS_0(offset, block_id) (CVMX_ADD_IO_SEG(0x0000000000001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x0ull) * 32) 494215976Sjmallett#endif 495215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_LCS_BA0(unsigned long block_id) 497215976Sjmallett{ 498215976Sjmallett if (!( 499215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 500215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_LCS_BA0(%lu) is invalid on this chip\n", block_id); 501215976Sjmallett return 0x0000000000000058ull; 502215976Sjmallett} 503215976Sjmallett#else 504215976Sjmallett#define CVMX_SRIOMAINTX_LCS_BA0(block_id) (0x0000000000000058ull) 505215976Sjmallett#endif 506215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_LCS_BA1(unsigned long block_id) 508215976Sjmallett{ 509215976Sjmallett if (!( 510215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 511215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_LCS_BA1(%lu) is invalid on this chip\n", block_id); 512215976Sjmallett return 0x000000000000005Cull; 513215976Sjmallett} 514215976Sjmallett#else 515215976Sjmallett#define CVMX_SRIOMAINTX_LCS_BA1(block_id) (0x000000000000005Cull) 516215976Sjmallett#endif 517215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START0(unsigned long block_id) 519215976Sjmallett{ 520215976Sjmallett if (!( 521215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 522215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START0(%lu) is invalid on this chip\n", block_id); 523215976Sjmallett return 0x0000000000200000ull; 524215976Sjmallett} 525215976Sjmallett#else 526215976Sjmallett#define CVMX_SRIOMAINTX_M2S_BAR0_START0(block_id) (0x0000000000200000ull) 527215976Sjmallett#endif 528215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START1(unsigned long block_id) 530215976Sjmallett{ 531215976Sjmallett if (!( 532215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 533215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START1(%lu) is invalid on this chip\n", block_id); 534215976Sjmallett return 0x0000000000200004ull; 535215976Sjmallett} 536215976Sjmallett#else 537215976Sjmallett#define CVMX_SRIOMAINTX_M2S_BAR0_START1(block_id) (0x0000000000200004ull) 538215976Sjmallett#endif 539215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START0(unsigned long block_id) 541215976Sjmallett{ 542215976Sjmallett if (!( 543215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 544215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START0(%lu) is invalid on this chip\n", block_id); 545215976Sjmallett return 0x0000000000200008ull; 546215976Sjmallett} 547215976Sjmallett#else 548215976Sjmallett#define CVMX_SRIOMAINTX_M2S_BAR1_START0(block_id) (0x0000000000200008ull) 549215976Sjmallett#endif 550215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START1(unsigned long block_id) 552215976Sjmallett{ 553215976Sjmallett if (!( 554215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 555215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START1(%lu) is invalid on this chip\n", block_id); 556215976Sjmallett return 0x000000000020000Cull; 557215976Sjmallett} 558215976Sjmallett#else 559215976Sjmallett#define CVMX_SRIOMAINTX_M2S_BAR1_START1(block_id) (0x000000000020000Cull) 560215976Sjmallett#endif 561215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_M2S_BAR2_START(unsigned long block_id) 563215976Sjmallett{ 564215976Sjmallett if (!( 565215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 566215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR2_START(%lu) is invalid on this chip\n", block_id); 567215976Sjmallett return 0x0000000000200050ull; 568215976Sjmallett} 569215976Sjmallett#else 570215976Sjmallett#define CVMX_SRIOMAINTX_M2S_BAR2_START(block_id) (0x0000000000200050ull) 571215976Sjmallett#endif 572215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_MAC_CTRL(unsigned long block_id) 574215976Sjmallett{ 575215976Sjmallett if (!( 576215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 577215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_MAC_CTRL(%lu) is invalid on this chip\n", block_id); 578215976Sjmallett return 0x0000000000200068ull; 579215976Sjmallett} 580215976Sjmallett#else 581215976Sjmallett#define CVMX_SRIOMAINTX_MAC_CTRL(block_id) (0x0000000000200068ull) 582215976Sjmallett#endif 583215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PE_FEAT(unsigned long block_id) 585215976Sjmallett{ 586215976Sjmallett if (!( 587215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 588215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PE_FEAT(%lu) is invalid on this chip\n", block_id); 589215976Sjmallett return 0x0000000000000010ull; 590215976Sjmallett} 591215976Sjmallett#else 592215976Sjmallett#define CVMX_SRIOMAINTX_PE_FEAT(block_id) (0x0000000000000010ull) 593215976Sjmallett#endif 594215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PE_LLC(unsigned long block_id) 596215976Sjmallett{ 597215976Sjmallett if (!( 598215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 599215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PE_LLC(%lu) is invalid on this chip\n", block_id); 600215976Sjmallett return 0x000000000000004Cull; 601215976Sjmallett} 602215976Sjmallett#else 603215976Sjmallett#define CVMX_SRIOMAINTX_PE_LLC(block_id) (0x000000000000004Cull) 604215976Sjmallett#endif 605215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL(unsigned long block_id) 607215976Sjmallett{ 608215976Sjmallett if (!( 609215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 610215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL(%lu) is invalid on this chip\n", block_id); 611215976Sjmallett return 0x000000000000015Cull; 612215976Sjmallett} 613215976Sjmallett#else 614215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_CTL(block_id) (0x000000000000015Cull) 615215976Sjmallett#endif 616215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long block_id) 618215976Sjmallett{ 619215976Sjmallett if (!( 620215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 621215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL2(%lu) is invalid on this chip\n", block_id); 622215976Sjmallett return 0x0000000000000154ull; 623215976Sjmallett} 624215976Sjmallett#else 625215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_CTL2(block_id) (0x0000000000000154ull) 626215976Sjmallett#endif 627215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_ERR_STAT(unsigned long block_id) 629215976Sjmallett{ 630215976Sjmallett if (!( 631215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 632215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_ERR_STAT(%lu) is invalid on this chip\n", block_id); 633215976Sjmallett return 0x0000000000000158ull; 634215976Sjmallett} 635215976Sjmallett#else 636215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_ERR_STAT(block_id) (0x0000000000000158ull) 637215976Sjmallett#endif 638215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 639215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_REQ(unsigned long block_id) 640215976Sjmallett{ 641215976Sjmallett if (!( 642215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 643215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_REQ(%lu) is invalid on this chip\n", block_id); 644215976Sjmallett return 0x0000000000000140ull; 645215976Sjmallett} 646215976Sjmallett#else 647215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_LINK_REQ(block_id) (0x0000000000000140ull) 648215976Sjmallett#endif 649215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_RESP(unsigned long block_id) 651215976Sjmallett{ 652215976Sjmallett if (!( 653215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 654215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_RESP(%lu) is invalid on this chip\n", block_id); 655215976Sjmallett return 0x0000000000000144ull; 656215976Sjmallett} 657215976Sjmallett#else 658215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_LINK_RESP(block_id) (0x0000000000000144ull) 659215976Sjmallett#endif 660215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(unsigned long block_id) 662215976Sjmallett{ 663215976Sjmallett if (!( 664215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 665215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(%lu) is invalid on this chip\n", block_id); 666215976Sjmallett return 0x0000000000000148ull; 667215976Sjmallett} 668215976Sjmallett#else 669215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(block_id) (0x0000000000000148ull) 670215976Sjmallett#endif 671215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_GEN_CTL(unsigned long block_id) 673215976Sjmallett{ 674215976Sjmallett if (!( 675215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 676215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_GEN_CTL(%lu) is invalid on this chip\n", block_id); 677215976Sjmallett return 0x000000000000013Cull; 678215976Sjmallett} 679215976Sjmallett#else 680215976Sjmallett#define CVMX_SRIOMAINTX_PORT_GEN_CTL(block_id) (0x000000000000013Cull) 681215976Sjmallett#endif 682215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_LT_CTL(unsigned long block_id) 684215976Sjmallett{ 685215976Sjmallett if (!( 686215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 687215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_LT_CTL(%lu) is invalid on this chip\n", block_id); 688215976Sjmallett return 0x0000000000000120ull; 689215976Sjmallett} 690215976Sjmallett#else 691215976Sjmallett#define CVMX_SRIOMAINTX_PORT_LT_CTL(block_id) (0x0000000000000120ull) 692215976Sjmallett#endif 693215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_MBH0(unsigned long block_id) 695215976Sjmallett{ 696215976Sjmallett if (!( 697215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 698215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_MBH0(%lu) is invalid on this chip\n", block_id); 699215976Sjmallett return 0x0000000000000100ull; 700215976Sjmallett} 701215976Sjmallett#else 702215976Sjmallett#define CVMX_SRIOMAINTX_PORT_MBH0(block_id) (0x0000000000000100ull) 703215976Sjmallett#endif 704215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_RT_CTL(unsigned long block_id) 706215976Sjmallett{ 707215976Sjmallett if (!( 708215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 709215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_RT_CTL(%lu) is invalid on this chip\n", block_id); 710215976Sjmallett return 0x0000000000000124ull; 711215976Sjmallett} 712215976Sjmallett#else 713215976Sjmallett#define CVMX_SRIOMAINTX_PORT_RT_CTL(block_id) (0x0000000000000124ull) 714215976Sjmallett#endif 715215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_TTL_CTL(unsigned long block_id) 717215976Sjmallett{ 718215976Sjmallett if (!( 719215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 720215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_TTL_CTL(%lu) is invalid on this chip\n", block_id); 721215976Sjmallett return 0x000000000000012Cull; 722215976Sjmallett} 723215976Sjmallett#else 724215976Sjmallett#define CVMX_SRIOMAINTX_PORT_TTL_CTL(block_id) (0x000000000000012Cull) 725215976Sjmallett#endif 726215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PRI_DEV_ID(unsigned long block_id) 728215976Sjmallett{ 729215976Sjmallett if (!( 730215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 731215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PRI_DEV_ID(%lu) is invalid on this chip\n", block_id); 732215976Sjmallett return 0x0000000000000060ull; 733215976Sjmallett} 734215976Sjmallett#else 735215976Sjmallett#define CVMX_SRIOMAINTX_PRI_DEV_ID(block_id) (0x0000000000000060ull) 736215976Sjmallett#endif 737215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_CTRL(unsigned long block_id) 739215976Sjmallett{ 740215976Sjmallett if (!( 741215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 742215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_CTRL(%lu) is invalid on this chip\n", block_id); 743215976Sjmallett return 0x0000000000200064ull; 744215976Sjmallett} 745215976Sjmallett#else 746215976Sjmallett#define CVMX_SRIOMAINTX_SEC_DEV_CTRL(block_id) (0x0000000000200064ull) 747215976Sjmallett#endif 748215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_ID(unsigned long block_id) 750215976Sjmallett{ 751215976Sjmallett if (!( 752215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 753215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_ID(%lu) is invalid on this chip\n", block_id); 754215976Sjmallett return 0x0000000000200060ull; 755215976Sjmallett} 756215976Sjmallett#else 757215976Sjmallett#define CVMX_SRIOMAINTX_SEC_DEV_ID(block_id) (0x0000000000200060ull) 758215976Sjmallett#endif 759215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_SERIAL_LANE_HDR(unsigned long block_id) 761215976Sjmallett{ 762215976Sjmallett if (!( 763215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 764215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_SERIAL_LANE_HDR(%lu) is invalid on this chip\n", block_id); 765215976Sjmallett return 0x0000000000001000ull; 766215976Sjmallett} 767215976Sjmallett#else 768215976Sjmallett#define CVMX_SRIOMAINTX_SERIAL_LANE_HDR(block_id) (0x0000000000001000ull) 769215976Sjmallett#endif 770215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_SRC_OPS(unsigned long block_id) 772215976Sjmallett{ 773215976Sjmallett if (!( 774215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 775215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_SRC_OPS(%lu) is invalid on this chip\n", block_id); 776215976Sjmallett return 0x0000000000000018ull; 777215976Sjmallett} 778215976Sjmallett#else 779215976Sjmallett#define CVMX_SRIOMAINTX_SRC_OPS(block_id) (0x0000000000000018ull) 780215976Sjmallett#endif 781215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 782215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_TX_DROP(unsigned long block_id) 783215976Sjmallett{ 784215976Sjmallett if (!( 785215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))))) 786215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_TX_DROP(%lu) is invalid on this chip\n", block_id); 787215976Sjmallett return 0x000000000020006Cull; 788215976Sjmallett} 789215976Sjmallett#else 790215976Sjmallett#define CVMX_SRIOMAINTX_TX_DROP(block_id) (0x000000000020006Cull) 791215976Sjmallett#endif 792215976Sjmallett 793215976Sjmallett/** 794215976Sjmallett * cvmx_sriomaint#_asmbly_id 795215976Sjmallett * 796215976Sjmallett * SRIOMAINT_ASMBLY_ID = SRIO Assembly ID 797215976Sjmallett * 798215976Sjmallett * The Assembly ID register shows the Assembly ID and Vendor 799215976Sjmallett * 800215976Sjmallett * Notes: 801215976Sjmallett * The Assembly ID register shows the Assembly ID and Vendor specified in $SRIO_ASMBLY_ID. 802215976Sjmallett * 803215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ASMBLY_ID hclk hrst_n 804215976Sjmallett */ 805215976Sjmallettunion cvmx_sriomaintx_asmbly_id 806215976Sjmallett{ 807215976Sjmallett uint32_t u32; 808215976Sjmallett struct cvmx_sriomaintx_asmbly_id_s 809215976Sjmallett { 810215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 811215976Sjmallett uint32_t assy_id : 16; /**< Assembly Identifer */ 812215976Sjmallett uint32_t assy_ven : 16; /**< Assembly Vendor Identifer */ 813215976Sjmallett#else 814215976Sjmallett uint32_t assy_ven : 16; 815215976Sjmallett uint32_t assy_id : 16; 816215976Sjmallett#endif 817215976Sjmallett } s; 818215976Sjmallett struct cvmx_sriomaintx_asmbly_id_s cn63xx; 819215976Sjmallett struct cvmx_sriomaintx_asmbly_id_s cn63xxp1; 820215976Sjmallett}; 821215976Sjmalletttypedef union cvmx_sriomaintx_asmbly_id cvmx_sriomaintx_asmbly_id_t; 822215976Sjmallett 823215976Sjmallett/** 824215976Sjmallett * cvmx_sriomaint#_asmbly_info 825215976Sjmallett * 826215976Sjmallett * SRIOMAINT_ASMBLY_INFO = SRIO Assembly Information 827215976Sjmallett * 828215976Sjmallett * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO 829215976Sjmallett * 830215976Sjmallett * Notes: 831215976Sjmallett * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO and Extended 832215976Sjmallett * Feature Pointer. 833215976Sjmallett * 834215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ASMBLY_INFO hclk hrst_n 835215976Sjmallett */ 836215976Sjmallettunion cvmx_sriomaintx_asmbly_info 837215976Sjmallett{ 838215976Sjmallett uint32_t u32; 839215976Sjmallett struct cvmx_sriomaintx_asmbly_info_s 840215976Sjmallett { 841215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 842215976Sjmallett uint32_t assy_rev : 16; /**< Assembly Revision */ 843215976Sjmallett uint32_t ext_fptr : 16; /**< Pointer to the first entry in the extended feature 844215976Sjmallett list. */ 845215976Sjmallett#else 846215976Sjmallett uint32_t ext_fptr : 16; 847215976Sjmallett uint32_t assy_rev : 16; 848215976Sjmallett#endif 849215976Sjmallett } s; 850215976Sjmallett struct cvmx_sriomaintx_asmbly_info_s cn63xx; 851215976Sjmallett struct cvmx_sriomaintx_asmbly_info_s cn63xxp1; 852215976Sjmallett}; 853215976Sjmalletttypedef union cvmx_sriomaintx_asmbly_info cvmx_sriomaintx_asmbly_info_t; 854215976Sjmallett 855215976Sjmallett/** 856215976Sjmallett * cvmx_sriomaint#_bar1_idx# 857215976Sjmallett * 858215976Sjmallett * SRIOMAINT_BAR1_IDXX = SRIO BAR1 IndexX Register 859215976Sjmallett * 860215976Sjmallett * Contains address index and control bits for access to memory ranges of BAR1. 861215976Sjmallett * 862215976Sjmallett * Notes: 863215976Sjmallett * This register specifies the Octeon address, endian swap and cache status associated with each of 864215976Sjmallett * the 16 BAR1 entries. The local address bits used are based on the BARSIZE field located in the 865215976Sjmallett * SRIOMAINT(0..1)_M2S_BAR1_START0 register. This register is only writeable over SRIO if the 866215976Sjmallett * SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero. 867215976Sjmallett * 868215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_BAR1_IDX[0:15] hclk hrst_n 869215976Sjmallett */ 870215976Sjmallettunion cvmx_sriomaintx_bar1_idxx 871215976Sjmallett{ 872215976Sjmallett uint32_t u32; 873215976Sjmallett struct cvmx_sriomaintx_bar1_idxx_s 874215976Sjmallett { 875215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 876215976Sjmallett uint32_t reserved_30_31 : 2; 877215976Sjmallett uint32_t la : 22; /**< L2/DRAM Address bits [37:16] 878215976Sjmallett Not all LA[21:0] bits are used by SRIO hardware, 879215976Sjmallett depending on SRIOMAINT(0..1)_M2S_BAR1_START1[BARSIZE]. 880215976Sjmallett 881215976Sjmallett Become 882215976Sjmallett L2/DRAM 883215976Sjmallett Address Entry 884215976Sjmallett BARSIZE LA Bits Used Bits Size 885215976Sjmallett 0 LA[21:0] [37:16] 64KB 886215976Sjmallett 1 LA[21:1] [37:17] 128KB 887215976Sjmallett 2 LA[21:2] [37:18] 256KB 888215976Sjmallett 3 LA[21:3] [37:19] 512KB 889215976Sjmallett 4 LA[21:4] [37:20] 1MB 890215976Sjmallett 5 LA[21:5] [37:21] 2MB 891215976Sjmallett 6 LA[21:6] [37:22] 4MB 892215976Sjmallett 7 LA[21:7] [37:23] 8MB 893215976Sjmallett 8 ** not in pass 1 894215976Sjmallett 9 ** not in pass 1 895215976Sjmallett 10 ** not in pass 1 896215976Sjmallett 11 ** not in pass 1 897215976Sjmallett 12 ** not in pass 1 898215976Sjmallett 13 ** not in pass 1 */ 899215976Sjmallett uint32_t reserved_6_7 : 2; 900215976Sjmallett uint32_t es : 2; /**< Endian Swap Mode. 901215976Sjmallett 0 = No Swap 902215976Sjmallett 1 = 64-bit Swap Bytes [ABCD_EFGH] -> [HGFE_DCBA] 903215976Sjmallett 2 = 32-bit Swap Words [ABCD_EFGH] -> [DCBA_HGFE] 904215976Sjmallett 3 = 32-bit Word Exch [ABCD_EFGH] -> [EFGH_ABCD] */ 905215976Sjmallett uint32_t nca : 1; /**< Non-Cacheable Access Mode. When set, transfers 906215976Sjmallett through this window are not cacheable. */ 907215976Sjmallett uint32_t reserved_1_2 : 2; 908215976Sjmallett uint32_t enable : 1; /**< When set the selected index address is valid. */ 909215976Sjmallett#else 910215976Sjmallett uint32_t enable : 1; 911215976Sjmallett uint32_t reserved_1_2 : 2; 912215976Sjmallett uint32_t nca : 1; 913215976Sjmallett uint32_t es : 2; 914215976Sjmallett uint32_t reserved_6_7 : 2; 915215976Sjmallett uint32_t la : 22; 916215976Sjmallett uint32_t reserved_30_31 : 2; 917215976Sjmallett#endif 918215976Sjmallett } s; 919215976Sjmallett struct cvmx_sriomaintx_bar1_idxx_s cn63xx; 920215976Sjmallett struct cvmx_sriomaintx_bar1_idxx_s cn63xxp1; 921215976Sjmallett}; 922215976Sjmalletttypedef union cvmx_sriomaintx_bar1_idxx cvmx_sriomaintx_bar1_idxx_t; 923215976Sjmallett 924215976Sjmallett/** 925215976Sjmallett * cvmx_sriomaint#_bell_status 926215976Sjmallett * 927215976Sjmallett * SRIOMAINT_BELL_STATUS = SRIO Incoming Doorbell Status 928215976Sjmallett * 929215976Sjmallett * The SRIO Incoming (RX) Doorbell Status 930215976Sjmallett * 931215976Sjmallett * Notes: 932215976Sjmallett * This register displays the status of the doorbells received. If FULL is set the SRIO device will 933215976Sjmallett * retry incoming transactions. 934215976Sjmallett * 935215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_BELL_STATUS hclk hrst_n 936215976Sjmallett */ 937215976Sjmallettunion cvmx_sriomaintx_bell_status 938215976Sjmallett{ 939215976Sjmallett uint32_t u32; 940215976Sjmallett struct cvmx_sriomaintx_bell_status_s 941215976Sjmallett { 942215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 943215976Sjmallett uint32_t reserved_1_31 : 31; 944215976Sjmallett uint32_t full : 1; /**< Not able to receive Doorbell Transactions */ 945215976Sjmallett#else 946215976Sjmallett uint32_t full : 1; 947215976Sjmallett uint32_t reserved_1_31 : 31; 948215976Sjmallett#endif 949215976Sjmallett } s; 950215976Sjmallett struct cvmx_sriomaintx_bell_status_s cn63xx; 951215976Sjmallett struct cvmx_sriomaintx_bell_status_s cn63xxp1; 952215976Sjmallett}; 953215976Sjmalletttypedef union cvmx_sriomaintx_bell_status cvmx_sriomaintx_bell_status_t; 954215976Sjmallett 955215976Sjmallett/** 956215976Sjmallett * cvmx_sriomaint#_comp_tag 957215976Sjmallett * 958215976Sjmallett * SRIOMAINT_COMP_TAG = SRIO Component Tag 959215976Sjmallett * 960215976Sjmallett * Component Tag 961215976Sjmallett * 962215976Sjmallett * Notes: 963215976Sjmallett * This register contains a component tag value for the processing element and the value can be 964215976Sjmallett * assigned by software when the device is initialized. 965215976Sjmallett * 966215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_COMP_TAG hclk hrst_n 967215976Sjmallett */ 968215976Sjmallettunion cvmx_sriomaintx_comp_tag 969215976Sjmallett{ 970215976Sjmallett uint32_t u32; 971215976Sjmallett struct cvmx_sriomaintx_comp_tag_s 972215976Sjmallett { 973215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 974215976Sjmallett uint32_t comp_tag : 32; /**< Component Tag for Firmware Use */ 975215976Sjmallett#else 976215976Sjmallett uint32_t comp_tag : 32; 977215976Sjmallett#endif 978215976Sjmallett } s; 979215976Sjmallett struct cvmx_sriomaintx_comp_tag_s cn63xx; 980215976Sjmallett struct cvmx_sriomaintx_comp_tag_s cn63xxp1; 981215976Sjmallett}; 982215976Sjmalletttypedef union cvmx_sriomaintx_comp_tag cvmx_sriomaintx_comp_tag_t; 983215976Sjmallett 984215976Sjmallett/** 985215976Sjmallett * cvmx_sriomaint#_core_enables 986215976Sjmallett * 987215976Sjmallett * SRIOMAINT_CORE_ENABLES = SRIO Core Control 988215976Sjmallett * 989215976Sjmallett * Core Control 990215976Sjmallett * 991215976Sjmallett * Notes: 992215976Sjmallett * This register displays the reset state of the Octeon Core Logic while the SRIO Link is running. 993215976Sjmallett * The bit should be set after the software has initialized the chip to allow memory operations. 994215976Sjmallett * 995215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_CORE_ENABLES hclk hrst_n, srst_n 996215976Sjmallett */ 997215976Sjmallettunion cvmx_sriomaintx_core_enables 998215976Sjmallett{ 999215976Sjmallett uint32_t u32; 1000215976Sjmallett struct cvmx_sriomaintx_core_enables_s 1001215976Sjmallett { 1002215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1003215976Sjmallett uint32_t reserved_5_31 : 27; 1004215976Sjmallett uint32_t halt : 1; /**< OCTEON currently in Reset 1005215976Sjmallett 0 = All OCTEON resources are available. 1006215976Sjmallett 1 = The OCTEON is in reset. When this bit is set, 1007215976Sjmallett SRIO maintenance registers can be accessed, 1008215976Sjmallett but BAR0, BAR1, and BAR2 cannot be. */ 1009215976Sjmallett uint32_t imsg1 : 1; /**< Allow Incoming Message Unit 1 Operations 1010215976Sjmallett Note: This bit is cleared when the C63XX is reset 1011215976Sjmallett 0 = SRIO Incoming Messages to Unit 1 ignored and 1012215976Sjmallett return error response 1013215976Sjmallett 1 = SRIO Incoming Messages to Unit 1 */ 1014215976Sjmallett uint32_t imsg0 : 1; /**< Allow Incoming Message Unit 0 Operations 1015215976Sjmallett Note: This bit is cleared when the C63XX is reset 1016215976Sjmallett 0 = SRIO Incoming Messages to Unit 0 ignored and 1017215976Sjmallett return error response 1018215976Sjmallett 1 = SRIO Incoming Messages to Unit 0 */ 1019215976Sjmallett uint32_t doorbell : 1; /**< Allow Inbound Doorbell Operations 1020215976Sjmallett Note: This bit is cleared when the C63XX is reset 1021215976Sjmallett 0 = SRIO Doorbell OPs ignored and return error 1022215976Sjmallett response 1023215976Sjmallett 1 = SRIO Doorbell OPs Allowed */ 1024215976Sjmallett uint32_t memory : 1; /**< Allow Inbound/Outbound Memory Operations 1025215976Sjmallett Note: This bit is cleared when the C63XX is reset 1026215976Sjmallett 0 = SRIO Incoming Nwrites and Swrites are 1027215976Sjmallett dropped. Incoming Nreads, Atomics and 1028215976Sjmallett NwriteRs return responses with ERROR status. 1029215976Sjmallett SRIO Incoming Maintenance BAR Memory Accesses 1030215976Sjmallett are processed normally. 1031215976Sjmallett Outgoing Store Operations are Dropped 1032215976Sjmallett Outgoing Load Operations are not issued and 1033215976Sjmallett return all 1's with an ERROR status. 1034215976Sjmallett In Flight Operations started while the bit is 1035215976Sjmallett set in both directions will complete normally. 1036215976Sjmallett 1 = SRIO Memory Read/Write OPs Allowed */ 1037215976Sjmallett#else 1038215976Sjmallett uint32_t memory : 1; 1039215976Sjmallett uint32_t doorbell : 1; 1040215976Sjmallett uint32_t imsg0 : 1; 1041215976Sjmallett uint32_t imsg1 : 1; 1042215976Sjmallett uint32_t halt : 1; 1043215976Sjmallett uint32_t reserved_5_31 : 27; 1044215976Sjmallett#endif 1045215976Sjmallett } s; 1046215976Sjmallett struct cvmx_sriomaintx_core_enables_s cn63xx; 1047215976Sjmallett struct cvmx_sriomaintx_core_enables_s cn63xxp1; 1048215976Sjmallett}; 1049215976Sjmalletttypedef union cvmx_sriomaintx_core_enables cvmx_sriomaintx_core_enables_t; 1050215976Sjmallett 1051215976Sjmallett/** 1052215976Sjmallett * cvmx_sriomaint#_dev_id 1053215976Sjmallett * 1054215976Sjmallett * SRIOMAINT_DEV_ID = SRIO Device ID 1055215976Sjmallett * 1056215976Sjmallett * The DeviceVendor Identity field identifies the vendor that manufactured the device 1057215976Sjmallett * 1058215976Sjmallett * Notes: 1059215976Sjmallett * This register identifies Cavium Networks and the Product ID. 1060215976Sjmallett * 1061215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_DEV_ID hclk hrst_n 1062215976Sjmallett */ 1063215976Sjmallettunion cvmx_sriomaintx_dev_id 1064215976Sjmallett{ 1065215976Sjmallett uint32_t u32; 1066215976Sjmallett struct cvmx_sriomaintx_dev_id_s 1067215976Sjmallett { 1068215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1069215976Sjmallett uint32_t device : 16; /**< Product Identity */ 1070215976Sjmallett uint32_t vendor : 16; /**< Cavium Vendor Identity */ 1071215976Sjmallett#else 1072215976Sjmallett uint32_t vendor : 16; 1073215976Sjmallett uint32_t device : 16; 1074215976Sjmallett#endif 1075215976Sjmallett } s; 1076215976Sjmallett struct cvmx_sriomaintx_dev_id_s cn63xx; 1077215976Sjmallett struct cvmx_sriomaintx_dev_id_s cn63xxp1; 1078215976Sjmallett}; 1079215976Sjmalletttypedef union cvmx_sriomaintx_dev_id cvmx_sriomaintx_dev_id_t; 1080215976Sjmallett 1081215976Sjmallett/** 1082215976Sjmallett * cvmx_sriomaint#_dev_rev 1083215976Sjmallett * 1084215976Sjmallett * SRIOMAINT_DEV_REV = SRIO Device Revision 1085215976Sjmallett * 1086215976Sjmallett * The Device Revision register identifies the chip pass and revision 1087215976Sjmallett * 1088215976Sjmallett * Notes: 1089215976Sjmallett * This register identifies the chip pass and revision derived from the fuses. 1090215976Sjmallett * 1091215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_DEV_REV hclk hrst_n 1092215976Sjmallett */ 1093215976Sjmallettunion cvmx_sriomaintx_dev_rev 1094215976Sjmallett{ 1095215976Sjmallett uint32_t u32; 1096215976Sjmallett struct cvmx_sriomaintx_dev_rev_s 1097215976Sjmallett { 1098215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1099215976Sjmallett uint32_t reserved_8_31 : 24; 1100215976Sjmallett uint32_t revision : 8; /**< Chip Pass/Revision */ 1101215976Sjmallett#else 1102215976Sjmallett uint32_t revision : 8; 1103215976Sjmallett uint32_t reserved_8_31 : 24; 1104215976Sjmallett#endif 1105215976Sjmallett } s; 1106215976Sjmallett struct cvmx_sriomaintx_dev_rev_s cn63xx; 1107215976Sjmallett struct cvmx_sriomaintx_dev_rev_s cn63xxp1; 1108215976Sjmallett}; 1109215976Sjmalletttypedef union cvmx_sriomaintx_dev_rev cvmx_sriomaintx_dev_rev_t; 1110215976Sjmallett 1111215976Sjmallett/** 1112215976Sjmallett * cvmx_sriomaint#_dst_ops 1113215976Sjmallett * 1114215976Sjmallett * SRIOMAINT_DST_OPS = SRIO Source Operations 1115215976Sjmallett * 1116215976Sjmallett * The logical operations supported from external devices. 1117215976Sjmallett * 1118215976Sjmallett * Notes: 1119215976Sjmallett * The logical operations supported from external devices. The Destination OPs register shows the 1120215976Sjmallett * operations specified in the SRIO(0..1)_IP_FEATURE.OPS register. 1121215976Sjmallett * 1122215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_DST_OPS hclk hrst_n 1123215976Sjmallett */ 1124215976Sjmallettunion cvmx_sriomaintx_dst_ops 1125215976Sjmallett{ 1126215976Sjmallett uint32_t u32; 1127215976Sjmallett struct cvmx_sriomaintx_dst_ops_s 1128215976Sjmallett { 1129215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1130215976Sjmallett uint32_t gsm_read : 1; /**< PE does not support Read Home operations. 1131215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */ 1132215976Sjmallett uint32_t i_read : 1; /**< PE does not support Instruction Read. 1133215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<30>] */ 1134215976Sjmallett uint32_t rd_own : 1; /**< PE does not support Read for Ownership. 1135215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<29>] */ 1136215976Sjmallett uint32_t d_invald : 1; /**< PE does not support Data Cache Invalidate. 1137215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<28>] */ 1138215976Sjmallett uint32_t castout : 1; /**< PE does not support Castout Operations. 1139215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<27>] */ 1140215976Sjmallett uint32_t d_flush : 1; /**< PE does not support Data Cache Flush. 1141215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<26>] */ 1142215976Sjmallett uint32_t io_read : 1; /**< PE does not support IO Read. 1143215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<25>] */ 1144215976Sjmallett uint32_t i_invald : 1; /**< PE does not support Instruction Cache Invalidate. 1145215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<24>] */ 1146215976Sjmallett uint32_t tlb_inv : 1; /**< PE does not support TLB Entry Invalidate. 1147215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<23>] */ 1148215976Sjmallett uint32_t tlb_invs : 1; /**< PE does not support TLB Entry Invalidate Sync. 1149215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<22>] */ 1150215976Sjmallett uint32_t reserved_16_21 : 6; 1151215976Sjmallett uint32_t read : 1; /**< PE can support Nread operations. 1152215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<15>] */ 1153215976Sjmallett uint32_t write : 1; /**< PE can support Nwrite operations. 1154215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<14>] */ 1155215976Sjmallett uint32_t swrite : 1; /**< PE can support Swrite operations. 1156215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<13>] */ 1157215976Sjmallett uint32_t write_r : 1; /**< PE can support Write with Response operations. 1158215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<12>] */ 1159215976Sjmallett uint32_t msg : 1; /**< PE can support Data Message operations. 1160215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<11>] */ 1161215976Sjmallett uint32_t doorbell : 1; /**< PE can support Doorbell operations. 1162215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<10>] */ 1163215976Sjmallett uint32_t compswap : 1; /**< PE does not support Atomic Compare and Swap. 1164215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<9>] */ 1165215976Sjmallett uint32_t testswap : 1; /**< PE does not support Atomic Test and Swap. 1166215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<8>] */ 1167215976Sjmallett uint32_t atom_inc : 1; /**< PE can support Atomic increment operations. 1168215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<7>] */ 1169215976Sjmallett uint32_t atom_dec : 1; /**< PE can support Atomic decrement operations. 1170215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<6>] */ 1171215976Sjmallett uint32_t atom_set : 1; /**< PE can support Atomic set operations. 1172215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<5>] */ 1173215976Sjmallett uint32_t atom_clr : 1; /**< PE can support Atomic clear operations. 1174215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<4>] */ 1175215976Sjmallett uint32_t atom_swp : 1; /**< PE does not support Atomic Swap. 1176215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<3>] */ 1177215976Sjmallett uint32_t port_wr : 1; /**< PE can Port Write operations. 1178215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<2>] */ 1179215976Sjmallett uint32_t reserved_0_1 : 2; 1180215976Sjmallett#else 1181215976Sjmallett uint32_t reserved_0_1 : 2; 1182215976Sjmallett uint32_t port_wr : 1; 1183215976Sjmallett uint32_t atom_swp : 1; 1184215976Sjmallett uint32_t atom_clr : 1; 1185215976Sjmallett uint32_t atom_set : 1; 1186215976Sjmallett uint32_t atom_dec : 1; 1187215976Sjmallett uint32_t atom_inc : 1; 1188215976Sjmallett uint32_t testswap : 1; 1189215976Sjmallett uint32_t compswap : 1; 1190215976Sjmallett uint32_t doorbell : 1; 1191215976Sjmallett uint32_t msg : 1; 1192215976Sjmallett uint32_t write_r : 1; 1193215976Sjmallett uint32_t swrite : 1; 1194215976Sjmallett uint32_t write : 1; 1195215976Sjmallett uint32_t read : 1; 1196215976Sjmallett uint32_t reserved_16_21 : 6; 1197215976Sjmallett uint32_t tlb_invs : 1; 1198215976Sjmallett uint32_t tlb_inv : 1; 1199215976Sjmallett uint32_t i_invald : 1; 1200215976Sjmallett uint32_t io_read : 1; 1201215976Sjmallett uint32_t d_flush : 1; 1202215976Sjmallett uint32_t castout : 1; 1203215976Sjmallett uint32_t d_invald : 1; 1204215976Sjmallett uint32_t rd_own : 1; 1205215976Sjmallett uint32_t i_read : 1; 1206215976Sjmallett uint32_t gsm_read : 1; 1207215976Sjmallett#endif 1208215976Sjmallett } s; 1209215976Sjmallett struct cvmx_sriomaintx_dst_ops_s cn63xx; 1210215976Sjmallett struct cvmx_sriomaintx_dst_ops_s cn63xxp1; 1211215976Sjmallett}; 1212215976Sjmalletttypedef union cvmx_sriomaintx_dst_ops cvmx_sriomaintx_dst_ops_t; 1213215976Sjmallett 1214215976Sjmallett/** 1215215976Sjmallett * cvmx_sriomaint#_erb_attr_capt 1216215976Sjmallett * 1217215976Sjmallett * SRIOMAINT_ERB_ATTR_CAPT = SRIO Attributes Capture 1218215976Sjmallett * 1219215976Sjmallett * Attributes Capture 1220215976Sjmallett * 1221215976Sjmallett * Notes: 1222215976Sjmallett * This register contains the information captured during the error. 1223215976Sjmallett * The HW will not update this register (i.e. this register is locked) while 1224215976Sjmallett * VALID is set in this CSR. 1225215976Sjmallett * The HW sets SRIO_INT_REG[PHY_ERB] every time it sets VALID in this CSR. 1226215976Sjmallett * To handle the interrupt, the following procedure may be best: 1227215976Sjmallett * (1) clear SRIO_INT_REG[PHY_ERB], 1228215976Sjmallett * (2) read this CSR, corresponding SRIOMAINT*_ERB_ERR_DET, SRIOMAINT*_ERB_PACK_SYM_CAPT, 1229215976Sjmallett * SRIOMAINT*_ERB_PACK_CAPT_1, SRIOMAINT*_ERB_PACK_CAPT_2, and SRIOMAINT*_ERB_PACK_CAPT_3 1230215976Sjmallett * (3) Write VALID in this CSR to 0. 1231215976Sjmallett * 1232215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_ATTR_CAPT hclk hrst_n 1233215976Sjmallett */ 1234215976Sjmallettunion cvmx_sriomaintx_erb_attr_capt 1235215976Sjmallett{ 1236215976Sjmallett uint32_t u32; 1237215976Sjmallett struct cvmx_sriomaintx_erb_attr_capt_s 1238215976Sjmallett { 1239215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1240215976Sjmallett uint32_t inf_type : 3; /**< Type of Information Logged. 1241215976Sjmallett 000 - Packet 1242215976Sjmallett 010 - Short Control Symbol 1243215976Sjmallett (use only first capture register) 1244215976Sjmallett All Others Reserved */ 1245215976Sjmallett uint32_t err_type : 5; /**< The encoded value of the 31 minus the bit in 1246215976Sjmallett SRIOMAINT(0..1)_ERB_ERR_DET that describes the error 1247215976Sjmallett captured in SRIOMAINT(0..1)_ERB_*CAPT Registers. 1248215976Sjmallett (For example a value of 5 indicates 31-5 = bit 26) */ 1249215976Sjmallett uint32_t err_info : 20; /**< Error Info. (Pass 2) 1250215976Sjmallett ERR_TYPE Bits Description 1251215976Sjmallett 0 23 TX Protocol Error 1252215976Sjmallett 22 RX Protocol Error 1253215976Sjmallett 21 TX Link Response Timeout 1254215976Sjmallett 20 TX ACKID Timeout 1255215976Sjmallett - 19:16 Reserved 1256215976Sjmallett - 15:12 TX Protocol ID 1257215976Sjmallett 1 = Rcvd Unexpected Link Response 1258215976Sjmallett 2 = Rcvd Link Response before Req 1259215976Sjmallett 3 = Rcvd NACK servicing NACK 1260215976Sjmallett 4 = Rcvd NACK 1261215976Sjmallett 5 = Rcvd RETRY servicing RETRY 1262215976Sjmallett 6 = Rcvd RETRY servicing NACK 1263215976Sjmallett 7 = Rcvd ACK servicing RETRY 1264215976Sjmallett 8 = Rcvd ACK servicing NACK 1265215976Sjmallett 9 = Unexp ACKID on ACK or RETRY 1266215976Sjmallett 10 = Unexp ACK or RETRY 1267215976Sjmallett - 11:8 Reserved 1268215976Sjmallett - 7:4 RX Protocol ID 1269215976Sjmallett 1 = Rcvd EOP w/o Prev SOP 1270215976Sjmallett 2 = Rcvd STOMP w/o Prev SOP 1271215976Sjmallett 3 = Unexp RESTART 1272215976Sjmallett 4 = Redundant Status from LinkReq 1273215976Sjmallett 9-16 23:20 RX K Bits 1274215976Sjmallett - 19:0 Reserved 1275215976Sjmallett 26 23:20 RX K Bits 1276215976Sjmallett - 19:0 Reserved 1277215976Sjmallett 27 23:12 Type 1278215976Sjmallett 0x000 TX 1279215976Sjmallett 0x010 RX 1280215976Sjmallett - 11:8 RX or TX Protocol ID (see above) 1281215976Sjmallett - 7:4 Reserved 1282215976Sjmallett 30 23:20 RX K Bits 1283215976Sjmallett - 19:0 Reserved 1284215976Sjmallett 31 23:16 ACKID Timeout 0x2 1285215976Sjmallett - 15:14 Reserved 1286215976Sjmallett - 13:8 AckID 1287215976Sjmallett - 7:4 Reserved 1288215976Sjmallett All others ERR_TYPEs are reserved. */ 1289215976Sjmallett uint32_t reserved_1_3 : 3; 1290215976Sjmallett uint32_t valid : 1; /**< This bit is set by hardware to indicate that the 1291215976Sjmallett Packet/control symbol capture registers contain 1292215976Sjmallett valid information. For control symbols, only 1293215976Sjmallett capture register 0 will contain meaningful 1294215976Sjmallett information. This bit must be cleared by software 1295215976Sjmallett to allow capture of other errors. */ 1296215976Sjmallett#else 1297215976Sjmallett uint32_t valid : 1; 1298215976Sjmallett uint32_t reserved_1_3 : 3; 1299215976Sjmallett uint32_t err_info : 20; 1300215976Sjmallett uint32_t err_type : 5; 1301215976Sjmallett uint32_t inf_type : 3; 1302215976Sjmallett#endif 1303215976Sjmallett } s; 1304215976Sjmallett struct cvmx_sriomaintx_erb_attr_capt_s cn63xx; 1305215976Sjmallett struct cvmx_sriomaintx_erb_attr_capt_cn63xxp1 1306215976Sjmallett { 1307215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1308215976Sjmallett uint32_t inf_type : 3; /**< Type of Information Logged. 1309215976Sjmallett 000 - Packet 1310215976Sjmallett 010 - Short Control Symbol 1311215976Sjmallett (use only first capture register) 1312215976Sjmallett All Others Reserved */ 1313215976Sjmallett uint32_t err_type : 5; /**< The encoded value of the 31 minus the bit in 1314215976Sjmallett SRIOMAINT(0..1)_ERB_ERR_DET that describes the error 1315215976Sjmallett captured in SRIOMAINT(0..1)_ERB_*CAPT Registers. 1316215976Sjmallett (For example a value of 5 indicates 31-5 = bit 26) */ 1317215976Sjmallett uint32_t reserved_1_23 : 23; 1318215976Sjmallett uint32_t valid : 1; /**< This bit is set by hardware to indicate that the 1319215976Sjmallett Packet/control symbol capture registers contain 1320215976Sjmallett valid information. For control symbols, only 1321215976Sjmallett capture register 0 will contain meaningful 1322215976Sjmallett information. This bit must be cleared by software 1323215976Sjmallett to allow capture of other errors. */ 1324215976Sjmallett#else 1325215976Sjmallett uint32_t valid : 1; 1326215976Sjmallett uint32_t reserved_1_23 : 23; 1327215976Sjmallett uint32_t err_type : 5; 1328215976Sjmallett uint32_t inf_type : 3; 1329215976Sjmallett#endif 1330215976Sjmallett } cn63xxp1; 1331215976Sjmallett}; 1332215976Sjmalletttypedef union cvmx_sriomaintx_erb_attr_capt cvmx_sriomaintx_erb_attr_capt_t; 1333215976Sjmallett 1334215976Sjmallett/** 1335215976Sjmallett * cvmx_sriomaint#_erb_err_det 1336215976Sjmallett * 1337215976Sjmallett * SRIOMAINT_ERB_ERR_DET = SRIO Error Detect 1338215976Sjmallett * 1339215976Sjmallett * Error Detect 1340215976Sjmallett * 1341215976Sjmallett * Notes: 1342215976Sjmallett * The Error Detect Register indicates physical layer transmission errors detected by the hardware. 1343215976Sjmallett * The HW will not update this register (i.e. this register is locked) while 1344215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. 1345215976Sjmallett * 1346215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_DET hclk hrst_n 1347215976Sjmallett */ 1348215976Sjmallettunion cvmx_sriomaintx_erb_err_det 1349215976Sjmallett{ 1350215976Sjmallett uint32_t u32; 1351215976Sjmallett struct cvmx_sriomaintx_erb_err_det_s 1352215976Sjmallett { 1353215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1354215976Sjmallett uint32_t imp_err : 1; /**< Implementation Specific Error added for Pass 2. */ 1355215976Sjmallett uint32_t reserved_23_30 : 8; 1356215976Sjmallett uint32_t ctl_crc : 1; /**< Received a control symbol with a bad CRC value 1357215976Sjmallett Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1358215976Sjmallett uint32_t uns_id : 1; /**< Received an acknowledge control symbol with an 1359215976Sjmallett unexpected ackID (packet-accepted or packet_retry) 1360215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1361215976Sjmallett uint32_t nack : 1; /**< Received packet-not-accepted acknowledge control 1362215976Sjmallett symbols. 1363215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1364215976Sjmallett uint32_t out_ack : 1; /**< Received packet with unexpected ackID value 1365215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1366215976Sjmallett uint32_t pkt_crc : 1; /**< Received a packet with a bad CRC value 1367215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1368215976Sjmallett uint32_t size : 1; /**< Received packet which exceeds the maximum allowed 1369215976Sjmallett size of 276 bytes. 1370215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1371215976Sjmallett uint32_t inv_char : 1; /**< Received illegal, 8B/10B error or undefined 1372215976Sjmallett codegroup within a packet. (Pass 2) 1373215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1374215976Sjmallett uint32_t inv_data : 1; /**< Received data codegroup or 8B/10B error within an 1375215976Sjmallett IDLE sequence. (Pass 2) 1376215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1377215976Sjmallett uint32_t reserved_6_14 : 9; 1378215976Sjmallett uint32_t bad_ack : 1; /**< Link_response received with an ackID that is not 1379215976Sjmallett outstanding. 1380215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1381215976Sjmallett uint32_t proterr : 1; /**< An unexpected packet or control symbol was 1382215976Sjmallett received. 1383215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1384215976Sjmallett uint32_t f_toggle : 1; /**< Reserved. */ 1385215976Sjmallett uint32_t del_err : 1; /**< Received illegal or undefined codegroup. 1386215976Sjmallett (either INV_DATA or INV_CHAR) (Pass 2) 1387215976Sjmallett Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1388215976Sjmallett uint32_t uns_ack : 1; /**< An unexpected acknowledge control symbol was 1389215976Sjmallett received. 1390215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1391215976Sjmallett uint32_t lnk_tout : 1; /**< An acknowledge or link-response control symbol is 1392215976Sjmallett not received within the specified timeout interval 1393215976Sjmallett Partial Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1394215976Sjmallett#else 1395215976Sjmallett uint32_t lnk_tout : 1; 1396215976Sjmallett uint32_t uns_ack : 1; 1397215976Sjmallett uint32_t del_err : 1; 1398215976Sjmallett uint32_t f_toggle : 1; 1399215976Sjmallett uint32_t proterr : 1; 1400215976Sjmallett uint32_t bad_ack : 1; 1401215976Sjmallett uint32_t reserved_6_14 : 9; 1402215976Sjmallett uint32_t inv_data : 1; 1403215976Sjmallett uint32_t inv_char : 1; 1404215976Sjmallett uint32_t size : 1; 1405215976Sjmallett uint32_t pkt_crc : 1; 1406215976Sjmallett uint32_t out_ack : 1; 1407215976Sjmallett uint32_t nack : 1; 1408215976Sjmallett uint32_t uns_id : 1; 1409215976Sjmallett uint32_t ctl_crc : 1; 1410215976Sjmallett uint32_t reserved_23_30 : 8; 1411215976Sjmallett uint32_t imp_err : 1; 1412215976Sjmallett#endif 1413215976Sjmallett } s; 1414215976Sjmallett struct cvmx_sriomaintx_erb_err_det_s cn63xx; 1415215976Sjmallett struct cvmx_sriomaintx_erb_err_det_cn63xxp1 1416215976Sjmallett { 1417215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1418215976Sjmallett uint32_t reserved_23_31 : 9; 1419215976Sjmallett uint32_t ctl_crc : 1; /**< Received a control symbol with a bad CRC value 1420215976Sjmallett Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1421215976Sjmallett uint32_t uns_id : 1; /**< Received an acknowledge control symbol with an 1422215976Sjmallett unexpected ackID (packet-accepted or packet_retry) 1423215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1424215976Sjmallett uint32_t nack : 1; /**< Received packet-not-accepted acknowledge control 1425215976Sjmallett symbols. 1426215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1427215976Sjmallett uint32_t out_ack : 1; /**< Received packet with unexpected ackID value 1428215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1429215976Sjmallett uint32_t pkt_crc : 1; /**< Received a packet with a bad CRC value 1430215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1431215976Sjmallett uint32_t size : 1; /**< Received packet which exceeds the maximum allowed 1432215976Sjmallett size of 276 bytes. 1433215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1434215976Sjmallett uint32_t reserved_6_16 : 11; 1435215976Sjmallett uint32_t bad_ack : 1; /**< Link_response received with an ackID that is not 1436215976Sjmallett outstanding. 1437215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1438215976Sjmallett uint32_t proterr : 1; /**< An unexpected packet or control symbol was 1439215976Sjmallett received. 1440215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1441215976Sjmallett uint32_t f_toggle : 1; /**< Reserved. */ 1442215976Sjmallett uint32_t del_err : 1; /**< Received illegal or undefined codegroup. 1443215976Sjmallett (either INV_DATA or INV_CHAR) (Pass 2) 1444215976Sjmallett Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1445215976Sjmallett uint32_t uns_ack : 1; /**< An unexpected acknowledge control symbol was 1446215976Sjmallett received. 1447215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1448215976Sjmallett uint32_t lnk_tout : 1; /**< An acknowledge or link-response control symbol is 1449215976Sjmallett not received within the specified timeout interval 1450215976Sjmallett Partial Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1451215976Sjmallett#else 1452215976Sjmallett uint32_t lnk_tout : 1; 1453215976Sjmallett uint32_t uns_ack : 1; 1454215976Sjmallett uint32_t del_err : 1; 1455215976Sjmallett uint32_t f_toggle : 1; 1456215976Sjmallett uint32_t proterr : 1; 1457215976Sjmallett uint32_t bad_ack : 1; 1458215976Sjmallett uint32_t reserved_6_16 : 11; 1459215976Sjmallett uint32_t size : 1; 1460215976Sjmallett uint32_t pkt_crc : 1; 1461215976Sjmallett uint32_t out_ack : 1; 1462215976Sjmallett uint32_t nack : 1; 1463215976Sjmallett uint32_t uns_id : 1; 1464215976Sjmallett uint32_t ctl_crc : 1; 1465215976Sjmallett uint32_t reserved_23_31 : 9; 1466215976Sjmallett#endif 1467215976Sjmallett } cn63xxp1; 1468215976Sjmallett}; 1469215976Sjmalletttypedef union cvmx_sriomaintx_erb_err_det cvmx_sriomaintx_erb_err_det_t; 1470215976Sjmallett 1471215976Sjmallett/** 1472215976Sjmallett * cvmx_sriomaint#_erb_err_rate 1473215976Sjmallett * 1474215976Sjmallett * SRIOMAINT_ERB_ERR_RATE = SRIO Error Rate 1475215976Sjmallett * 1476215976Sjmallett * Error Rate 1477215976Sjmallett * 1478215976Sjmallett * Notes: 1479215976Sjmallett * The Error Rate register is used with the Error Rate Threshold register to monitor and control the 1480215976Sjmallett * reporting of transmission errors. 1481215976Sjmallett * 1482215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_RATE hclk hrst_n 1483215976Sjmallett */ 1484215976Sjmallettunion cvmx_sriomaintx_erb_err_rate 1485215976Sjmallett{ 1486215976Sjmallett uint32_t u32; 1487215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_s 1488215976Sjmallett { 1489215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1490215976Sjmallett uint32_t err_bias : 8; /**< These bits provide the error rate bias value. 1491215976Sjmallett 0x00 - do not decrement the error rate counter 1492215976Sjmallett 0x01 - decrement every 1ms (+/-34%) 1493215976Sjmallett 0x02 - decrement every 10ms (+/-34%) 1494215976Sjmallett 0x04 - decrement every 100ms (+/-34%) 1495215976Sjmallett 0x08 - decrement every 1s (+/-34%) 1496215976Sjmallett 0x10 - decrement every 10s (+/-34%) 1497215976Sjmallett 0x20 - decrement every 100s (+/-34%) 1498215976Sjmallett 0x40 - decrement every 1000s (+/-34%) 1499215976Sjmallett 0x80 - decrement every 10000s (+/-34%) 1500215976Sjmallett All other values are reserved */ 1501215976Sjmallett uint32_t reserved_18_23 : 6; 1502215976Sjmallett uint32_t rate_lim : 2; /**< These bits limit the incrementing of the error 1503215976Sjmallett rate counter above the failed threshold trigger. 1504215976Sjmallett 00 - only count 2 errors above 1505215976Sjmallett 01 - only count 4 errors above 1506215976Sjmallett 10 - only count 16 error above 1507215976Sjmallett 11 - do not limit incrementing the error rate ct */ 1508215976Sjmallett uint32_t pk_rate : 8; /**< Peak Value attainted by the error rate counter */ 1509215976Sjmallett uint32_t rate_cnt : 8; /**< These bits maintain a count of the number of 1510215976Sjmallett transmission errors that have been detected by the 1511215976Sjmallett port, decremented by the Error Rate Bias 1512215976Sjmallett mechanism, to create an indication of the link 1513215976Sjmallett error rate. */ 1514215976Sjmallett#else 1515215976Sjmallett uint32_t rate_cnt : 8; 1516215976Sjmallett uint32_t pk_rate : 8; 1517215976Sjmallett uint32_t rate_lim : 2; 1518215976Sjmallett uint32_t reserved_18_23 : 6; 1519215976Sjmallett uint32_t err_bias : 8; 1520215976Sjmallett#endif 1521215976Sjmallett } s; 1522215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_s cn63xx; 1523215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_s cn63xxp1; 1524215976Sjmallett}; 1525215976Sjmalletttypedef union cvmx_sriomaintx_erb_err_rate cvmx_sriomaintx_erb_err_rate_t; 1526215976Sjmallett 1527215976Sjmallett/** 1528215976Sjmallett * cvmx_sriomaint#_erb_err_rate_en 1529215976Sjmallett * 1530215976Sjmallett * SRIOMAINT_ERB_ERR_RATE_EN = SRIO Error Rate Enable 1531215976Sjmallett * 1532215976Sjmallett * Error Rate Enable 1533215976Sjmallett * 1534215976Sjmallett * Notes: 1535215976Sjmallett * This register contains the bits that control when an error condition is allowed to increment the 1536215976Sjmallett * error rate counter in the Error Rate Threshold Register and lock the Error Capture registers. 1537215976Sjmallett * 1538215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_RATE_EN hclk hrst_n 1539215976Sjmallett */ 1540215976Sjmallettunion cvmx_sriomaintx_erb_err_rate_en 1541215976Sjmallett{ 1542215976Sjmallett uint32_t u32; 1543215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_en_s 1544215976Sjmallett { 1545215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1546215976Sjmallett uint32_t imp_err : 1; /**< Enable Implementation Specific Error (Pass 2). */ 1547215976Sjmallett uint32_t reserved_23_30 : 8; 1548215976Sjmallett uint32_t ctl_crc : 1; /**< Enable error rate counting of control symbols with 1549215976Sjmallett bad CRC values */ 1550215976Sjmallett uint32_t uns_id : 1; /**< Enable error rate counting of acknowledge control 1551215976Sjmallett symbol with unexpected ackIDs 1552215976Sjmallett (packet-accepted or packet_retry) */ 1553215976Sjmallett uint32_t nack : 1; /**< Enable error rate counting of packet-not-accepted 1554215976Sjmallett acknowledge control symbols. */ 1555215976Sjmallett uint32_t out_ack : 1; /**< Enable error rate counting of received packet with 1556215976Sjmallett unexpected ackID value */ 1557215976Sjmallett uint32_t pkt_crc : 1; /**< Enable error rate counting of received a packet 1558215976Sjmallett with a bad CRC value */ 1559215976Sjmallett uint32_t size : 1; /**< Enable error rate counting of received packet 1560215976Sjmallett which exceeds the maximum size of 276 bytes. */ 1561215976Sjmallett uint32_t inv_char : 1; /**< Enable error rate counting of received illegal 1562215976Sjmallett illegal, 8B/10B error or undefined codegroup 1563215976Sjmallett within a packet. (Pass 2) */ 1564215976Sjmallett uint32_t inv_data : 1; /**< Enable error rate counting of received data 1565215976Sjmallett codegroup or 8B/10B error within IDLE sequence. 1566215976Sjmallett (Pass 2) */ 1567215976Sjmallett uint32_t reserved_6_14 : 9; 1568215976Sjmallett uint32_t bad_ack : 1; /**< Enable error rate counting of link_responses with 1569215976Sjmallett an ackID that is not outstanding. */ 1570215976Sjmallett uint32_t proterr : 1; /**< Enable error rate counting of unexpected packet or 1571215976Sjmallett control symbols received. */ 1572215976Sjmallett uint32_t f_toggle : 1; /**< Reserved. */ 1573215976Sjmallett uint32_t del_err : 1; /**< Enable error rate counting of illegal or undefined 1574215976Sjmallett codegroups (either INV_DATA or INV_CHAR). (Pass 2) */ 1575215976Sjmallett uint32_t uns_ack : 1; /**< Enable error rate counting of unexpected 1576215976Sjmallett acknowledge control symbols received. */ 1577215976Sjmallett uint32_t lnk_tout : 1; /**< Enable error rate counting of acknowledge or 1578215976Sjmallett link-response control symbols not received within 1579215976Sjmallett the specified timeout interval */ 1580215976Sjmallett#else 1581215976Sjmallett uint32_t lnk_tout : 1; 1582215976Sjmallett uint32_t uns_ack : 1; 1583215976Sjmallett uint32_t del_err : 1; 1584215976Sjmallett uint32_t f_toggle : 1; 1585215976Sjmallett uint32_t proterr : 1; 1586215976Sjmallett uint32_t bad_ack : 1; 1587215976Sjmallett uint32_t reserved_6_14 : 9; 1588215976Sjmallett uint32_t inv_data : 1; 1589215976Sjmallett uint32_t inv_char : 1; 1590215976Sjmallett uint32_t size : 1; 1591215976Sjmallett uint32_t pkt_crc : 1; 1592215976Sjmallett uint32_t out_ack : 1; 1593215976Sjmallett uint32_t nack : 1; 1594215976Sjmallett uint32_t uns_id : 1; 1595215976Sjmallett uint32_t ctl_crc : 1; 1596215976Sjmallett uint32_t reserved_23_30 : 8; 1597215976Sjmallett uint32_t imp_err : 1; 1598215976Sjmallett#endif 1599215976Sjmallett } s; 1600215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_en_s cn63xx; 1601215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_en_cn63xxp1 1602215976Sjmallett { 1603215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1604215976Sjmallett uint32_t reserved_23_31 : 9; 1605215976Sjmallett uint32_t ctl_crc : 1; /**< Enable error rate counting of control symbols with 1606215976Sjmallett bad CRC values */ 1607215976Sjmallett uint32_t uns_id : 1; /**< Enable error rate counting of acknowledge control 1608215976Sjmallett symbol with unexpected ackIDs 1609215976Sjmallett (packet-accepted or packet_retry) */ 1610215976Sjmallett uint32_t nack : 1; /**< Enable error rate counting of packet-not-accepted 1611215976Sjmallett acknowledge control symbols. */ 1612215976Sjmallett uint32_t out_ack : 1; /**< Enable error rate counting of received packet with 1613215976Sjmallett unexpected ackID value */ 1614215976Sjmallett uint32_t pkt_crc : 1; /**< Enable error rate counting of received a packet 1615215976Sjmallett with a bad CRC value */ 1616215976Sjmallett uint32_t size : 1; /**< Enable error rate counting of received packet 1617215976Sjmallett which exceeds the maximum size of 276 bytes. */ 1618215976Sjmallett uint32_t reserved_6_16 : 11; 1619215976Sjmallett uint32_t bad_ack : 1; /**< Enable error rate counting of link_responses with 1620215976Sjmallett an ackID that is not outstanding. */ 1621215976Sjmallett uint32_t proterr : 1; /**< Enable error rate counting of unexpected packet or 1622215976Sjmallett control symbols received. */ 1623215976Sjmallett uint32_t f_toggle : 1; /**< Reserved. */ 1624215976Sjmallett uint32_t del_err : 1; /**< Enable error rate counting of illegal or undefined 1625215976Sjmallett codegroups (either INV_DATA or INV_CHAR). (Pass 2) */ 1626215976Sjmallett uint32_t uns_ack : 1; /**< Enable error rate counting of unexpected 1627215976Sjmallett acknowledge control symbols received. */ 1628215976Sjmallett uint32_t lnk_tout : 1; /**< Enable error rate counting of acknowledge or 1629215976Sjmallett link-response control symbols not received within 1630215976Sjmallett the specified timeout interval */ 1631215976Sjmallett#else 1632215976Sjmallett uint32_t lnk_tout : 1; 1633215976Sjmallett uint32_t uns_ack : 1; 1634215976Sjmallett uint32_t del_err : 1; 1635215976Sjmallett uint32_t f_toggle : 1; 1636215976Sjmallett uint32_t proterr : 1; 1637215976Sjmallett uint32_t bad_ack : 1; 1638215976Sjmallett uint32_t reserved_6_16 : 11; 1639215976Sjmallett uint32_t size : 1; 1640215976Sjmallett uint32_t pkt_crc : 1; 1641215976Sjmallett uint32_t out_ack : 1; 1642215976Sjmallett uint32_t nack : 1; 1643215976Sjmallett uint32_t uns_id : 1; 1644215976Sjmallett uint32_t ctl_crc : 1; 1645215976Sjmallett uint32_t reserved_23_31 : 9; 1646215976Sjmallett#endif 1647215976Sjmallett } cn63xxp1; 1648215976Sjmallett}; 1649215976Sjmalletttypedef union cvmx_sriomaintx_erb_err_rate_en cvmx_sriomaintx_erb_err_rate_en_t; 1650215976Sjmallett 1651215976Sjmallett/** 1652215976Sjmallett * cvmx_sriomaint#_erb_err_rate_thr 1653215976Sjmallett * 1654215976Sjmallett * SRIOMAINT_ERB_ERR_RATE_THR = SRIO Error Rate Threshold 1655215976Sjmallett * 1656215976Sjmallett * Error Rate Threshold 1657215976Sjmallett * 1658215976Sjmallett * Notes: 1659215976Sjmallett * The Error Rate Threshold register is used to control the reporting of errors to the link status. 1660215976Sjmallett * Typically the Degraded Threshold is less than the Fail Threshold. 1661215976Sjmallett * 1662215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_ERR_RATE_THR hclk hrst_n 1663215976Sjmallett */ 1664215976Sjmallettunion cvmx_sriomaintx_erb_err_rate_thr 1665215976Sjmallett{ 1666215976Sjmallett uint32_t u32; 1667215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_thr_s 1668215976Sjmallett { 1669215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1670215976Sjmallett uint32_t fail_th : 8; /**< These bits provide the threshold value for 1671215976Sjmallett reporting an error condition due to a possibly 1672215976Sjmallett broken link. 1673215976Sjmallett 0x00 - Disable the Error Rate Failed Threshold 1674215976Sjmallett Trigger 1675215976Sjmallett 0x01 - Set the error reporting threshold to 1 1676215976Sjmallett 0x02 - Set the error reporting threshold to 2 1677215976Sjmallett - ... 1678215976Sjmallett 0xFF - Set the error reporting threshold to 255 */ 1679215976Sjmallett uint32_t dgrad_th : 8; /**< These bits provide the threshold value for 1680215976Sjmallett reporting an error condition due to a possibly 1681215976Sjmallett degrading link. 1682215976Sjmallett 0x00 - Disable the Degrade Rate Failed Threshold 1683215976Sjmallett Trigger 1684215976Sjmallett 0x01 - Set the error reporting threshold to 1 1685215976Sjmallett 0x02 - Set the error reporting threshold to 2 1686215976Sjmallett - ... 1687215976Sjmallett 0xFF - Set the error reporting threshold to 255 */ 1688215976Sjmallett uint32_t reserved_0_15 : 16; 1689215976Sjmallett#else 1690215976Sjmallett uint32_t reserved_0_15 : 16; 1691215976Sjmallett uint32_t dgrad_th : 8; 1692215976Sjmallett uint32_t fail_th : 8; 1693215976Sjmallett#endif 1694215976Sjmallett } s; 1695215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xx; 1696215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xxp1; 1697215976Sjmallett}; 1698215976Sjmalletttypedef union cvmx_sriomaintx_erb_err_rate_thr cvmx_sriomaintx_erb_err_rate_thr_t; 1699215976Sjmallett 1700215976Sjmallett/** 1701215976Sjmallett * cvmx_sriomaint#_erb_hdr 1702215976Sjmallett * 1703215976Sjmallett * SRIOMAINT_ERB_HDR = SRIO Error Reporting Block Header 1704215976Sjmallett * 1705215976Sjmallett * Error Reporting Block Header 1706215976Sjmallett * 1707215976Sjmallett * Notes: 1708215976Sjmallett * The error management extensions block header register contains the EF_PTR to the next EF_BLK and 1709215976Sjmallett * the EF_ID that identifies this as the error management extensions block header. In this 1710215976Sjmallett * implementation this is the last block and therefore the EF_PTR is a NULL pointer. 1711215976Sjmallett * 1712215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_HDR hclk hrst_n 1713215976Sjmallett */ 1714215976Sjmallettunion cvmx_sriomaintx_erb_hdr 1715215976Sjmallett{ 1716215976Sjmallett uint32_t u32; 1717215976Sjmallett struct cvmx_sriomaintx_erb_hdr_s 1718215976Sjmallett { 1719215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1720215976Sjmallett uint32_t ef_ptr : 16; /**< Pointer to the next block in the extended features 1721215976Sjmallett data structure. */ 1722215976Sjmallett uint32_t ef_id : 16; /**< Single Port ID */ 1723215976Sjmallett#else 1724215976Sjmallett uint32_t ef_id : 16; 1725215976Sjmallett uint32_t ef_ptr : 16; 1726215976Sjmallett#endif 1727215976Sjmallett } s; 1728215976Sjmallett struct cvmx_sriomaintx_erb_hdr_s cn63xx; 1729215976Sjmallett struct cvmx_sriomaintx_erb_hdr_s cn63xxp1; 1730215976Sjmallett}; 1731215976Sjmalletttypedef union cvmx_sriomaintx_erb_hdr cvmx_sriomaintx_erb_hdr_t; 1732215976Sjmallett 1733215976Sjmallett/** 1734215976Sjmallett * cvmx_sriomaint#_erb_lt_addr_capt_h 1735215976Sjmallett * 1736215976Sjmallett * SRIOMAINT_ERB_LT_ADDR_CAPT_H = SRIO Logical/Transport Layer High Address Capture 1737215976Sjmallett * 1738215976Sjmallett * Logical/Transport Layer High Address Capture 1739215976Sjmallett * 1740215976Sjmallett * Notes: 1741215976Sjmallett * This register contains error information. It is locked when a Logical/Transport error is detected 1742215976Sjmallett * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be 1743215976Sjmallett * written only when error detection is disabled. This register is only required for end point 1744215976Sjmallett * transactions of 50 or 66 bits. 1745215976Sjmallett * 1746215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ADDR_CAPT_H hclk hrst_n 1747215976Sjmallett */ 1748215976Sjmallettunion cvmx_sriomaintx_erb_lt_addr_capt_h 1749215976Sjmallett{ 1750215976Sjmallett uint32_t u32; 1751215976Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_h_s 1752215976Sjmallett { 1753215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1754215976Sjmallett uint32_t addr : 32; /**< Most significant 32 bits of the address associated 1755215976Sjmallett with the error. Information supplied for requests 1756215976Sjmallett and responses if available. */ 1757215976Sjmallett#else 1758215976Sjmallett uint32_t addr : 32; 1759215976Sjmallett#endif 1760215976Sjmallett } s; 1761215976Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xx; 1762215976Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xxp1; 1763215976Sjmallett}; 1764215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_addr_capt_h cvmx_sriomaintx_erb_lt_addr_capt_h_t; 1765215976Sjmallett 1766215976Sjmallett/** 1767215976Sjmallett * cvmx_sriomaint#_erb_lt_addr_capt_l 1768215976Sjmallett * 1769215976Sjmallett * SRIOMAINT_ERB_LT_ADDR_CAPT_L = SRIO Logical/Transport Layer Low Address Capture 1770215976Sjmallett * 1771215976Sjmallett * Logical/Transport Layer Low Address Capture 1772215976Sjmallett * 1773215976Sjmallett * Notes: 1774215976Sjmallett * This register contains error information. It is locked when a Logical/Transport error is detected 1775215976Sjmallett * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be 1776215976Sjmallett * written only when error detection is disabled. 1777215976Sjmallett * 1778215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ADDR_CAPT_L hclk hrst_n 1779215976Sjmallett */ 1780215976Sjmallettunion cvmx_sriomaintx_erb_lt_addr_capt_l 1781215976Sjmallett{ 1782215976Sjmallett uint32_t u32; 1783215976Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_l_s 1784215976Sjmallett { 1785215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1786215976Sjmallett uint32_t addr : 29; /**< Least significant 29 bits of the address 1787215976Sjmallett associated with the error. Bits 31:24 specify the 1788215976Sjmallett request HOP count for Maintenance Operations. 1789215976Sjmallett Information supplied for requests and responses if 1790215976Sjmallett available. */ 1791215976Sjmallett uint32_t reserved_2_2 : 1; 1792215976Sjmallett uint32_t xaddr : 2; /**< Extended address bits of the address associated 1793215976Sjmallett with the error. Information supplied for requests 1794215976Sjmallett and responses if available. */ 1795215976Sjmallett#else 1796215976Sjmallett uint32_t xaddr : 2; 1797215976Sjmallett uint32_t reserved_2_2 : 1; 1798215976Sjmallett uint32_t addr : 29; 1799215976Sjmallett#endif 1800215976Sjmallett } s; 1801215976Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xx; 1802215976Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xxp1; 1803215976Sjmallett}; 1804215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_addr_capt_l cvmx_sriomaintx_erb_lt_addr_capt_l_t; 1805215976Sjmallett 1806215976Sjmallett/** 1807215976Sjmallett * cvmx_sriomaint#_erb_lt_ctrl_capt 1808215976Sjmallett * 1809215976Sjmallett * SRIOMAINT_ERB_LT_CTRL_CAPT = SRIO Logical/Transport Layer Control Capture 1810215976Sjmallett * 1811215976Sjmallett * Logical/Transport Layer Control Capture 1812215976Sjmallett * 1813215976Sjmallett * Notes: 1814215976Sjmallett * This register contains error information. It is locked when a Logical/Transport error is detected 1815215976Sjmallett * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be 1816215976Sjmallett * written only when error detection is disabled. 1817215976Sjmallett * 1818215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_CTRL_CAPT hclk hrst_n 1819215976Sjmallett */ 1820215976Sjmallettunion cvmx_sriomaintx_erb_lt_ctrl_capt 1821215976Sjmallett{ 1822215976Sjmallett uint32_t u32; 1823215976Sjmallett struct cvmx_sriomaintx_erb_lt_ctrl_capt_s 1824215976Sjmallett { 1825215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1826215976Sjmallett uint32_t ftype : 4; /**< Format Type associated with the error */ 1827215976Sjmallett uint32_t ttype : 4; /**< Transaction Type associated with the error 1828215976Sjmallett (For Messages) 1829215976Sjmallett Message Length */ 1830215976Sjmallett uint32_t extra : 8; /**< Additional Information 1831215976Sjmallett (For Messages) 1832215976Sjmallett - 23:22 Letter 1833215976Sjmallett - 21:20 Mbox 1834215976Sjmallett - 19:16 Msgseg/xmbox 1835215976Sjmallett Information for the last message request sent 1836215976Sjmallett for the mailbox that had an error 1837215976Sjmallett (For Responses) 1838215976Sjmallett - 23:20 Response Request FTYPE 1839215976Sjmallett - 19:16 Response Request TTYPE 1840215976Sjmallett (For all other types) 1841215976Sjmallett Reserved. */ 1842215976Sjmallett uint32_t status : 4; /**< Response Status. 1843215976Sjmallett (For all other Requests) 1844215976Sjmallett Reserved. */ 1845215976Sjmallett uint32_t size : 4; /**< Size associated with the transaction. */ 1846215976Sjmallett uint32_t tt : 1; /**< Transfer Type 0=ID8, 1=ID16. */ 1847215976Sjmallett uint32_t wdptr : 1; /**< Word Pointer associated with the error. */ 1848215976Sjmallett uint32_t reserved_5_5 : 1; 1849215976Sjmallett uint32_t capt_idx : 5; /**< Capture Index. 31 - Bit set in 1850215976Sjmallett SRIOMAINT(0..1)_ERB_LT_ERR_DET. */ 1851215976Sjmallett#else 1852215976Sjmallett uint32_t capt_idx : 5; 1853215976Sjmallett uint32_t reserved_5_5 : 1; 1854215976Sjmallett uint32_t wdptr : 1; 1855215976Sjmallett uint32_t tt : 1; 1856215976Sjmallett uint32_t size : 4; 1857215976Sjmallett uint32_t status : 4; 1858215976Sjmallett uint32_t extra : 8; 1859215976Sjmallett uint32_t ttype : 4; 1860215976Sjmallett uint32_t ftype : 4; 1861215976Sjmallett#endif 1862215976Sjmallett } s; 1863215976Sjmallett struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xx; 1864215976Sjmallett struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xxp1; 1865215976Sjmallett}; 1866215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_ctrl_capt cvmx_sriomaintx_erb_lt_ctrl_capt_t; 1867215976Sjmallett 1868215976Sjmallett/** 1869215976Sjmallett * cvmx_sriomaint#_erb_lt_dev_id 1870215976Sjmallett * 1871215976Sjmallett * SRIOMAINT_ERB_LT_DEV_ID = SRIO Port-write Target deviceID 1872215976Sjmallett * 1873215976Sjmallett * Port-write Target deviceID 1874215976Sjmallett * 1875215976Sjmallett * Notes: 1876215976Sjmallett * This SRIO interface does not support generating Port-Writes based on ERB Errors. This register is 1877215976Sjmallett * currently unused and should be treated as reserved. 1878215976Sjmallett * 1879215976Sjmallett * Clk_Rst: SRIOMAINT_ERB_LT_DEV_ID hclk hrst_n 1880215976Sjmallett */ 1881215976Sjmallettunion cvmx_sriomaintx_erb_lt_dev_id 1882215976Sjmallett{ 1883215976Sjmallett uint32_t u32; 1884215976Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_s 1885215976Sjmallett { 1886215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1887215976Sjmallett uint32_t id16 : 8; /**< This is the most significant byte of the 1888215976Sjmallett port-write destination deviceID (large transport 1889215976Sjmallett systems only) 1890215976Sjmallett destination ID used for Port Write errors */ 1891215976Sjmallett uint32_t id8 : 8; /**< This is the port-write destination deviceID */ 1892215976Sjmallett uint32_t tt : 1; /**< Transport Type used for Port Write 1893215976Sjmallett 0 = Small Transport, ID8 Only 1894215976Sjmallett 1 = Large Transport, ID16 and ID8 */ 1895215976Sjmallett uint32_t reserved_0_14 : 15; 1896215976Sjmallett#else 1897215976Sjmallett uint32_t reserved_0_14 : 15; 1898215976Sjmallett uint32_t tt : 1; 1899215976Sjmallett uint32_t id8 : 8; 1900215976Sjmallett uint32_t id16 : 8; 1901215976Sjmallett#endif 1902215976Sjmallett } s; 1903215976Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xx; 1904215976Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xxp1; 1905215976Sjmallett}; 1906215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_dev_id cvmx_sriomaintx_erb_lt_dev_id_t; 1907215976Sjmallett 1908215976Sjmallett/** 1909215976Sjmallett * cvmx_sriomaint#_erb_lt_dev_id_capt 1910215976Sjmallett * 1911215976Sjmallett * SRIOMAINT_ERB_LT_DEV_ID_CAPT = SRIO Logical/Transport Layer Device ID Capture 1912215976Sjmallett * 1913215976Sjmallett * Logical/Transport Layer Device ID Capture 1914215976Sjmallett * 1915215976Sjmallett * Notes: 1916215976Sjmallett * This register contains error information. It is locked when a Logical/Transport error is detected 1917215976Sjmallett * and unlocked when the SRIOMAINT(0..1)_ERB_LT_ERR_DET is written to zero. This register should be 1918215976Sjmallett * written only when error detection is disabled. 1919215976Sjmallett * 1920215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_DEV_ID_CAPT hclk hrst_n 1921215976Sjmallett */ 1922215976Sjmallettunion cvmx_sriomaintx_erb_lt_dev_id_capt 1923215976Sjmallett{ 1924215976Sjmallett uint32_t u32; 1925215976Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_capt_s 1926215976Sjmallett { 1927215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1928215976Sjmallett uint32_t dst_id16 : 8; /**< Most significant byte of the large transport 1929215976Sjmallett destination ID associated with the error */ 1930215976Sjmallett uint32_t dst_id8 : 8; /**< Least significant byte of the large transport 1931215976Sjmallett destination ID or the 8-bit small transport 1932215976Sjmallett destination ID associated with the error */ 1933215976Sjmallett uint32_t src_id16 : 8; /**< Most significant byte of the large transport 1934215976Sjmallett source ID associated with the error */ 1935215976Sjmallett uint32_t src_id8 : 8; /**< Least significant byte of the large transport 1936215976Sjmallett source ID or the 8-bit small transport source ID 1937215976Sjmallett associated with the error */ 1938215976Sjmallett#else 1939215976Sjmallett uint32_t src_id8 : 8; 1940215976Sjmallett uint32_t src_id16 : 8; 1941215976Sjmallett uint32_t dst_id8 : 8; 1942215976Sjmallett uint32_t dst_id16 : 8; 1943215976Sjmallett#endif 1944215976Sjmallett } s; 1945215976Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xx; 1946215976Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xxp1; 1947215976Sjmallett}; 1948215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_dev_id_capt cvmx_sriomaintx_erb_lt_dev_id_capt_t; 1949215976Sjmallett 1950215976Sjmallett/** 1951215976Sjmallett * cvmx_sriomaint#_erb_lt_err_det 1952215976Sjmallett * 1953215976Sjmallett * SRIOMAINT_ERB_LT_ERR_DET = SRIO Logical/Transport Layer Error Detect 1954215976Sjmallett * 1955215976Sjmallett * SRIO Logical/Transport Layer Error Detect 1956215976Sjmallett * 1957215976Sjmallett * Notes: 1958215976Sjmallett * This register indicates the error that was detected by the Logical or Transport logic layer. 1959215976Sjmallett * Once a bit is set in this CSR, HW will lock the register until SW writes a zero to clear all the 1960215976Sjmallett * fields. The HW sets SRIO_INT_REG[LOG_ERB] every time it sets one of the bits. 1961215976Sjmallett * To handle the interrupt, the following procedure may be best: 1962215976Sjmallett * (1) clear SRIO_INT_REG[LOG_ERB], 1963215976Sjmallett * (2) read this CSR, corresponding SRIOMAINT*_ERB_LT_ADDR_CAPT_H, SRIOMAINT*_ERB_LT_ADDR_CAPT_L, 1964215976Sjmallett * SRIOMAINT*_ERB_LT_DEV_ID_CAPT, and SRIOMAINT*_ERB_LT_CTRL_CAPT 1965215976Sjmallett * (3) Write this CSR to 0. 1966215976Sjmallett * 1967215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ERR_DET hclk hrst_n 1968215976Sjmallett */ 1969215976Sjmallettunion cvmx_sriomaintx_erb_lt_err_det 1970215976Sjmallett{ 1971215976Sjmallett uint32_t u32; 1972215976Sjmallett struct cvmx_sriomaintx_erb_lt_err_det_s 1973215976Sjmallett { 1974215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 1975215976Sjmallett uint32_t io_err : 1; /**< Received a response of ERROR for an IO Logical 1976215976Sjmallett Layer Request. This includes all Maintenance and 1977215976Sjmallett Memory Responses not destined for the RX Soft 1978215976Sjmallett Packet FIFO. When SRIO receives an ERROR response 1979215976Sjmallett for a read, the issuing core or DPI DMA engine 1980215976Sjmallett receives result bytes with all bits set. In the 1981215976Sjmallett case of writes with response, this bit is the only 1982215976Sjmallett indication of failure. */ 1983215976Sjmallett uint32_t msg_err : 1; /**< Received a response of ERROR for an outgoing 1984215976Sjmallett message segment. This bit is the only direct 1985215976Sjmallett indication of a MSG_ERR. When a MSG_ERR occurs, 1986215976Sjmallett SRIO drops the message segment and will not set 1987215976Sjmallett SRIO*_INT_REG[OMSG*] after the message 1988215976Sjmallett "transfer". NOTE: SRIO can continue to send or 1989215976Sjmallett retry other segments from the same message after 1990215976Sjmallett a MSG_ERR. */ 1991215976Sjmallett uint32_t gsm_err : 1; /**< Received a response of ERROR for an GSM Logical 1992215976Sjmallett Request. SRIO hardware never sets this bit. GSM 1993215976Sjmallett operations are not supported (outside of the Soft 1994215976Sjmallett Packet FIFO). */ 1995215976Sjmallett uint32_t msg_fmt : 1; /**< Received an incoming Message Segment with a 1996215976Sjmallett formating error. A MSG_FMT error occurs when SRIO 1997215976Sjmallett receives a message segment with a reserved SSIZE, 1998215976Sjmallett or a illegal data payload size, or a MSGSEG greater 1999215976Sjmallett than MSGLEN, or a MSGSEG that is the duplicate of 2000215976Sjmallett one already received by an inflight message. 2001215976Sjmallett When a non-duplicate MSG_FMT error occurs, SRIO 2002215976Sjmallett drops the segment and sends an ERROR response. 2003215976Sjmallett When a duplicate MSG_FMT error occurs, SRIO 2004215976Sjmallett (internally) terminates the currently-inflight 2005215976Sjmallett message with an error and processes the duplicate, 2006215976Sjmallett which may result in a new message being generated 2007215976Sjmallett internally for the duplicate. */ 2008215976Sjmallett uint32_t ill_tran : 1; /**< Received illegal fields in the request/response 2009215976Sjmallett packet for a supported transaction or any packet 2010215976Sjmallett with a reserved transaction type. When an ILL_TRAN 2011215976Sjmallett error occurs, SRIO ignores the packet. ILL_TRAN 2012215976Sjmallett errors are 2nd priority after ILL_TGT and may mask 2013215976Sjmallett other problems. Packets with ILL_TRAN errors cannot 2014215976Sjmallett enter the RX Soft Packet FIFO. 2015215976Sjmallett There are two things that can set ILL_TRAN: 2016215976Sjmallett (1) SRIO received a packet with a tt value is not 2017215976Sjmallett 0 or 1, or (2) SRIO received a response to an 2018215976Sjmallett outstanding message segment whose status was not 2019215976Sjmallett DONE, RETRY, or ERROR. */ 2020215976Sjmallett uint32_t ill_tgt : 1; /**< Received a packet that contained a destination ID 2021215976Sjmallett other than SRIOMAINT*_PRI_DEV_ID or 2022215976Sjmallett SRIOMAINT*_SEC_DEV_ID. When an ILL_TGT error 2023215976Sjmallett occurs, SRIO drops the packet. ILL_TGT errors are 2024215976Sjmallett highest priority, so may mask other problems. 2025215976Sjmallett Packets with ILL_TGT errors cannot enter the RX 2026215976Sjmallett soft packet fifo. */ 2027215976Sjmallett uint32_t msg_tout : 1; /**< An expected incoming message request has not been 2028215976Sjmallett received within the time-out interval specified in 2029215976Sjmallett SRIOMAINT(0..1)_PORT_RT_CTL. When a MSG_TOUT occurs, 2030215976Sjmallett SRIO (internally) terminates the inflight message 2031215976Sjmallett with an error. */ 2032215976Sjmallett uint32_t pkt_tout : 1; /**< A required response has not been received to an 2033215976Sjmallett outgoing memory, maintenance or message request 2034215976Sjmallett before the time-out interval specified in 2035215976Sjmallett SRIOMAINT(0..1)_PORT_RT_CTL. When an IO or maintenance 2036215976Sjmallett read request operation has a PKT_TOUT, the issuing 2037215976Sjmallett core load or DPI DMA engine receive all ones for 2038215976Sjmallett the result. When an IO NWRITE_R has a PKT_TOUT, 2039215976Sjmallett this bit is the only indication of failure. When a 2040215976Sjmallett message request operation has a PKT_TOUT, SRIO 2041215976Sjmallett discards the the outgoing message segment, and 2042215976Sjmallett this bit is the only direct indication of failure. 2043215976Sjmallett NOTE: SRIO may continue to send or retry other 2044215976Sjmallett segments from the same message. When one or more of 2045215976Sjmallett the segments in an outgoing message have a 2046215976Sjmallett PKT_TOUT, SRIO will not set SRIO*_INT_REG[OMSG*] 2047215976Sjmallett after the message "transfer". */ 2048215976Sjmallett uint32_t uns_resp : 1; /**< An unsolicited/unexpected memory, maintenance or 2049215976Sjmallett message response packet was received that was not 2050215976Sjmallett destined for the RX Soft Packet FIFO. When this 2051215976Sjmallett condition is detected, the packet is dropped. */ 2052215976Sjmallett uint32_t uns_tran : 1; /**< A transaction is received that is not supported. 2053215976Sjmallett SRIO HW will never set this bit - SRIO routes all 2054215976Sjmallett unsupported transactions to the RX soft packet 2055215976Sjmallett FIFO. */ 2056215976Sjmallett uint32_t reserved_1_21 : 21; 2057215976Sjmallett uint32_t resp_sz : 1; /**< Received an incoming Memory or Maintenance 2058215976Sjmallett Read response packet with a DONE status and less 2059215976Sjmallett data then expected. This condition causes the 2060215976Sjmallett Read to be completed and an error response to be 2061215976Sjmallett returned with all the data bits set to the issuing 2062215976Sjmallett Core or DMA Engine. */ 2063215976Sjmallett#else 2064215976Sjmallett uint32_t resp_sz : 1; 2065215976Sjmallett uint32_t reserved_1_21 : 21; 2066215976Sjmallett uint32_t uns_tran : 1; 2067215976Sjmallett uint32_t uns_resp : 1; 2068215976Sjmallett uint32_t pkt_tout : 1; 2069215976Sjmallett uint32_t msg_tout : 1; 2070215976Sjmallett uint32_t ill_tgt : 1; 2071215976Sjmallett uint32_t ill_tran : 1; 2072215976Sjmallett uint32_t msg_fmt : 1; 2073215976Sjmallett uint32_t gsm_err : 1; 2074215976Sjmallett uint32_t msg_err : 1; 2075215976Sjmallett uint32_t io_err : 1; 2076215976Sjmallett#endif 2077215976Sjmallett } s; 2078215976Sjmallett struct cvmx_sriomaintx_erb_lt_err_det_s cn63xx; 2079215976Sjmallett struct cvmx_sriomaintx_erb_lt_err_det_s cn63xxp1; 2080215976Sjmallett}; 2081215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_err_det cvmx_sriomaintx_erb_lt_err_det_t; 2082215976Sjmallett 2083215976Sjmallett/** 2084215976Sjmallett * cvmx_sriomaint#_erb_lt_err_en 2085215976Sjmallett * 2086215976Sjmallett * SRIOMAINT_ERB_LT_ERR_EN = SRIO Logical/Transport Layer Error Enable 2087215976Sjmallett * 2088215976Sjmallett * SRIO Logical/Transport Layer Error Enable 2089215976Sjmallett * 2090215976Sjmallett * Notes: 2091215976Sjmallett * This register contains the bits that control if an error condition locks the Logical/Transport 2092215976Sjmallett * Layer Error Detect and Capture registers and is reported to the system host. 2093215976Sjmallett * 2094215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_LT_ERR_EN hclk hrst_n 2095215976Sjmallett */ 2096215976Sjmallettunion cvmx_sriomaintx_erb_lt_err_en 2097215976Sjmallett{ 2098215976Sjmallett uint32_t u32; 2099215976Sjmallett struct cvmx_sriomaintx_erb_lt_err_en_s 2100215976Sjmallett { 2101215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2102215976Sjmallett uint32_t io_err : 1; /**< Enable reporting of an IO error response. Save and 2103215976Sjmallett lock original request transaction information in 2104215976Sjmallett all Logical/Transport Layer Capture CSRs. */ 2105215976Sjmallett uint32_t msg_err : 1; /**< Enable reporting of a Message error response. Save 2106215976Sjmallett and lock original request transaction information 2107215976Sjmallett in all Logical/Transport Layer Capture CSRs. */ 2108215976Sjmallett uint32_t gsm_err : 1; /**< Enable reporting of a GSM error response. Save and 2109215976Sjmallett lock original request transaction capture 2110215976Sjmallett information in all Logical/Transport Layer Capture 2111215976Sjmallett CSRs. */ 2112215976Sjmallett uint32_t msg_fmt : 1; /**< Enable reporting of a message format error. Save 2113215976Sjmallett and lock transaction capture information in 2114215976Sjmallett Logical/Transport Layer Device ID and Control 2115215976Sjmallett Capture CSRs. */ 2116215976Sjmallett uint32_t ill_tran : 1; /**< Enable reporting of an illegal transaction decode 2117215976Sjmallett error Save and lock transaction capture 2118215976Sjmallett information in Logical/Transport Layer Device ID 2119215976Sjmallett and Control Capture CSRs. */ 2120215976Sjmallett uint32_t ill_tgt : 1; /**< Enable reporting of an illegal transaction target 2121215976Sjmallett error. Save and lock transaction capture 2122215976Sjmallett information in Logical/Transport Layer Device ID 2123215976Sjmallett and Control Capture CSRs. */ 2124215976Sjmallett uint32_t msg_tout : 1; /**< Enable reporting of a Message Request time-out 2125215976Sjmallett error. Save and lock transaction capture 2126215976Sjmallett information in Logical/Transport Layer Device ID 2127215976Sjmallett and Control Capture CSRs for the last Message 2128215976Sjmallett request segment packet received. */ 2129215976Sjmallett uint32_t pkt_tout : 1; /**< Enable reporting of a packet response time-out 2130215976Sjmallett error. Save and lock original request address in 2131215976Sjmallett Logical/Transport Layer Address Capture CSRs. 2132215976Sjmallett Save and lock original request Destination ID in 2133215976Sjmallett Logical/Transport Layer Device ID Capture CSR. */ 2134215976Sjmallett uint32_t uns_resp : 1; /**< Enable reporting of an unsolicited response error. 2135215976Sjmallett Save and lock transaction capture information in 2136215976Sjmallett Logical/Transport Layer Device ID and Control 2137215976Sjmallett Capture CSRs. */ 2138215976Sjmallett uint32_t uns_tran : 1; /**< Enable reporting of an unsupported transaction 2139215976Sjmallett error. Save and lock transaction capture 2140215976Sjmallett information in Logical/Transport Layer Device ID 2141215976Sjmallett and Control Capture CSRs. */ 2142215976Sjmallett uint32_t reserved_1_21 : 21; 2143215976Sjmallett uint32_t resp_sz : 1; /**< Enable reporting of an incoming response with 2144215976Sjmallett unexpected data size */ 2145215976Sjmallett#else 2146215976Sjmallett uint32_t resp_sz : 1; 2147215976Sjmallett uint32_t reserved_1_21 : 21; 2148215976Sjmallett uint32_t uns_tran : 1; 2149215976Sjmallett uint32_t uns_resp : 1; 2150215976Sjmallett uint32_t pkt_tout : 1; 2151215976Sjmallett uint32_t msg_tout : 1; 2152215976Sjmallett uint32_t ill_tgt : 1; 2153215976Sjmallett uint32_t ill_tran : 1; 2154215976Sjmallett uint32_t msg_fmt : 1; 2155215976Sjmallett uint32_t gsm_err : 1; 2156215976Sjmallett uint32_t msg_err : 1; 2157215976Sjmallett uint32_t io_err : 1; 2158215976Sjmallett#endif 2159215976Sjmallett } s; 2160215976Sjmallett struct cvmx_sriomaintx_erb_lt_err_en_s cn63xx; 2161215976Sjmallett struct cvmx_sriomaintx_erb_lt_err_en_s cn63xxp1; 2162215976Sjmallett}; 2163215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_err_en cvmx_sriomaintx_erb_lt_err_en_t; 2164215976Sjmallett 2165215976Sjmallett/** 2166215976Sjmallett * cvmx_sriomaint#_erb_pack_capt_1 2167215976Sjmallett * 2168215976Sjmallett * SRIOMAINT_ERB_PACK_CAPT_1 = SRIO Packet Capture 1 2169215976Sjmallett * 2170215976Sjmallett * Packet Capture 1 2171215976Sjmallett * 2172215976Sjmallett * Notes: 2173215976Sjmallett * Error capture register 1 contains either long symbol capture information or bytes 4 through 7 of 2174215976Sjmallett * the packet header. 2175215976Sjmallett * The HW will not update this register (i.e. this register is locked) while 2176215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2177215976Sjmallett * 2178215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_CAPT_1 hclk hrst_n 2179215976Sjmallett */ 2180215976Sjmallettunion cvmx_sriomaintx_erb_pack_capt_1 2181215976Sjmallett{ 2182215976Sjmallett uint32_t u32; 2183215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_1_s 2184215976Sjmallett { 2185215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2186215976Sjmallett uint32_t capture : 32; /**< Bytes 4 thru 7 of the packet header. */ 2187215976Sjmallett#else 2188215976Sjmallett uint32_t capture : 32; 2189215976Sjmallett#endif 2190215976Sjmallett } s; 2191215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xx; 2192215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xxp1; 2193215976Sjmallett}; 2194215976Sjmalletttypedef union cvmx_sriomaintx_erb_pack_capt_1 cvmx_sriomaintx_erb_pack_capt_1_t; 2195215976Sjmallett 2196215976Sjmallett/** 2197215976Sjmallett * cvmx_sriomaint#_erb_pack_capt_2 2198215976Sjmallett * 2199215976Sjmallett * SRIOMAINT_ERB_PACK_CAPT_2 = SRIO Packet Capture 2 2200215976Sjmallett * 2201215976Sjmallett * Packet Capture 2 2202215976Sjmallett * 2203215976Sjmallett * Notes: 2204215976Sjmallett * Error capture register 2 contains bytes 8 through 11 of the packet header. 2205215976Sjmallett * The HW will not update this register (i.e. this register is locked) while 2206215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2207215976Sjmallett * 2208215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_CAPT_2 hclk hrst_n 2209215976Sjmallett */ 2210215976Sjmallettunion cvmx_sriomaintx_erb_pack_capt_2 2211215976Sjmallett{ 2212215976Sjmallett uint32_t u32; 2213215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_2_s 2214215976Sjmallett { 2215215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2216215976Sjmallett uint32_t capture : 32; /**< Bytes 8 thru 11 of the packet header. */ 2217215976Sjmallett#else 2218215976Sjmallett uint32_t capture : 32; 2219215976Sjmallett#endif 2220215976Sjmallett } s; 2221215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xx; 2222215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xxp1; 2223215976Sjmallett}; 2224215976Sjmalletttypedef union cvmx_sriomaintx_erb_pack_capt_2 cvmx_sriomaintx_erb_pack_capt_2_t; 2225215976Sjmallett 2226215976Sjmallett/** 2227215976Sjmallett * cvmx_sriomaint#_erb_pack_capt_3 2228215976Sjmallett * 2229215976Sjmallett * SRIOMAINT_ERB_PACK_CAPT_3 = SRIO Packet Capture 3 2230215976Sjmallett * 2231215976Sjmallett * Packet Capture 3 2232215976Sjmallett * 2233215976Sjmallett * Notes: 2234215976Sjmallett * Error capture register 3 contains bytes 12 through 15 of the packet header. 2235215976Sjmallett * The HW will not update this register (i.e. this register is locked) while 2236215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2237215976Sjmallett * 2238215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_CAPT_3 hclk hrst_n 2239215976Sjmallett */ 2240215976Sjmallettunion cvmx_sriomaintx_erb_pack_capt_3 2241215976Sjmallett{ 2242215976Sjmallett uint32_t u32; 2243215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_3_s 2244215976Sjmallett { 2245215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2246215976Sjmallett uint32_t capture : 32; /**< Bytes 12 thru 15 of the packet header. */ 2247215976Sjmallett#else 2248215976Sjmallett uint32_t capture : 32; 2249215976Sjmallett#endif 2250215976Sjmallett } s; 2251215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xx; 2252215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xxp1; 2253215976Sjmallett}; 2254215976Sjmalletttypedef union cvmx_sriomaintx_erb_pack_capt_3 cvmx_sriomaintx_erb_pack_capt_3_t; 2255215976Sjmallett 2256215976Sjmallett/** 2257215976Sjmallett * cvmx_sriomaint#_erb_pack_sym_capt 2258215976Sjmallett * 2259215976Sjmallett * SRIOMAINT_ERB_PACK_SYM_CAPT = SRIO Packet/Control Symbol Capture 2260215976Sjmallett * 2261215976Sjmallett * Packet/Control Symbol Capture 2262215976Sjmallett * 2263215976Sjmallett * Notes: 2264215976Sjmallett * This register contains either captured control symbol information or the first 4 bytes of captured 2265215976Sjmallett * packet information. The Errors that generate Partial Control Symbols can be found in 2266215976Sjmallett * SRIOMAINT*_ERB_ERR_DET. The HW will not update this register (i.e. this register is locked) while 2267215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2268215976Sjmallett * 2269215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT hclk hrst_n 2270215976Sjmallett */ 2271215976Sjmallettunion cvmx_sriomaintx_erb_pack_sym_capt 2272215976Sjmallett{ 2273215976Sjmallett uint32_t u32; 2274215976Sjmallett struct cvmx_sriomaintx_erb_pack_sym_capt_s 2275215976Sjmallett { 2276215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2277215976Sjmallett uint32_t capture : 32; /**< Control Character and Control Symbol or Bytes 0 to 2278215976Sjmallett 3 of Packet Header 2279215976Sjmallett The Control Symbol consists of 2280215976Sjmallett - 31:24 - SC Character (0 in Partial Symbol) 2281215976Sjmallett - 23:21 - Stype 0 2282215976Sjmallett - 20:16 - Parameter 0 2283215976Sjmallett - 15:11 - Parameter 1 2284215976Sjmallett - 10: 8 - Stype 1 (0 in Partial Symbol) 2285215976Sjmallett - 7: 5 - Command (0 in Partial Symbol) 2286215976Sjmallett - 4: 0 - CRC5 (0 in Partial Symbol) */ 2287215976Sjmallett#else 2288215976Sjmallett uint32_t capture : 32; 2289215976Sjmallett#endif 2290215976Sjmallett } s; 2291215976Sjmallett struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xx; 2292215976Sjmallett struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xxp1; 2293215976Sjmallett}; 2294215976Sjmalletttypedef union cvmx_sriomaintx_erb_pack_sym_capt cvmx_sriomaintx_erb_pack_sym_capt_t; 2295215976Sjmallett 2296215976Sjmallett/** 2297215976Sjmallett * cvmx_sriomaint#_hb_dev_id_lock 2298215976Sjmallett * 2299215976Sjmallett * SRIOMAINT_HB_DEV_ID_LOCK = SRIO Host Device ID Lock 2300215976Sjmallett * 2301215976Sjmallett * The Host Base Device ID 2302215976Sjmallett * 2303215976Sjmallett * Notes: 2304215976Sjmallett * This register contains the Device ID of the Host responsible for initializing this SRIO device. 2305215976Sjmallett * The register contains a special write once function that captures the first HOSTID written to it 2306215976Sjmallett * after reset. The function allows several potential hosts to write to this register and then read 2307215976Sjmallett * it to see if they have responsibility for initialization. The register can be unlocked by 2308215976Sjmallett * rewriting the current host value. This will reset the lock and restore the value to 0xFFFF. 2309215976Sjmallett * 2310215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_HB_DEV_ID_LOCK hclk hrst_n 2311215976Sjmallett */ 2312215976Sjmallettunion cvmx_sriomaintx_hb_dev_id_lock 2313215976Sjmallett{ 2314215976Sjmallett uint32_t u32; 2315215976Sjmallett struct cvmx_sriomaintx_hb_dev_id_lock_s 2316215976Sjmallett { 2317215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2318215976Sjmallett uint32_t reserved_16_31 : 16; 2319215976Sjmallett uint32_t hostid : 16; /**< Primary 16-bit Device ID */ 2320215976Sjmallett#else 2321215976Sjmallett uint32_t hostid : 16; 2322215976Sjmallett uint32_t reserved_16_31 : 16; 2323215976Sjmallett#endif 2324215976Sjmallett } s; 2325215976Sjmallett struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xx; 2326215976Sjmallett struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xxp1; 2327215976Sjmallett}; 2328215976Sjmalletttypedef union cvmx_sriomaintx_hb_dev_id_lock cvmx_sriomaintx_hb_dev_id_lock_t; 2329215976Sjmallett 2330215976Sjmallett/** 2331215976Sjmallett * cvmx_sriomaint#_ir_buffer_config 2332215976Sjmallett * 2333215976Sjmallett * SRIOMAINT_IR_BUFFER_CONFIG = SRIO Buffer Configuration 2334215976Sjmallett * 2335215976Sjmallett * Buffer Configuration 2336215976Sjmallett * 2337215976Sjmallett * Notes: 2338215976Sjmallett * This register controls the operation of the SRIO Core buffer mux logic. 2339215976Sjmallett * 2340215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_BUFFER_CONFIG hclk hrst_n 2341215976Sjmallett */ 2342215976Sjmallettunion cvmx_sriomaintx_ir_buffer_config 2343215976Sjmallett{ 2344215976Sjmallett uint32_t u32; 2345215976Sjmallett struct cvmx_sriomaintx_ir_buffer_config_s 2346215976Sjmallett { 2347215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2348215976Sjmallett uint32_t tx_wm0 : 4; /**< Transmitter Flow Control Priority 0 Threshold. 2349215976Sjmallett Number of Receive Buffers available before packet 2350215976Sjmallett can be scheduled for transmission. 2351215976Sjmallett Maximum Value 8. 2352215976Sjmallett Generally, TX_WM0 Must be > TX_WM1 to reserve 2353215976Sjmallett buffers for priority 1-3 packets when transmitting 2354215976Sjmallett in transmitter-controlled flow control mode. 2355215976Sjmallett TX_WM0 is not used by the hardware when TX_FLOW=0 2356215976Sjmallett or whenever transmitting in 2357215976Sjmallett receiver-controlled flow-control mode. */ 2358215976Sjmallett uint32_t tx_wm1 : 4; /**< Transmitter Flow Control Priority 1 Threshold. 2359215976Sjmallett Number of Receive Buffers available before packet 2360215976Sjmallett can be scheduled for transmission. 2361215976Sjmallett Maximum Value 8. 2362215976Sjmallett Generally, TX_WM1 Must be > TX_WM2 to reserve 2363215976Sjmallett buffers for priority 2-3 packets when transmitting 2364215976Sjmallett in transmitter-controlled flow control mode. 2365215976Sjmallett TX_WM1 is not used by the hardware when TX_FLOW=0 2366215976Sjmallett or whenever transmitting in 2367215976Sjmallett receiver-controlled flow-control mode. */ 2368215976Sjmallett uint32_t tx_wm2 : 4; /**< Transmitter Flow Control Priority 2 Threshold. 2369215976Sjmallett Number of Receive Buffers available before packet 2370215976Sjmallett can be scheduled for transmission. 2371215976Sjmallett Maximum Value 8. 2372215976Sjmallett Generally, TX_WM2 Must be > 0 to reserve a 2373215976Sjmallett buffer for priority 3 packets when transmitting 2374215976Sjmallett in transmitter-controlled flow control mode. 2375215976Sjmallett TX_WM2 is not used by the hardware when TX_FLOW=0 2376215976Sjmallett or whenever transmitting in 2377215976Sjmallett receiver-controlled flow-control mode. */ 2378215976Sjmallett uint32_t reserved_3_19 : 17; 2379215976Sjmallett uint32_t tx_flow : 1; /**< Controls whether Transmitter Flow Control is 2380215976Sjmallett permitted on this device. 2381215976Sjmallett 0 - Disabled 2382215976Sjmallett 1 - Permitted 2383215976Sjmallett The reset value of this field is 2384215976Sjmallett SRIO*_IP_FEATURE[TX_FLOW]. */ 2385215976Sjmallett uint32_t tx_sync : 1; /**< Controls whether the synchronizers are enabled 2386215976Sjmallett between the SRIO TXCLK and the Internal Clocks. 2387215976Sjmallett 0 - Synchronizers are enabled 2388215976Sjmallett 1 - Synchronizers are disabled */ 2389215976Sjmallett uint32_t rx_sync : 1; /**< Controls whether the synchronizers are enabled 2390215976Sjmallett between the SRIO RXCLK and the Internal Clocks. 2391215976Sjmallett 0 - Synchronizers are enabled 2392215976Sjmallett 1 - Synchronizers are disabled */ 2393215976Sjmallett#else 2394215976Sjmallett uint32_t rx_sync : 1; 2395215976Sjmallett uint32_t tx_sync : 1; 2396215976Sjmallett uint32_t tx_flow : 1; 2397215976Sjmallett uint32_t reserved_3_19 : 17; 2398215976Sjmallett uint32_t tx_wm2 : 4; 2399215976Sjmallett uint32_t tx_wm1 : 4; 2400215976Sjmallett uint32_t tx_wm0 : 4; 2401215976Sjmallett#endif 2402215976Sjmallett } s; 2403215976Sjmallett struct cvmx_sriomaintx_ir_buffer_config_s cn63xx; 2404215976Sjmallett struct cvmx_sriomaintx_ir_buffer_config_s cn63xxp1; 2405215976Sjmallett}; 2406215976Sjmalletttypedef union cvmx_sriomaintx_ir_buffer_config cvmx_sriomaintx_ir_buffer_config_t; 2407215976Sjmallett 2408215976Sjmallett/** 2409215976Sjmallett * cvmx_sriomaint#_ir_buffer_config2 2410215976Sjmallett * 2411215976Sjmallett * SRIOMAINT_IR_BUFFER_CONFIG2 = SRIO Buffer Configuration 2 (Pass 2) 2412215976Sjmallett * 2413215976Sjmallett * Buffer Configuration 2 2414215976Sjmallett * 2415215976Sjmallett * Notes: 2416215976Sjmallett * This register controls the RX and TX Buffer availablility by priority. The typical values are 2417215976Sjmallett * optimized for normal operation. Care must be taken when changing these values to avoid values 2418215976Sjmallett * which can result in deadlocks. Disabling a priority is not recommended and can result in system 2419215976Sjmallett * level failures. 2420215976Sjmallett * 2421215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_BUFFER_CONFIG2 hclk hrst_n 2422215976Sjmallett */ 2423215976Sjmallettunion cvmx_sriomaintx_ir_buffer_config2 2424215976Sjmallett{ 2425215976Sjmallett uint32_t u32; 2426215976Sjmallett struct cvmx_sriomaintx_ir_buffer_config2_s 2427215976Sjmallett { 2428215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2429215976Sjmallett uint32_t tx_wm3 : 4; /**< Number of buffers free before a priority 3 packet 2430215976Sjmallett will be transmitted. A value of 9 will disable 2431215976Sjmallett this priority. */ 2432215976Sjmallett uint32_t tx_wm2 : 4; /**< Number of buffers free before a priority 2 packet 2433215976Sjmallett will be transmitted. A value of 9 will disable 2434215976Sjmallett this priority. */ 2435215976Sjmallett uint32_t tx_wm1 : 4; /**< Number of buffers free before a priority 1 packet 2436215976Sjmallett will be transmitted. A value of 9 will disable 2437215976Sjmallett this priority. */ 2438215976Sjmallett uint32_t tx_wm0 : 4; /**< Number of buffers free before a priority 0 packet 2439215976Sjmallett will be transmitted. A value of 9 will disable 2440215976Sjmallett this priority. */ 2441215976Sjmallett uint32_t rx_wm3 : 4; /**< Number of buffers free before a priority 3 packet 2442215976Sjmallett will be accepted. A value of 9 will disable this 2443215976Sjmallett priority and always cause a physical layer RETRY. */ 2444215976Sjmallett uint32_t rx_wm2 : 4; /**< Number of buffers free before a priority 2 packet 2445215976Sjmallett will be accepted. A value of 9 will disable this 2446215976Sjmallett priority and always cause a physical layer RETRY. */ 2447215976Sjmallett uint32_t rx_wm1 : 4; /**< Number of buffers free before a priority 1 packet 2448215976Sjmallett will be accepted. A value of 9 will disable this 2449215976Sjmallett priority and always cause a physical layer RETRY. */ 2450215976Sjmallett uint32_t rx_wm0 : 4; /**< Number of buffers free before a priority 0 packet 2451215976Sjmallett will be accepted. A value of 9 will disable this 2452215976Sjmallett priority and always cause a physical layer RETRY. */ 2453215976Sjmallett#else 2454215976Sjmallett uint32_t rx_wm0 : 4; 2455215976Sjmallett uint32_t rx_wm1 : 4; 2456215976Sjmallett uint32_t rx_wm2 : 4; 2457215976Sjmallett uint32_t rx_wm3 : 4; 2458215976Sjmallett uint32_t tx_wm0 : 4; 2459215976Sjmallett uint32_t tx_wm1 : 4; 2460215976Sjmallett uint32_t tx_wm2 : 4; 2461215976Sjmallett uint32_t tx_wm3 : 4; 2462215976Sjmallett#endif 2463215976Sjmallett } s; 2464215976Sjmallett struct cvmx_sriomaintx_ir_buffer_config2_s cn63xx; 2465215976Sjmallett}; 2466215976Sjmalletttypedef union cvmx_sriomaintx_ir_buffer_config2 cvmx_sriomaintx_ir_buffer_config2_t; 2467215976Sjmallett 2468215976Sjmallett/** 2469215976Sjmallett * cvmx_sriomaint#_ir_pd_phy_ctrl 2470215976Sjmallett * 2471215976Sjmallett * SRIOMAINT_IR_PD_PHY_CTRL = SRIO Platform Dependent PHY Control 2472215976Sjmallett * 2473215976Sjmallett * Platform Dependent PHY Control 2474215976Sjmallett * 2475215976Sjmallett * Notes: 2476215976Sjmallett * This register can be used for testing. The register is otherwise unused by the hardware. 2477215976Sjmallett * 2478215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_PD_PHY_CTRL hclk hrst_n 2479215976Sjmallett */ 2480215976Sjmallettunion cvmx_sriomaintx_ir_pd_phy_ctrl 2481215976Sjmallett{ 2482215976Sjmallett uint32_t u32; 2483215976Sjmallett struct cvmx_sriomaintx_ir_pd_phy_ctrl_s 2484215976Sjmallett { 2485215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2486215976Sjmallett uint32_t pd_ctrl : 32; /**< Unused Register available for testing */ 2487215976Sjmallett#else 2488215976Sjmallett uint32_t pd_ctrl : 32; 2489215976Sjmallett#endif 2490215976Sjmallett } s; 2491215976Sjmallett struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xx; 2492215976Sjmallett struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xxp1; 2493215976Sjmallett}; 2494215976Sjmalletttypedef union cvmx_sriomaintx_ir_pd_phy_ctrl cvmx_sriomaintx_ir_pd_phy_ctrl_t; 2495215976Sjmallett 2496215976Sjmallett/** 2497215976Sjmallett * cvmx_sriomaint#_ir_pd_phy_stat 2498215976Sjmallett * 2499215976Sjmallett * SRIOMAINT_IR_PD_PHY_STAT = SRIO Platform Dependent PHY Status 2500215976Sjmallett * 2501215976Sjmallett * Platform Dependent PHY Status 2502215976Sjmallett * 2503215976Sjmallett * Notes: 2504215976Sjmallett * This register is used to monitor PHY status on each lane. They are documented here to assist in 2505215976Sjmallett * debugging only. The lane numbers take into account the lane swap pin. 2506215976Sjmallett * 2507215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_PD_PHY_STAT hclk hrst_n 2508215976Sjmallett */ 2509215976Sjmallettunion cvmx_sriomaintx_ir_pd_phy_stat 2510215976Sjmallett{ 2511215976Sjmallett uint32_t u32; 2512215976Sjmallett struct cvmx_sriomaintx_ir_pd_phy_stat_s 2513215976Sjmallett { 2514215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2515215976Sjmallett uint32_t reserved_16_31 : 16; 2516215976Sjmallett uint32_t ln3_rx : 3; /**< Phy Lane 3 RX Status 2517215976Sjmallett 0XX = Normal Operation 2518215976Sjmallett 100 = 8B/10B Error 2519215976Sjmallett 101 = Elastic Buffer Overflow (Data Lost) 2520215976Sjmallett 110 = Elastic Buffer Underflow (Data Corrupted) 2521215976Sjmallett 111 = Disparity Error */ 2522215976Sjmallett uint32_t ln3_dis : 1; /**< Lane 3 Phy Clock Disabled 2523215976Sjmallett 0 = Phy Clock Valid 2524215976Sjmallett 1 = Phy Clock InValid */ 2525215976Sjmallett uint32_t ln2_rx : 3; /**< Phy Lane 2 RX Status 2526215976Sjmallett 0XX = Normal Operation 2527215976Sjmallett 100 = 8B/10B Error 2528215976Sjmallett 101 = Elastic Buffer Overflow (Data Lost) 2529215976Sjmallett 110 = Elastic Buffer Underflow (Data Corrupted) 2530215976Sjmallett 111 = Disparity Error */ 2531215976Sjmallett uint32_t ln2_dis : 1; /**< Lane 2 Phy Clock Disabled 2532215976Sjmallett 0 = Phy Clock Valid 2533215976Sjmallett 1 = Phy Clock InValid */ 2534215976Sjmallett uint32_t ln1_rx : 3; /**< Phy Lane 1 RX Status 2535215976Sjmallett 0XX = Normal Operation 2536215976Sjmallett 100 = 8B/10B Error 2537215976Sjmallett 101 = Elastic Buffer Overflow (Data Lost) 2538215976Sjmallett 110 = Elastic Buffer Underflow (Data Corrupted) 2539215976Sjmallett 111 = Disparity Error */ 2540215976Sjmallett uint32_t ln1_dis : 1; /**< Lane 1 Phy Clock Disabled 2541215976Sjmallett 0 = Phy Clock Valid 2542215976Sjmallett 1 = Phy Clock InValid */ 2543215976Sjmallett uint32_t ln0_rx : 3; /**< Phy Lane 0 RX Status 2544215976Sjmallett 0XX = Normal Operation 2545215976Sjmallett 100 = 8B/10B Error 2546215976Sjmallett 101 = Elastic Buffer Overflow (Data Lost) 2547215976Sjmallett 110 = Elastic Buffer Underflow (Data Corrupted) 2548215976Sjmallett 111 = Disparity Error */ 2549215976Sjmallett uint32_t ln0_dis : 1; /**< Lane 0 Phy Clock Disabled 2550215976Sjmallett 0 = Phy Clock Valid 2551215976Sjmallett 1 = Phy Clock InValid */ 2552215976Sjmallett#else 2553215976Sjmallett uint32_t ln0_dis : 1; 2554215976Sjmallett uint32_t ln0_rx : 3; 2555215976Sjmallett uint32_t ln1_dis : 1; 2556215976Sjmallett uint32_t ln1_rx : 3; 2557215976Sjmallett uint32_t ln2_dis : 1; 2558215976Sjmallett uint32_t ln2_rx : 3; 2559215976Sjmallett uint32_t ln3_dis : 1; 2560215976Sjmallett uint32_t ln3_rx : 3; 2561215976Sjmallett uint32_t reserved_16_31 : 16; 2562215976Sjmallett#endif 2563215976Sjmallett } s; 2564215976Sjmallett struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xx; 2565215976Sjmallett struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xxp1; 2566215976Sjmallett}; 2567215976Sjmalletttypedef union cvmx_sriomaintx_ir_pd_phy_stat cvmx_sriomaintx_ir_pd_phy_stat_t; 2568215976Sjmallett 2569215976Sjmallett/** 2570215976Sjmallett * cvmx_sriomaint#_ir_pi_phy_ctrl 2571215976Sjmallett * 2572215976Sjmallett * SRIOMAINT_IR_PI_PHY_CTRL = SRIO Platform Independent PHY Control 2573215976Sjmallett * 2574215976Sjmallett * Platform Independent PHY Control 2575215976Sjmallett * 2576215976Sjmallett * Notes: 2577215976Sjmallett * This register is used to control platform independent operating modes of the transceivers. These 2578215976Sjmallett * control bits are uniform across all platforms. 2579215976Sjmallett * 2580215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_PI_PHY_CTRL hclk hrst_n 2581215976Sjmallett */ 2582215976Sjmallettunion cvmx_sriomaintx_ir_pi_phy_ctrl 2583215976Sjmallett{ 2584215976Sjmallett uint32_t u32; 2585215976Sjmallett struct cvmx_sriomaintx_ir_pi_phy_ctrl_s 2586215976Sjmallett { 2587215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2588215976Sjmallett uint32_t tx_reset : 1; /**< Outgoing PHY Logic Reset. 0=Reset, 1=Normal Op */ 2589215976Sjmallett uint32_t rx_reset : 1; /**< Incoming PHY Logic Reset. 0=Reset, 1=Normal Op */ 2590215976Sjmallett uint32_t reserved_29_29 : 1; 2591215976Sjmallett uint32_t loopback : 2; /**< These bits control the state of the loopback 2592215976Sjmallett control vector on the transceiver interface. The 2593215976Sjmallett loopback modes are enumerated as follows: 2594215976Sjmallett 00 - No Loopback 2595215976Sjmallett 01 - Near End PCS Loopback 2596215976Sjmallett 10 - Far End PCS Loopback 2597215976Sjmallett 11 - Both Near and Far End PCS Loopback */ 2598215976Sjmallett uint32_t reserved_0_26 : 27; 2599215976Sjmallett#else 2600215976Sjmallett uint32_t reserved_0_26 : 27; 2601215976Sjmallett uint32_t loopback : 2; 2602215976Sjmallett uint32_t reserved_29_29 : 1; 2603215976Sjmallett uint32_t rx_reset : 1; 2604215976Sjmallett uint32_t tx_reset : 1; 2605215976Sjmallett#endif 2606215976Sjmallett } s; 2607215976Sjmallett struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xx; 2608215976Sjmallett struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xxp1; 2609215976Sjmallett}; 2610215976Sjmalletttypedef union cvmx_sriomaintx_ir_pi_phy_ctrl cvmx_sriomaintx_ir_pi_phy_ctrl_t; 2611215976Sjmallett 2612215976Sjmallett/** 2613215976Sjmallett * cvmx_sriomaint#_ir_pi_phy_stat 2614215976Sjmallett * 2615215976Sjmallett * SRIOMAINT_IR_PI_PHY_STAT = SRIO Platform Independent PHY Status 2616215976Sjmallett * 2617215976Sjmallett * Platform Independent PHY Status 2618215976Sjmallett * 2619215976Sjmallett * Notes: 2620215976Sjmallett * This register displays the status of the link initialization state machine. Changes to this state 2621215976Sjmallett * cause the SRIO(0..1)_INT_REG.LINK_UP or SRIO(0..1)_INT_REG.LINK_DOWN interrupts. 2622215976Sjmallett * 2623215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_PI_PHY_STAT hclk hrst_n 2624215976Sjmallett */ 2625215976Sjmallettunion cvmx_sriomaintx_ir_pi_phy_stat 2626215976Sjmallett{ 2627215976Sjmallett uint32_t u32; 2628215976Sjmallett struct cvmx_sriomaintx_ir_pi_phy_stat_s 2629215976Sjmallett { 2630215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2631215976Sjmallett uint32_t reserved_12_31 : 20; 2632215976Sjmallett uint32_t tx_rdy : 1; /**< Minimum number of Status Transmitted (Pass 2) */ 2633215976Sjmallett uint32_t rx_rdy : 1; /**< Minimum number of Good Status Received (Pass 2) */ 2634215976Sjmallett uint32_t init_sm : 10; /**< Initialization State Machine 2635215976Sjmallett 001 - Silent 2636215976Sjmallett 002 - Seek 2637215976Sjmallett 004 - Discovery 2638215976Sjmallett 008 - 1x_Mode_Lane0 2639215976Sjmallett 010 - 1x_Mode_Lane1 2640215976Sjmallett 020 - 1x_Mode_Lane2 2641215976Sjmallett 040 - 1x_Recovery 2642215976Sjmallett 080 - 2x_Mode 2643215976Sjmallett 100 - 2x_Recovery 2644215976Sjmallett 200 - 4x_Mode 2645215976Sjmallett All others are reserved */ 2646215976Sjmallett#else 2647215976Sjmallett uint32_t init_sm : 10; 2648215976Sjmallett uint32_t rx_rdy : 1; 2649215976Sjmallett uint32_t tx_rdy : 1; 2650215976Sjmallett uint32_t reserved_12_31 : 20; 2651215976Sjmallett#endif 2652215976Sjmallett } s; 2653215976Sjmallett struct cvmx_sriomaintx_ir_pi_phy_stat_s cn63xx; 2654215976Sjmallett struct cvmx_sriomaintx_ir_pi_phy_stat_cn63xxp1 2655215976Sjmallett { 2656215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2657215976Sjmallett uint32_t reserved_10_31 : 22; 2658215976Sjmallett uint32_t init_sm : 10; /**< Initialization State Machine 2659215976Sjmallett 001 - Silent 2660215976Sjmallett 002 - Seek 2661215976Sjmallett 004 - Discovery 2662215976Sjmallett 008 - 1x_Mode_Lane0 2663215976Sjmallett 010 - 1x_Mode_Lane1 2664215976Sjmallett 020 - 1x_Mode_Lane2 2665215976Sjmallett 040 - 1x_Recovery 2666215976Sjmallett 080 - 2x_Mode 2667215976Sjmallett 100 - 2x_Recovery 2668215976Sjmallett 200 - 4x_Mode 2669215976Sjmallett All others are reserved */ 2670215976Sjmallett#else 2671215976Sjmallett uint32_t init_sm : 10; 2672215976Sjmallett uint32_t reserved_10_31 : 22; 2673215976Sjmallett#endif 2674215976Sjmallett } cn63xxp1; 2675215976Sjmallett}; 2676215976Sjmalletttypedef union cvmx_sriomaintx_ir_pi_phy_stat cvmx_sriomaintx_ir_pi_phy_stat_t; 2677215976Sjmallett 2678215976Sjmallett/** 2679215976Sjmallett * cvmx_sriomaint#_ir_sp_rx_ctrl 2680215976Sjmallett * 2681215976Sjmallett * SRIOMAINT_IR_SP_RX_CTRL = SRIO Soft Packet FIFO Receive Control 2682215976Sjmallett * 2683215976Sjmallett * Soft Packet FIFO Receive Control 2684215976Sjmallett * 2685215976Sjmallett * Notes: 2686215976Sjmallett * This register is used to configure events generated by the reception of packets using the soft 2687215976Sjmallett * packet FIFO. 2688215976Sjmallett * 2689215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_SP_RX_CTRL hclk hrst_n 2690215976Sjmallett */ 2691215976Sjmallettunion cvmx_sriomaintx_ir_sp_rx_ctrl 2692215976Sjmallett{ 2693215976Sjmallett uint32_t u32; 2694215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_ctrl_s 2695215976Sjmallett { 2696215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2697215976Sjmallett uint32_t reserved_1_31 : 31; 2698215976Sjmallett uint32_t overwrt : 1; /**< When clear, SRIO drops received packets that should 2699215976Sjmallett enter the soft packet FIFO when the FIFO is full. 2700215976Sjmallett When set, SRIO 2701215976Sjmallett stalls received packets that should enter the soft 2702215976Sjmallett packet FIFO when the FIFO is full. SRIO may stop 2703215976Sjmallett receiving any packets in this stall case if 2704215976Sjmallett software does not drain the receive soft packet 2705215976Sjmallett FIFO. */ 2706215976Sjmallett#else 2707215976Sjmallett uint32_t overwrt : 1; 2708215976Sjmallett uint32_t reserved_1_31 : 31; 2709215976Sjmallett#endif 2710215976Sjmallett } s; 2711215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xx; 2712215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xxp1; 2713215976Sjmallett}; 2714215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_rx_ctrl cvmx_sriomaintx_ir_sp_rx_ctrl_t; 2715215976Sjmallett 2716215976Sjmallett/** 2717215976Sjmallett * cvmx_sriomaint#_ir_sp_rx_data 2718215976Sjmallett * 2719215976Sjmallett * SRIOMAINT_IR_SP_RX_DATA = SRIO Soft Packet FIFO Receive Data 2720215976Sjmallett * 2721215976Sjmallett * Soft Packet FIFO Receive Data 2722215976Sjmallett * 2723215976Sjmallett * Notes: 2724215976Sjmallett * This register is used to read data from the soft packet FIFO. The Soft Packet FIFO contains the 2725215976Sjmallett * majority of the packet data received from the SRIO link. The packet does not include the Control 2726215976Sjmallett * Symbols or the initial byte containing AckId, 2 Reserved Bits and the CRF. In the case of packets 2727215976Sjmallett * with less than 80 bytes (including AckId byte) both the trailing CRC and Pad (if present) are 2728215976Sjmallett * included in the FIFO and Octet Count. In the case of a packet with exactly 80 bytes (including 2729215976Sjmallett * the AckId byte) the CRC is removed and the Pad is maintained so the Octet Count will read 81 bytes 2730215976Sjmallett * instead of the expected 83. In cases over 80 bytes the CRC at 80 bytes is removed but the 2731215976Sjmallett * trailing CRC and Pad (if necessary) are present. 2732215976Sjmallett * 2733215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_SP_RX_DATA hclk hrst_n 2734215976Sjmallett */ 2735215976Sjmallettunion cvmx_sriomaintx_ir_sp_rx_data 2736215976Sjmallett{ 2737215976Sjmallett uint32_t u32; 2738215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_data_s 2739215976Sjmallett { 2740215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2741215976Sjmallett uint32_t pkt_data : 32; /**< This register is used to read packet data from the 2742215976Sjmallett RX FIFO. */ 2743215976Sjmallett#else 2744215976Sjmallett uint32_t pkt_data : 32; 2745215976Sjmallett#endif 2746215976Sjmallett } s; 2747215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xx; 2748215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xxp1; 2749215976Sjmallett}; 2750215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_rx_data cvmx_sriomaintx_ir_sp_rx_data_t; 2751215976Sjmallett 2752215976Sjmallett/** 2753215976Sjmallett * cvmx_sriomaint#_ir_sp_rx_stat 2754215976Sjmallett * 2755215976Sjmallett * SRIOMAINT_IR_SP_RX_STAT = SRIO Soft Packet FIFO Receive Status 2756215976Sjmallett * 2757215976Sjmallett * Soft Packet FIFO Receive Status 2758215976Sjmallett * 2759215976Sjmallett * Notes: 2760215976Sjmallett * This register is used to monitor the reception of packets using the soft packet FIFO. 2761215976Sjmallett * The HW sets SRIO_INT_REG[SOFT_RX] every time a packet arrives in the soft packet FIFO. To read 2762215976Sjmallett * out (one or more) packets, the following procedure may be best: 2763215976Sjmallett * (1) clear SRIO_INT_REG[SOFT_RX], 2764215976Sjmallett * (2) read this CSR to determine how many packets there are, 2765215976Sjmallett * (3) read the packets out (via SRIOMAINT*_IR_SP_RX_DATA). 2766215976Sjmallett * This procedure could lead to situations where SOFT_RX will be set even though there are currently 2767215976Sjmallett * no packets - the SW interrupt handler would need to properly handle this case 2768215976Sjmallett * 2769215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_SP_RX_STAT hclk hrst_n 2770215976Sjmallett */ 2771215976Sjmallettunion cvmx_sriomaintx_ir_sp_rx_stat 2772215976Sjmallett{ 2773215976Sjmallett uint32_t u32; 2774215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_stat_s 2775215976Sjmallett { 2776215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2777215976Sjmallett uint32_t octets : 16; /**< This field shows how many octets are remaining 2778215976Sjmallett in the current packet in the RX FIFO. */ 2779215976Sjmallett uint32_t buffers : 4; /**< This field indicates how many complete packets are 2780215976Sjmallett stored in the Rx FIFO. */ 2781215976Sjmallett uint32_t drop_cnt : 7; /**< Number of Packets Received when the RX FIFO was 2782215976Sjmallett full and then discarded. 2783215976Sjmallett This field always reads zero in Pass 1 */ 2784215976Sjmallett uint32_t full : 1; /**< This bit is set when the value of Buffers Filled 2785215976Sjmallett equals the number of available reception buffers. 2786215976Sjmallett This bit always reads zero in Pass 1 */ 2787215976Sjmallett uint32_t fifo_st : 4; /**< These bits display the state of the state machine 2788215976Sjmallett that controls loading of packet data into the RX 2789215976Sjmallett FIFO. The enumeration of states are as follows: 2790215976Sjmallett 0000 - Idle 2791215976Sjmallett 0001 - Armed 2792215976Sjmallett 0010 - Active 2793215976Sjmallett All other states are reserved. */ 2794215976Sjmallett#else 2795215976Sjmallett uint32_t fifo_st : 4; 2796215976Sjmallett uint32_t full : 1; 2797215976Sjmallett uint32_t drop_cnt : 7; 2798215976Sjmallett uint32_t buffers : 4; 2799215976Sjmallett uint32_t octets : 16; 2800215976Sjmallett#endif 2801215976Sjmallett } s; 2802215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_stat_s cn63xx; 2803215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_stat_cn63xxp1 2804215976Sjmallett { 2805215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2806215976Sjmallett uint32_t octets : 16; /**< This field shows how many octets are remaining 2807215976Sjmallett in the current packet in the RX FIFO. */ 2808215976Sjmallett uint32_t buffers : 4; /**< This field indicates how many complete packets are 2809215976Sjmallett stored in the Rx FIFO. */ 2810215976Sjmallett uint32_t reserved_5_11 : 7; 2811215976Sjmallett uint32_t full : 1; /**< This bit is set when the value of Buffers Filled 2812215976Sjmallett equals the number of available reception buffers. 2813215976Sjmallett This bit always reads zero in Pass 1 */ 2814215976Sjmallett uint32_t fifo_st : 4; /**< These bits display the state of the state machine 2815215976Sjmallett that controls loading of packet data into the RX 2816215976Sjmallett FIFO. The enumeration of states are as follows: 2817215976Sjmallett 0000 - Idle 2818215976Sjmallett 0001 - Armed 2819215976Sjmallett 0010 - Active 2820215976Sjmallett All other states are reserved. */ 2821215976Sjmallett#else 2822215976Sjmallett uint32_t fifo_st : 4; 2823215976Sjmallett uint32_t full : 1; 2824215976Sjmallett uint32_t reserved_5_11 : 7; 2825215976Sjmallett uint32_t buffers : 4; 2826215976Sjmallett uint32_t octets : 16; 2827215976Sjmallett#endif 2828215976Sjmallett } cn63xxp1; 2829215976Sjmallett}; 2830215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_rx_stat cvmx_sriomaintx_ir_sp_rx_stat_t; 2831215976Sjmallett 2832215976Sjmallett/** 2833215976Sjmallett * cvmx_sriomaint#_ir_sp_tx_ctrl 2834215976Sjmallett * 2835215976Sjmallett * SRIOMAINT_IR_SP_TX_CTRL = SRIO Soft Packet FIFO Transmit Control 2836215976Sjmallett * 2837215976Sjmallett * Soft Packet FIFO Transmit Control 2838215976Sjmallett * 2839215976Sjmallett * Notes: 2840215976Sjmallett * This register is used to configure and control the transmission of packets using the soft packet 2841215976Sjmallett * FIFO. 2842215976Sjmallett * 2843215976Sjmallett * Clk_Rst: SRIOMAINT_IR_SP_TX_CTRL hclk hrst_n 2844215976Sjmallett */ 2845215976Sjmallettunion cvmx_sriomaintx_ir_sp_tx_ctrl 2846215976Sjmallett{ 2847215976Sjmallett uint32_t u32; 2848215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_ctrl_s 2849215976Sjmallett { 2850215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2851215976Sjmallett uint32_t octets : 16; /**< Writing a non-zero value (N) to this field arms 2852215976Sjmallett the packet FIFO for packet transmission. The FIFO 2853215976Sjmallett control logic will transmit the next N bytes 2854215976Sjmallett written 4-bytes at a time to the 2855215976Sjmallett SRIOMAINT(0..1)_IR_SP_TX_DATA Register and create a 2856215976Sjmallett single RapidIO packet. */ 2857215976Sjmallett uint32_t reserved_0_15 : 16; 2858215976Sjmallett#else 2859215976Sjmallett uint32_t reserved_0_15 : 16; 2860215976Sjmallett uint32_t octets : 16; 2861215976Sjmallett#endif 2862215976Sjmallett } s; 2863215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xx; 2864215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xxp1; 2865215976Sjmallett}; 2866215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_tx_ctrl cvmx_sriomaintx_ir_sp_tx_ctrl_t; 2867215976Sjmallett 2868215976Sjmallett/** 2869215976Sjmallett * cvmx_sriomaint#_ir_sp_tx_data 2870215976Sjmallett * 2871215976Sjmallett * SRIOMAINT_IR_SP_TX_DATA = SRIO Soft Packet FIFO Transmit Data 2872215976Sjmallett * 2873215976Sjmallett * Soft Packet FIFO Transmit Data 2874215976Sjmallett * 2875215976Sjmallett * Notes: 2876215976Sjmallett * This register is used to write data to the soft packet FIFO. The format of the packet follows the 2877215976Sjmallett * Internal Packet Format (add link here). Care must be taken on creating TIDs for the packets which 2878215976Sjmallett * generate a response. Bits [7:6] of the 8 bit TID must be set for all Soft Packet FIFO generated 2879215976Sjmallett * packets. TID values of 0x00 - 0xBF are reserved for hardware generated Tags. The remainer of the 2880215976Sjmallett * TID[5:0] must be unique for each packet in flight and cannot be reused until a response is received 2881215976Sjmallett * in the SRIOMAINT(0..1)_IR_SP_RX_DATA register. 2882215976Sjmallett * 2883215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_SP_TX_DATA hclk hrst_n 2884215976Sjmallett */ 2885215976Sjmallettunion cvmx_sriomaintx_ir_sp_tx_data 2886215976Sjmallett{ 2887215976Sjmallett uint32_t u32; 2888215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_data_s 2889215976Sjmallett { 2890215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2891215976Sjmallett uint32_t pkt_data : 32; /**< This register is used to write packet data to the 2892215976Sjmallett Tx FIFO. Reads of this register will return zero. */ 2893215976Sjmallett#else 2894215976Sjmallett uint32_t pkt_data : 32; 2895215976Sjmallett#endif 2896215976Sjmallett } s; 2897215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xx; 2898215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xxp1; 2899215976Sjmallett}; 2900215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_tx_data cvmx_sriomaintx_ir_sp_tx_data_t; 2901215976Sjmallett 2902215976Sjmallett/** 2903215976Sjmallett * cvmx_sriomaint#_ir_sp_tx_stat 2904215976Sjmallett * 2905215976Sjmallett * SRIOMAINT_IR_SP_TX_STAT = SRIO Soft Packet FIFO Transmit Status 2906215976Sjmallett * 2907215976Sjmallett * Soft Packet FIFO Transmit Status 2908215976Sjmallett * 2909215976Sjmallett * Notes: 2910215976Sjmallett * This register is used to monitor the transmission of packets using the soft packet FIFO. 2911215976Sjmallett * 2912215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_IR_SP_TX_STAT hclk hrst_n 2913215976Sjmallett */ 2914215976Sjmallettunion cvmx_sriomaintx_ir_sp_tx_stat 2915215976Sjmallett{ 2916215976Sjmallett uint32_t u32; 2917215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_stat_s 2918215976Sjmallett { 2919215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2920215976Sjmallett uint32_t octets : 16; /**< This field shows how many octets are still to be 2921215976Sjmallett loaded in the current packet. */ 2922215976Sjmallett uint32_t buffers : 4; /**< This field indicates how many complete packets are 2923215976Sjmallett stored in the Tx FIFO. The field always reads 2924215976Sjmallett zero in the current hardware. */ 2925215976Sjmallett uint32_t reserved_5_11 : 7; 2926215976Sjmallett uint32_t full : 1; /**< This bit is set when the value of Buffers Filled 2927215976Sjmallett equals the number of available transmission 2928215976Sjmallett buffers. */ 2929215976Sjmallett uint32_t fifo_st : 4; /**< These bits display the state of the state machine 2930215976Sjmallett that controls loading of packet data into the TX 2931215976Sjmallett FIFO. The enumeration of states are as follows: 2932215976Sjmallett 0000 - Idle 2933215976Sjmallett 0001 - Armed 2934215976Sjmallett 0010 - Active 2935215976Sjmallett All other states are reserved. */ 2936215976Sjmallett#else 2937215976Sjmallett uint32_t fifo_st : 4; 2938215976Sjmallett uint32_t full : 1; 2939215976Sjmallett uint32_t reserved_5_11 : 7; 2940215976Sjmallett uint32_t buffers : 4; 2941215976Sjmallett uint32_t octets : 16; 2942215976Sjmallett#endif 2943215976Sjmallett } s; 2944215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xx; 2945215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xxp1; 2946215976Sjmallett}; 2947215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_tx_stat cvmx_sriomaintx_ir_sp_tx_stat_t; 2948215976Sjmallett 2949215976Sjmallett/** 2950215976Sjmallett * cvmx_sriomaint#_lane_#_status_0 2951215976Sjmallett * 2952215976Sjmallett * SRIOMAINT_LANE_X_STATUS_0 = SRIO Lane X Status 0 2953215976Sjmallett * 2954215976Sjmallett * SRIO Lane Status 0 2955215976Sjmallett * 2956215976Sjmallett * Notes: 2957215976Sjmallett * This register contains status information about the local lane transceiver. 2958215976Sjmallett * 2959215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_LANE_[0:3]_STATUS_0 hclk hrst_n 2960215976Sjmallett */ 2961215976Sjmallettunion cvmx_sriomaintx_lane_x_status_0 2962215976Sjmallett{ 2963215976Sjmallett uint32_t u32; 2964215976Sjmallett struct cvmx_sriomaintx_lane_x_status_0_s 2965215976Sjmallett { 2966215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 2967215976Sjmallett uint32_t port : 8; /**< The number of the port within the device to which 2968215976Sjmallett the lane is assigned. */ 2969215976Sjmallett uint32_t lane : 4; /**< Lane Number within the port. */ 2970215976Sjmallett uint32_t tx_type : 1; /**< Transmitter Type 2971215976Sjmallett 0 = Short Run 2972215976Sjmallett 1 = Long Run */ 2973215976Sjmallett uint32_t tx_mode : 1; /**< Transmitter Operating Mode 2974215976Sjmallett 0 = Short Run 2975215976Sjmallett 1 = Long Run */ 2976215976Sjmallett uint32_t rx_type : 2; /**< Receiver Type 2977215976Sjmallett 0 = Short Run 2978215976Sjmallett 1 = Medium Run 2979215976Sjmallett 2 = Long Run 2980215976Sjmallett 3 = Reserved */ 2981215976Sjmallett uint32_t rx_inv : 1; /**< Receiver Input Inverted 2982215976Sjmallett 0 = No Inversion 2983215976Sjmallett 1 = Input Inverted */ 2984215976Sjmallett uint32_t rx_adapt : 1; /**< Receiver Trained 2985215976Sjmallett 0 = One or more adaptive equalizers are 2986215976Sjmallett controlled by the lane receiver and at least 2987215976Sjmallett one is not trained. 2988215976Sjmallett 1 = The lane receiver controls no adaptive 2989215976Sjmallett equalizers or all the equalizers are trained. */ 2990215976Sjmallett uint32_t rx_sync : 1; /**< Receiver Lane Sync'd */ 2991215976Sjmallett uint32_t rx_train : 1; /**< Receiver Lane Trained */ 2992215976Sjmallett uint32_t dec_err : 4; /**< 8Bit/10Bit Decoding Errors 2993215976Sjmallett 0 = No Errors since last read 2994215976Sjmallett 1-14 = Number of Errors since last read 2995215976Sjmallett 15 = Fifteen or more Errors since last read */ 2996215976Sjmallett uint32_t xsync : 1; /**< Receiver Lane Sync Change 2997215976Sjmallett 0 = Lane Sync has not changed since last read 2998215976Sjmallett 1 = Lane Sync has changed since last read */ 2999215976Sjmallett uint32_t xtrain : 1; /**< Receiver Training Change 3000215976Sjmallett 0 = Training has not changed since last read 3001215976Sjmallett 1 = Training has changed since last read */ 3002215976Sjmallett uint32_t reserved_4_5 : 2; 3003215976Sjmallett uint32_t status1 : 1; /**< Status 1 CSR Implemented */ 3004215976Sjmallett uint32_t statusn : 3; /**< Status 2-7 Not Implemented */ 3005215976Sjmallett#else 3006215976Sjmallett uint32_t statusn : 3; 3007215976Sjmallett uint32_t status1 : 1; 3008215976Sjmallett uint32_t reserved_4_5 : 2; 3009215976Sjmallett uint32_t xtrain : 1; 3010215976Sjmallett uint32_t xsync : 1; 3011215976Sjmallett uint32_t dec_err : 4; 3012215976Sjmallett uint32_t rx_train : 1; 3013215976Sjmallett uint32_t rx_sync : 1; 3014215976Sjmallett uint32_t rx_adapt : 1; 3015215976Sjmallett uint32_t rx_inv : 1; 3016215976Sjmallett uint32_t rx_type : 2; 3017215976Sjmallett uint32_t tx_mode : 1; 3018215976Sjmallett uint32_t tx_type : 1; 3019215976Sjmallett uint32_t lane : 4; 3020215976Sjmallett uint32_t port : 8; 3021215976Sjmallett#endif 3022215976Sjmallett } s; 3023215976Sjmallett struct cvmx_sriomaintx_lane_x_status_0_s cn63xx; 3024215976Sjmallett struct cvmx_sriomaintx_lane_x_status_0_s cn63xxp1; 3025215976Sjmallett}; 3026215976Sjmalletttypedef union cvmx_sriomaintx_lane_x_status_0 cvmx_sriomaintx_lane_x_status_0_t; 3027215976Sjmallett 3028215976Sjmallett/** 3029215976Sjmallett * cvmx_sriomaint#_lcs_ba0 3030215976Sjmallett * 3031215976Sjmallett * SRIOMAINT_LCS_BA0 = SRIO Local Configuration Space MSB Base Address 3032215976Sjmallett * 3033215976Sjmallett * MSBs of SRIO Address Space mapped to Maintenance BAR. 3034215976Sjmallett * 3035215976Sjmallett * Notes: 3036215976Sjmallett * The double word aligned SRIO address window mapped to the SRIO Maintenance BAR. This window has 3037215976Sjmallett * the highest priority and eclipses matches to the BAR0, BAR1 and BAR2 windows. Note: Address bits 3038215976Sjmallett * not supplied in the transfer are considered zero. For example, SRIO Address 65:35 must be set to 3039215976Sjmallett * zero to match in a 34-bit access. SRIO Address 65:50 must be set to zero to match in a 50-bit 3040215976Sjmallett * access. This coding allows the Maintenance Bar window to appear in specific address spaces. The 3041215976Sjmallett * remaining bits are located in SRIOMAINT(0..1)_LCS_BA1. This SRIO maintenance BAR is effectively 3042215976Sjmallett * disabled when LCSBA[30] is set with 34 or 50-bit addressing. 3043215976Sjmallett * 3044215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_LCS_BA0 hclk hrst_n 3045215976Sjmallett */ 3046215976Sjmallettunion cvmx_sriomaintx_lcs_ba0 3047215976Sjmallett{ 3048215976Sjmallett uint32_t u32; 3049215976Sjmallett struct cvmx_sriomaintx_lcs_ba0_s 3050215976Sjmallett { 3051215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3052215976Sjmallett uint32_t reserved_31_31 : 1; 3053215976Sjmallett uint32_t lcsba : 31; /**< SRIO Address 65:35 */ 3054215976Sjmallett#else 3055215976Sjmallett uint32_t lcsba : 31; 3056215976Sjmallett uint32_t reserved_31_31 : 1; 3057215976Sjmallett#endif 3058215976Sjmallett } s; 3059215976Sjmallett struct cvmx_sriomaintx_lcs_ba0_s cn63xx; 3060215976Sjmallett struct cvmx_sriomaintx_lcs_ba0_s cn63xxp1; 3061215976Sjmallett}; 3062215976Sjmalletttypedef union cvmx_sriomaintx_lcs_ba0 cvmx_sriomaintx_lcs_ba0_t; 3063215976Sjmallett 3064215976Sjmallett/** 3065215976Sjmallett * cvmx_sriomaint#_lcs_ba1 3066215976Sjmallett * 3067215976Sjmallett * SRIOMAINT_LCS_BA1 = SRIO Local Configuration Space LSB Base Address 3068215976Sjmallett * 3069215976Sjmallett * LSBs of SRIO Address Space mapped to Maintenance BAR. 3070215976Sjmallett * 3071215976Sjmallett * Notes: 3072215976Sjmallett * The double word aligned SRIO address window mapped to the SRIO Maintenance BAR. This window has 3073215976Sjmallett * the highest priority and eclipses matches to the BAR0, BAR1 and BAR2 windows. Address bits not 3074215976Sjmallett * supplied in the transfer are considered zero. For example, SRIO Address 65:35 must be set to zero 3075215976Sjmallett * to match in a 34-bit access and SRIO Address 65:50 must be set to zero to match in a 50-bit access. 3076215976Sjmallett * This coding allows the Maintenance Bar window to appear in specific address spaces. Accesses 3077215976Sjmallett * through this BAR are limited to single word (32-bit) aligned transfers of one to four bytes. 3078215976Sjmallett * Accesses which violate this rule will return an error response if possible and be otherwise 3079215976Sjmallett * ignored. The remaining bits are located in SRIOMAINT(0..1)_LCS_BA0. 3080215976Sjmallett * 3081215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_LCS_BA1 hclk hrst_n 3082215976Sjmallett */ 3083215976Sjmallettunion cvmx_sriomaintx_lcs_ba1 3084215976Sjmallett{ 3085215976Sjmallett uint32_t u32; 3086215976Sjmallett struct cvmx_sriomaintx_lcs_ba1_s 3087215976Sjmallett { 3088215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3089215976Sjmallett uint32_t lcsba : 11; /**< SRIO Address 34:24 */ 3090215976Sjmallett uint32_t reserved_0_20 : 21; 3091215976Sjmallett#else 3092215976Sjmallett uint32_t reserved_0_20 : 21; 3093215976Sjmallett uint32_t lcsba : 11; 3094215976Sjmallett#endif 3095215976Sjmallett } s; 3096215976Sjmallett struct cvmx_sriomaintx_lcs_ba1_s cn63xx; 3097215976Sjmallett struct cvmx_sriomaintx_lcs_ba1_s cn63xxp1; 3098215976Sjmallett}; 3099215976Sjmalletttypedef union cvmx_sriomaintx_lcs_ba1 cvmx_sriomaintx_lcs_ba1_t; 3100215976Sjmallett 3101215976Sjmallett/** 3102215976Sjmallett * cvmx_sriomaint#_m2s_bar0_start0 3103215976Sjmallett * 3104215976Sjmallett * SRIOMAINT_M2S_BAR0_START0 = SRIO Device Access BAR0 MSB Start 3105215976Sjmallett * 3106215976Sjmallett * The starting SRIO address to forwarded to the NPEI Configuration Space. 3107215976Sjmallett * 3108215976Sjmallett * Notes: 3109215976Sjmallett * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR0 Space. See 3110215976Sjmallett * SRIOMAINT(0..1)_M2S_BAR0_START1 for more details. This register is only writeable over SRIO if the 3111215976Sjmallett * SRIO(0..1)_ACC_CTRL.DENY_BAR0 bit is zero. 3112215976Sjmallett * 3113215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR0_START0 hclk hrst_n 3114215976Sjmallett */ 3115215976Sjmallettunion cvmx_sriomaintx_m2s_bar0_start0 3116215976Sjmallett{ 3117215976Sjmallett uint32_t u32; 3118215976Sjmallett struct cvmx_sriomaintx_m2s_bar0_start0_s 3119215976Sjmallett { 3120215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3121215976Sjmallett uint32_t addr64 : 16; /**< SRIO Address 63:48 */ 3122215976Sjmallett uint32_t addr48 : 16; /**< SRIO Address 47:32 */ 3123215976Sjmallett#else 3124215976Sjmallett uint32_t addr48 : 16; 3125215976Sjmallett uint32_t addr64 : 16; 3126215976Sjmallett#endif 3127215976Sjmallett } s; 3128215976Sjmallett struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xx; 3129215976Sjmallett struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xxp1; 3130215976Sjmallett}; 3131215976Sjmalletttypedef union cvmx_sriomaintx_m2s_bar0_start0 cvmx_sriomaintx_m2s_bar0_start0_t; 3132215976Sjmallett 3133215976Sjmallett/** 3134215976Sjmallett * cvmx_sriomaint#_m2s_bar0_start1 3135215976Sjmallett * 3136215976Sjmallett * SRIOMAINT_M2S_BAR0_START1 = SRIO Device Access BAR0 LSB Start 3137215976Sjmallett * 3138215976Sjmallett * The starting SRIO address to forwarded to the NPEI Configuration Space. 3139215976Sjmallett * 3140215976Sjmallett * Notes: 3141215976Sjmallett * This register specifies the SRIO Address mapped to the BAR0 RSL Space. If the transaction has not 3142215976Sjmallett * already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers, if 3143215976Sjmallett * ENABLE is set and the address bits match then the SRIO Memory transactions will map to Octeon SLI 3144215976Sjmallett * Registers. 34-bit address transactions require a match in SRIO Address 33:14 and require all the 3145215976Sjmallett * other bits in ADDR48, ADDR64 and ADDR66 fields to be zero. 50-bit address transactions a match of 3146215976Sjmallett * SRIO Address 49:14 and require all the other bits of ADDR64 and ADDR66 to be zero. 66-bit address 3147215976Sjmallett * transactions require matches of all valid address field bits. Reads and Writes through Bar0 3148215976Sjmallett * have a size limit of 8 bytes and cannot cross a 64-bit boundry. All accesses with sizes greater 3149215976Sjmallett * than this limit will be ignored and return an error on any SRIO responses. Note: ADDR48 and 3150215976Sjmallett * ADDR64 fields are located in SRIOMAINT(0..1)_M2S_BAR0_START0. This register is only writeable over 3151215976Sjmallett * SRIO if the SRIO(0..1)_ACC_CTRL.DENY_BAR0 bit is zero. 3152215976Sjmallett * 3153215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR0_START1 hclk hrst_n 3154215976Sjmallett */ 3155215976Sjmallettunion cvmx_sriomaintx_m2s_bar0_start1 3156215976Sjmallett{ 3157215976Sjmallett uint32_t u32; 3158215976Sjmallett struct cvmx_sriomaintx_m2s_bar0_start1_s 3159215976Sjmallett { 3160215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3161215976Sjmallett uint32_t addr32 : 18; /**< SRIO Address 31:14 */ 3162215976Sjmallett uint32_t reserved_3_13 : 11; 3163215976Sjmallett uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3164215976Sjmallett uint32_t enable : 1; /**< Enable BAR0 Access */ 3165215976Sjmallett#else 3166215976Sjmallett uint32_t enable : 1; 3167215976Sjmallett uint32_t addr66 : 2; 3168215976Sjmallett uint32_t reserved_3_13 : 11; 3169215976Sjmallett uint32_t addr32 : 18; 3170215976Sjmallett#endif 3171215976Sjmallett } s; 3172215976Sjmallett struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xx; 3173215976Sjmallett struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xxp1; 3174215976Sjmallett}; 3175215976Sjmalletttypedef union cvmx_sriomaintx_m2s_bar0_start1 cvmx_sriomaintx_m2s_bar0_start1_t; 3176215976Sjmallett 3177215976Sjmallett/** 3178215976Sjmallett * cvmx_sriomaint#_m2s_bar1_start0 3179215976Sjmallett * 3180215976Sjmallett * SRIOMAINT_M2S_BAR1_START0 = SRIO Device Access BAR1 MSB Start 3181215976Sjmallett * 3182215976Sjmallett * The starting SRIO address to forwarded to the BAR1 Memory Space. 3183215976Sjmallett * 3184215976Sjmallett * Notes: 3185215976Sjmallett * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR1 Space. See 3186215976Sjmallett * SRIOMAINT(0..1)_M2S_BAR1_START1 for more details. This register is only writeable over SRIO if the 3187215976Sjmallett * SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero. 3188215976Sjmallett * 3189215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR1_START0 hclk hrst_n 3190215976Sjmallett */ 3191215976Sjmallettunion cvmx_sriomaintx_m2s_bar1_start0 3192215976Sjmallett{ 3193215976Sjmallett uint32_t u32; 3194215976Sjmallett struct cvmx_sriomaintx_m2s_bar1_start0_s 3195215976Sjmallett { 3196215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3197215976Sjmallett uint32_t addr64 : 16; /**< SRIO Address 63:48 */ 3198215976Sjmallett uint32_t addr48 : 16; /**< SRIO Address 47:32 */ 3199215976Sjmallett#else 3200215976Sjmallett uint32_t addr48 : 16; 3201215976Sjmallett uint32_t addr64 : 16; 3202215976Sjmallett#endif 3203215976Sjmallett } s; 3204215976Sjmallett struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xx; 3205215976Sjmallett struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xxp1; 3206215976Sjmallett}; 3207215976Sjmalletttypedef union cvmx_sriomaintx_m2s_bar1_start0 cvmx_sriomaintx_m2s_bar1_start0_t; 3208215976Sjmallett 3209215976Sjmallett/** 3210215976Sjmallett * cvmx_sriomaint#_m2s_bar1_start1 3211215976Sjmallett * 3212215976Sjmallett * SRIOMAINT_M2S_BAR1_START1 = SRIO Device to BAR1 Start 3213215976Sjmallett * 3214215976Sjmallett * The starting SRIO address to forwarded to the BAR1 Memory Space. 3215215976Sjmallett * 3216215976Sjmallett * Notes: 3217215976Sjmallett * This register specifies the SRIO Address mapped to the BAR1 Space. If the transaction has not 3218215976Sjmallett * already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers and the 3219215976Sjmallett * address bits do not match enabled BAR0 addresses and if ENABLE is set and the addresses match the 3220215976Sjmallett * BAR1 addresses then SRIO Memory transactions will map to Octeon Memory Space specified by 3221215976Sjmallett * SRIOMAINT(0..1)_BAR1_IDX[31:0] registers. The BARSIZE field determines the size of BAR1, the entry 3222215976Sjmallett * select bits, and the size of each entry. A 34-bit address matches BAR1 when it matches 3223215976Sjmallett * SRIO_Address[33:20+BARSIZE] while all the other bits in ADDR48, ADDR64 and ADDR66 are zero. 3224215976Sjmallett * A 50-bit address matches BAR1 when it matches SRIO_Address[49:20+BARSIZE] while all the 3225215976Sjmallett * other bits of ADDR64 and ADDR66 are zero. A 66-bit address matches BAR1 when all of 3226215976Sjmallett * SRIO_Address[65:20+BARSIZE] match all corresponding address CSR field bits. Note: ADDR48 and 3227215976Sjmallett * ADDR64 fields are located in SRIOMAINT(0..1)_M2S_BAR1_START0. This register is only writeable from SRIO 3228215976Sjmallett * if the SRIO(0..1)_ACC_CTRL.DENY_BAR1 bit is zero. 3229215976Sjmallett * 3230215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR1_START1 hclk hrst_n 3231215976Sjmallett */ 3232215976Sjmallettunion cvmx_sriomaintx_m2s_bar1_start1 3233215976Sjmallett{ 3234215976Sjmallett uint32_t u32; 3235215976Sjmallett struct cvmx_sriomaintx_m2s_bar1_start1_s 3236215976Sjmallett { 3237215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3238215976Sjmallett uint32_t addr32 : 12; /**< SRIO Address 31:20 3239215976Sjmallett With BARSIZE < 12, the upper 12-BARSIZE 3240215976Sjmallett bits of this field are used, and the lower BARSIZE 3241215976Sjmallett bits of this field are unused by the SRIO hardware. */ 3242215976Sjmallett uint32_t reserved_7_19 : 13; 3243215976Sjmallett uint32_t barsize : 4; /**< Bar Size. 3244215976Sjmallett SRIO_Address* 3245215976Sjmallett --------------------- 3246215976Sjmallett / \ 3247215976Sjmallett BARSIZE BAR Entry Entry Entry 3248215976Sjmallett Value BAR compare Select Offset Size 3249215976Sjmallett Size bits bits bits 3250215976Sjmallett 0 1MB 65:20 19:16 15:0 64KB 3251215976Sjmallett 1 2MB 65:21 20:17 16:0 128KB 3252215976Sjmallett 2 4MB 65:22 21:18 17:0 256KB 3253215976Sjmallett 3 8MB 65:23 22:19 18:0 512KB 3254215976Sjmallett 4 16MB 65:24 23:20 19:0 1MB 3255215976Sjmallett 5 32MB 65:25 24:21 20:0 2MB 3256215976Sjmallett 6 64MB 65:26 25:22 21:0 4MB 3257215976Sjmallett 7 128MB 65:27 26:23 22:0 8MB 3258215976Sjmallett 8 256MB ** not in pass 1 3259215976Sjmallett 9 512MB ** not in pass 1 3260215976Sjmallett 10 1GB ** not in pass 1 3261215976Sjmallett 11 2GB ** not in pass 1 3262215976Sjmallett 12 4GB ** not in pass 1 3263215976Sjmallett 13 8GB ** not in pass 1 3264215976Sjmallett 3265215976Sjmallett *The SRIO Transaction Address 3266215976Sjmallett The entry select bits is the X that select an 3267215976Sjmallett SRIOMAINT(0..1)_BAR1_IDXX entry. 3268215976Sjmallett 3269215976Sjmallett In O63 pass 2, BARSIZE is 4 bits (6:3 in this 3270215976Sjmallett CSR), and BARSIZE values 8-13 are implemented, 3271215976Sjmallett providing a total possible BAR1 size range from 3272215976Sjmallett 1MB up to 8GB. */ 3273215976Sjmallett uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3274215976Sjmallett uint32_t enable : 1; /**< Enable BAR1 Access */ 3275215976Sjmallett#else 3276215976Sjmallett uint32_t enable : 1; 3277215976Sjmallett uint32_t addr66 : 2; 3278215976Sjmallett uint32_t barsize : 4; 3279215976Sjmallett uint32_t reserved_7_19 : 13; 3280215976Sjmallett uint32_t addr32 : 12; 3281215976Sjmallett#endif 3282215976Sjmallett } s; 3283215976Sjmallett struct cvmx_sriomaintx_m2s_bar1_start1_s cn63xx; 3284215976Sjmallett struct cvmx_sriomaintx_m2s_bar1_start1_cn63xxp1 3285215976Sjmallett { 3286215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3287215976Sjmallett uint32_t addr32 : 12; /**< SRIO Address 31:20 3288215976Sjmallett With BARSIZE < 12, the upper 12-BARSIZE 3289215976Sjmallett bits of this field are used, and the lower BARSIZE 3290215976Sjmallett bits of this field are unused by the SRIO hardware. */ 3291215976Sjmallett uint32_t reserved_6_19 : 14; 3292215976Sjmallett uint32_t barsize : 3; /**< Bar Size. 3293215976Sjmallett SRIO_Address* 3294215976Sjmallett --------------------- 3295215976Sjmallett / \ 3296215976Sjmallett BARSIZE BAR Entry Entry Entry 3297215976Sjmallett Value BAR compare Select Offset Size 3298215976Sjmallett Size bits bits bits 3299215976Sjmallett 0 1MB 65:20 19:16 15:0 64KB 3300215976Sjmallett 1 2MB 65:21 20:17 16:0 128KB 3301215976Sjmallett 2 4MB 65:22 21:18 17:0 256KB 3302215976Sjmallett 3 8MB 65:23 22:19 18:0 512KB 3303215976Sjmallett 4 16MB 65:24 23:20 19:0 1MB 3304215976Sjmallett 5 32MB 65:25 24:21 20:0 2MB 3305215976Sjmallett 6 64MB 65:26 25:22 21:0 4MB 3306215976Sjmallett 7 128MB 65:27 26:23 22:0 8MB 3307215976Sjmallett 8 256MB ** not in pass 1 3308215976Sjmallett 9 512MB ** not in pass 1 3309215976Sjmallett 10 1GB ** not in pass 1 3310215976Sjmallett 11 2GB ** not in pass 1 3311215976Sjmallett 12 4GB ** not in pass 1 3312215976Sjmallett 13 8GB ** not in pass 1 3313215976Sjmallett 3314215976Sjmallett *The SRIO Transaction Address 3315215976Sjmallett The entry select bits is the X that select an 3316215976Sjmallett SRIOMAINT(0..1)_BAR1_IDXX entry. 3317215976Sjmallett 3318215976Sjmallett In O63 pass 2, BARSIZE is 4 bits (6:3 in this 3319215976Sjmallett CSR), and BARSIZE values 8-13 are implemented, 3320215976Sjmallett providing a total possible BAR1 size range from 3321215976Sjmallett 1MB up to 8GB. */ 3322215976Sjmallett uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3323215976Sjmallett uint32_t enable : 1; /**< Enable BAR1 Access */ 3324215976Sjmallett#else 3325215976Sjmallett uint32_t enable : 1; 3326215976Sjmallett uint32_t addr66 : 2; 3327215976Sjmallett uint32_t barsize : 3; 3328215976Sjmallett uint32_t reserved_6_19 : 14; 3329215976Sjmallett uint32_t addr32 : 12; 3330215976Sjmallett#endif 3331215976Sjmallett } cn63xxp1; 3332215976Sjmallett}; 3333215976Sjmalletttypedef union cvmx_sriomaintx_m2s_bar1_start1 cvmx_sriomaintx_m2s_bar1_start1_t; 3334215976Sjmallett 3335215976Sjmallett/** 3336215976Sjmallett * cvmx_sriomaint#_m2s_bar2_start 3337215976Sjmallett * 3338215976Sjmallett * SRIOMAINT_M2S_BAR2_START = SRIO Device to BAR2 Start 3339215976Sjmallett * 3340215976Sjmallett * The starting SRIO address to forwarded to the BAR2 Memory Space. 3341215976Sjmallett * 3342215976Sjmallett * Notes: 3343215976Sjmallett * This register specifies the SRIO Address mapped to the BAR2 Space. If ENABLE is set and the 3344215976Sjmallett * address bits do not match and other enabled BAR address and match the BAR2 addresses then the SRIO 3345215976Sjmallett * Memory transactions will map to Octeon BAR2 Memory Space. 34-bit address transactions require 3346215976Sjmallett * ADDR66, ADDR64 and ADDR48 fields set to zero and supplies zeros for unused addresses 40:34. 3347215976Sjmallett * 50-bit address transactions a match of SRIO Address 49:41 and require all the other bits of ADDR64 3348215976Sjmallett * and ADDR66 to be zero. 66-bit address transactions require matches of all valid address field 3349215976Sjmallett * bits. This register is only writeable over SRIO if the SRIO(0..1)_ACC_CTRL.DENY_BAR2 bit is zero. 3350215976Sjmallett * 3351215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_M2S_BAR2_START hclk hrst_n 3352215976Sjmallett */ 3353215976Sjmallettunion cvmx_sriomaintx_m2s_bar2_start 3354215976Sjmallett{ 3355215976Sjmallett uint32_t u32; 3356215976Sjmallett struct cvmx_sriomaintx_m2s_bar2_start_s 3357215976Sjmallett { 3358215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3359215976Sjmallett uint32_t addr64 : 16; /**< SRIO Address 63:48 */ 3360215976Sjmallett uint32_t addr48 : 7; /**< SRIO Address 47:41 */ 3361215976Sjmallett uint32_t reserved_6_8 : 3; 3362215976Sjmallett uint32_t esx : 2; /**< Endian Swap Mode used for SRIO 34-bit access. 3363215976Sjmallett For 50/66-bit assesses Endian Swap is determine 3364215976Sjmallett by ESX XOR'd with SRIO Addr 39:38. 3365215976Sjmallett 0 = No Swap 3366215976Sjmallett 1 = 64-bit Swap Bytes [ABCD_EFGH] -> [HGFE_DCBA] 3367215976Sjmallett 2 = 32-bit Swap Words [ABCD_EFGH] -> [DCBA_HGFE] 3368215976Sjmallett 3 = 32-bit Word Exch [ABCD_EFGH] -> [EFGH_ABCD] */ 3369215976Sjmallett uint32_t cax : 1; /**< Cacheable Access Mode. When set transfer is 3370215976Sjmallett cached. This bit is used for SRIO 34-bit access. 3371215976Sjmallett For 50/66-bit accessas NCA is determine by CAX 3372215976Sjmallett XOR'd with SRIO Addr 40. */ 3373215976Sjmallett uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3374215976Sjmallett uint32_t enable : 1; /**< Enable BAR2 Access */ 3375215976Sjmallett#else 3376215976Sjmallett uint32_t enable : 1; 3377215976Sjmallett uint32_t addr66 : 2; 3378215976Sjmallett uint32_t cax : 1; 3379215976Sjmallett uint32_t esx : 2; 3380215976Sjmallett uint32_t reserved_6_8 : 3; 3381215976Sjmallett uint32_t addr48 : 7; 3382215976Sjmallett uint32_t addr64 : 16; 3383215976Sjmallett#endif 3384215976Sjmallett } s; 3385215976Sjmallett struct cvmx_sriomaintx_m2s_bar2_start_s cn63xx; 3386215976Sjmallett struct cvmx_sriomaintx_m2s_bar2_start_s cn63xxp1; 3387215976Sjmallett}; 3388215976Sjmalletttypedef union cvmx_sriomaintx_m2s_bar2_start cvmx_sriomaintx_m2s_bar2_start_t; 3389215976Sjmallett 3390215976Sjmallett/** 3391215976Sjmallett * cvmx_sriomaint#_mac_ctrl 3392215976Sjmallett * 3393215976Sjmallett * SRIOMAINT_MAC_CTRL = SRIO MAC Control (Pass 2) 3394215976Sjmallett * 3395215976Sjmallett * Control for MAC Features 3396215976Sjmallett * 3397215976Sjmallett * Notes: 3398215976Sjmallett * This register enables MAC optimizations that may not be supported by all SRIO devices. The 3399215976Sjmallett * default values should be supported. This register can be changed at any time while the MAC is 3400215976Sjmallett * out of reset. 3401215976Sjmallett * 3402215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_MAC_CTRL hclk hrst_n 3403215976Sjmallett */ 3404215976Sjmallettunion cvmx_sriomaintx_mac_ctrl 3405215976Sjmallett{ 3406215976Sjmallett uint32_t u32; 3407215976Sjmallett struct cvmx_sriomaintx_mac_ctrl_s 3408215976Sjmallett { 3409215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3410215976Sjmallett uint32_t reserved_19_31 : 13; 3411215976Sjmallett uint32_t rx_spf : 1; /**< Route all received packets to RX Soft Packet FIFO. 3412215976Sjmallett No logical layer ERB Errors will be reported. 3413215976Sjmallett Used for Diagnostics Only. */ 3414215976Sjmallett uint32_t eop_mrg : 1; /**< Transmitted Packets can eliminate EOP Symbol on 3415215976Sjmallett back to back packets. */ 3416215976Sjmallett uint32_t type_mrg : 1; /**< Allow STYPE Merging on Transmit. */ 3417215976Sjmallett uint32_t lnk_rtry : 16; /**< Number of times MAC will reissue Link Request 3418215976Sjmallett after timeout. If retry count is exceeded Fatal 3419215976Sjmallett Port Error will occur (see SRIO(0..1)_INT_REG.F_ERROR) */ 3420215976Sjmallett#else 3421215976Sjmallett uint32_t lnk_rtry : 16; 3422215976Sjmallett uint32_t type_mrg : 1; 3423215976Sjmallett uint32_t eop_mrg : 1; 3424215976Sjmallett uint32_t rx_spf : 1; 3425215976Sjmallett uint32_t reserved_19_31 : 13; 3426215976Sjmallett#endif 3427215976Sjmallett } s; 3428215976Sjmallett struct cvmx_sriomaintx_mac_ctrl_s cn63xx; 3429215976Sjmallett}; 3430215976Sjmalletttypedef union cvmx_sriomaintx_mac_ctrl cvmx_sriomaintx_mac_ctrl_t; 3431215976Sjmallett 3432215976Sjmallett/** 3433215976Sjmallett * cvmx_sriomaint#_pe_feat 3434215976Sjmallett * 3435215976Sjmallett * SRIOMAINT_PE_FEAT = SRIO Processing Element Features 3436215976Sjmallett * 3437215976Sjmallett * The Supported Processing Element Features. 3438215976Sjmallett * 3439215976Sjmallett * Notes: 3440215976Sjmallett * The Processing Element Feature register describes the major functionality provided by the SRIO 3441215976Sjmallett * device. 3442215976Sjmallett * 3443215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PE_FEAT hclk hrst_n 3444215976Sjmallett */ 3445215976Sjmallettunion cvmx_sriomaintx_pe_feat 3446215976Sjmallett{ 3447215976Sjmallett uint32_t u32; 3448215976Sjmallett struct cvmx_sriomaintx_pe_feat_s 3449215976Sjmallett { 3450215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3451215976Sjmallett uint32_t bridge : 1; /**< Bridge Functions not supported. */ 3452215976Sjmallett uint32_t memory : 1; /**< PE contains addressable memory. */ 3453215976Sjmallett uint32_t proc : 1; /**< PE contains a local processor. */ 3454215976Sjmallett uint32_t switchf : 1; /**< Switch Functions not supported. */ 3455215976Sjmallett uint32_t mult_prt : 1; /**< Multiport Functions not supported. */ 3456215976Sjmallett uint32_t reserved_7_26 : 20; 3457215976Sjmallett uint32_t suppress : 1; /**< Error Recovery Suppression not supported. */ 3458215976Sjmallett uint32_t crf : 1; /**< Critical Request Flow not supported. */ 3459215976Sjmallett uint32_t lg_tran : 1; /**< Large Transport (16-bit Device IDs) supported. */ 3460215976Sjmallett uint32_t ex_feat : 1; /**< Extended Feature Pointer is valid. */ 3461215976Sjmallett uint32_t ex_addr : 3; /**< PE supports 66, 50 and 34-bit addresses. 3462215976Sjmallett [2:1] are a RO copy of SRIO*_IP_FEATURE[A66,A50]. */ 3463215976Sjmallett#else 3464215976Sjmallett uint32_t ex_addr : 3; 3465215976Sjmallett uint32_t ex_feat : 1; 3466215976Sjmallett uint32_t lg_tran : 1; 3467215976Sjmallett uint32_t crf : 1; 3468215976Sjmallett uint32_t suppress : 1; 3469215976Sjmallett uint32_t reserved_7_26 : 20; 3470215976Sjmallett uint32_t mult_prt : 1; 3471215976Sjmallett uint32_t switchf : 1; 3472215976Sjmallett uint32_t proc : 1; 3473215976Sjmallett uint32_t memory : 1; 3474215976Sjmallett uint32_t bridge : 1; 3475215976Sjmallett#endif 3476215976Sjmallett } s; 3477215976Sjmallett struct cvmx_sriomaintx_pe_feat_s cn63xx; 3478215976Sjmallett struct cvmx_sriomaintx_pe_feat_s cn63xxp1; 3479215976Sjmallett}; 3480215976Sjmalletttypedef union cvmx_sriomaintx_pe_feat cvmx_sriomaintx_pe_feat_t; 3481215976Sjmallett 3482215976Sjmallett/** 3483215976Sjmallett * cvmx_sriomaint#_pe_llc 3484215976Sjmallett * 3485215976Sjmallett * SRIOMAINT_PE_LLC = SRIO Processing Element Logical Layer Control 3486215976Sjmallett * 3487215976Sjmallett * Addresses supported by the SRIO Device. 3488215976Sjmallett * 3489215976Sjmallett * Notes: 3490215976Sjmallett * The Processing Element Logical Layer is used for general configuration for the logical interface. 3491215976Sjmallett * 3492215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PE_LLC hclk hrst_n 3493215976Sjmallett */ 3494215976Sjmallettunion cvmx_sriomaintx_pe_llc 3495215976Sjmallett{ 3496215976Sjmallett uint32_t u32; 3497215976Sjmallett struct cvmx_sriomaintx_pe_llc_s 3498215976Sjmallett { 3499215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3500215976Sjmallett uint32_t reserved_3_31 : 29; 3501215976Sjmallett uint32_t ex_addr : 3; /**< Controls the number of address bits generated by 3502215976Sjmallett PE as a source and processed by the PE as a 3503215976Sjmallett target of an operation. 3504215976Sjmallett 001 = 34-bit Addresses 3505215976Sjmallett 010 = 50-bit Addresses 3506215976Sjmallett 100 = 66-bit Addresses 3507215976Sjmallett All other encodings are reserved. */ 3508215976Sjmallett#else 3509215976Sjmallett uint32_t ex_addr : 3; 3510215976Sjmallett uint32_t reserved_3_31 : 29; 3511215976Sjmallett#endif 3512215976Sjmallett } s; 3513215976Sjmallett struct cvmx_sriomaintx_pe_llc_s cn63xx; 3514215976Sjmallett struct cvmx_sriomaintx_pe_llc_s cn63xxp1; 3515215976Sjmallett}; 3516215976Sjmalletttypedef union cvmx_sriomaintx_pe_llc cvmx_sriomaintx_pe_llc_t; 3517215976Sjmallett 3518215976Sjmallett/** 3519215976Sjmallett * cvmx_sriomaint#_port_0_ctl 3520215976Sjmallett * 3521215976Sjmallett * SRIOMAINT_PORT_0_CTL = SRIO Port 0 Control 3522215976Sjmallett * 3523215976Sjmallett * Port 0 Control 3524215976Sjmallett * 3525215976Sjmallett * Notes: 3526215976Sjmallett * This register contains assorted control bits. 3527215976Sjmallett * 3528215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_0_CTL hclk hrst_n 3529215976Sjmallett */ 3530215976Sjmallettunion cvmx_sriomaintx_port_0_ctl 3531215976Sjmallett{ 3532215976Sjmallett uint32_t u32; 3533215976Sjmallett struct cvmx_sriomaintx_port_0_ctl_s 3534215976Sjmallett { 3535215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3536215976Sjmallett uint32_t pt_width : 2; /**< Hardware Port Width. 3537215976Sjmallett 00 = One Lane supported. 3538215976Sjmallett 01 = One/Two Lanes supported. 3539215976Sjmallett 10 = One/Four Lanes supported. 3540215976Sjmallett 11 = One/Two/Four Lanes supported. 3541215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[PT_WIDTH]. */ 3542215976Sjmallett uint32_t it_width : 3; /**< Initialized Port Width 3543215976Sjmallett 000 = Single-lane, Lane 0 3544215976Sjmallett 001 = Single-lane, Lane 1 or 2 3545215976Sjmallett 010 = Four-lane 3546215976Sjmallett 011 = Two-lane 3547215976Sjmallett Others = Reserved */ 3548215976Sjmallett uint32_t ov_width : 3; /**< Override Port Width. Writing this register causes 3549215976Sjmallett the port to reinitialize. 3550215976Sjmallett 000 = No Override all lanes possible 3551215976Sjmallett 001 = Reserved 3552215976Sjmallett 010 = Force Single-lane, Lane 0 3553215976Sjmallett 011 = Force Single-lane, Lane 2 3554215976Sjmallett (Lane 1 if only lanes 0,1 are connected) 3555215976Sjmallett 100 = Reserved 3556215976Sjmallett 101 = Force Two-lane, Disable Four-Lane 3557215976Sjmallett 110 = Force Four-lane, Disable Two-Lane 3558215976Sjmallett 111 = All lanes sizes enabled */ 3559215976Sjmallett uint32_t disable : 1; /**< Port Disable. Setting this bit disables both 3560215976Sjmallett drivers and receivers. */ 3561215976Sjmallett uint32_t o_enable : 1; /**< Port Output Enable. When cleared, port will 3562215976Sjmallett generate control symbols and respond to 3563215976Sjmallett maintenance transactions only. When set, all 3564215976Sjmallett transactions are allowed. */ 3565215976Sjmallett uint32_t i_enable : 1; /**< Port Input Enable. When cleared, port will 3566215976Sjmallett generate control symbols and respond to 3567215976Sjmallett maintenance packets only. All other packets will 3568215976Sjmallett not be accepted. */ 3569215976Sjmallett uint32_t dis_err : 1; /**< Disable Error Checking. Diagnostic Only. */ 3570215976Sjmallett uint32_t mcast : 1; /**< Reserved. */ 3571215976Sjmallett uint32_t reserved_18_18 : 1; 3572215976Sjmallett uint32_t enumb : 1; /**< Enumeration Boundry. SW can use this bit to 3573215976Sjmallett determine port enumeration. */ 3574215976Sjmallett uint32_t reserved_16_16 : 1; 3575215976Sjmallett uint32_t ex_width : 2; /**< Extended Port Width not supported. */ 3576215976Sjmallett uint32_t ex_stat : 2; /**< Extended Port Width Status. 00 = not supported */ 3577215976Sjmallett uint32_t suppress : 8; /**< Retransmit Suppression Mask. CRF not Supported. */ 3578215976Sjmallett uint32_t stp_port : 1; /**< Stop on Failed Port. This bit is used with the 3579215976Sjmallett DROP_PKT bit to force certain behavior when the 3580215976Sjmallett Error Rate Failed Threshold has been met or 3581215976Sjmallett exceeded. */ 3582215976Sjmallett uint32_t drop_pkt : 1; /**< Drop on Failed Port. This bit is used with the 3583215976Sjmallett STP_PORT bit to force certain behavior when the 3584215976Sjmallett Error Rate Failed Threshold has been met or 3585215976Sjmallett exceeded. */ 3586215976Sjmallett uint32_t prt_lock : 1; /**< When this bit is cleared, the packets that may be 3587215976Sjmallett received and issued are controlled by the state of 3588215976Sjmallett the O_ENABLE and I_ENABLE bits. When this bit is 3589215976Sjmallett set, this port is stopped and is not enabled to 3590215976Sjmallett issue or receive any packets; the input port can 3591215976Sjmallett still follow the training procedure and can still 3592215976Sjmallett send and respond to link-requests; all received 3593215976Sjmallett packets return packet-not-accepted control symbols 3594215976Sjmallett to force an error condition to be signaled by the 3595215976Sjmallett sending device. */ 3596215976Sjmallett uint32_t pt_type : 1; /**< Port Type. 1 = Serial port. */ 3597215976Sjmallett#else 3598215976Sjmallett uint32_t pt_type : 1; 3599215976Sjmallett uint32_t prt_lock : 1; 3600215976Sjmallett uint32_t drop_pkt : 1; 3601215976Sjmallett uint32_t stp_port : 1; 3602215976Sjmallett uint32_t suppress : 8; 3603215976Sjmallett uint32_t ex_stat : 2; 3604215976Sjmallett uint32_t ex_width : 2; 3605215976Sjmallett uint32_t reserved_16_16 : 1; 3606215976Sjmallett uint32_t enumb : 1; 3607215976Sjmallett uint32_t reserved_18_18 : 1; 3608215976Sjmallett uint32_t mcast : 1; 3609215976Sjmallett uint32_t dis_err : 1; 3610215976Sjmallett uint32_t i_enable : 1; 3611215976Sjmallett uint32_t o_enable : 1; 3612215976Sjmallett uint32_t disable : 1; 3613215976Sjmallett uint32_t ov_width : 3; 3614215976Sjmallett uint32_t it_width : 3; 3615215976Sjmallett uint32_t pt_width : 2; 3616215976Sjmallett#endif 3617215976Sjmallett } s; 3618215976Sjmallett struct cvmx_sriomaintx_port_0_ctl_s cn63xx; 3619215976Sjmallett struct cvmx_sriomaintx_port_0_ctl_s cn63xxp1; 3620215976Sjmallett}; 3621215976Sjmalletttypedef union cvmx_sriomaintx_port_0_ctl cvmx_sriomaintx_port_0_ctl_t; 3622215976Sjmallett 3623215976Sjmallett/** 3624215976Sjmallett * cvmx_sriomaint#_port_0_ctl2 3625215976Sjmallett * 3626215976Sjmallett * SRIOMAINT_PORT_0_CTL2 = SRIO Port 0 Control 2 3627215976Sjmallett * 3628215976Sjmallett * Port 0 Control 2 3629215976Sjmallett * 3630215976Sjmallett * Notes: 3631215976Sjmallett * These registers are accessed when a local processor or an external device wishes to examine the 3632215976Sjmallett * port baudrate information. WARNING: Writes to this register will reinitialize the SRIO link. 3633215976Sjmallett * 3634215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_0_CTL2 hclk hrst_n 3635215976Sjmallett */ 3636215976Sjmallettunion cvmx_sriomaintx_port_0_ctl2 3637215976Sjmallett{ 3638215976Sjmallett uint32_t u32; 3639215976Sjmallett struct cvmx_sriomaintx_port_0_ctl2_s 3640215976Sjmallett { 3641215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3642215976Sjmallett uint32_t sel_baud : 4; /**< Link Baud Rate Selected. 3643215976Sjmallett 0000 - No rate selected 3644215976Sjmallett 0001 - 1.25 GBaud 3645215976Sjmallett 0010 - 2.5 GBaud 3646215976Sjmallett 0011 - 3.125 GBaud 3647215976Sjmallett 0100 - 5.0 GBaud 3648215976Sjmallett 0101 - 6.25 GBaud (reserved) 3649215976Sjmallett 0110 - 0b1111 - Reserved 3650215976Sjmallett Indicates the speed of the interface SERDES lanes 3651215976Sjmallett (should match the value selected by SUP_* /ENB_* 3652215976Sjmallett below). */ 3653215976Sjmallett uint32_t baud_sup : 1; /**< Automatic Baud Rate Discovery not supported. */ 3654215976Sjmallett uint32_t baud_enb : 1; /**< Auto Baud Rate Discovery Enable. */ 3655215976Sjmallett uint32_t sup_125g : 1; /**< 1.25GB Rate Operation supported. 3656215976Sjmallett Set when the interface SERDES lanes are operating 3657215976Sjmallett at 1.25 Gbaud (as selected by QLM*_SPD straps). */ 3658215976Sjmallett uint32_t enb_125g : 1; /**< 1.25GB Rate Operation enable. 3659215976Sjmallett Reset to 1 when the interface SERDES lanes are 3660215976Sjmallett operating at 1.25 Gbaud (as selected by QLM*_SPD 3661215976Sjmallett straps). Reset to 0 otherwise. */ 3662215976Sjmallett uint32_t sup_250g : 1; /**< 2.50GB Rate Operation supported. 3663215976Sjmallett Set when the interface SERDES lanes are operating 3664215976Sjmallett at 2.5 Gbaud (as selected by QLM*_SPD straps). */ 3665215976Sjmallett uint32_t enb_250g : 1; /**< 2.50GB Rate Operation enable. 3666215976Sjmallett Reset to 1 when the interface SERDES lanes are 3667215976Sjmallett operating at 2.5 Gbaud (as selected by QLM*_SPD 3668215976Sjmallett straps). Reset to 0 otherwise. */ 3669215976Sjmallett uint32_t sup_312g : 1; /**< 3.125GB Rate Operation supported. 3670215976Sjmallett Set when the interface SERDES lanes are operating 3671215976Sjmallett at 3.125 Gbaud (as selected by QLM*_SPD straps). */ 3672215976Sjmallett uint32_t enb_312g : 1; /**< 3.125GB Rate Operation enable. 3673215976Sjmallett Reset to 1 when the interface SERDES lanes are 3674215976Sjmallett operating at 3.125 Gbaud (as selected by QLM*_SPD 3675215976Sjmallett straps). Reset to 0 otherwise. */ 3676215976Sjmallett uint32_t sub_500g : 1; /**< 5.0GB Rate Operation supported. 3677215976Sjmallett Set when the interface SERDES lanes are operating 3678215976Sjmallett at 5.0 Gbaud (as selected by QLM*_SPD straps). */ 3679215976Sjmallett uint32_t enb_500g : 1; /**< 5.0GB Rate Operation enable. 3680215976Sjmallett Reset to 1 when the interface SERDES lanes are 3681215976Sjmallett operating at 5.0 Gbaud (as selected by QLM*_SPD 3682215976Sjmallett straps). Reset to 0 otherwise. */ 3683215976Sjmallett uint32_t sup_625g : 1; /**< 6.25GB Rate Operation (not supported). */ 3684215976Sjmallett uint32_t enb_625g : 1; /**< 6.25GB Rate Operation enable. */ 3685215976Sjmallett uint32_t reserved_2_15 : 14; 3686215976Sjmallett uint32_t tx_emph : 1; /**< Indicates whether is port is able to transmit 3687215976Sjmallett commands to control the transmit emphasis in the 3688215976Sjmallett connected port. */ 3689215976Sjmallett uint32_t emph_en : 1; /**< Controls whether a port may adjust the 3690215976Sjmallett transmit emphasis in the connected port. This bit 3691215976Sjmallett should be cleared for normal operation. */ 3692215976Sjmallett#else 3693215976Sjmallett uint32_t emph_en : 1; 3694215976Sjmallett uint32_t tx_emph : 1; 3695215976Sjmallett uint32_t reserved_2_15 : 14; 3696215976Sjmallett uint32_t enb_625g : 1; 3697215976Sjmallett uint32_t sup_625g : 1; 3698215976Sjmallett uint32_t enb_500g : 1; 3699215976Sjmallett uint32_t sub_500g : 1; 3700215976Sjmallett uint32_t enb_312g : 1; 3701215976Sjmallett uint32_t sup_312g : 1; 3702215976Sjmallett uint32_t enb_250g : 1; 3703215976Sjmallett uint32_t sup_250g : 1; 3704215976Sjmallett uint32_t enb_125g : 1; 3705215976Sjmallett uint32_t sup_125g : 1; 3706215976Sjmallett uint32_t baud_enb : 1; 3707215976Sjmallett uint32_t baud_sup : 1; 3708215976Sjmallett uint32_t sel_baud : 4; 3709215976Sjmallett#endif 3710215976Sjmallett } s; 3711215976Sjmallett struct cvmx_sriomaintx_port_0_ctl2_s cn63xx; 3712215976Sjmallett struct cvmx_sriomaintx_port_0_ctl2_s cn63xxp1; 3713215976Sjmallett}; 3714215976Sjmalletttypedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t; 3715215976Sjmallett 3716215976Sjmallett/** 3717215976Sjmallett * cvmx_sriomaint#_port_0_err_stat 3718215976Sjmallett * 3719215976Sjmallett * SRIOMAINT_PORT_0_ERR_STAT = SRIO Port 0 Error and Status 3720215976Sjmallett * 3721215976Sjmallett * Port 0 Error and Status 3722215976Sjmallett * 3723215976Sjmallett * Notes: 3724215976Sjmallett * This register displays port error and status information. Several port error conditions are 3725215976Sjmallett * captured here and must be cleared by writing 1's to the individual bits. 3726215976Sjmallett * 3727215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_0_ERR_STAT hclk hrst_n 3728215976Sjmallett */ 3729215976Sjmallettunion cvmx_sriomaintx_port_0_err_stat 3730215976Sjmallett{ 3731215976Sjmallett uint32_t u32; 3732215976Sjmallett struct cvmx_sriomaintx_port_0_err_stat_s 3733215976Sjmallett { 3734215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3735215976Sjmallett uint32_t reserved_27_31 : 5; 3736215976Sjmallett uint32_t pkt_drop : 1; /**< Output Packet Dropped. */ 3737215976Sjmallett uint32_t o_fail : 1; /**< Output Port has encountered a failure condition, 3738215976Sjmallett meaning the port's failed error threshold has 3739215976Sjmallett reached SRIOMAINT(0..1)_ERB_ERR_RATE_THR.ER_FAIL value. */ 3740215976Sjmallett uint32_t o_dgrad : 1; /**< Output Port has encountered a degraded condition, 3741215976Sjmallett meaning the port's degraded threshold has 3742215976Sjmallett reached SRIOMAINT(0..1)_ERB_ERR_RATE_THR.ER_DGRAD 3743215976Sjmallett value. */ 3744215976Sjmallett uint32_t reserved_21_23 : 3; 3745215976Sjmallett uint32_t o_retry : 1; /**< Output Retry Encountered. This bit is set when 3746215976Sjmallett bit 18 is set. */ 3747215976Sjmallett uint32_t o_rtried : 1; /**< Output Port has received a packet-retry condition 3748215976Sjmallett and cannot make forward progress. This bit is set 3749215976Sjmallett when bit 18 is set and is cleared when a packet- 3750215976Sjmallett accepted or a packet-not-accepted control symbol 3751215976Sjmallett is received. */ 3752215976Sjmallett uint32_t o_sm_ret : 1; /**< Output Port State Machine has received a 3753215976Sjmallett packet-retry control symbol and is retrying the 3754215976Sjmallett packet. */ 3755215976Sjmallett uint32_t o_error : 1; /**< Output Error Encountered and possibly recovered 3756215976Sjmallett from. This sticky bit is set with bit 16. */ 3757215976Sjmallett uint32_t o_sm_err : 1; /**< Output Port State Machine has encountered an 3758215976Sjmallett error. */ 3759215976Sjmallett uint32_t reserved_11_15 : 5; 3760215976Sjmallett uint32_t i_sm_ret : 1; /**< Input Port State Machine has received a 3761215976Sjmallett packet-retry control symbol and is retrying the 3762215976Sjmallett packet. */ 3763215976Sjmallett uint32_t i_error : 1; /**< Input Error Encountered and possibly recovered 3764215976Sjmallett from. This sticky bit is set with bit 8. */ 3765215976Sjmallett uint32_t i_sm_err : 1; /**< Input Port State Machine has encountered an 3766215976Sjmallett error. */ 3767215976Sjmallett uint32_t reserved_5_7 : 3; 3768215976Sjmallett uint32_t pt_write : 1; /**< Port has encountered a condition which required it 3769215976Sjmallett initiate a Maintenance Port-Write Operation. */ 3770215976Sjmallett uint32_t reserved_3_3 : 1; 3771215976Sjmallett uint32_t pt_error : 1; /**< Input or Output Port has encountered an 3772215976Sjmallett unrecoverable error condition. */ 3773215976Sjmallett uint32_t pt_ok : 1; /**< Input or Output Port are intitialized and the port 3774215976Sjmallett is exchanging error free control symbols with 3775215976Sjmallett attached device. */ 3776215976Sjmallett uint32_t pt_uinit : 1; /**< Port is uninitialized. This bit and bit 1 are 3777215976Sjmallett mutually exclusive. */ 3778215976Sjmallett#else 3779215976Sjmallett uint32_t pt_uinit : 1; 3780215976Sjmallett uint32_t pt_ok : 1; 3781215976Sjmallett uint32_t pt_error : 1; 3782215976Sjmallett uint32_t reserved_3_3 : 1; 3783215976Sjmallett uint32_t pt_write : 1; 3784215976Sjmallett uint32_t reserved_5_7 : 3; 3785215976Sjmallett uint32_t i_sm_err : 1; 3786215976Sjmallett uint32_t i_error : 1; 3787215976Sjmallett uint32_t i_sm_ret : 1; 3788215976Sjmallett uint32_t reserved_11_15 : 5; 3789215976Sjmallett uint32_t o_sm_err : 1; 3790215976Sjmallett uint32_t o_error : 1; 3791215976Sjmallett uint32_t o_sm_ret : 1; 3792215976Sjmallett uint32_t o_rtried : 1; 3793215976Sjmallett uint32_t o_retry : 1; 3794215976Sjmallett uint32_t reserved_21_23 : 3; 3795215976Sjmallett uint32_t o_dgrad : 1; 3796215976Sjmallett uint32_t o_fail : 1; 3797215976Sjmallett uint32_t pkt_drop : 1; 3798215976Sjmallett uint32_t reserved_27_31 : 5; 3799215976Sjmallett#endif 3800215976Sjmallett } s; 3801215976Sjmallett struct cvmx_sriomaintx_port_0_err_stat_s cn63xx; 3802215976Sjmallett struct cvmx_sriomaintx_port_0_err_stat_s cn63xxp1; 3803215976Sjmallett}; 3804215976Sjmalletttypedef union cvmx_sriomaintx_port_0_err_stat cvmx_sriomaintx_port_0_err_stat_t; 3805215976Sjmallett 3806215976Sjmallett/** 3807215976Sjmallett * cvmx_sriomaint#_port_0_link_req 3808215976Sjmallett * 3809215976Sjmallett * SRIOMAINT_PORT_0_LINK_REQ = SRIO Port 0 Link Request (Pass 2) 3810215976Sjmallett * 3811215976Sjmallett * Port 0 Manual Link Request 3812215976Sjmallett * 3813215976Sjmallett * Notes: 3814215976Sjmallett * Writing this register generates the link request symbol or eight device reset symbols. The 3815215976Sjmallett * progress of the request can be determined by reading SRIOMAINT(0..1)_PORT_0_LINK_RESP. Only a single 3816215976Sjmallett * request should be generated at a time. 3817215976Sjmallett * 3818215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_0_LINK_REQ hclk hrst_n 3819215976Sjmallett */ 3820215976Sjmallettunion cvmx_sriomaintx_port_0_link_req 3821215976Sjmallett{ 3822215976Sjmallett uint32_t u32; 3823215976Sjmallett struct cvmx_sriomaintx_port_0_link_req_s 3824215976Sjmallett { 3825215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3826215976Sjmallett uint32_t reserved_3_31 : 29; 3827215976Sjmallett uint32_t cmd : 3; /**< Link Request Command. 3828215976Sjmallett 011 - Reset Device 3829215976Sjmallett 100 - Link Request 3830215976Sjmallett All other values reserved. */ 3831215976Sjmallett#else 3832215976Sjmallett uint32_t cmd : 3; 3833215976Sjmallett uint32_t reserved_3_31 : 29; 3834215976Sjmallett#endif 3835215976Sjmallett } s; 3836215976Sjmallett struct cvmx_sriomaintx_port_0_link_req_s cn63xx; 3837215976Sjmallett}; 3838215976Sjmalletttypedef union cvmx_sriomaintx_port_0_link_req cvmx_sriomaintx_port_0_link_req_t; 3839215976Sjmallett 3840215976Sjmallett/** 3841215976Sjmallett * cvmx_sriomaint#_port_0_link_resp 3842215976Sjmallett * 3843215976Sjmallett * SRIOMAINT_PORT_0_LINK_RESP = SRIO Port 0 Link Response (Pass 2) 3844215976Sjmallett * 3845215976Sjmallett * Port 0 Manual Link Response 3846215976Sjmallett * 3847215976Sjmallett * Notes: 3848215976Sjmallett * This register only returns responses generated by writes to SRIOMAINT(0..1)_PORT_0_LINK_REQ. 3849215976Sjmallett * 3850215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_0_LINK_RESP hclk hrst_n 3851215976Sjmallett */ 3852215976Sjmallettunion cvmx_sriomaintx_port_0_link_resp 3853215976Sjmallett{ 3854215976Sjmallett uint32_t u32; 3855215976Sjmallett struct cvmx_sriomaintx_port_0_link_resp_s 3856215976Sjmallett { 3857215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3858215976Sjmallett uint32_t valid : 1; /**< Link Response Valid. 3859215976Sjmallett 1 = Link Response Received or Reset Device 3860215976Sjmallett Symbols Transmitted. Value cleared on read. 3861215976Sjmallett 0 = No response received. */ 3862215976Sjmallett uint32_t reserved_11_30 : 20; 3863215976Sjmallett uint32_t ackid : 6; /**< AckID received from link response. 3864215976Sjmallett Reset Device symbol response is always zero. 3865215976Sjmallett Bit 10 is used for IDLE2 and always reads zero. */ 3866215976Sjmallett uint32_t status : 5; /**< Link Response Status. 3867215976Sjmallett Status supplied by link response. 3868215976Sjmallett Reset Device symbol response is always zero. */ 3869215976Sjmallett#else 3870215976Sjmallett uint32_t status : 5; 3871215976Sjmallett uint32_t ackid : 6; 3872215976Sjmallett uint32_t reserved_11_30 : 20; 3873215976Sjmallett uint32_t valid : 1; 3874215976Sjmallett#endif 3875215976Sjmallett } s; 3876215976Sjmallett struct cvmx_sriomaintx_port_0_link_resp_s cn63xx; 3877215976Sjmallett}; 3878215976Sjmalletttypedef union cvmx_sriomaintx_port_0_link_resp cvmx_sriomaintx_port_0_link_resp_t; 3879215976Sjmallett 3880215976Sjmallett/** 3881215976Sjmallett * cvmx_sriomaint#_port_0_local_ackid 3882215976Sjmallett * 3883215976Sjmallett * SRIOMAINT_PORT_0_LOCAL_ACKID = SRIO Port 0 Local AckID (Pass 2) 3884215976Sjmallett * 3885215976Sjmallett * Port 0 Local AckID Control 3886215976Sjmallett * 3887215976Sjmallett * Notes: 3888215976Sjmallett * This register is typically only written when recovering from a failed link. It may be read at any 3889215976Sjmallett * time the MAC is out of reset. Writes to the O_ACKID field will be used for both the O_ACKID and 3890215976Sjmallett * E_ACKID. Care must be taken to ensure that no packets are pending at the time of a write. The 3891215976Sjmallett * number of pending packets can be read in the TX_INUSE field of SRIO(0..1)_MAC_BUFFERS. 3892215976Sjmallett * 3893215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_0_LOCAL_ACKID hclk hrst_n 3894215976Sjmallett */ 3895215976Sjmallettunion cvmx_sriomaintx_port_0_local_ackid 3896215976Sjmallett{ 3897215976Sjmallett uint32_t u32; 3898215976Sjmallett struct cvmx_sriomaintx_port_0_local_ackid_s 3899215976Sjmallett { 3900215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3901215976Sjmallett uint32_t reserved_30_31 : 2; 3902215976Sjmallett uint32_t i_ackid : 6; /**< Next Expected Inbound AckID. 3903215976Sjmallett Bit 29 is used for IDLE2 and should be zero. */ 3904215976Sjmallett uint32_t reserved_14_23 : 10; 3905215976Sjmallett uint32_t e_ackid : 6; /**< Next Expected Unacknowledged AckID. 3906215976Sjmallett Bit 13 is used for IDLE2 and should be zero. */ 3907215976Sjmallett uint32_t reserved_6_7 : 2; 3908215976Sjmallett uint32_t o_ackid : 6; /**< Next Outgoing Packet AckID. 3909215976Sjmallett Bit 5 is used for IDLE2 and should be zero. */ 3910215976Sjmallett#else 3911215976Sjmallett uint32_t o_ackid : 6; 3912215976Sjmallett uint32_t reserved_6_7 : 2; 3913215976Sjmallett uint32_t e_ackid : 6; 3914215976Sjmallett uint32_t reserved_14_23 : 10; 3915215976Sjmallett uint32_t i_ackid : 6; 3916215976Sjmallett uint32_t reserved_30_31 : 2; 3917215976Sjmallett#endif 3918215976Sjmallett } s; 3919215976Sjmallett struct cvmx_sriomaintx_port_0_local_ackid_s cn63xx; 3920215976Sjmallett}; 3921215976Sjmalletttypedef union cvmx_sriomaintx_port_0_local_ackid cvmx_sriomaintx_port_0_local_ackid_t; 3922215976Sjmallett 3923215976Sjmallett/** 3924215976Sjmallett * cvmx_sriomaint#_port_gen_ctl 3925215976Sjmallett * 3926215976Sjmallett * SRIOMAINT_PORT_GEN_CTL = SRIO Port General Control 3927215976Sjmallett * 3928215976Sjmallett * Port General Control 3929215976Sjmallett * 3930215976Sjmallett * Notes: 3931215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_GEN_CTL hclk hrst_n 3932215976Sjmallett * 3933215976Sjmallett */ 3934215976Sjmallettunion cvmx_sriomaintx_port_gen_ctl 3935215976Sjmallett{ 3936215976Sjmallett uint32_t u32; 3937215976Sjmallett struct cvmx_sriomaintx_port_gen_ctl_s 3938215976Sjmallett { 3939215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3940215976Sjmallett uint32_t host : 1; /**< Host Device. 3941215976Sjmallett The HOST reset value is based on corresponding 3942215976Sjmallett MIO_RST_CTL*[PRTMODE], whose reset value is 3943215976Sjmallett selected by the corresponding QLM*_HOST_MODE strap 3944215976Sjmallett on a chip cold reset (and can be later modified by 3945215976Sjmallett software). HOST resets to 1 when 3946215976Sjmallett MIO_RST_CTL*[PRTMODE] selects RC (i.e. host) mode, 3947215976Sjmallett else 0. */ 3948215976Sjmallett uint32_t menable : 1; /**< Master Enable. Must be set for device to issue 3949215976Sjmallett read, write, doorbell, message requests. */ 3950215976Sjmallett uint32_t discover : 1; /**< Discovered. The device has been discovered by the 3951215976Sjmallett host responsible for initialization. */ 3952215976Sjmallett uint32_t reserved_0_28 : 29; 3953215976Sjmallett#else 3954215976Sjmallett uint32_t reserved_0_28 : 29; 3955215976Sjmallett uint32_t discover : 1; 3956215976Sjmallett uint32_t menable : 1; 3957215976Sjmallett uint32_t host : 1; 3958215976Sjmallett#endif 3959215976Sjmallett } s; 3960215976Sjmallett struct cvmx_sriomaintx_port_gen_ctl_s cn63xx; 3961215976Sjmallett struct cvmx_sriomaintx_port_gen_ctl_s cn63xxp1; 3962215976Sjmallett}; 3963215976Sjmalletttypedef union cvmx_sriomaintx_port_gen_ctl cvmx_sriomaintx_port_gen_ctl_t; 3964215976Sjmallett 3965215976Sjmallett/** 3966215976Sjmallett * cvmx_sriomaint#_port_lt_ctl 3967215976Sjmallett * 3968215976Sjmallett * SRIOMAINT_PORT_LT_CTL = SRIO Link Layer Timeout Control 3969215976Sjmallett * 3970215976Sjmallett * Link Layer Timeout Control 3971215976Sjmallett * 3972215976Sjmallett * Notes: 3973215976Sjmallett * This register controls the timeout for link layer transactions. It is used as the timeout between 3974215976Sjmallett * sending a packet (of any type) or link request to receiving the corresponding link acknowledge or 3975215976Sjmallett * link-response. Each count represents 200ns. The minimum timeout period is the TIMEOUT x 200nS 3976215976Sjmallett * and the maximum is twice that number. A value less than 32 may not guarantee that all timeout 3977215976Sjmallett * errors will be reported correctly. When the timeout period expires the packet or link request is 3978215976Sjmallett * dropped and the error is logged in the LNK_TOUT field of the SRIOMAINT(0..1)_ERB_ERR_DET register. A 3979215976Sjmallett * value of 0 in this register will allow the packet or link request to be issued but it will timeout 3980215976Sjmallett * immediately. This value is not recommended for normal operation. 3981215976Sjmallett * 3982215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_LT_CTL hclk hrst_n 3983215976Sjmallett */ 3984215976Sjmallettunion cvmx_sriomaintx_port_lt_ctl 3985215976Sjmallett{ 3986215976Sjmallett uint32_t u32; 3987215976Sjmallett struct cvmx_sriomaintx_port_lt_ctl_s 3988215976Sjmallett { 3989215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 3990215976Sjmallett uint32_t timeout : 24; /**< Timeout Value */ 3991215976Sjmallett uint32_t reserved_0_7 : 8; 3992215976Sjmallett#else 3993215976Sjmallett uint32_t reserved_0_7 : 8; 3994215976Sjmallett uint32_t timeout : 24; 3995215976Sjmallett#endif 3996215976Sjmallett } s; 3997215976Sjmallett struct cvmx_sriomaintx_port_lt_ctl_s cn63xx; 3998215976Sjmallett struct cvmx_sriomaintx_port_lt_ctl_s cn63xxp1; 3999215976Sjmallett}; 4000215976Sjmalletttypedef union cvmx_sriomaintx_port_lt_ctl cvmx_sriomaintx_port_lt_ctl_t; 4001215976Sjmallett 4002215976Sjmallett/** 4003215976Sjmallett * cvmx_sriomaint#_port_mbh0 4004215976Sjmallett * 4005215976Sjmallett * SRIOMAINT_PORT_MBH0 = SRIO Port Maintenance Block Header 0 4006215976Sjmallett * 4007215976Sjmallett * Port Maintenance Block Header 0 4008215976Sjmallett * 4009215976Sjmallett * Notes: 4010215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_MBH0 hclk hrst_n 4011215976Sjmallett * 4012215976Sjmallett */ 4013215976Sjmallettunion cvmx_sriomaintx_port_mbh0 4014215976Sjmallett{ 4015215976Sjmallett uint32_t u32; 4016215976Sjmallett struct cvmx_sriomaintx_port_mbh0_s 4017215976Sjmallett { 4018215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4019215976Sjmallett uint32_t ef_ptr : 16; /**< Pointer to Error Management Block. */ 4020215976Sjmallett uint32_t ef_id : 16; /**< Extended Feature ID (Generic Endpoint Device) */ 4021215976Sjmallett#else 4022215976Sjmallett uint32_t ef_id : 16; 4023215976Sjmallett uint32_t ef_ptr : 16; 4024215976Sjmallett#endif 4025215976Sjmallett } s; 4026215976Sjmallett struct cvmx_sriomaintx_port_mbh0_s cn63xx; 4027215976Sjmallett struct cvmx_sriomaintx_port_mbh0_s cn63xxp1; 4028215976Sjmallett}; 4029215976Sjmalletttypedef union cvmx_sriomaintx_port_mbh0 cvmx_sriomaintx_port_mbh0_t; 4030215976Sjmallett 4031215976Sjmallett/** 4032215976Sjmallett * cvmx_sriomaint#_port_rt_ctl 4033215976Sjmallett * 4034215976Sjmallett * SRIOMAINT_PORT_RT_CTL = SRIO Logical Layer Timeout Control 4035215976Sjmallett * 4036215976Sjmallett * Logical Layer Timeout Control 4037215976Sjmallett * 4038215976Sjmallett * Notes: 4039215976Sjmallett * This register controls the timeout for logical layer transactions. It is used under two 4040215976Sjmallett * conditions. First, it is used as the timeout period between sending a packet requiring a packet 4041215976Sjmallett * response being sent to receiving the corresponding response. This is used for all outgoing packet 4042215976Sjmallett * types including memory, maintenance, doorbells and message operations. When the timeout period 4043215976Sjmallett * expires the packet is disgarded and the error is logged in the PKT_TOUT field of the 4044215976Sjmallett * SRIOMAINT(0..1)_ERB_LT_ERR_DET register. The second use of this register is as a timeout period 4045215976Sjmallett * between incoming message segments of the same message. If a message segment is received then the 4046215976Sjmallett * MSG_TOUT field of the SRIOMAINT(0..1)_ERB_LT_ERR_DET register is set if the next segment has not been 4047215976Sjmallett * received before the time expires. In both cases, each count represents 200ns. The minimum 4048215976Sjmallett * timeout period is the TIMEOUT x 200nS and the maximum is twice that number. A value less than 32 4049215976Sjmallett * may not guarantee that all timeout errors will be reported correctly. A value of 0 disables the 4050215976Sjmallett * logical layer timeouts and is not recommended for normal operation. 4051215976Sjmallett * 4052215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_RT_CTL hclk hrst_n 4053215976Sjmallett */ 4054215976Sjmallettunion cvmx_sriomaintx_port_rt_ctl 4055215976Sjmallett{ 4056215976Sjmallett uint32_t u32; 4057215976Sjmallett struct cvmx_sriomaintx_port_rt_ctl_s 4058215976Sjmallett { 4059215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4060215976Sjmallett uint32_t timeout : 24; /**< Timeout Value */ 4061215976Sjmallett uint32_t reserved_0_7 : 8; 4062215976Sjmallett#else 4063215976Sjmallett uint32_t reserved_0_7 : 8; 4064215976Sjmallett uint32_t timeout : 24; 4065215976Sjmallett#endif 4066215976Sjmallett } s; 4067215976Sjmallett struct cvmx_sriomaintx_port_rt_ctl_s cn63xx; 4068215976Sjmallett struct cvmx_sriomaintx_port_rt_ctl_s cn63xxp1; 4069215976Sjmallett}; 4070215976Sjmalletttypedef union cvmx_sriomaintx_port_rt_ctl cvmx_sriomaintx_port_rt_ctl_t; 4071215976Sjmallett 4072215976Sjmallett/** 4073215976Sjmallett * cvmx_sriomaint#_port_ttl_ctl 4074215976Sjmallett * 4075215976Sjmallett * SRIOMAINT_PORT_TTL_CTL = SRIO Packet Time to Live Control (Pass 2) 4076215976Sjmallett * 4077215976Sjmallett * Packet Time to Live 4078215976Sjmallett * 4079215976Sjmallett * Notes: 4080215976Sjmallett * This register controls the timeout for outgoing packets. It is used to make sure packets are 4081215976Sjmallett * being transmitted and acknowledged within a reasonable period of time. The timeout value 4082215976Sjmallett * corresponds to TIMEOUT x 200ns and a value of 0 disables the timer. The actualy value of the 4083215976Sjmallett * should be greater than the physical layer timout specified in SRIOMAINT(0..1)_PORT_LT_CTL and is 4084215976Sjmallett * typically a less SRIOMAINT(0..1)_PORT_LT_CTL timeout than the response timeout specified in 4085215976Sjmallett * SRIOMAINT(0..1)_PORT_RT_CTL. When the timeout expires the TTL interrupt is asserted, any packets 4086215976Sjmallett * currently being transmitted are dropped, the SRIOMAINT(0..1)_TX_DROP.DROP bit is set (causing any 4087215976Sjmallett * scheduled packets to be dropped), the SRIOMAINT(0..1)_TX_DROP.DROP_CNT is incremented and the SRIO 4088215976Sjmallett * output state is set to IDLE (all errors are cleared). Software must clear the 4089215976Sjmallett * SRIOMAINT(0..1)_TX_DROP.DROP bit to resume transmitting packets. 4090215976Sjmallett * 4091215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PORT_RT_CTL hclk hrst_n 4092215976Sjmallett */ 4093215976Sjmallettunion cvmx_sriomaintx_port_ttl_ctl 4094215976Sjmallett{ 4095215976Sjmallett uint32_t u32; 4096215976Sjmallett struct cvmx_sriomaintx_port_ttl_ctl_s 4097215976Sjmallett { 4098215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4099215976Sjmallett uint32_t timeout : 24; /**< Timeout Value */ 4100215976Sjmallett uint32_t reserved_0_7 : 8; 4101215976Sjmallett#else 4102215976Sjmallett uint32_t reserved_0_7 : 8; 4103215976Sjmallett uint32_t timeout : 24; 4104215976Sjmallett#endif 4105215976Sjmallett } s; 4106215976Sjmallett struct cvmx_sriomaintx_port_ttl_ctl_s cn63xx; 4107215976Sjmallett}; 4108215976Sjmalletttypedef union cvmx_sriomaintx_port_ttl_ctl cvmx_sriomaintx_port_ttl_ctl_t; 4109215976Sjmallett 4110215976Sjmallett/** 4111215976Sjmallett * cvmx_sriomaint#_pri_dev_id 4112215976Sjmallett * 4113215976Sjmallett * SRIOMAINT_PRI_DEV_ID = SRIO Primary Device ID 4114215976Sjmallett * 4115215976Sjmallett * Primary 8 and 16 bit Device IDs 4116215976Sjmallett * 4117215976Sjmallett * Notes: 4118215976Sjmallett * This register defines the primary 8 and 16 bit device IDs used for large and small transport. An 4119215976Sjmallett * optional secondary set of device IDs are located in SRIOMAINT(0..1)_SEC_DEV_ID. 4120215976Sjmallett * 4121215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_PRI_DEV_ID hclk hrst_n 4122215976Sjmallett */ 4123215976Sjmallettunion cvmx_sriomaintx_pri_dev_id 4124215976Sjmallett{ 4125215976Sjmallett uint32_t u32; 4126215976Sjmallett struct cvmx_sriomaintx_pri_dev_id_s 4127215976Sjmallett { 4128215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4129215976Sjmallett uint32_t reserved_24_31 : 8; 4130215976Sjmallett uint32_t id8 : 8; /**< Primary 8-bit Device ID */ 4131215976Sjmallett uint32_t id16 : 16; /**< Primary 16-bit Device ID */ 4132215976Sjmallett#else 4133215976Sjmallett uint32_t id16 : 16; 4134215976Sjmallett uint32_t id8 : 8; 4135215976Sjmallett uint32_t reserved_24_31 : 8; 4136215976Sjmallett#endif 4137215976Sjmallett } s; 4138215976Sjmallett struct cvmx_sriomaintx_pri_dev_id_s cn63xx; 4139215976Sjmallett struct cvmx_sriomaintx_pri_dev_id_s cn63xxp1; 4140215976Sjmallett}; 4141215976Sjmalletttypedef union cvmx_sriomaintx_pri_dev_id cvmx_sriomaintx_pri_dev_id_t; 4142215976Sjmallett 4143215976Sjmallett/** 4144215976Sjmallett * cvmx_sriomaint#_sec_dev_ctrl 4145215976Sjmallett * 4146215976Sjmallett * SRIOMAINT_SEC_DEV_CTRL = SRIO Secondary Device ID Control 4147215976Sjmallett * 4148215976Sjmallett * Control for Secondary Device IDs 4149215976Sjmallett * 4150215976Sjmallett * Notes: 4151215976Sjmallett * This register enables the secondary 8 and 16 bit device IDs used for large and small transport. 4152215976Sjmallett * The corresponding secondary ID must be written before the ID is enabled. The secondary IDs should 4153215976Sjmallett * not be enabled if the values of the primary and secondary IDs are identical. 4154215976Sjmallett * 4155215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_SEC_DEV_CTRL hclk hrst_n 4156215976Sjmallett */ 4157215976Sjmallettunion cvmx_sriomaintx_sec_dev_ctrl 4158215976Sjmallett{ 4159215976Sjmallett uint32_t u32; 4160215976Sjmallett struct cvmx_sriomaintx_sec_dev_ctrl_s 4161215976Sjmallett { 4162215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4163215976Sjmallett uint32_t reserved_2_31 : 30; 4164215976Sjmallett uint32_t enable8 : 1; /**< Enable matches to secondary 8-bit Device ID */ 4165215976Sjmallett uint32_t enable16 : 1; /**< Enable matches to secondary 16-bit Device ID */ 4166215976Sjmallett#else 4167215976Sjmallett uint32_t enable16 : 1; 4168215976Sjmallett uint32_t enable8 : 1; 4169215976Sjmallett uint32_t reserved_2_31 : 30; 4170215976Sjmallett#endif 4171215976Sjmallett } s; 4172215976Sjmallett struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xx; 4173215976Sjmallett struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xxp1; 4174215976Sjmallett}; 4175215976Sjmalletttypedef union cvmx_sriomaintx_sec_dev_ctrl cvmx_sriomaintx_sec_dev_ctrl_t; 4176215976Sjmallett 4177215976Sjmallett/** 4178215976Sjmallett * cvmx_sriomaint#_sec_dev_id 4179215976Sjmallett * 4180215976Sjmallett * SRIOMAINT_SEC_DEV_ID = SRIO Secondary Device ID 4181215976Sjmallett * 4182215976Sjmallett * Secondary 8 and 16 bit Device IDs 4183215976Sjmallett * 4184215976Sjmallett * Notes: 4185215976Sjmallett * This register defines the secondary 8 and 16 bit device IDs used for large and small transport. 4186215976Sjmallett * The corresponding secondary ID must be written before the ID is enabled in the 4187215976Sjmallett * SRIOMAINT(0..1)_SEC_DEV_CTRL register. The primary set of device IDs are located in 4188215976Sjmallett * SRIOMAINT(0..1)_PRI_DEV_ID register. The secondary IDs should not be written to the same values as the 4189215976Sjmallett * corresponding primary IDs. 4190215976Sjmallett * 4191215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_SEC_DEV_ID hclk hrst_n 4192215976Sjmallett */ 4193215976Sjmallettunion cvmx_sriomaintx_sec_dev_id 4194215976Sjmallett{ 4195215976Sjmallett uint32_t u32; 4196215976Sjmallett struct cvmx_sriomaintx_sec_dev_id_s 4197215976Sjmallett { 4198215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4199215976Sjmallett uint32_t reserved_24_31 : 8; 4200215976Sjmallett uint32_t id8 : 8; /**< Secondary 8-bit Device ID */ 4201215976Sjmallett uint32_t id16 : 16; /**< Secondary 16-bit Device ID */ 4202215976Sjmallett#else 4203215976Sjmallett uint32_t id16 : 16; 4204215976Sjmallett uint32_t id8 : 8; 4205215976Sjmallett uint32_t reserved_24_31 : 8; 4206215976Sjmallett#endif 4207215976Sjmallett } s; 4208215976Sjmallett struct cvmx_sriomaintx_sec_dev_id_s cn63xx; 4209215976Sjmallett struct cvmx_sriomaintx_sec_dev_id_s cn63xxp1; 4210215976Sjmallett}; 4211215976Sjmalletttypedef union cvmx_sriomaintx_sec_dev_id cvmx_sriomaintx_sec_dev_id_t; 4212215976Sjmallett 4213215976Sjmallett/** 4214215976Sjmallett * cvmx_sriomaint#_serial_lane_hdr 4215215976Sjmallett * 4216215976Sjmallett * SRIOMAINT_SERIAL_LANE_HDR = SRIO Serial Lane Header 4217215976Sjmallett * 4218215976Sjmallett * SRIO Serial Lane Header 4219215976Sjmallett * 4220215976Sjmallett * Notes: 4221215976Sjmallett * The error management extensions block header register contains the EF_PTR to the next EF_BLK and 4222215976Sjmallett * the EF_ID that identifies this as the Serial Lane Status Block. 4223215976Sjmallett * 4224215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_SERIAL_LANE_HDR hclk hrst_n 4225215976Sjmallett */ 4226215976Sjmallettunion cvmx_sriomaintx_serial_lane_hdr 4227215976Sjmallett{ 4228215976Sjmallett uint32_t u32; 4229215976Sjmallett struct cvmx_sriomaintx_serial_lane_hdr_s 4230215976Sjmallett { 4231215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4232215976Sjmallett uint32_t ef_ptr : 16; /**< Pointer to the next block in the extended features 4233215976Sjmallett data structure. */ 4234215976Sjmallett uint32_t ef_id : 16; 4235215976Sjmallett#else 4236215976Sjmallett uint32_t ef_id : 16; 4237215976Sjmallett uint32_t ef_ptr : 16; 4238215976Sjmallett#endif 4239215976Sjmallett } s; 4240215976Sjmallett struct cvmx_sriomaintx_serial_lane_hdr_s cn63xx; 4241215976Sjmallett struct cvmx_sriomaintx_serial_lane_hdr_s cn63xxp1; 4242215976Sjmallett}; 4243215976Sjmalletttypedef union cvmx_sriomaintx_serial_lane_hdr cvmx_sriomaintx_serial_lane_hdr_t; 4244215976Sjmallett 4245215976Sjmallett/** 4246215976Sjmallett * cvmx_sriomaint#_src_ops 4247215976Sjmallett * 4248215976Sjmallett * SRIOMAINT_SRC_OPS = SRIO Source Operations 4249215976Sjmallett * 4250215976Sjmallett * The logical operations initiated by the Octeon. 4251215976Sjmallett * 4252215976Sjmallett * Notes: 4253215976Sjmallett * The logical operations initiated by the Cores. The Source OPs register shows the operations 4254215976Sjmallett * specified in the SRIO(0..1)_IP_FEATURE.OPS register. 4255215976Sjmallett * 4256215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_SRC_OPS hclk hrst_n 4257215976Sjmallett */ 4258215976Sjmallettunion cvmx_sriomaintx_src_ops 4259215976Sjmallett{ 4260215976Sjmallett uint32_t u32; 4261215976Sjmallett struct cvmx_sriomaintx_src_ops_s 4262215976Sjmallett { 4263215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4264215976Sjmallett uint32_t gsm_read : 1; /**< PE does not support Read Home operations. 4265215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */ 4266215976Sjmallett uint32_t i_read : 1; /**< PE does not support Instruction Read. 4267215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<30>] */ 4268215976Sjmallett uint32_t rd_own : 1; /**< PE does not support Read for Ownership. 4269215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<29>] */ 4270215976Sjmallett uint32_t d_invald : 1; /**< PE does not support Data Cache Invalidate. 4271215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<28>] */ 4272215976Sjmallett uint32_t castout : 1; /**< PE does not support Castout Operations. 4273215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<27>] */ 4274215976Sjmallett uint32_t d_flush : 1; /**< PE does not support Data Cache Flush. 4275215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<26>] */ 4276215976Sjmallett uint32_t io_read : 1; /**< PE does not support IO Read. 4277215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<25>] */ 4278215976Sjmallett uint32_t i_invald : 1; /**< PE does not support Instruction Cache Invalidate. 4279215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<24>] */ 4280215976Sjmallett uint32_t tlb_inv : 1; /**< PE does not support TLB Entry Invalidate. 4281215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<23>] */ 4282215976Sjmallett uint32_t tlb_invs : 1; /**< PE does not support TLB Entry Invalidate Sync. 4283215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<22>] */ 4284215976Sjmallett uint32_t reserved_16_21 : 6; 4285215976Sjmallett uint32_t read : 1; /**< PE can support Nread operations. 4286215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<15>] */ 4287215976Sjmallett uint32_t write : 1; /**< PE can support Nwrite operations. 4288215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<14>] */ 4289215976Sjmallett uint32_t swrite : 1; /**< PE can support Swrite operations. 4290215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<13>] */ 4291215976Sjmallett uint32_t write_r : 1; /**< PE can support Write with Response operations. 4292215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<12>] */ 4293215976Sjmallett uint32_t msg : 1; /**< PE can support Data Message operations. 4294215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<11>] */ 4295215976Sjmallett uint32_t doorbell : 1; /**< PE can support Doorbell operations. 4296215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<10>] */ 4297215976Sjmallett uint32_t compswap : 1; /**< PE does not support Atomic Compare and Swap. 4298215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<9>] */ 4299215976Sjmallett uint32_t testswap : 1; /**< PE does not support Atomic Test and Swap. 4300215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<8>] */ 4301215976Sjmallett uint32_t atom_inc : 1; /**< PE can support Atomic increment operations. 4302215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<7>] */ 4303215976Sjmallett uint32_t atom_dec : 1; /**< PE can support Atomic decrement operations. 4304215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<6>] */ 4305215976Sjmallett uint32_t atom_set : 1; /**< PE can support Atomic set operations. 4306215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<5>] */ 4307215976Sjmallett uint32_t atom_clr : 1; /**< PE can support Atomic clear operations. 4308215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<4>] */ 4309215976Sjmallett uint32_t atom_swp : 1; /**< PE does not support Atomic Swap. 4310215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<3>] */ 4311215976Sjmallett uint32_t port_wr : 1; /**< PE can Port Write operations. 4312215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<2>] */ 4313215976Sjmallett uint32_t reserved_0_1 : 2; 4314215976Sjmallett#else 4315215976Sjmallett uint32_t reserved_0_1 : 2; 4316215976Sjmallett uint32_t port_wr : 1; 4317215976Sjmallett uint32_t atom_swp : 1; 4318215976Sjmallett uint32_t atom_clr : 1; 4319215976Sjmallett uint32_t atom_set : 1; 4320215976Sjmallett uint32_t atom_dec : 1; 4321215976Sjmallett uint32_t atom_inc : 1; 4322215976Sjmallett uint32_t testswap : 1; 4323215976Sjmallett uint32_t compswap : 1; 4324215976Sjmallett uint32_t doorbell : 1; 4325215976Sjmallett uint32_t msg : 1; 4326215976Sjmallett uint32_t write_r : 1; 4327215976Sjmallett uint32_t swrite : 1; 4328215976Sjmallett uint32_t write : 1; 4329215976Sjmallett uint32_t read : 1; 4330215976Sjmallett uint32_t reserved_16_21 : 6; 4331215976Sjmallett uint32_t tlb_invs : 1; 4332215976Sjmallett uint32_t tlb_inv : 1; 4333215976Sjmallett uint32_t i_invald : 1; 4334215976Sjmallett uint32_t io_read : 1; 4335215976Sjmallett uint32_t d_flush : 1; 4336215976Sjmallett uint32_t castout : 1; 4337215976Sjmallett uint32_t d_invald : 1; 4338215976Sjmallett uint32_t rd_own : 1; 4339215976Sjmallett uint32_t i_read : 1; 4340215976Sjmallett uint32_t gsm_read : 1; 4341215976Sjmallett#endif 4342215976Sjmallett } s; 4343215976Sjmallett struct cvmx_sriomaintx_src_ops_s cn63xx; 4344215976Sjmallett struct cvmx_sriomaintx_src_ops_s cn63xxp1; 4345215976Sjmallett}; 4346215976Sjmalletttypedef union cvmx_sriomaintx_src_ops cvmx_sriomaintx_src_ops_t; 4347215976Sjmallett 4348215976Sjmallett/** 4349215976Sjmallett * cvmx_sriomaint#_tx_drop 4350215976Sjmallett * 4351215976Sjmallett * SRIOMAINT_TX_DROP = SRIO MAC Outgoing Packet Drop (Pass 2) 4352215976Sjmallett * 4353215976Sjmallett * Outging SRIO Packet Drop Control/Status 4354215976Sjmallett * 4355215976Sjmallett * Notes: 4356215976Sjmallett * This register controls and provides status for dropping outgoing SRIO packets. The DROP bit 4357215976Sjmallett * should only be cleared when no packets are currently being dropped. This can be guaranteed by 4358215976Sjmallett * clearing the SRIOMAINT(0..1)_PORT_0_CTL.O_ENABLE bit before changing the DROP bit and restoring the 4359215976Sjmallett * O_ENABLE afterwards. 4360215976Sjmallett * 4361215976Sjmallett * Clk_Rst: SRIOMAINT(0..1)_MAC_CTRL hclk hrst_n 4362215976Sjmallett */ 4363215976Sjmallettunion cvmx_sriomaintx_tx_drop 4364215976Sjmallett{ 4365215976Sjmallett uint32_t u32; 4366215976Sjmallett struct cvmx_sriomaintx_tx_drop_s 4367215976Sjmallett { 4368215976Sjmallett#if __BYTE_ORDER == __BIG_ENDIAN 4369215976Sjmallett uint32_t reserved_17_31 : 15; 4370215976Sjmallett uint32_t drop : 1; /**< All outgoing packets are dropped. Any packets 4371215976Sjmallett requiring a response will return 1's after the 4372215976Sjmallett SRIOMAINT(0..1)_PORT_RT_CTL Timeout expires. This bit 4373215976Sjmallett is set automatically when the TTL Timeout occurs 4374215976Sjmallett or can be set by software and must always be 4375215976Sjmallett cleared by software. */ 4376215976Sjmallett uint32_t drop_cnt : 16; /**< Number of packets dropped by transmit logic. 4377215976Sjmallett Packets are dropped whenever a packet is ready to 4378215976Sjmallett be transmitted and a TTL Timeouts occur, the DROP 4379215976Sjmallett bit is set or the SRIOMAINT(0..1)_ERB_ERR_RATE_THR 4380215976Sjmallett FAIL_TH has been reached and the DROP_PKT bit is 4381215976Sjmallett set in SRIOMAINT(0..1)_PORT_0_CTL. */ 4382215976Sjmallett#else 4383215976Sjmallett uint32_t drop_cnt : 16; 4384215976Sjmallett uint32_t drop : 1; 4385215976Sjmallett uint32_t reserved_17_31 : 15; 4386215976Sjmallett#endif 4387215976Sjmallett } s; 4388215976Sjmallett struct cvmx_sriomaintx_tx_drop_s cn63xx; 4389215976Sjmallett}; 4390215976Sjmalletttypedef union cvmx_sriomaintx_tx_drop cvmx_sriomaintx_tx_drop_t; 4391215976Sjmallett 4392215976Sjmallett#endif 4393