1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-sriomaintx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon sriomaintx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_SRIOMAINTX_DEFS_H__ 53232812Sjmallett#define __CVMX_SRIOMAINTX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 60232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 61215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id); 62215976Sjmallett return 0x0000000000000008ull; 63215976Sjmallett} 64215976Sjmallett#else 65215976Sjmallett#define CVMX_SRIOMAINTX_ASMBLY_ID(block_id) (0x0000000000000008ull) 66215976Sjmallett#endif 67215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id) 69215976Sjmallett{ 70215976Sjmallett if (!( 71232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 72232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 73215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id); 74215976Sjmallett return 0x000000000000000Cull; 75215976Sjmallett} 76215976Sjmallett#else 77215976Sjmallett#define CVMX_SRIOMAINTX_ASMBLY_INFO(block_id) (0x000000000000000Cull) 78215976Sjmallett#endif 79215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 80215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_BAR1_IDXX(unsigned long offset, unsigned long block_id) 81215976Sjmallett{ 82215976Sjmallett if (!( 83232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) || 84232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 85215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_BAR1_IDXX(%lu,%lu) is invalid on this chip\n", offset, block_id); 86232812Sjmallett return 0x0000000000200010ull + (((offset) & 15) + ((block_id) & 3) * 0x0ull) * 4; 87215976Sjmallett} 88215976Sjmallett#else 89232812Sjmallett#define CVMX_SRIOMAINTX_BAR1_IDXX(offset, block_id) (0x0000000000200010ull + (((offset) & 15) + ((block_id) & 3) * 0x0ull) * 4) 90215976Sjmallett#endif 91215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 92215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_BELL_STATUS(unsigned long block_id) 93215976Sjmallett{ 94215976Sjmallett if (!( 95232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 96232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 97215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_BELL_STATUS(%lu) is invalid on this chip\n", block_id); 98215976Sjmallett return 0x0000000000200080ull; 99215976Sjmallett} 100215976Sjmallett#else 101215976Sjmallett#define CVMX_SRIOMAINTX_BELL_STATUS(block_id) (0x0000000000200080ull) 102215976Sjmallett#endif 103215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_COMP_TAG(unsigned long block_id) 105215976Sjmallett{ 106215976Sjmallett if (!( 107232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 108232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 109215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_COMP_TAG(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return 0x000000000000006Cull; 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_SRIOMAINTX_COMP_TAG(block_id) (0x000000000000006Cull) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_CORE_ENABLES(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 120232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 121215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_CORE_ENABLES(%lu) is invalid on this chip\n", block_id); 122215976Sjmallett return 0x0000000000200070ull; 123215976Sjmallett} 124215976Sjmallett#else 125215976Sjmallett#define CVMX_SRIOMAINTX_CORE_ENABLES(block_id) (0x0000000000200070ull) 126215976Sjmallett#endif 127215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_DEV_ID(unsigned long block_id) 129215976Sjmallett{ 130215976Sjmallett if (!( 131232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 132232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 133215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_DEV_ID(%lu) is invalid on this chip\n", block_id); 134215976Sjmallett return 0x0000000000000000ull; 135215976Sjmallett} 136215976Sjmallett#else 137215976Sjmallett#define CVMX_SRIOMAINTX_DEV_ID(block_id) (0x0000000000000000ull) 138215976Sjmallett#endif 139215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 140215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_DEV_REV(unsigned long block_id) 141215976Sjmallett{ 142215976Sjmallett if (!( 143232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 144232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 145215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_DEV_REV(%lu) is invalid on this chip\n", block_id); 146215976Sjmallett return 0x0000000000000004ull; 147215976Sjmallett} 148215976Sjmallett#else 149215976Sjmallett#define CVMX_SRIOMAINTX_DEV_REV(block_id) (0x0000000000000004ull) 150215976Sjmallett#endif 151215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 152215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_DST_OPS(unsigned long block_id) 153215976Sjmallett{ 154215976Sjmallett if (!( 155232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 156232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 157215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_DST_OPS(%lu) is invalid on this chip\n", block_id); 158215976Sjmallett return 0x000000000000001Cull; 159215976Sjmallett} 160215976Sjmallett#else 161215976Sjmallett#define CVMX_SRIOMAINTX_DST_OPS(block_id) (0x000000000000001Cull) 162215976Sjmallett#endif 163215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_ATTR_CAPT(unsigned long block_id) 165215976Sjmallett{ 166215976Sjmallett if (!( 167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 168232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 169215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_ATTR_CAPT(%lu) is invalid on this chip\n", block_id); 170215976Sjmallett return 0x0000000000002048ull; 171215976Sjmallett} 172215976Sjmallett#else 173215976Sjmallett#define CVMX_SRIOMAINTX_ERB_ATTR_CAPT(block_id) (0x0000000000002048ull) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_DET(unsigned long block_id) 177215976Sjmallett{ 178215976Sjmallett if (!( 179232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 180232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 181215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_DET(%lu) is invalid on this chip\n", block_id); 182215976Sjmallett return 0x0000000000002040ull; 183215976Sjmallett} 184215976Sjmallett#else 185215976Sjmallett#define CVMX_SRIOMAINTX_ERB_ERR_DET(block_id) (0x0000000000002040ull) 186215976Sjmallett#endif 187215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE(unsigned long block_id) 189215976Sjmallett{ 190215976Sjmallett if (!( 191232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 192232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 193215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE(%lu) is invalid on this chip\n", block_id); 194215976Sjmallett return 0x0000000000002068ull; 195215976Sjmallett} 196215976Sjmallett#else 197215976Sjmallett#define CVMX_SRIOMAINTX_ERB_ERR_RATE(block_id) (0x0000000000002068ull) 198215976Sjmallett#endif 199215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 200215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(unsigned long block_id) 201215976Sjmallett{ 202215976Sjmallett if (!( 203232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 204232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 205215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(%lu) is invalid on this chip\n", block_id); 206215976Sjmallett return 0x0000000000002044ull; 207215976Sjmallett} 208215976Sjmallett#else 209215976Sjmallett#define CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(block_id) (0x0000000000002044ull) 210215976Sjmallett#endif 211215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(unsigned long block_id) 213215976Sjmallett{ 214215976Sjmallett if (!( 215232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 216232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 217215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(%lu) is invalid on this chip\n", block_id); 218215976Sjmallett return 0x000000000000206Cull; 219215976Sjmallett} 220215976Sjmallett#else 221215976Sjmallett#define CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(block_id) (0x000000000000206Cull) 222215976Sjmallett#endif 223215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 224215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_HDR(unsigned long block_id) 225215976Sjmallett{ 226215976Sjmallett if (!( 227232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 228232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 229215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_HDR(%lu) is invalid on this chip\n", block_id); 230215976Sjmallett return 0x0000000000002000ull; 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_SRIOMAINTX_ERB_HDR(block_id) (0x0000000000002000ull) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(unsigned long block_id) 237215976Sjmallett{ 238215976Sjmallett if (!( 239232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 240232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 241215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(%lu) is invalid on this chip\n", block_id); 242215976Sjmallett return 0x0000000000002010ull; 243215976Sjmallett} 244215976Sjmallett#else 245215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(block_id) (0x0000000000002010ull) 246215976Sjmallett#endif 247215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 248215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(unsigned long block_id) 249215976Sjmallett{ 250215976Sjmallett if (!( 251232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 252232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 253215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(%lu) is invalid on this chip\n", block_id); 254215976Sjmallett return 0x0000000000002014ull; 255215976Sjmallett} 256215976Sjmallett#else 257215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(block_id) (0x0000000000002014ull) 258215976Sjmallett#endif 259215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 260215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(unsigned long block_id) 261215976Sjmallett{ 262215976Sjmallett if (!( 263232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 264232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 265215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(%lu) is invalid on this chip\n", block_id); 266215976Sjmallett return 0x000000000000201Cull; 267215976Sjmallett} 268215976Sjmallett#else 269215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(block_id) (0x000000000000201Cull) 270215976Sjmallett#endif 271215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 272215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID(unsigned long block_id) 273215976Sjmallett{ 274215976Sjmallett if (!( 275232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 276232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 277215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID(%lu) is invalid on this chip\n", block_id); 278215976Sjmallett return 0x0000000000002028ull; 279215976Sjmallett} 280215976Sjmallett#else 281215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_DEV_ID(block_id) (0x0000000000002028ull) 282215976Sjmallett#endif 283215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 284215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(unsigned long block_id) 285215976Sjmallett{ 286215976Sjmallett if (!( 287232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 288232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 289215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(%lu) is invalid on this chip\n", block_id); 290215976Sjmallett return 0x0000000000002018ull; 291215976Sjmallett} 292215976Sjmallett#else 293215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(block_id) (0x0000000000002018ull) 294215976Sjmallett#endif 295215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_DET(unsigned long block_id) 297215976Sjmallett{ 298215976Sjmallett if (!( 299232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 300232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 301215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_DET(%lu) is invalid on this chip\n", block_id); 302215976Sjmallett return 0x0000000000002008ull; 303215976Sjmallett} 304215976Sjmallett#else 305215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_ERR_DET(block_id) (0x0000000000002008ull) 306215976Sjmallett#endif 307215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_EN(unsigned long block_id) 309215976Sjmallett{ 310215976Sjmallett if (!( 311232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 312232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 313215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_EN(%lu) is invalid on this chip\n", block_id); 314215976Sjmallett return 0x000000000000200Cull; 315215976Sjmallett} 316215976Sjmallett#else 317215976Sjmallett#define CVMX_SRIOMAINTX_ERB_LT_ERR_EN(block_id) (0x000000000000200Cull) 318215976Sjmallett#endif 319215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(unsigned long block_id) 321215976Sjmallett{ 322215976Sjmallett if (!( 323232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 324232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 325215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(%lu) is invalid on this chip\n", block_id); 326215976Sjmallett return 0x0000000000002050ull; 327215976Sjmallett} 328215976Sjmallett#else 329215976Sjmallett#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(block_id) (0x0000000000002050ull) 330215976Sjmallett#endif 331215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 332215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(unsigned long block_id) 333215976Sjmallett{ 334215976Sjmallett if (!( 335232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 336232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 337215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(%lu) is invalid on this chip\n", block_id); 338215976Sjmallett return 0x0000000000002054ull; 339215976Sjmallett} 340215976Sjmallett#else 341215976Sjmallett#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(block_id) (0x0000000000002054ull) 342215976Sjmallett#endif 343215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 344215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(unsigned long block_id) 345215976Sjmallett{ 346215976Sjmallett if (!( 347232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 348232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 349215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(%lu) is invalid on this chip\n", block_id); 350215976Sjmallett return 0x0000000000002058ull; 351215976Sjmallett} 352215976Sjmallett#else 353215976Sjmallett#define CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(block_id) (0x0000000000002058ull) 354215976Sjmallett#endif 355215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 356215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(unsigned long block_id) 357215976Sjmallett{ 358215976Sjmallett if (!( 359232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 360232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 361215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(%lu) is invalid on this chip\n", block_id); 362215976Sjmallett return 0x000000000000204Cull; 363215976Sjmallett} 364215976Sjmallett#else 365215976Sjmallett#define CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(block_id) (0x000000000000204Cull) 366215976Sjmallett#endif 367215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 368215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(unsigned long block_id) 369215976Sjmallett{ 370215976Sjmallett if (!( 371232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 372232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 373215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(%lu) is invalid on this chip\n", block_id); 374215976Sjmallett return 0x0000000000000068ull; 375215976Sjmallett} 376215976Sjmallett#else 377215976Sjmallett#define CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(block_id) (0x0000000000000068ull) 378215976Sjmallett#endif 379215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 380215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(unsigned long block_id) 381215976Sjmallett{ 382215976Sjmallett if (!( 383232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 384232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 385215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(%lu) is invalid on this chip\n", block_id); 386215976Sjmallett return 0x0000000000102000ull; 387215976Sjmallett} 388215976Sjmallett#else 389215976Sjmallett#define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(block_id) (0x0000000000102000ull) 390215976Sjmallett#endif 391215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 392215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(unsigned long block_id) 393215976Sjmallett{ 394215976Sjmallett if (!( 395232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 396232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 397215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(%lu) is invalid on this chip\n", block_id); 398215976Sjmallett return 0x0000000000102004ull; 399215976Sjmallett} 400215976Sjmallett#else 401215976Sjmallett#define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(block_id) (0x0000000000102004ull) 402215976Sjmallett#endif 403215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 404215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(unsigned long block_id) 405215976Sjmallett{ 406215976Sjmallett if (!( 407232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 408232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 409215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(%lu) is invalid on this chip\n", block_id); 410215976Sjmallett return 0x0000000000107028ull; 411215976Sjmallett} 412215976Sjmallett#else 413215976Sjmallett#define CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(block_id) (0x0000000000107028ull) 414215976Sjmallett#endif 415215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 416215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_STAT(unsigned long block_id) 417215976Sjmallett{ 418215976Sjmallett if (!( 419232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 420232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 421215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_STAT(%lu) is invalid on this chip\n", block_id); 422215976Sjmallett return 0x000000000010702Cull; 423215976Sjmallett} 424215976Sjmallett#else 425215976Sjmallett#define CVMX_SRIOMAINTX_IR_PD_PHY_STAT(block_id) (0x000000000010702Cull) 426215976Sjmallett#endif 427215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 428215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(unsigned long block_id) 429215976Sjmallett{ 430215976Sjmallett if (!( 431232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 432232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 433215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(%lu) is invalid on this chip\n", block_id); 434215976Sjmallett return 0x0000000000107020ull; 435215976Sjmallett} 436215976Sjmallett#else 437215976Sjmallett#define CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(block_id) (0x0000000000107020ull) 438215976Sjmallett#endif 439215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 440215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_STAT(unsigned long block_id) 441215976Sjmallett{ 442215976Sjmallett if (!( 443232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 444232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 445215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_STAT(%lu) is invalid on this chip\n", block_id); 446215976Sjmallett return 0x0000000000107024ull; 447215976Sjmallett} 448215976Sjmallett#else 449215976Sjmallett#define CVMX_SRIOMAINTX_IR_PI_PHY_STAT(block_id) (0x0000000000107024ull) 450215976Sjmallett#endif 451215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_CTRL(unsigned long block_id) 453215976Sjmallett{ 454215976Sjmallett if (!( 455232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 456232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 457215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_CTRL(%lu) is invalid on this chip\n", block_id); 458215976Sjmallett return 0x000000000010700Cull; 459215976Sjmallett} 460215976Sjmallett#else 461215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_RX_CTRL(block_id) (0x000000000010700Cull) 462215976Sjmallett#endif 463215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 464215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_DATA(unsigned long block_id) 465215976Sjmallett{ 466215976Sjmallett if (!( 467232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 468232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 469215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_DATA(%lu) is invalid on this chip\n", block_id); 470215976Sjmallett return 0x0000000000107014ull; 471215976Sjmallett} 472215976Sjmallett#else 473215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_RX_DATA(block_id) (0x0000000000107014ull) 474215976Sjmallett#endif 475215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 476215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_STAT(unsigned long block_id) 477215976Sjmallett{ 478215976Sjmallett if (!( 479232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 480232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 481215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_STAT(%lu) is invalid on this chip\n", block_id); 482215976Sjmallett return 0x0000000000107010ull; 483215976Sjmallett} 484215976Sjmallett#else 485215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_RX_STAT(block_id) (0x0000000000107010ull) 486215976Sjmallett#endif 487215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 488215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_CTRL(unsigned long block_id) 489215976Sjmallett{ 490215976Sjmallett if (!( 491232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 492232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 493215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_CTRL(%lu) is invalid on this chip\n", block_id); 494215976Sjmallett return 0x0000000000107000ull; 495215976Sjmallett} 496215976Sjmallett#else 497215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_TX_CTRL(block_id) (0x0000000000107000ull) 498215976Sjmallett#endif 499215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 500215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_DATA(unsigned long block_id) 501215976Sjmallett{ 502215976Sjmallett if (!( 503232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 504232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 505215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_DATA(%lu) is invalid on this chip\n", block_id); 506215976Sjmallett return 0x0000000000107008ull; 507215976Sjmallett} 508215976Sjmallett#else 509215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_TX_DATA(block_id) (0x0000000000107008ull) 510215976Sjmallett#endif 511215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 512215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_STAT(unsigned long block_id) 513215976Sjmallett{ 514215976Sjmallett if (!( 515232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 516232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 517215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_STAT(%lu) is invalid on this chip\n", block_id); 518215976Sjmallett return 0x0000000000107004ull; 519215976Sjmallett} 520215976Sjmallett#else 521215976Sjmallett#define CVMX_SRIOMAINTX_IR_SP_TX_STAT(block_id) (0x0000000000107004ull) 522215976Sjmallett#endif 523215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 524215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_LANE_X_STATUS_0(unsigned long offset, unsigned long block_id) 525215976Sjmallett{ 526215976Sjmallett if (!( 527232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) || 528232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id == 0) || (block_id == 2) || (block_id == 3)))))) 529215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_LANE_X_STATUS_0(%lu,%lu) is invalid on this chip\n", offset, block_id); 530232812Sjmallett return 0x0000000000001010ull + (((offset) & 3) + ((block_id) & 3) * 0x0ull) * 32; 531215976Sjmallett} 532215976Sjmallett#else 533232812Sjmallett#define CVMX_SRIOMAINTX_LANE_X_STATUS_0(offset, block_id) (0x0000000000001010ull + (((offset) & 3) + ((block_id) & 3) * 0x0ull) * 32) 534215976Sjmallett#endif 535215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 536215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_LCS_BA0(unsigned long block_id) 537215976Sjmallett{ 538215976Sjmallett if (!( 539232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 540232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 541215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_LCS_BA0(%lu) is invalid on this chip\n", block_id); 542215976Sjmallett return 0x0000000000000058ull; 543215976Sjmallett} 544215976Sjmallett#else 545215976Sjmallett#define CVMX_SRIOMAINTX_LCS_BA0(block_id) (0x0000000000000058ull) 546215976Sjmallett#endif 547215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 548215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_LCS_BA1(unsigned long block_id) 549215976Sjmallett{ 550215976Sjmallett if (!( 551232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 552232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 553215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_LCS_BA1(%lu) is invalid on this chip\n", block_id); 554215976Sjmallett return 0x000000000000005Cull; 555215976Sjmallett} 556215976Sjmallett#else 557215976Sjmallett#define CVMX_SRIOMAINTX_LCS_BA1(block_id) (0x000000000000005Cull) 558215976Sjmallett#endif 559215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 560215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START0(unsigned long block_id) 561215976Sjmallett{ 562215976Sjmallett if (!( 563232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 564232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 565215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START0(%lu) is invalid on this chip\n", block_id); 566215976Sjmallett return 0x0000000000200000ull; 567215976Sjmallett} 568215976Sjmallett#else 569215976Sjmallett#define CVMX_SRIOMAINTX_M2S_BAR0_START0(block_id) (0x0000000000200000ull) 570215976Sjmallett#endif 571215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 572215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START1(unsigned long block_id) 573215976Sjmallett{ 574215976Sjmallett if (!( 575232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 576232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 577215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START1(%lu) is invalid on this chip\n", block_id); 578215976Sjmallett return 0x0000000000200004ull; 579215976Sjmallett} 580215976Sjmallett#else 581215976Sjmallett#define CVMX_SRIOMAINTX_M2S_BAR0_START1(block_id) (0x0000000000200004ull) 582215976Sjmallett#endif 583215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START0(unsigned long block_id) 585215976Sjmallett{ 586215976Sjmallett if (!( 587232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 588232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 589215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START0(%lu) is invalid on this chip\n", block_id); 590215976Sjmallett return 0x0000000000200008ull; 591215976Sjmallett} 592215976Sjmallett#else 593215976Sjmallett#define CVMX_SRIOMAINTX_M2S_BAR1_START0(block_id) (0x0000000000200008ull) 594215976Sjmallett#endif 595215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 596215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START1(unsigned long block_id) 597215976Sjmallett{ 598215976Sjmallett if (!( 599232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 600232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 601215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START1(%lu) is invalid on this chip\n", block_id); 602215976Sjmallett return 0x000000000020000Cull; 603215976Sjmallett} 604215976Sjmallett#else 605215976Sjmallett#define CVMX_SRIOMAINTX_M2S_BAR1_START1(block_id) (0x000000000020000Cull) 606215976Sjmallett#endif 607215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 608215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_M2S_BAR2_START(unsigned long block_id) 609215976Sjmallett{ 610215976Sjmallett if (!( 611232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 612232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 613215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR2_START(%lu) is invalid on this chip\n", block_id); 614215976Sjmallett return 0x0000000000200050ull; 615215976Sjmallett} 616215976Sjmallett#else 617215976Sjmallett#define CVMX_SRIOMAINTX_M2S_BAR2_START(block_id) (0x0000000000200050ull) 618215976Sjmallett#endif 619215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 620215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_MAC_CTRL(unsigned long block_id) 621215976Sjmallett{ 622215976Sjmallett if (!( 623232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 624232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 625215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_MAC_CTRL(%lu) is invalid on this chip\n", block_id); 626215976Sjmallett return 0x0000000000200068ull; 627215976Sjmallett} 628215976Sjmallett#else 629215976Sjmallett#define CVMX_SRIOMAINTX_MAC_CTRL(block_id) (0x0000000000200068ull) 630215976Sjmallett#endif 631215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 632215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PE_FEAT(unsigned long block_id) 633215976Sjmallett{ 634215976Sjmallett if (!( 635232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 636232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 637215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PE_FEAT(%lu) is invalid on this chip\n", block_id); 638215976Sjmallett return 0x0000000000000010ull; 639215976Sjmallett} 640215976Sjmallett#else 641215976Sjmallett#define CVMX_SRIOMAINTX_PE_FEAT(block_id) (0x0000000000000010ull) 642215976Sjmallett#endif 643215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 644215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PE_LLC(unsigned long block_id) 645215976Sjmallett{ 646215976Sjmallett if (!( 647232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 648232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 649215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PE_LLC(%lu) is invalid on this chip\n", block_id); 650215976Sjmallett return 0x000000000000004Cull; 651215976Sjmallett} 652215976Sjmallett#else 653215976Sjmallett#define CVMX_SRIOMAINTX_PE_LLC(block_id) (0x000000000000004Cull) 654215976Sjmallett#endif 655215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 656215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL(unsigned long block_id) 657215976Sjmallett{ 658215976Sjmallett if (!( 659232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 660232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 661215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL(%lu) is invalid on this chip\n", block_id); 662215976Sjmallett return 0x000000000000015Cull; 663215976Sjmallett} 664215976Sjmallett#else 665215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_CTL(block_id) (0x000000000000015Cull) 666215976Sjmallett#endif 667215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 668215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long block_id) 669215976Sjmallett{ 670215976Sjmallett if (!( 671232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 672232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 673215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL2(%lu) is invalid on this chip\n", block_id); 674215976Sjmallett return 0x0000000000000154ull; 675215976Sjmallett} 676215976Sjmallett#else 677215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_CTL2(block_id) (0x0000000000000154ull) 678215976Sjmallett#endif 679215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 680215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_ERR_STAT(unsigned long block_id) 681215976Sjmallett{ 682215976Sjmallett if (!( 683232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 684232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 685215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_ERR_STAT(%lu) is invalid on this chip\n", block_id); 686215976Sjmallett return 0x0000000000000158ull; 687215976Sjmallett} 688215976Sjmallett#else 689215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_ERR_STAT(block_id) (0x0000000000000158ull) 690215976Sjmallett#endif 691215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 692215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_REQ(unsigned long block_id) 693215976Sjmallett{ 694215976Sjmallett if (!( 695232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 696232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 697215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_REQ(%lu) is invalid on this chip\n", block_id); 698215976Sjmallett return 0x0000000000000140ull; 699215976Sjmallett} 700215976Sjmallett#else 701215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_LINK_REQ(block_id) (0x0000000000000140ull) 702215976Sjmallett#endif 703215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 704215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_RESP(unsigned long block_id) 705215976Sjmallett{ 706215976Sjmallett if (!( 707232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 708232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 709215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_RESP(%lu) is invalid on this chip\n", block_id); 710215976Sjmallett return 0x0000000000000144ull; 711215976Sjmallett} 712215976Sjmallett#else 713215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_LINK_RESP(block_id) (0x0000000000000144ull) 714215976Sjmallett#endif 715215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(unsigned long block_id) 717215976Sjmallett{ 718215976Sjmallett if (!( 719232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 720232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 721215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(%lu) is invalid on this chip\n", block_id); 722215976Sjmallett return 0x0000000000000148ull; 723215976Sjmallett} 724215976Sjmallett#else 725215976Sjmallett#define CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(block_id) (0x0000000000000148ull) 726215976Sjmallett#endif 727215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 728215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_GEN_CTL(unsigned long block_id) 729215976Sjmallett{ 730215976Sjmallett if (!( 731232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 732232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 733215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_GEN_CTL(%lu) is invalid on this chip\n", block_id); 734215976Sjmallett return 0x000000000000013Cull; 735215976Sjmallett} 736215976Sjmallett#else 737215976Sjmallett#define CVMX_SRIOMAINTX_PORT_GEN_CTL(block_id) (0x000000000000013Cull) 738215976Sjmallett#endif 739215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 740215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_LT_CTL(unsigned long block_id) 741215976Sjmallett{ 742215976Sjmallett if (!( 743232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 744232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 745215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_LT_CTL(%lu) is invalid on this chip\n", block_id); 746215976Sjmallett return 0x0000000000000120ull; 747215976Sjmallett} 748215976Sjmallett#else 749215976Sjmallett#define CVMX_SRIOMAINTX_PORT_LT_CTL(block_id) (0x0000000000000120ull) 750215976Sjmallett#endif 751215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 752215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_MBH0(unsigned long block_id) 753215976Sjmallett{ 754215976Sjmallett if (!( 755232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 756232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 757215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_MBH0(%lu) is invalid on this chip\n", block_id); 758215976Sjmallett return 0x0000000000000100ull; 759215976Sjmallett} 760215976Sjmallett#else 761215976Sjmallett#define CVMX_SRIOMAINTX_PORT_MBH0(block_id) (0x0000000000000100ull) 762215976Sjmallett#endif 763215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 764215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_RT_CTL(unsigned long block_id) 765215976Sjmallett{ 766215976Sjmallett if (!( 767232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 768232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 769215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_RT_CTL(%lu) is invalid on this chip\n", block_id); 770215976Sjmallett return 0x0000000000000124ull; 771215976Sjmallett} 772215976Sjmallett#else 773215976Sjmallett#define CVMX_SRIOMAINTX_PORT_RT_CTL(block_id) (0x0000000000000124ull) 774215976Sjmallett#endif 775215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 776215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PORT_TTL_CTL(unsigned long block_id) 777215976Sjmallett{ 778215976Sjmallett if (!( 779232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 780232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 781215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PORT_TTL_CTL(%lu) is invalid on this chip\n", block_id); 782215976Sjmallett return 0x000000000000012Cull; 783215976Sjmallett} 784215976Sjmallett#else 785215976Sjmallett#define CVMX_SRIOMAINTX_PORT_TTL_CTL(block_id) (0x000000000000012Cull) 786215976Sjmallett#endif 787215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 788215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_PRI_DEV_ID(unsigned long block_id) 789215976Sjmallett{ 790215976Sjmallett if (!( 791232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 792232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 793215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_PRI_DEV_ID(%lu) is invalid on this chip\n", block_id); 794215976Sjmallett return 0x0000000000000060ull; 795215976Sjmallett} 796215976Sjmallett#else 797215976Sjmallett#define CVMX_SRIOMAINTX_PRI_DEV_ID(block_id) (0x0000000000000060ull) 798215976Sjmallett#endif 799215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 800215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_CTRL(unsigned long block_id) 801215976Sjmallett{ 802215976Sjmallett if (!( 803232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 804232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 805215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_CTRL(%lu) is invalid on this chip\n", block_id); 806215976Sjmallett return 0x0000000000200064ull; 807215976Sjmallett} 808215976Sjmallett#else 809215976Sjmallett#define CVMX_SRIOMAINTX_SEC_DEV_CTRL(block_id) (0x0000000000200064ull) 810215976Sjmallett#endif 811215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 812215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_ID(unsigned long block_id) 813215976Sjmallett{ 814215976Sjmallett if (!( 815232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 816232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 817215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_ID(%lu) is invalid on this chip\n", block_id); 818215976Sjmallett return 0x0000000000200060ull; 819215976Sjmallett} 820215976Sjmallett#else 821215976Sjmallett#define CVMX_SRIOMAINTX_SEC_DEV_ID(block_id) (0x0000000000200060ull) 822215976Sjmallett#endif 823215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 824215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_SERIAL_LANE_HDR(unsigned long block_id) 825215976Sjmallett{ 826215976Sjmallett if (!( 827232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 828232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 829215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_SERIAL_LANE_HDR(%lu) is invalid on this chip\n", block_id); 830215976Sjmallett return 0x0000000000001000ull; 831215976Sjmallett} 832215976Sjmallett#else 833215976Sjmallett#define CVMX_SRIOMAINTX_SERIAL_LANE_HDR(block_id) (0x0000000000001000ull) 834215976Sjmallett#endif 835215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 836215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_SRC_OPS(unsigned long block_id) 837215976Sjmallett{ 838215976Sjmallett if (!( 839232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 840232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 841215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_SRC_OPS(%lu) is invalid on this chip\n", block_id); 842215976Sjmallett return 0x0000000000000018ull; 843215976Sjmallett} 844215976Sjmallett#else 845215976Sjmallett#define CVMX_SRIOMAINTX_SRC_OPS(block_id) (0x0000000000000018ull) 846215976Sjmallett#endif 847215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 848215976Sjmallettstatic inline uint64_t CVMX_SRIOMAINTX_TX_DROP(unsigned long block_id) 849215976Sjmallett{ 850215976Sjmallett if (!( 851232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 852232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3)))))) 853215976Sjmallett cvmx_warn("CVMX_SRIOMAINTX_TX_DROP(%lu) is invalid on this chip\n", block_id); 854215976Sjmallett return 0x000000000020006Cull; 855215976Sjmallett} 856215976Sjmallett#else 857215976Sjmallett#define CVMX_SRIOMAINTX_TX_DROP(block_id) (0x000000000020006Cull) 858215976Sjmallett#endif 859215976Sjmallett 860215976Sjmallett/** 861215976Sjmallett * cvmx_sriomaint#_asmbly_id 862215976Sjmallett * 863215976Sjmallett * SRIOMAINT_ASMBLY_ID = SRIO Assembly ID 864215976Sjmallett * 865215976Sjmallett * The Assembly ID register shows the Assembly ID and Vendor 866215976Sjmallett * 867215976Sjmallett * Notes: 868215976Sjmallett * The Assembly ID register shows the Assembly ID and Vendor specified in $SRIO_ASMBLY_ID. 869215976Sjmallett * 870232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ASMBLY_ID hclk hrst_n 871215976Sjmallett */ 872232812Sjmallettunion cvmx_sriomaintx_asmbly_id { 873215976Sjmallett uint32_t u32; 874232812Sjmallett struct cvmx_sriomaintx_asmbly_id_s { 875232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 876215976Sjmallett uint32_t assy_id : 16; /**< Assembly Identifer */ 877215976Sjmallett uint32_t assy_ven : 16; /**< Assembly Vendor Identifer */ 878215976Sjmallett#else 879215976Sjmallett uint32_t assy_ven : 16; 880215976Sjmallett uint32_t assy_id : 16; 881215976Sjmallett#endif 882215976Sjmallett } s; 883215976Sjmallett struct cvmx_sriomaintx_asmbly_id_s cn63xx; 884215976Sjmallett struct cvmx_sriomaintx_asmbly_id_s cn63xxp1; 885232812Sjmallett struct cvmx_sriomaintx_asmbly_id_s cn66xx; 886215976Sjmallett}; 887215976Sjmalletttypedef union cvmx_sriomaintx_asmbly_id cvmx_sriomaintx_asmbly_id_t; 888215976Sjmallett 889215976Sjmallett/** 890215976Sjmallett * cvmx_sriomaint#_asmbly_info 891215976Sjmallett * 892215976Sjmallett * SRIOMAINT_ASMBLY_INFO = SRIO Assembly Information 893215976Sjmallett * 894215976Sjmallett * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO 895215976Sjmallett * 896215976Sjmallett * Notes: 897215976Sjmallett * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO and Extended 898215976Sjmallett * Feature Pointer. 899215976Sjmallett * 900232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ASMBLY_INFO hclk hrst_n 901215976Sjmallett */ 902232812Sjmallettunion cvmx_sriomaintx_asmbly_info { 903215976Sjmallett uint32_t u32; 904232812Sjmallett struct cvmx_sriomaintx_asmbly_info_s { 905232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 906215976Sjmallett uint32_t assy_rev : 16; /**< Assembly Revision */ 907215976Sjmallett uint32_t ext_fptr : 16; /**< Pointer to the first entry in the extended feature 908215976Sjmallett list. */ 909215976Sjmallett#else 910215976Sjmallett uint32_t ext_fptr : 16; 911215976Sjmallett uint32_t assy_rev : 16; 912215976Sjmallett#endif 913215976Sjmallett } s; 914215976Sjmallett struct cvmx_sriomaintx_asmbly_info_s cn63xx; 915215976Sjmallett struct cvmx_sriomaintx_asmbly_info_s cn63xxp1; 916232812Sjmallett struct cvmx_sriomaintx_asmbly_info_s cn66xx; 917215976Sjmallett}; 918215976Sjmalletttypedef union cvmx_sriomaintx_asmbly_info cvmx_sriomaintx_asmbly_info_t; 919215976Sjmallett 920215976Sjmallett/** 921215976Sjmallett * cvmx_sriomaint#_bar1_idx# 922215976Sjmallett * 923215976Sjmallett * SRIOMAINT_BAR1_IDXX = SRIO BAR1 IndexX Register 924215976Sjmallett * 925215976Sjmallett * Contains address index and control bits for access to memory ranges of BAR1. 926215976Sjmallett * 927215976Sjmallett * Notes: 928215976Sjmallett * This register specifies the Octeon address, endian swap and cache status associated with each of 929215976Sjmallett * the 16 BAR1 entries. The local address bits used are based on the BARSIZE field located in the 930232812Sjmallett * SRIOMAINT(0,2..3)_M2S_BAR1_START0 register. This register is only writeable over SRIO if the 931232812Sjmallett * SRIO(0,2..3)_ACC_CTRL.DENY_BAR1 bit is zero. 932215976Sjmallett * 933232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_BAR1_IDX[0:15] hclk hrst_n 934215976Sjmallett */ 935232812Sjmallettunion cvmx_sriomaintx_bar1_idxx { 936215976Sjmallett uint32_t u32; 937232812Sjmallett struct cvmx_sriomaintx_bar1_idxx_s { 938232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 939215976Sjmallett uint32_t reserved_30_31 : 2; 940215976Sjmallett uint32_t la : 22; /**< L2/DRAM Address bits [37:16] 941215976Sjmallett Not all LA[21:0] bits are used by SRIO hardware, 942232812Sjmallett depending on SRIOMAINT(0,2..3)_M2S_BAR1_START1[BARSIZE]. 943215976Sjmallett 944215976Sjmallett Become 945215976Sjmallett L2/DRAM 946215976Sjmallett Address Entry 947215976Sjmallett BARSIZE LA Bits Used Bits Size 948215976Sjmallett 0 LA[21:0] [37:16] 64KB 949215976Sjmallett 1 LA[21:1] [37:17] 128KB 950215976Sjmallett 2 LA[21:2] [37:18] 256KB 951215976Sjmallett 3 LA[21:3] [37:19] 512KB 952215976Sjmallett 4 LA[21:4] [37:20] 1MB 953215976Sjmallett 5 LA[21:5] [37:21] 2MB 954215976Sjmallett 6 LA[21:6] [37:22] 4MB 955215976Sjmallett 7 LA[21:7] [37:23] 8MB 956232812Sjmallett 8 LA[21:8] [37:24] 16MB 957232812Sjmallett 9 LA[21:9] [37:25] 32MB 958232812Sjmallett 10 LA[21:10] [37:26] 64MB 959232812Sjmallett 11 LA[21:11] [37:27] 128MB 960232812Sjmallett 12 LA[21:12] [37:28] 256MB 961232812Sjmallett 13 LA[21:13] [37:29] 512MB */ 962215976Sjmallett uint32_t reserved_6_7 : 2; 963215976Sjmallett uint32_t es : 2; /**< Endian Swap Mode. 964215976Sjmallett 0 = No Swap 965215976Sjmallett 1 = 64-bit Swap Bytes [ABCD_EFGH] -> [HGFE_DCBA] 966215976Sjmallett 2 = 32-bit Swap Words [ABCD_EFGH] -> [DCBA_HGFE] 967215976Sjmallett 3 = 32-bit Word Exch [ABCD_EFGH] -> [EFGH_ABCD] */ 968215976Sjmallett uint32_t nca : 1; /**< Non-Cacheable Access Mode. When set, transfers 969215976Sjmallett through this window are not cacheable. */ 970215976Sjmallett uint32_t reserved_1_2 : 2; 971215976Sjmallett uint32_t enable : 1; /**< When set the selected index address is valid. */ 972215976Sjmallett#else 973215976Sjmallett uint32_t enable : 1; 974215976Sjmallett uint32_t reserved_1_2 : 2; 975215976Sjmallett uint32_t nca : 1; 976215976Sjmallett uint32_t es : 2; 977215976Sjmallett uint32_t reserved_6_7 : 2; 978215976Sjmallett uint32_t la : 22; 979215976Sjmallett uint32_t reserved_30_31 : 2; 980215976Sjmallett#endif 981215976Sjmallett } s; 982215976Sjmallett struct cvmx_sriomaintx_bar1_idxx_s cn63xx; 983215976Sjmallett struct cvmx_sriomaintx_bar1_idxx_s cn63xxp1; 984232812Sjmallett struct cvmx_sriomaintx_bar1_idxx_s cn66xx; 985215976Sjmallett}; 986215976Sjmalletttypedef union cvmx_sriomaintx_bar1_idxx cvmx_sriomaintx_bar1_idxx_t; 987215976Sjmallett 988215976Sjmallett/** 989215976Sjmallett * cvmx_sriomaint#_bell_status 990215976Sjmallett * 991215976Sjmallett * SRIOMAINT_BELL_STATUS = SRIO Incoming Doorbell Status 992215976Sjmallett * 993215976Sjmallett * The SRIO Incoming (RX) Doorbell Status 994215976Sjmallett * 995215976Sjmallett * Notes: 996215976Sjmallett * This register displays the status of the doorbells received. If FULL is set the SRIO device will 997215976Sjmallett * retry incoming transactions. 998215976Sjmallett * 999232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_BELL_STATUS hclk hrst_n 1000215976Sjmallett */ 1001232812Sjmallettunion cvmx_sriomaintx_bell_status { 1002215976Sjmallett uint32_t u32; 1003232812Sjmallett struct cvmx_sriomaintx_bell_status_s { 1004232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1005215976Sjmallett uint32_t reserved_1_31 : 31; 1006215976Sjmallett uint32_t full : 1; /**< Not able to receive Doorbell Transactions */ 1007215976Sjmallett#else 1008215976Sjmallett uint32_t full : 1; 1009215976Sjmallett uint32_t reserved_1_31 : 31; 1010215976Sjmallett#endif 1011215976Sjmallett } s; 1012215976Sjmallett struct cvmx_sriomaintx_bell_status_s cn63xx; 1013215976Sjmallett struct cvmx_sriomaintx_bell_status_s cn63xxp1; 1014232812Sjmallett struct cvmx_sriomaintx_bell_status_s cn66xx; 1015215976Sjmallett}; 1016215976Sjmalletttypedef union cvmx_sriomaintx_bell_status cvmx_sriomaintx_bell_status_t; 1017215976Sjmallett 1018215976Sjmallett/** 1019215976Sjmallett * cvmx_sriomaint#_comp_tag 1020215976Sjmallett * 1021215976Sjmallett * SRIOMAINT_COMP_TAG = SRIO Component Tag 1022215976Sjmallett * 1023215976Sjmallett * Component Tag 1024215976Sjmallett * 1025215976Sjmallett * Notes: 1026215976Sjmallett * This register contains a component tag value for the processing element and the value can be 1027215976Sjmallett * assigned by software when the device is initialized. 1028215976Sjmallett * 1029232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_COMP_TAG hclk hrst_n 1030215976Sjmallett */ 1031232812Sjmallettunion cvmx_sriomaintx_comp_tag { 1032215976Sjmallett uint32_t u32; 1033232812Sjmallett struct cvmx_sriomaintx_comp_tag_s { 1034232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1035215976Sjmallett uint32_t comp_tag : 32; /**< Component Tag for Firmware Use */ 1036215976Sjmallett#else 1037215976Sjmallett uint32_t comp_tag : 32; 1038215976Sjmallett#endif 1039215976Sjmallett } s; 1040215976Sjmallett struct cvmx_sriomaintx_comp_tag_s cn63xx; 1041215976Sjmallett struct cvmx_sriomaintx_comp_tag_s cn63xxp1; 1042232812Sjmallett struct cvmx_sriomaintx_comp_tag_s cn66xx; 1043215976Sjmallett}; 1044215976Sjmalletttypedef union cvmx_sriomaintx_comp_tag cvmx_sriomaintx_comp_tag_t; 1045215976Sjmallett 1046215976Sjmallett/** 1047215976Sjmallett * cvmx_sriomaint#_core_enables 1048215976Sjmallett * 1049215976Sjmallett * SRIOMAINT_CORE_ENABLES = SRIO Core Control 1050215976Sjmallett * 1051215976Sjmallett * Core Control 1052215976Sjmallett * 1053215976Sjmallett * Notes: 1054215976Sjmallett * This register displays the reset state of the Octeon Core Logic while the SRIO Link is running. 1055215976Sjmallett * The bit should be set after the software has initialized the chip to allow memory operations. 1056215976Sjmallett * 1057232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_CORE_ENABLES hclk hrst_n, srst_n 1058215976Sjmallett */ 1059232812Sjmallettunion cvmx_sriomaintx_core_enables { 1060215976Sjmallett uint32_t u32; 1061232812Sjmallett struct cvmx_sriomaintx_core_enables_s { 1062232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1063215976Sjmallett uint32_t reserved_5_31 : 27; 1064215976Sjmallett uint32_t halt : 1; /**< OCTEON currently in Reset 1065215976Sjmallett 0 = All OCTEON resources are available. 1066215976Sjmallett 1 = The OCTEON is in reset. When this bit is set, 1067215976Sjmallett SRIO maintenance registers can be accessed, 1068215976Sjmallett but BAR0, BAR1, and BAR2 cannot be. */ 1069215976Sjmallett uint32_t imsg1 : 1; /**< Allow Incoming Message Unit 1 Operations 1070215976Sjmallett Note: This bit is cleared when the C63XX is reset 1071215976Sjmallett 0 = SRIO Incoming Messages to Unit 1 ignored and 1072215976Sjmallett return error response 1073215976Sjmallett 1 = SRIO Incoming Messages to Unit 1 */ 1074215976Sjmallett uint32_t imsg0 : 1; /**< Allow Incoming Message Unit 0 Operations 1075215976Sjmallett Note: This bit is cleared when the C63XX is reset 1076215976Sjmallett 0 = SRIO Incoming Messages to Unit 0 ignored and 1077215976Sjmallett return error response 1078215976Sjmallett 1 = SRIO Incoming Messages to Unit 0 */ 1079215976Sjmallett uint32_t doorbell : 1; /**< Allow Inbound Doorbell Operations 1080215976Sjmallett Note: This bit is cleared when the C63XX is reset 1081215976Sjmallett 0 = SRIO Doorbell OPs ignored and return error 1082215976Sjmallett response 1083215976Sjmallett 1 = SRIO Doorbell OPs Allowed */ 1084215976Sjmallett uint32_t memory : 1; /**< Allow Inbound/Outbound Memory Operations 1085215976Sjmallett Note: This bit is cleared when the C63XX is reset 1086215976Sjmallett 0 = SRIO Incoming Nwrites and Swrites are 1087215976Sjmallett dropped. Incoming Nreads, Atomics and 1088215976Sjmallett NwriteRs return responses with ERROR status. 1089215976Sjmallett SRIO Incoming Maintenance BAR Memory Accesses 1090215976Sjmallett are processed normally. 1091215976Sjmallett Outgoing Store Operations are Dropped 1092215976Sjmallett Outgoing Load Operations are not issued and 1093215976Sjmallett return all 1's with an ERROR status. 1094215976Sjmallett In Flight Operations started while the bit is 1095215976Sjmallett set in both directions will complete normally. 1096215976Sjmallett 1 = SRIO Memory Read/Write OPs Allowed */ 1097215976Sjmallett#else 1098215976Sjmallett uint32_t memory : 1; 1099215976Sjmallett uint32_t doorbell : 1; 1100215976Sjmallett uint32_t imsg0 : 1; 1101215976Sjmallett uint32_t imsg1 : 1; 1102215976Sjmallett uint32_t halt : 1; 1103215976Sjmallett uint32_t reserved_5_31 : 27; 1104215976Sjmallett#endif 1105215976Sjmallett } s; 1106215976Sjmallett struct cvmx_sriomaintx_core_enables_s cn63xx; 1107215976Sjmallett struct cvmx_sriomaintx_core_enables_s cn63xxp1; 1108232812Sjmallett struct cvmx_sriomaintx_core_enables_s cn66xx; 1109215976Sjmallett}; 1110215976Sjmalletttypedef union cvmx_sriomaintx_core_enables cvmx_sriomaintx_core_enables_t; 1111215976Sjmallett 1112215976Sjmallett/** 1113215976Sjmallett * cvmx_sriomaint#_dev_id 1114215976Sjmallett * 1115215976Sjmallett * SRIOMAINT_DEV_ID = SRIO Device ID 1116215976Sjmallett * 1117215976Sjmallett * The DeviceVendor Identity field identifies the vendor that manufactured the device 1118215976Sjmallett * 1119215976Sjmallett * Notes: 1120232812Sjmallett * This register identifies Cavium Inc. and the Product ID. 1121215976Sjmallett * 1122232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_DEV_ID hclk hrst_n 1123215976Sjmallett */ 1124232812Sjmallettunion cvmx_sriomaintx_dev_id { 1125215976Sjmallett uint32_t u32; 1126232812Sjmallett struct cvmx_sriomaintx_dev_id_s { 1127232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1128215976Sjmallett uint32_t device : 16; /**< Product Identity */ 1129215976Sjmallett uint32_t vendor : 16; /**< Cavium Vendor Identity */ 1130215976Sjmallett#else 1131215976Sjmallett uint32_t vendor : 16; 1132215976Sjmallett uint32_t device : 16; 1133215976Sjmallett#endif 1134215976Sjmallett } s; 1135215976Sjmallett struct cvmx_sriomaintx_dev_id_s cn63xx; 1136215976Sjmallett struct cvmx_sriomaintx_dev_id_s cn63xxp1; 1137232812Sjmallett struct cvmx_sriomaintx_dev_id_s cn66xx; 1138215976Sjmallett}; 1139215976Sjmalletttypedef union cvmx_sriomaintx_dev_id cvmx_sriomaintx_dev_id_t; 1140215976Sjmallett 1141215976Sjmallett/** 1142215976Sjmallett * cvmx_sriomaint#_dev_rev 1143215976Sjmallett * 1144215976Sjmallett * SRIOMAINT_DEV_REV = SRIO Device Revision 1145215976Sjmallett * 1146215976Sjmallett * The Device Revision register identifies the chip pass and revision 1147215976Sjmallett * 1148215976Sjmallett * Notes: 1149215976Sjmallett * This register identifies the chip pass and revision derived from the fuses. 1150215976Sjmallett * 1151232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_DEV_REV hclk hrst_n 1152215976Sjmallett */ 1153232812Sjmallettunion cvmx_sriomaintx_dev_rev { 1154215976Sjmallett uint32_t u32; 1155232812Sjmallett struct cvmx_sriomaintx_dev_rev_s { 1156232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1157215976Sjmallett uint32_t reserved_8_31 : 24; 1158215976Sjmallett uint32_t revision : 8; /**< Chip Pass/Revision */ 1159215976Sjmallett#else 1160215976Sjmallett uint32_t revision : 8; 1161215976Sjmallett uint32_t reserved_8_31 : 24; 1162215976Sjmallett#endif 1163215976Sjmallett } s; 1164215976Sjmallett struct cvmx_sriomaintx_dev_rev_s cn63xx; 1165215976Sjmallett struct cvmx_sriomaintx_dev_rev_s cn63xxp1; 1166232812Sjmallett struct cvmx_sriomaintx_dev_rev_s cn66xx; 1167215976Sjmallett}; 1168215976Sjmalletttypedef union cvmx_sriomaintx_dev_rev cvmx_sriomaintx_dev_rev_t; 1169215976Sjmallett 1170215976Sjmallett/** 1171215976Sjmallett * cvmx_sriomaint#_dst_ops 1172215976Sjmallett * 1173215976Sjmallett * SRIOMAINT_DST_OPS = SRIO Source Operations 1174215976Sjmallett * 1175215976Sjmallett * The logical operations supported from external devices. 1176215976Sjmallett * 1177215976Sjmallett * Notes: 1178215976Sjmallett * The logical operations supported from external devices. The Destination OPs register shows the 1179232812Sjmallett * operations specified in the SRIO(0,2..3)_IP_FEATURE.OPS register. 1180215976Sjmallett * 1181232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_DST_OPS hclk hrst_n 1182215976Sjmallett */ 1183232812Sjmallettunion cvmx_sriomaintx_dst_ops { 1184215976Sjmallett uint32_t u32; 1185232812Sjmallett struct cvmx_sriomaintx_dst_ops_s { 1186232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1187215976Sjmallett uint32_t gsm_read : 1; /**< PE does not support Read Home operations. 1188215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */ 1189215976Sjmallett uint32_t i_read : 1; /**< PE does not support Instruction Read. 1190215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<30>] */ 1191215976Sjmallett uint32_t rd_own : 1; /**< PE does not support Read for Ownership. 1192215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<29>] */ 1193215976Sjmallett uint32_t d_invald : 1; /**< PE does not support Data Cache Invalidate. 1194215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<28>] */ 1195215976Sjmallett uint32_t castout : 1; /**< PE does not support Castout Operations. 1196215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<27>] */ 1197215976Sjmallett uint32_t d_flush : 1; /**< PE does not support Data Cache Flush. 1198215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<26>] */ 1199215976Sjmallett uint32_t io_read : 1; /**< PE does not support IO Read. 1200215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<25>] */ 1201215976Sjmallett uint32_t i_invald : 1; /**< PE does not support Instruction Cache Invalidate. 1202215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<24>] */ 1203215976Sjmallett uint32_t tlb_inv : 1; /**< PE does not support TLB Entry Invalidate. 1204215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<23>] */ 1205215976Sjmallett uint32_t tlb_invs : 1; /**< PE does not support TLB Entry Invalidate Sync. 1206215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<22>] */ 1207215976Sjmallett uint32_t reserved_16_21 : 6; 1208215976Sjmallett uint32_t read : 1; /**< PE can support Nread operations. 1209215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<15>] */ 1210215976Sjmallett uint32_t write : 1; /**< PE can support Nwrite operations. 1211215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<14>] */ 1212215976Sjmallett uint32_t swrite : 1; /**< PE can support Swrite operations. 1213215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<13>] */ 1214215976Sjmallett uint32_t write_r : 1; /**< PE can support Write with Response operations. 1215215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<12>] */ 1216215976Sjmallett uint32_t msg : 1; /**< PE can support Data Message operations. 1217215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<11>] */ 1218215976Sjmallett uint32_t doorbell : 1; /**< PE can support Doorbell operations. 1219215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<10>] */ 1220215976Sjmallett uint32_t compswap : 1; /**< PE does not support Atomic Compare and Swap. 1221215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<9>] */ 1222215976Sjmallett uint32_t testswap : 1; /**< PE does not support Atomic Test and Swap. 1223215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<8>] */ 1224215976Sjmallett uint32_t atom_inc : 1; /**< PE can support Atomic increment operations. 1225215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<7>] */ 1226215976Sjmallett uint32_t atom_dec : 1; /**< PE can support Atomic decrement operations. 1227215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<6>] */ 1228215976Sjmallett uint32_t atom_set : 1; /**< PE can support Atomic set operations. 1229215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<5>] */ 1230215976Sjmallett uint32_t atom_clr : 1; /**< PE can support Atomic clear operations. 1231215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<4>] */ 1232215976Sjmallett uint32_t atom_swp : 1; /**< PE does not support Atomic Swap. 1233215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<3>] */ 1234215976Sjmallett uint32_t port_wr : 1; /**< PE can Port Write operations. 1235215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<2>] */ 1236215976Sjmallett uint32_t reserved_0_1 : 2; 1237215976Sjmallett#else 1238215976Sjmallett uint32_t reserved_0_1 : 2; 1239215976Sjmallett uint32_t port_wr : 1; 1240215976Sjmallett uint32_t atom_swp : 1; 1241215976Sjmallett uint32_t atom_clr : 1; 1242215976Sjmallett uint32_t atom_set : 1; 1243215976Sjmallett uint32_t atom_dec : 1; 1244215976Sjmallett uint32_t atom_inc : 1; 1245215976Sjmallett uint32_t testswap : 1; 1246215976Sjmallett uint32_t compswap : 1; 1247215976Sjmallett uint32_t doorbell : 1; 1248215976Sjmallett uint32_t msg : 1; 1249215976Sjmallett uint32_t write_r : 1; 1250215976Sjmallett uint32_t swrite : 1; 1251215976Sjmallett uint32_t write : 1; 1252215976Sjmallett uint32_t read : 1; 1253215976Sjmallett uint32_t reserved_16_21 : 6; 1254215976Sjmallett uint32_t tlb_invs : 1; 1255215976Sjmallett uint32_t tlb_inv : 1; 1256215976Sjmallett uint32_t i_invald : 1; 1257215976Sjmallett uint32_t io_read : 1; 1258215976Sjmallett uint32_t d_flush : 1; 1259215976Sjmallett uint32_t castout : 1; 1260215976Sjmallett uint32_t d_invald : 1; 1261215976Sjmallett uint32_t rd_own : 1; 1262215976Sjmallett uint32_t i_read : 1; 1263215976Sjmallett uint32_t gsm_read : 1; 1264215976Sjmallett#endif 1265215976Sjmallett } s; 1266215976Sjmallett struct cvmx_sriomaintx_dst_ops_s cn63xx; 1267215976Sjmallett struct cvmx_sriomaintx_dst_ops_s cn63xxp1; 1268232812Sjmallett struct cvmx_sriomaintx_dst_ops_s cn66xx; 1269215976Sjmallett}; 1270215976Sjmalletttypedef union cvmx_sriomaintx_dst_ops cvmx_sriomaintx_dst_ops_t; 1271215976Sjmallett 1272215976Sjmallett/** 1273215976Sjmallett * cvmx_sriomaint#_erb_attr_capt 1274215976Sjmallett * 1275215976Sjmallett * SRIOMAINT_ERB_ATTR_CAPT = SRIO Attributes Capture 1276215976Sjmallett * 1277215976Sjmallett * Attributes Capture 1278215976Sjmallett * 1279215976Sjmallett * Notes: 1280215976Sjmallett * This register contains the information captured during the error. 1281215976Sjmallett * The HW will not update this register (i.e. this register is locked) while 1282215976Sjmallett * VALID is set in this CSR. 1283215976Sjmallett * The HW sets SRIO_INT_REG[PHY_ERB] every time it sets VALID in this CSR. 1284215976Sjmallett * To handle the interrupt, the following procedure may be best: 1285215976Sjmallett * (1) clear SRIO_INT_REG[PHY_ERB], 1286215976Sjmallett * (2) read this CSR, corresponding SRIOMAINT*_ERB_ERR_DET, SRIOMAINT*_ERB_PACK_SYM_CAPT, 1287215976Sjmallett * SRIOMAINT*_ERB_PACK_CAPT_1, SRIOMAINT*_ERB_PACK_CAPT_2, and SRIOMAINT*_ERB_PACK_CAPT_3 1288215976Sjmallett * (3) Write VALID in this CSR to 0. 1289215976Sjmallett * 1290232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ATTR_CAPT hclk hrst_n 1291215976Sjmallett */ 1292232812Sjmallettunion cvmx_sriomaintx_erb_attr_capt { 1293215976Sjmallett uint32_t u32; 1294232812Sjmallett struct cvmx_sriomaintx_erb_attr_capt_s { 1295232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1296215976Sjmallett uint32_t inf_type : 3; /**< Type of Information Logged. 1297215976Sjmallett 000 - Packet 1298215976Sjmallett 010 - Short Control Symbol 1299215976Sjmallett (use only first capture register) 1300232812Sjmallett 100 - Implementation Specific Error Reporting 1301215976Sjmallett All Others Reserved */ 1302215976Sjmallett uint32_t err_type : 5; /**< The encoded value of the 31 minus the bit in 1303232812Sjmallett SRIOMAINT(0,2..3)_ERB_ERR_DET that describes the error 1304232812Sjmallett captured in SRIOMAINT(0,2..3)_ERB_*CAPT Registers. 1305215976Sjmallett (For example a value of 5 indicates 31-5 = bit 26) */ 1306232812Sjmallett uint32_t err_info : 20; /**< Error Info. 1307215976Sjmallett ERR_TYPE Bits Description 1308215976Sjmallett 0 23 TX Protocol Error 1309215976Sjmallett 22 RX Protocol Error 1310215976Sjmallett 21 TX Link Response Timeout 1311215976Sjmallett 20 TX ACKID Timeout 1312215976Sjmallett - 19:16 Reserved 1313215976Sjmallett - 15:12 TX Protocol ID 1314215976Sjmallett 1 = Rcvd Unexpected Link Response 1315215976Sjmallett 2 = Rcvd Link Response before Req 1316215976Sjmallett 3 = Rcvd NACK servicing NACK 1317215976Sjmallett 4 = Rcvd NACK 1318215976Sjmallett 5 = Rcvd RETRY servicing RETRY 1319215976Sjmallett 6 = Rcvd RETRY servicing NACK 1320215976Sjmallett 7 = Rcvd ACK servicing RETRY 1321215976Sjmallett 8 = Rcvd ACK servicing NACK 1322215976Sjmallett 9 = Unexp ACKID on ACK or RETRY 1323215976Sjmallett 10 = Unexp ACK or RETRY 1324215976Sjmallett - 11:8 Reserved 1325215976Sjmallett - 7:4 RX Protocol ID 1326215976Sjmallett 1 = Rcvd EOP w/o Prev SOP 1327215976Sjmallett 2 = Rcvd STOMP w/o Prev SOP 1328215976Sjmallett 3 = Unexp RESTART 1329215976Sjmallett 4 = Redundant Status from LinkReq 1330215976Sjmallett 9-16 23:20 RX K Bits 1331215976Sjmallett - 19:0 Reserved 1332215976Sjmallett 26 23:20 RX K Bits 1333215976Sjmallett - 19:0 Reserved 1334215976Sjmallett 27 23:12 Type 1335215976Sjmallett 0x000 TX 1336215976Sjmallett 0x010 RX 1337215976Sjmallett - 11:8 RX or TX Protocol ID (see above) 1338215976Sjmallett - 7:4 Reserved 1339215976Sjmallett 30 23:20 RX K Bits 1340215976Sjmallett - 19:0 Reserved 1341215976Sjmallett 31 23:16 ACKID Timeout 0x2 1342215976Sjmallett - 15:14 Reserved 1343215976Sjmallett - 13:8 AckID 1344215976Sjmallett - 7:4 Reserved 1345215976Sjmallett All others ERR_TYPEs are reserved. */ 1346215976Sjmallett uint32_t reserved_1_3 : 3; 1347215976Sjmallett uint32_t valid : 1; /**< This bit is set by hardware to indicate that the 1348215976Sjmallett Packet/control symbol capture registers contain 1349215976Sjmallett valid information. For control symbols, only 1350215976Sjmallett capture register 0 will contain meaningful 1351215976Sjmallett information. This bit must be cleared by software 1352215976Sjmallett to allow capture of other errors. */ 1353215976Sjmallett#else 1354215976Sjmallett uint32_t valid : 1; 1355215976Sjmallett uint32_t reserved_1_3 : 3; 1356215976Sjmallett uint32_t err_info : 20; 1357215976Sjmallett uint32_t err_type : 5; 1358215976Sjmallett uint32_t inf_type : 3; 1359215976Sjmallett#endif 1360215976Sjmallett } s; 1361215976Sjmallett struct cvmx_sriomaintx_erb_attr_capt_s cn63xx; 1362232812Sjmallett struct cvmx_sriomaintx_erb_attr_capt_cn63xxp1 { 1363232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1364215976Sjmallett uint32_t inf_type : 3; /**< Type of Information Logged. 1365215976Sjmallett 000 - Packet 1366215976Sjmallett 010 - Short Control Symbol 1367215976Sjmallett (use only first capture register) 1368215976Sjmallett All Others Reserved */ 1369215976Sjmallett uint32_t err_type : 5; /**< The encoded value of the 31 minus the bit in 1370215976Sjmallett SRIOMAINT(0..1)_ERB_ERR_DET that describes the error 1371215976Sjmallett captured in SRIOMAINT(0..1)_ERB_*CAPT Registers. 1372215976Sjmallett (For example a value of 5 indicates 31-5 = bit 26) */ 1373215976Sjmallett uint32_t reserved_1_23 : 23; 1374215976Sjmallett uint32_t valid : 1; /**< This bit is set by hardware to indicate that the 1375215976Sjmallett Packet/control symbol capture registers contain 1376215976Sjmallett valid information. For control symbols, only 1377215976Sjmallett capture register 0 will contain meaningful 1378215976Sjmallett information. This bit must be cleared by software 1379215976Sjmallett to allow capture of other errors. */ 1380215976Sjmallett#else 1381215976Sjmallett uint32_t valid : 1; 1382215976Sjmallett uint32_t reserved_1_23 : 23; 1383215976Sjmallett uint32_t err_type : 5; 1384215976Sjmallett uint32_t inf_type : 3; 1385215976Sjmallett#endif 1386215976Sjmallett } cn63xxp1; 1387232812Sjmallett struct cvmx_sriomaintx_erb_attr_capt_s cn66xx; 1388215976Sjmallett}; 1389215976Sjmalletttypedef union cvmx_sriomaintx_erb_attr_capt cvmx_sriomaintx_erb_attr_capt_t; 1390215976Sjmallett 1391215976Sjmallett/** 1392215976Sjmallett * cvmx_sriomaint#_erb_err_det 1393215976Sjmallett * 1394215976Sjmallett * SRIOMAINT_ERB_ERR_DET = SRIO Error Detect 1395215976Sjmallett * 1396215976Sjmallett * Error Detect 1397215976Sjmallett * 1398215976Sjmallett * Notes: 1399215976Sjmallett * The Error Detect Register indicates physical layer transmission errors detected by the hardware. 1400215976Sjmallett * The HW will not update this register (i.e. this register is locked) while 1401215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. 1402215976Sjmallett * 1403232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_DET hclk hrst_n 1404215976Sjmallett */ 1405232812Sjmallettunion cvmx_sriomaintx_erb_err_det { 1406215976Sjmallett uint32_t u32; 1407232812Sjmallett struct cvmx_sriomaintx_erb_err_det_s { 1408232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1409232812Sjmallett uint32_t imp_err : 1; /**< Implementation Specific Error. */ 1410215976Sjmallett uint32_t reserved_23_30 : 8; 1411215976Sjmallett uint32_t ctl_crc : 1; /**< Received a control symbol with a bad CRC value 1412232812Sjmallett Complete Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1413215976Sjmallett uint32_t uns_id : 1; /**< Received an acknowledge control symbol with an 1414215976Sjmallett unexpected ackID (packet-accepted or packet_retry) 1415232812Sjmallett Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1416215976Sjmallett uint32_t nack : 1; /**< Received packet-not-accepted acknowledge control 1417215976Sjmallett symbols. 1418232812Sjmallett Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1419215976Sjmallett uint32_t out_ack : 1; /**< Received packet with unexpected ackID value 1420232812Sjmallett Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1421215976Sjmallett uint32_t pkt_crc : 1; /**< Received a packet with a bad CRC value 1422232812Sjmallett Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1423215976Sjmallett uint32_t size : 1; /**< Received packet which exceeds the maximum allowed 1424215976Sjmallett size of 276 bytes. 1425232812Sjmallett Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1426215976Sjmallett uint32_t inv_char : 1; /**< Received illegal, 8B/10B error or undefined 1427232812Sjmallett codegroup within a packet. 1428232812Sjmallett Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1429215976Sjmallett uint32_t inv_data : 1; /**< Received data codegroup or 8B/10B error within an 1430232812Sjmallett IDLE sequence. 1431232812Sjmallett Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1432215976Sjmallett uint32_t reserved_6_14 : 9; 1433215976Sjmallett uint32_t bad_ack : 1; /**< Link_response received with an ackID that is not 1434215976Sjmallett outstanding. 1435232812Sjmallett Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1436215976Sjmallett uint32_t proterr : 1; /**< An unexpected packet or control symbol was 1437215976Sjmallett received. 1438232812Sjmallett Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1439215976Sjmallett uint32_t f_toggle : 1; /**< Reserved. */ 1440215976Sjmallett uint32_t del_err : 1; /**< Received illegal or undefined codegroup. 1441232812Sjmallett (either INV_DATA or INV_CHAR) 1442232812Sjmallett Complete Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1443215976Sjmallett uint32_t uns_ack : 1; /**< An unexpected acknowledge control symbol was 1444215976Sjmallett received. 1445232812Sjmallett Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1446215976Sjmallett uint32_t lnk_tout : 1; /**< An acknowledge or link-response control symbol is 1447215976Sjmallett not received within the specified timeout interval 1448232812Sjmallett Partial Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */ 1449215976Sjmallett#else 1450215976Sjmallett uint32_t lnk_tout : 1; 1451215976Sjmallett uint32_t uns_ack : 1; 1452215976Sjmallett uint32_t del_err : 1; 1453215976Sjmallett uint32_t f_toggle : 1; 1454215976Sjmallett uint32_t proterr : 1; 1455215976Sjmallett uint32_t bad_ack : 1; 1456215976Sjmallett uint32_t reserved_6_14 : 9; 1457215976Sjmallett uint32_t inv_data : 1; 1458215976Sjmallett uint32_t inv_char : 1; 1459215976Sjmallett uint32_t size : 1; 1460215976Sjmallett uint32_t pkt_crc : 1; 1461215976Sjmallett uint32_t out_ack : 1; 1462215976Sjmallett uint32_t nack : 1; 1463215976Sjmallett uint32_t uns_id : 1; 1464215976Sjmallett uint32_t ctl_crc : 1; 1465215976Sjmallett uint32_t reserved_23_30 : 8; 1466215976Sjmallett uint32_t imp_err : 1; 1467215976Sjmallett#endif 1468215976Sjmallett } s; 1469215976Sjmallett struct cvmx_sriomaintx_erb_err_det_s cn63xx; 1470232812Sjmallett struct cvmx_sriomaintx_erb_err_det_cn63xxp1 { 1471232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1472215976Sjmallett uint32_t reserved_23_31 : 9; 1473215976Sjmallett uint32_t ctl_crc : 1; /**< Received a control symbol with a bad CRC value 1474215976Sjmallett Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1475215976Sjmallett uint32_t uns_id : 1; /**< Received an acknowledge control symbol with an 1476215976Sjmallett unexpected ackID (packet-accepted or packet_retry) 1477215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1478215976Sjmallett uint32_t nack : 1; /**< Received packet-not-accepted acknowledge control 1479215976Sjmallett symbols. 1480215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1481215976Sjmallett uint32_t out_ack : 1; /**< Received packet with unexpected ackID value 1482215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1483215976Sjmallett uint32_t pkt_crc : 1; /**< Received a packet with a bad CRC value 1484215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1485215976Sjmallett uint32_t size : 1; /**< Received packet which exceeds the maximum allowed 1486215976Sjmallett size of 276 bytes. 1487215976Sjmallett Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1488215976Sjmallett uint32_t reserved_6_16 : 11; 1489215976Sjmallett uint32_t bad_ack : 1; /**< Link_response received with an ackID that is not 1490215976Sjmallett outstanding. 1491215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1492215976Sjmallett uint32_t proterr : 1; /**< An unexpected packet or control symbol was 1493215976Sjmallett received. 1494215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1495215976Sjmallett uint32_t f_toggle : 1; /**< Reserved. */ 1496215976Sjmallett uint32_t del_err : 1; /**< Received illegal or undefined codegroup. 1497215976Sjmallett (either INV_DATA or INV_CHAR) (Pass 2) 1498215976Sjmallett Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1499215976Sjmallett uint32_t uns_ack : 1; /**< An unexpected acknowledge control symbol was 1500215976Sjmallett received. 1501215976Sjmallett Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1502215976Sjmallett uint32_t lnk_tout : 1; /**< An acknowledge or link-response control symbol is 1503215976Sjmallett not received within the specified timeout interval 1504215976Sjmallett Partial Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */ 1505215976Sjmallett#else 1506215976Sjmallett uint32_t lnk_tout : 1; 1507215976Sjmallett uint32_t uns_ack : 1; 1508215976Sjmallett uint32_t del_err : 1; 1509215976Sjmallett uint32_t f_toggle : 1; 1510215976Sjmallett uint32_t proterr : 1; 1511215976Sjmallett uint32_t bad_ack : 1; 1512215976Sjmallett uint32_t reserved_6_16 : 11; 1513215976Sjmallett uint32_t size : 1; 1514215976Sjmallett uint32_t pkt_crc : 1; 1515215976Sjmallett uint32_t out_ack : 1; 1516215976Sjmallett uint32_t nack : 1; 1517215976Sjmallett uint32_t uns_id : 1; 1518215976Sjmallett uint32_t ctl_crc : 1; 1519215976Sjmallett uint32_t reserved_23_31 : 9; 1520215976Sjmallett#endif 1521215976Sjmallett } cn63xxp1; 1522232812Sjmallett struct cvmx_sriomaintx_erb_err_det_s cn66xx; 1523215976Sjmallett}; 1524215976Sjmalletttypedef union cvmx_sriomaintx_erb_err_det cvmx_sriomaintx_erb_err_det_t; 1525215976Sjmallett 1526215976Sjmallett/** 1527215976Sjmallett * cvmx_sriomaint#_erb_err_rate 1528215976Sjmallett * 1529215976Sjmallett * SRIOMAINT_ERB_ERR_RATE = SRIO Error Rate 1530215976Sjmallett * 1531215976Sjmallett * Error Rate 1532215976Sjmallett * 1533215976Sjmallett * Notes: 1534215976Sjmallett * The Error Rate register is used with the Error Rate Threshold register to monitor and control the 1535215976Sjmallett * reporting of transmission errors. 1536215976Sjmallett * 1537232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_RATE hclk hrst_n 1538215976Sjmallett */ 1539232812Sjmallettunion cvmx_sriomaintx_erb_err_rate { 1540215976Sjmallett uint32_t u32; 1541232812Sjmallett struct cvmx_sriomaintx_erb_err_rate_s { 1542232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1543215976Sjmallett uint32_t err_bias : 8; /**< These bits provide the error rate bias value. 1544215976Sjmallett 0x00 - do not decrement the error rate counter 1545215976Sjmallett 0x01 - decrement every 1ms (+/-34%) 1546215976Sjmallett 0x02 - decrement every 10ms (+/-34%) 1547215976Sjmallett 0x04 - decrement every 100ms (+/-34%) 1548215976Sjmallett 0x08 - decrement every 1s (+/-34%) 1549215976Sjmallett 0x10 - decrement every 10s (+/-34%) 1550215976Sjmallett 0x20 - decrement every 100s (+/-34%) 1551215976Sjmallett 0x40 - decrement every 1000s (+/-34%) 1552215976Sjmallett 0x80 - decrement every 10000s (+/-34%) 1553215976Sjmallett All other values are reserved */ 1554215976Sjmallett uint32_t reserved_18_23 : 6; 1555215976Sjmallett uint32_t rate_lim : 2; /**< These bits limit the incrementing of the error 1556215976Sjmallett rate counter above the failed threshold trigger. 1557215976Sjmallett 00 - only count 2 errors above 1558215976Sjmallett 01 - only count 4 errors above 1559215976Sjmallett 10 - only count 16 error above 1560215976Sjmallett 11 - do not limit incrementing the error rate ct */ 1561215976Sjmallett uint32_t pk_rate : 8; /**< Peak Value attainted by the error rate counter */ 1562215976Sjmallett uint32_t rate_cnt : 8; /**< These bits maintain a count of the number of 1563215976Sjmallett transmission errors that have been detected by the 1564215976Sjmallett port, decremented by the Error Rate Bias 1565215976Sjmallett mechanism, to create an indication of the link 1566215976Sjmallett error rate. */ 1567215976Sjmallett#else 1568215976Sjmallett uint32_t rate_cnt : 8; 1569215976Sjmallett uint32_t pk_rate : 8; 1570215976Sjmallett uint32_t rate_lim : 2; 1571215976Sjmallett uint32_t reserved_18_23 : 6; 1572215976Sjmallett uint32_t err_bias : 8; 1573215976Sjmallett#endif 1574215976Sjmallett } s; 1575215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_s cn63xx; 1576215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_s cn63xxp1; 1577232812Sjmallett struct cvmx_sriomaintx_erb_err_rate_s cn66xx; 1578215976Sjmallett}; 1579215976Sjmalletttypedef union cvmx_sriomaintx_erb_err_rate cvmx_sriomaintx_erb_err_rate_t; 1580215976Sjmallett 1581215976Sjmallett/** 1582215976Sjmallett * cvmx_sriomaint#_erb_err_rate_en 1583215976Sjmallett * 1584215976Sjmallett * SRIOMAINT_ERB_ERR_RATE_EN = SRIO Error Rate Enable 1585215976Sjmallett * 1586215976Sjmallett * Error Rate Enable 1587215976Sjmallett * 1588215976Sjmallett * Notes: 1589215976Sjmallett * This register contains the bits that control when an error condition is allowed to increment the 1590215976Sjmallett * error rate counter in the Error Rate Threshold Register and lock the Error Capture registers. 1591215976Sjmallett * 1592232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_RATE_EN hclk hrst_n 1593215976Sjmallett */ 1594232812Sjmallettunion cvmx_sriomaintx_erb_err_rate_en { 1595215976Sjmallett uint32_t u32; 1596232812Sjmallett struct cvmx_sriomaintx_erb_err_rate_en_s { 1597232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1598232812Sjmallett uint32_t imp_err : 1; /**< Enable Implementation Specific Error. */ 1599215976Sjmallett uint32_t reserved_23_30 : 8; 1600215976Sjmallett uint32_t ctl_crc : 1; /**< Enable error rate counting of control symbols with 1601215976Sjmallett bad CRC values */ 1602215976Sjmallett uint32_t uns_id : 1; /**< Enable error rate counting of acknowledge control 1603215976Sjmallett symbol with unexpected ackIDs 1604215976Sjmallett (packet-accepted or packet_retry) */ 1605215976Sjmallett uint32_t nack : 1; /**< Enable error rate counting of packet-not-accepted 1606215976Sjmallett acknowledge control symbols. */ 1607215976Sjmallett uint32_t out_ack : 1; /**< Enable error rate counting of received packet with 1608215976Sjmallett unexpected ackID value */ 1609215976Sjmallett uint32_t pkt_crc : 1; /**< Enable error rate counting of received a packet 1610215976Sjmallett with a bad CRC value */ 1611215976Sjmallett uint32_t size : 1; /**< Enable error rate counting of received packet 1612215976Sjmallett which exceeds the maximum size of 276 bytes. */ 1613215976Sjmallett uint32_t inv_char : 1; /**< Enable error rate counting of received illegal 1614215976Sjmallett illegal, 8B/10B error or undefined codegroup 1615232812Sjmallett within a packet. */ 1616215976Sjmallett uint32_t inv_data : 1; /**< Enable error rate counting of received data 1617232812Sjmallett codegroup or 8B/10B error within IDLE sequence. */ 1618215976Sjmallett uint32_t reserved_6_14 : 9; 1619215976Sjmallett uint32_t bad_ack : 1; /**< Enable error rate counting of link_responses with 1620215976Sjmallett an ackID that is not outstanding. */ 1621215976Sjmallett uint32_t proterr : 1; /**< Enable error rate counting of unexpected packet or 1622215976Sjmallett control symbols received. */ 1623215976Sjmallett uint32_t f_toggle : 1; /**< Reserved. */ 1624215976Sjmallett uint32_t del_err : 1; /**< Enable error rate counting of illegal or undefined 1625232812Sjmallett codegroups (either INV_DATA or INV_CHAR). */ 1626215976Sjmallett uint32_t uns_ack : 1; /**< Enable error rate counting of unexpected 1627215976Sjmallett acknowledge control symbols received. */ 1628215976Sjmallett uint32_t lnk_tout : 1; /**< Enable error rate counting of acknowledge or 1629215976Sjmallett link-response control symbols not received within 1630215976Sjmallett the specified timeout interval */ 1631215976Sjmallett#else 1632215976Sjmallett uint32_t lnk_tout : 1; 1633215976Sjmallett uint32_t uns_ack : 1; 1634215976Sjmallett uint32_t del_err : 1; 1635215976Sjmallett uint32_t f_toggle : 1; 1636215976Sjmallett uint32_t proterr : 1; 1637215976Sjmallett uint32_t bad_ack : 1; 1638215976Sjmallett uint32_t reserved_6_14 : 9; 1639215976Sjmallett uint32_t inv_data : 1; 1640215976Sjmallett uint32_t inv_char : 1; 1641215976Sjmallett uint32_t size : 1; 1642215976Sjmallett uint32_t pkt_crc : 1; 1643215976Sjmallett uint32_t out_ack : 1; 1644215976Sjmallett uint32_t nack : 1; 1645215976Sjmallett uint32_t uns_id : 1; 1646215976Sjmallett uint32_t ctl_crc : 1; 1647215976Sjmallett uint32_t reserved_23_30 : 8; 1648215976Sjmallett uint32_t imp_err : 1; 1649215976Sjmallett#endif 1650215976Sjmallett } s; 1651215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_en_s cn63xx; 1652232812Sjmallett struct cvmx_sriomaintx_erb_err_rate_en_cn63xxp1 { 1653232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1654215976Sjmallett uint32_t reserved_23_31 : 9; 1655215976Sjmallett uint32_t ctl_crc : 1; /**< Enable error rate counting of control symbols with 1656215976Sjmallett bad CRC values */ 1657215976Sjmallett uint32_t uns_id : 1; /**< Enable error rate counting of acknowledge control 1658215976Sjmallett symbol with unexpected ackIDs 1659215976Sjmallett (packet-accepted or packet_retry) */ 1660215976Sjmallett uint32_t nack : 1; /**< Enable error rate counting of packet-not-accepted 1661215976Sjmallett acknowledge control symbols. */ 1662215976Sjmallett uint32_t out_ack : 1; /**< Enable error rate counting of received packet with 1663215976Sjmallett unexpected ackID value */ 1664215976Sjmallett uint32_t pkt_crc : 1; /**< Enable error rate counting of received a packet 1665215976Sjmallett with a bad CRC value */ 1666215976Sjmallett uint32_t size : 1; /**< Enable error rate counting of received packet 1667215976Sjmallett which exceeds the maximum size of 276 bytes. */ 1668215976Sjmallett uint32_t reserved_6_16 : 11; 1669215976Sjmallett uint32_t bad_ack : 1; /**< Enable error rate counting of link_responses with 1670215976Sjmallett an ackID that is not outstanding. */ 1671215976Sjmallett uint32_t proterr : 1; /**< Enable error rate counting of unexpected packet or 1672215976Sjmallett control symbols received. */ 1673215976Sjmallett uint32_t f_toggle : 1; /**< Reserved. */ 1674215976Sjmallett uint32_t del_err : 1; /**< Enable error rate counting of illegal or undefined 1675215976Sjmallett codegroups (either INV_DATA or INV_CHAR). (Pass 2) */ 1676215976Sjmallett uint32_t uns_ack : 1; /**< Enable error rate counting of unexpected 1677215976Sjmallett acknowledge control symbols received. */ 1678215976Sjmallett uint32_t lnk_tout : 1; /**< Enable error rate counting of acknowledge or 1679215976Sjmallett link-response control symbols not received within 1680215976Sjmallett the specified timeout interval */ 1681215976Sjmallett#else 1682215976Sjmallett uint32_t lnk_tout : 1; 1683215976Sjmallett uint32_t uns_ack : 1; 1684215976Sjmallett uint32_t del_err : 1; 1685215976Sjmallett uint32_t f_toggle : 1; 1686215976Sjmallett uint32_t proterr : 1; 1687215976Sjmallett uint32_t bad_ack : 1; 1688215976Sjmallett uint32_t reserved_6_16 : 11; 1689215976Sjmallett uint32_t size : 1; 1690215976Sjmallett uint32_t pkt_crc : 1; 1691215976Sjmallett uint32_t out_ack : 1; 1692215976Sjmallett uint32_t nack : 1; 1693215976Sjmallett uint32_t uns_id : 1; 1694215976Sjmallett uint32_t ctl_crc : 1; 1695215976Sjmallett uint32_t reserved_23_31 : 9; 1696215976Sjmallett#endif 1697215976Sjmallett } cn63xxp1; 1698232812Sjmallett struct cvmx_sriomaintx_erb_err_rate_en_s cn66xx; 1699215976Sjmallett}; 1700215976Sjmalletttypedef union cvmx_sriomaintx_erb_err_rate_en cvmx_sriomaintx_erb_err_rate_en_t; 1701215976Sjmallett 1702215976Sjmallett/** 1703215976Sjmallett * cvmx_sriomaint#_erb_err_rate_thr 1704215976Sjmallett * 1705215976Sjmallett * SRIOMAINT_ERB_ERR_RATE_THR = SRIO Error Rate Threshold 1706215976Sjmallett * 1707215976Sjmallett * Error Rate Threshold 1708215976Sjmallett * 1709215976Sjmallett * Notes: 1710215976Sjmallett * The Error Rate Threshold register is used to control the reporting of errors to the link status. 1711215976Sjmallett * Typically the Degraded Threshold is less than the Fail Threshold. 1712215976Sjmallett * 1713232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR hclk hrst_n 1714215976Sjmallett */ 1715232812Sjmallettunion cvmx_sriomaintx_erb_err_rate_thr { 1716215976Sjmallett uint32_t u32; 1717232812Sjmallett struct cvmx_sriomaintx_erb_err_rate_thr_s { 1718232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1719215976Sjmallett uint32_t fail_th : 8; /**< These bits provide the threshold value for 1720215976Sjmallett reporting an error condition due to a possibly 1721215976Sjmallett broken link. 1722215976Sjmallett 0x00 - Disable the Error Rate Failed Threshold 1723215976Sjmallett Trigger 1724215976Sjmallett 0x01 - Set the error reporting threshold to 1 1725215976Sjmallett 0x02 - Set the error reporting threshold to 2 1726215976Sjmallett - ... 1727215976Sjmallett 0xFF - Set the error reporting threshold to 255 */ 1728215976Sjmallett uint32_t dgrad_th : 8; /**< These bits provide the threshold value for 1729215976Sjmallett reporting an error condition due to a possibly 1730215976Sjmallett degrading link. 1731215976Sjmallett 0x00 - Disable the Degrade Rate Failed Threshold 1732215976Sjmallett Trigger 1733215976Sjmallett 0x01 - Set the error reporting threshold to 1 1734215976Sjmallett 0x02 - Set the error reporting threshold to 2 1735215976Sjmallett - ... 1736215976Sjmallett 0xFF - Set the error reporting threshold to 255 */ 1737215976Sjmallett uint32_t reserved_0_15 : 16; 1738215976Sjmallett#else 1739215976Sjmallett uint32_t reserved_0_15 : 16; 1740215976Sjmallett uint32_t dgrad_th : 8; 1741215976Sjmallett uint32_t fail_th : 8; 1742215976Sjmallett#endif 1743215976Sjmallett } s; 1744215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xx; 1745215976Sjmallett struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xxp1; 1746232812Sjmallett struct cvmx_sriomaintx_erb_err_rate_thr_s cn66xx; 1747215976Sjmallett}; 1748215976Sjmalletttypedef union cvmx_sriomaintx_erb_err_rate_thr cvmx_sriomaintx_erb_err_rate_thr_t; 1749215976Sjmallett 1750215976Sjmallett/** 1751215976Sjmallett * cvmx_sriomaint#_erb_hdr 1752215976Sjmallett * 1753215976Sjmallett * SRIOMAINT_ERB_HDR = SRIO Error Reporting Block Header 1754215976Sjmallett * 1755215976Sjmallett * Error Reporting Block Header 1756215976Sjmallett * 1757215976Sjmallett * Notes: 1758215976Sjmallett * The error management extensions block header register contains the EF_PTR to the next EF_BLK and 1759215976Sjmallett * the EF_ID that identifies this as the error management extensions block header. In this 1760215976Sjmallett * implementation this is the last block and therefore the EF_PTR is a NULL pointer. 1761215976Sjmallett * 1762232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_HDR hclk hrst_n 1763215976Sjmallett */ 1764232812Sjmallettunion cvmx_sriomaintx_erb_hdr { 1765215976Sjmallett uint32_t u32; 1766232812Sjmallett struct cvmx_sriomaintx_erb_hdr_s { 1767232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1768215976Sjmallett uint32_t ef_ptr : 16; /**< Pointer to the next block in the extended features 1769215976Sjmallett data structure. */ 1770215976Sjmallett uint32_t ef_id : 16; /**< Single Port ID */ 1771215976Sjmallett#else 1772215976Sjmallett uint32_t ef_id : 16; 1773215976Sjmallett uint32_t ef_ptr : 16; 1774215976Sjmallett#endif 1775215976Sjmallett } s; 1776215976Sjmallett struct cvmx_sriomaintx_erb_hdr_s cn63xx; 1777215976Sjmallett struct cvmx_sriomaintx_erb_hdr_s cn63xxp1; 1778232812Sjmallett struct cvmx_sriomaintx_erb_hdr_s cn66xx; 1779215976Sjmallett}; 1780215976Sjmalletttypedef union cvmx_sriomaintx_erb_hdr cvmx_sriomaintx_erb_hdr_t; 1781215976Sjmallett 1782215976Sjmallett/** 1783215976Sjmallett * cvmx_sriomaint#_erb_lt_addr_capt_h 1784215976Sjmallett * 1785215976Sjmallett * SRIOMAINT_ERB_LT_ADDR_CAPT_H = SRIO Logical/Transport Layer High Address Capture 1786215976Sjmallett * 1787215976Sjmallett * Logical/Transport Layer High Address Capture 1788215976Sjmallett * 1789215976Sjmallett * Notes: 1790215976Sjmallett * This register contains error information. It is locked when a Logical/Transport error is detected 1791232812Sjmallett * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be 1792215976Sjmallett * written only when error detection is disabled. This register is only required for end point 1793215976Sjmallett * transactions of 50 or 66 bits. 1794215976Sjmallett * 1795232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ADDR_CAPT_H hclk hrst_n 1796215976Sjmallett */ 1797232812Sjmallettunion cvmx_sriomaintx_erb_lt_addr_capt_h { 1798215976Sjmallett uint32_t u32; 1799232812Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_h_s { 1800232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1801215976Sjmallett uint32_t addr : 32; /**< Most significant 32 bits of the address associated 1802215976Sjmallett with the error. Information supplied for requests 1803215976Sjmallett and responses if available. */ 1804215976Sjmallett#else 1805215976Sjmallett uint32_t addr : 32; 1806215976Sjmallett#endif 1807215976Sjmallett } s; 1808215976Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xx; 1809215976Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xxp1; 1810232812Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn66xx; 1811215976Sjmallett}; 1812215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_addr_capt_h cvmx_sriomaintx_erb_lt_addr_capt_h_t; 1813215976Sjmallett 1814215976Sjmallett/** 1815215976Sjmallett * cvmx_sriomaint#_erb_lt_addr_capt_l 1816215976Sjmallett * 1817215976Sjmallett * SRIOMAINT_ERB_LT_ADDR_CAPT_L = SRIO Logical/Transport Layer Low Address Capture 1818215976Sjmallett * 1819215976Sjmallett * Logical/Transport Layer Low Address Capture 1820215976Sjmallett * 1821215976Sjmallett * Notes: 1822215976Sjmallett * This register contains error information. It is locked when a Logical/Transport error is detected 1823232812Sjmallett * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be 1824215976Sjmallett * written only when error detection is disabled. 1825215976Sjmallett * 1826232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ADDR_CAPT_L hclk hrst_n 1827215976Sjmallett */ 1828232812Sjmallettunion cvmx_sriomaintx_erb_lt_addr_capt_l { 1829215976Sjmallett uint32_t u32; 1830232812Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_l_s { 1831232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1832215976Sjmallett uint32_t addr : 29; /**< Least significant 29 bits of the address 1833215976Sjmallett associated with the error. Bits 31:24 specify the 1834215976Sjmallett request HOP count for Maintenance Operations. 1835215976Sjmallett Information supplied for requests and responses if 1836215976Sjmallett available. */ 1837215976Sjmallett uint32_t reserved_2_2 : 1; 1838215976Sjmallett uint32_t xaddr : 2; /**< Extended address bits of the address associated 1839215976Sjmallett with the error. Information supplied for requests 1840215976Sjmallett and responses if available. */ 1841215976Sjmallett#else 1842215976Sjmallett uint32_t xaddr : 2; 1843215976Sjmallett uint32_t reserved_2_2 : 1; 1844215976Sjmallett uint32_t addr : 29; 1845215976Sjmallett#endif 1846215976Sjmallett } s; 1847215976Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xx; 1848215976Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xxp1; 1849232812Sjmallett struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn66xx; 1850215976Sjmallett}; 1851215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_addr_capt_l cvmx_sriomaintx_erb_lt_addr_capt_l_t; 1852215976Sjmallett 1853215976Sjmallett/** 1854215976Sjmallett * cvmx_sriomaint#_erb_lt_ctrl_capt 1855215976Sjmallett * 1856215976Sjmallett * SRIOMAINT_ERB_LT_CTRL_CAPT = SRIO Logical/Transport Layer Control Capture 1857215976Sjmallett * 1858215976Sjmallett * Logical/Transport Layer Control Capture 1859215976Sjmallett * 1860215976Sjmallett * Notes: 1861215976Sjmallett * This register contains error information. It is locked when a Logical/Transport error is detected 1862232812Sjmallett * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be 1863215976Sjmallett * written only when error detection is disabled. 1864215976Sjmallett * 1865232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_CTRL_CAPT hclk hrst_n 1866215976Sjmallett */ 1867232812Sjmallettunion cvmx_sriomaintx_erb_lt_ctrl_capt { 1868215976Sjmallett uint32_t u32; 1869232812Sjmallett struct cvmx_sriomaintx_erb_lt_ctrl_capt_s { 1870232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1871215976Sjmallett uint32_t ftype : 4; /**< Format Type associated with the error */ 1872215976Sjmallett uint32_t ttype : 4; /**< Transaction Type associated with the error 1873215976Sjmallett (For Messages) 1874215976Sjmallett Message Length */ 1875215976Sjmallett uint32_t extra : 8; /**< Additional Information 1876215976Sjmallett (For Messages) 1877215976Sjmallett - 23:22 Letter 1878215976Sjmallett - 21:20 Mbox 1879215976Sjmallett - 19:16 Msgseg/xmbox 1880215976Sjmallett Information for the last message request sent 1881215976Sjmallett for the mailbox that had an error 1882215976Sjmallett (For Responses) 1883215976Sjmallett - 23:20 Response Request FTYPE 1884215976Sjmallett - 19:16 Response Request TTYPE 1885215976Sjmallett (For all other types) 1886215976Sjmallett Reserved. */ 1887215976Sjmallett uint32_t status : 4; /**< Response Status. 1888215976Sjmallett (For all other Requests) 1889215976Sjmallett Reserved. */ 1890215976Sjmallett uint32_t size : 4; /**< Size associated with the transaction. */ 1891215976Sjmallett uint32_t tt : 1; /**< Transfer Type 0=ID8, 1=ID16. */ 1892215976Sjmallett uint32_t wdptr : 1; /**< Word Pointer associated with the error. */ 1893215976Sjmallett uint32_t reserved_5_5 : 1; 1894215976Sjmallett uint32_t capt_idx : 5; /**< Capture Index. 31 - Bit set in 1895232812Sjmallett SRIOMAINT(0,2..3)_ERB_LT_ERR_DET. */ 1896215976Sjmallett#else 1897215976Sjmallett uint32_t capt_idx : 5; 1898215976Sjmallett uint32_t reserved_5_5 : 1; 1899215976Sjmallett uint32_t wdptr : 1; 1900215976Sjmallett uint32_t tt : 1; 1901215976Sjmallett uint32_t size : 4; 1902215976Sjmallett uint32_t status : 4; 1903215976Sjmallett uint32_t extra : 8; 1904215976Sjmallett uint32_t ttype : 4; 1905215976Sjmallett uint32_t ftype : 4; 1906215976Sjmallett#endif 1907215976Sjmallett } s; 1908215976Sjmallett struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xx; 1909215976Sjmallett struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xxp1; 1910232812Sjmallett struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn66xx; 1911215976Sjmallett}; 1912215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_ctrl_capt cvmx_sriomaintx_erb_lt_ctrl_capt_t; 1913215976Sjmallett 1914215976Sjmallett/** 1915215976Sjmallett * cvmx_sriomaint#_erb_lt_dev_id 1916215976Sjmallett * 1917215976Sjmallett * SRIOMAINT_ERB_LT_DEV_ID = SRIO Port-write Target deviceID 1918215976Sjmallett * 1919215976Sjmallett * Port-write Target deviceID 1920215976Sjmallett * 1921215976Sjmallett * Notes: 1922215976Sjmallett * This SRIO interface does not support generating Port-Writes based on ERB Errors. This register is 1923215976Sjmallett * currently unused and should be treated as reserved. 1924215976Sjmallett * 1925215976Sjmallett * Clk_Rst: SRIOMAINT_ERB_LT_DEV_ID hclk hrst_n 1926215976Sjmallett */ 1927232812Sjmallettunion cvmx_sriomaintx_erb_lt_dev_id { 1928215976Sjmallett uint32_t u32; 1929232812Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_s { 1930232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1931215976Sjmallett uint32_t id16 : 8; /**< This is the most significant byte of the 1932215976Sjmallett port-write destination deviceID (large transport 1933215976Sjmallett systems only) 1934215976Sjmallett destination ID used for Port Write errors */ 1935215976Sjmallett uint32_t id8 : 8; /**< This is the port-write destination deviceID */ 1936215976Sjmallett uint32_t tt : 1; /**< Transport Type used for Port Write 1937215976Sjmallett 0 = Small Transport, ID8 Only 1938215976Sjmallett 1 = Large Transport, ID16 and ID8 */ 1939215976Sjmallett uint32_t reserved_0_14 : 15; 1940215976Sjmallett#else 1941215976Sjmallett uint32_t reserved_0_14 : 15; 1942215976Sjmallett uint32_t tt : 1; 1943215976Sjmallett uint32_t id8 : 8; 1944215976Sjmallett uint32_t id16 : 8; 1945215976Sjmallett#endif 1946215976Sjmallett } s; 1947215976Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xx; 1948215976Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xxp1; 1949232812Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_s cn66xx; 1950215976Sjmallett}; 1951215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_dev_id cvmx_sriomaintx_erb_lt_dev_id_t; 1952215976Sjmallett 1953215976Sjmallett/** 1954215976Sjmallett * cvmx_sriomaint#_erb_lt_dev_id_capt 1955215976Sjmallett * 1956215976Sjmallett * SRIOMAINT_ERB_LT_DEV_ID_CAPT = SRIO Logical/Transport Layer Device ID Capture 1957215976Sjmallett * 1958215976Sjmallett * Logical/Transport Layer Device ID Capture 1959215976Sjmallett * 1960215976Sjmallett * Notes: 1961215976Sjmallett * This register contains error information. It is locked when a Logical/Transport error is detected 1962232812Sjmallett * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be 1963215976Sjmallett * written only when error detection is disabled. 1964215976Sjmallett * 1965232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_DEV_ID_CAPT hclk hrst_n 1966215976Sjmallett */ 1967232812Sjmallettunion cvmx_sriomaintx_erb_lt_dev_id_capt { 1968215976Sjmallett uint32_t u32; 1969232812Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_capt_s { 1970232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1971215976Sjmallett uint32_t dst_id16 : 8; /**< Most significant byte of the large transport 1972215976Sjmallett destination ID associated with the error */ 1973215976Sjmallett uint32_t dst_id8 : 8; /**< Least significant byte of the large transport 1974215976Sjmallett destination ID or the 8-bit small transport 1975215976Sjmallett destination ID associated with the error */ 1976215976Sjmallett uint32_t src_id16 : 8; /**< Most significant byte of the large transport 1977215976Sjmallett source ID associated with the error */ 1978215976Sjmallett uint32_t src_id8 : 8; /**< Least significant byte of the large transport 1979215976Sjmallett source ID or the 8-bit small transport source ID 1980215976Sjmallett associated with the error */ 1981215976Sjmallett#else 1982215976Sjmallett uint32_t src_id8 : 8; 1983215976Sjmallett uint32_t src_id16 : 8; 1984215976Sjmallett uint32_t dst_id8 : 8; 1985215976Sjmallett uint32_t dst_id16 : 8; 1986215976Sjmallett#endif 1987215976Sjmallett } s; 1988215976Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xx; 1989215976Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xxp1; 1990232812Sjmallett struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn66xx; 1991215976Sjmallett}; 1992215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_dev_id_capt cvmx_sriomaintx_erb_lt_dev_id_capt_t; 1993215976Sjmallett 1994215976Sjmallett/** 1995215976Sjmallett * cvmx_sriomaint#_erb_lt_err_det 1996215976Sjmallett * 1997215976Sjmallett * SRIOMAINT_ERB_LT_ERR_DET = SRIO Logical/Transport Layer Error Detect 1998215976Sjmallett * 1999215976Sjmallett * SRIO Logical/Transport Layer Error Detect 2000215976Sjmallett * 2001215976Sjmallett * Notes: 2002215976Sjmallett * This register indicates the error that was detected by the Logical or Transport logic layer. 2003215976Sjmallett * Once a bit is set in this CSR, HW will lock the register until SW writes a zero to clear all the 2004215976Sjmallett * fields. The HW sets SRIO_INT_REG[LOG_ERB] every time it sets one of the bits. 2005215976Sjmallett * To handle the interrupt, the following procedure may be best: 2006215976Sjmallett * (1) clear SRIO_INT_REG[LOG_ERB], 2007215976Sjmallett * (2) read this CSR, corresponding SRIOMAINT*_ERB_LT_ADDR_CAPT_H, SRIOMAINT*_ERB_LT_ADDR_CAPT_L, 2008215976Sjmallett * SRIOMAINT*_ERB_LT_DEV_ID_CAPT, and SRIOMAINT*_ERB_LT_CTRL_CAPT 2009215976Sjmallett * (3) Write this CSR to 0. 2010215976Sjmallett * 2011232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ERR_DET hclk hrst_n 2012215976Sjmallett */ 2013232812Sjmallettunion cvmx_sriomaintx_erb_lt_err_det { 2014215976Sjmallett uint32_t u32; 2015232812Sjmallett struct cvmx_sriomaintx_erb_lt_err_det_s { 2016232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2017215976Sjmallett uint32_t io_err : 1; /**< Received a response of ERROR for an IO Logical 2018215976Sjmallett Layer Request. This includes all Maintenance and 2019215976Sjmallett Memory Responses not destined for the RX Soft 2020215976Sjmallett Packet FIFO. When SRIO receives an ERROR response 2021215976Sjmallett for a read, the issuing core or DPI DMA engine 2022215976Sjmallett receives result bytes with all bits set. In the 2023215976Sjmallett case of writes with response, this bit is the only 2024215976Sjmallett indication of failure. */ 2025215976Sjmallett uint32_t msg_err : 1; /**< Received a response of ERROR for an outgoing 2026215976Sjmallett message segment. This bit is the only direct 2027215976Sjmallett indication of a MSG_ERR. When a MSG_ERR occurs, 2028215976Sjmallett SRIO drops the message segment and will not set 2029215976Sjmallett SRIO*_INT_REG[OMSG*] after the message 2030215976Sjmallett "transfer". NOTE: SRIO can continue to send or 2031215976Sjmallett retry other segments from the same message after 2032215976Sjmallett a MSG_ERR. */ 2033215976Sjmallett uint32_t gsm_err : 1; /**< Received a response of ERROR for an GSM Logical 2034215976Sjmallett Request. SRIO hardware never sets this bit. GSM 2035215976Sjmallett operations are not supported (outside of the Soft 2036215976Sjmallett Packet FIFO). */ 2037215976Sjmallett uint32_t msg_fmt : 1; /**< Received an incoming Message Segment with a 2038215976Sjmallett formating error. A MSG_FMT error occurs when SRIO 2039215976Sjmallett receives a message segment with a reserved SSIZE, 2040215976Sjmallett or a illegal data payload size, or a MSGSEG greater 2041215976Sjmallett than MSGLEN, or a MSGSEG that is the duplicate of 2042215976Sjmallett one already received by an inflight message. 2043215976Sjmallett When a non-duplicate MSG_FMT error occurs, SRIO 2044215976Sjmallett drops the segment and sends an ERROR response. 2045215976Sjmallett When a duplicate MSG_FMT error occurs, SRIO 2046215976Sjmallett (internally) terminates the currently-inflight 2047215976Sjmallett message with an error and processes the duplicate, 2048215976Sjmallett which may result in a new message being generated 2049215976Sjmallett internally for the duplicate. */ 2050215976Sjmallett uint32_t ill_tran : 1; /**< Received illegal fields in the request/response 2051215976Sjmallett packet for a supported transaction or any packet 2052215976Sjmallett with a reserved transaction type. When an ILL_TRAN 2053215976Sjmallett error occurs, SRIO ignores the packet. ILL_TRAN 2054215976Sjmallett errors are 2nd priority after ILL_TGT and may mask 2055215976Sjmallett other problems. Packets with ILL_TRAN errors cannot 2056215976Sjmallett enter the RX Soft Packet FIFO. 2057215976Sjmallett There are two things that can set ILL_TRAN: 2058215976Sjmallett (1) SRIO received a packet with a tt value is not 2059215976Sjmallett 0 or 1, or (2) SRIO received a response to an 2060215976Sjmallett outstanding message segment whose status was not 2061215976Sjmallett DONE, RETRY, or ERROR. */ 2062215976Sjmallett uint32_t ill_tgt : 1; /**< Received a packet that contained a destination ID 2063215976Sjmallett other than SRIOMAINT*_PRI_DEV_ID or 2064215976Sjmallett SRIOMAINT*_SEC_DEV_ID. When an ILL_TGT error 2065215976Sjmallett occurs, SRIO drops the packet. ILL_TGT errors are 2066215976Sjmallett highest priority, so may mask other problems. 2067215976Sjmallett Packets with ILL_TGT errors cannot enter the RX 2068215976Sjmallett soft packet fifo. */ 2069215976Sjmallett uint32_t msg_tout : 1; /**< An expected incoming message request has not been 2070215976Sjmallett received within the time-out interval specified in 2071232812Sjmallett SRIOMAINT(0,2..3)_PORT_RT_CTL. When a MSG_TOUT occurs, 2072215976Sjmallett SRIO (internally) terminates the inflight message 2073215976Sjmallett with an error. */ 2074215976Sjmallett uint32_t pkt_tout : 1; /**< A required response has not been received to an 2075215976Sjmallett outgoing memory, maintenance or message request 2076215976Sjmallett before the time-out interval specified in 2077232812Sjmallett SRIOMAINT(0,2..3)_PORT_RT_CTL. When an IO or maintenance 2078215976Sjmallett read request operation has a PKT_TOUT, the issuing 2079215976Sjmallett core load or DPI DMA engine receive all ones for 2080215976Sjmallett the result. When an IO NWRITE_R has a PKT_TOUT, 2081215976Sjmallett this bit is the only indication of failure. When a 2082215976Sjmallett message request operation has a PKT_TOUT, SRIO 2083215976Sjmallett discards the the outgoing message segment, and 2084215976Sjmallett this bit is the only direct indication of failure. 2085215976Sjmallett NOTE: SRIO may continue to send or retry other 2086215976Sjmallett segments from the same message. When one or more of 2087215976Sjmallett the segments in an outgoing message have a 2088215976Sjmallett PKT_TOUT, SRIO will not set SRIO*_INT_REG[OMSG*] 2089215976Sjmallett after the message "transfer". */ 2090215976Sjmallett uint32_t uns_resp : 1; /**< An unsolicited/unexpected memory, maintenance or 2091215976Sjmallett message response packet was received that was not 2092215976Sjmallett destined for the RX Soft Packet FIFO. When this 2093215976Sjmallett condition is detected, the packet is dropped. */ 2094215976Sjmallett uint32_t uns_tran : 1; /**< A transaction is received that is not supported. 2095215976Sjmallett SRIO HW will never set this bit - SRIO routes all 2096215976Sjmallett unsupported transactions to the RX soft packet 2097215976Sjmallett FIFO. */ 2098215976Sjmallett uint32_t reserved_1_21 : 21; 2099215976Sjmallett uint32_t resp_sz : 1; /**< Received an incoming Memory or Maintenance 2100215976Sjmallett Read response packet with a DONE status and less 2101215976Sjmallett data then expected. This condition causes the 2102215976Sjmallett Read to be completed and an error response to be 2103215976Sjmallett returned with all the data bits set to the issuing 2104215976Sjmallett Core or DMA Engine. */ 2105215976Sjmallett#else 2106215976Sjmallett uint32_t resp_sz : 1; 2107215976Sjmallett uint32_t reserved_1_21 : 21; 2108215976Sjmallett uint32_t uns_tran : 1; 2109215976Sjmallett uint32_t uns_resp : 1; 2110215976Sjmallett uint32_t pkt_tout : 1; 2111215976Sjmallett uint32_t msg_tout : 1; 2112215976Sjmallett uint32_t ill_tgt : 1; 2113215976Sjmallett uint32_t ill_tran : 1; 2114215976Sjmallett uint32_t msg_fmt : 1; 2115215976Sjmallett uint32_t gsm_err : 1; 2116215976Sjmallett uint32_t msg_err : 1; 2117215976Sjmallett uint32_t io_err : 1; 2118215976Sjmallett#endif 2119215976Sjmallett } s; 2120215976Sjmallett struct cvmx_sriomaintx_erb_lt_err_det_s cn63xx; 2121215976Sjmallett struct cvmx_sriomaintx_erb_lt_err_det_s cn63xxp1; 2122232812Sjmallett struct cvmx_sriomaintx_erb_lt_err_det_s cn66xx; 2123215976Sjmallett}; 2124215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_err_det cvmx_sriomaintx_erb_lt_err_det_t; 2125215976Sjmallett 2126215976Sjmallett/** 2127215976Sjmallett * cvmx_sriomaint#_erb_lt_err_en 2128215976Sjmallett * 2129215976Sjmallett * SRIOMAINT_ERB_LT_ERR_EN = SRIO Logical/Transport Layer Error Enable 2130215976Sjmallett * 2131215976Sjmallett * SRIO Logical/Transport Layer Error Enable 2132215976Sjmallett * 2133215976Sjmallett * Notes: 2134215976Sjmallett * This register contains the bits that control if an error condition locks the Logical/Transport 2135215976Sjmallett * Layer Error Detect and Capture registers and is reported to the system host. 2136215976Sjmallett * 2137232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ERR_EN hclk hrst_n 2138215976Sjmallett */ 2139232812Sjmallettunion cvmx_sriomaintx_erb_lt_err_en { 2140215976Sjmallett uint32_t u32; 2141232812Sjmallett struct cvmx_sriomaintx_erb_lt_err_en_s { 2142232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2143215976Sjmallett uint32_t io_err : 1; /**< Enable reporting of an IO error response. Save and 2144215976Sjmallett lock original request transaction information in 2145215976Sjmallett all Logical/Transport Layer Capture CSRs. */ 2146215976Sjmallett uint32_t msg_err : 1; /**< Enable reporting of a Message error response. Save 2147215976Sjmallett and lock original request transaction information 2148215976Sjmallett in all Logical/Transport Layer Capture CSRs. */ 2149215976Sjmallett uint32_t gsm_err : 1; /**< Enable reporting of a GSM error response. Save and 2150215976Sjmallett lock original request transaction capture 2151215976Sjmallett information in all Logical/Transport Layer Capture 2152215976Sjmallett CSRs. */ 2153215976Sjmallett uint32_t msg_fmt : 1; /**< Enable reporting of a message format error. Save 2154215976Sjmallett and lock transaction capture information in 2155215976Sjmallett Logical/Transport Layer Device ID and Control 2156215976Sjmallett Capture CSRs. */ 2157215976Sjmallett uint32_t ill_tran : 1; /**< Enable reporting of an illegal transaction decode 2158215976Sjmallett error Save and lock transaction capture 2159215976Sjmallett information in Logical/Transport Layer Device ID 2160215976Sjmallett and Control Capture CSRs. */ 2161215976Sjmallett uint32_t ill_tgt : 1; /**< Enable reporting of an illegal transaction target 2162215976Sjmallett error. Save and lock transaction capture 2163215976Sjmallett information in Logical/Transport Layer Device ID 2164215976Sjmallett and Control Capture CSRs. */ 2165215976Sjmallett uint32_t msg_tout : 1; /**< Enable reporting of a Message Request time-out 2166215976Sjmallett error. Save and lock transaction capture 2167215976Sjmallett information in Logical/Transport Layer Device ID 2168215976Sjmallett and Control Capture CSRs for the last Message 2169215976Sjmallett request segment packet received. */ 2170215976Sjmallett uint32_t pkt_tout : 1; /**< Enable reporting of a packet response time-out 2171215976Sjmallett error. Save and lock original request address in 2172215976Sjmallett Logical/Transport Layer Address Capture CSRs. 2173215976Sjmallett Save and lock original request Destination ID in 2174215976Sjmallett Logical/Transport Layer Device ID Capture CSR. */ 2175215976Sjmallett uint32_t uns_resp : 1; /**< Enable reporting of an unsolicited response error. 2176215976Sjmallett Save and lock transaction capture information in 2177215976Sjmallett Logical/Transport Layer Device ID and Control 2178215976Sjmallett Capture CSRs. */ 2179215976Sjmallett uint32_t uns_tran : 1; /**< Enable reporting of an unsupported transaction 2180215976Sjmallett error. Save and lock transaction capture 2181215976Sjmallett information in Logical/Transport Layer Device ID 2182215976Sjmallett and Control Capture CSRs. */ 2183215976Sjmallett uint32_t reserved_1_21 : 21; 2184215976Sjmallett uint32_t resp_sz : 1; /**< Enable reporting of an incoming response with 2185215976Sjmallett unexpected data size */ 2186215976Sjmallett#else 2187215976Sjmallett uint32_t resp_sz : 1; 2188215976Sjmallett uint32_t reserved_1_21 : 21; 2189215976Sjmallett uint32_t uns_tran : 1; 2190215976Sjmallett uint32_t uns_resp : 1; 2191215976Sjmallett uint32_t pkt_tout : 1; 2192215976Sjmallett uint32_t msg_tout : 1; 2193215976Sjmallett uint32_t ill_tgt : 1; 2194215976Sjmallett uint32_t ill_tran : 1; 2195215976Sjmallett uint32_t msg_fmt : 1; 2196215976Sjmallett uint32_t gsm_err : 1; 2197215976Sjmallett uint32_t msg_err : 1; 2198215976Sjmallett uint32_t io_err : 1; 2199215976Sjmallett#endif 2200215976Sjmallett } s; 2201215976Sjmallett struct cvmx_sriomaintx_erb_lt_err_en_s cn63xx; 2202215976Sjmallett struct cvmx_sriomaintx_erb_lt_err_en_s cn63xxp1; 2203232812Sjmallett struct cvmx_sriomaintx_erb_lt_err_en_s cn66xx; 2204215976Sjmallett}; 2205215976Sjmalletttypedef union cvmx_sriomaintx_erb_lt_err_en cvmx_sriomaintx_erb_lt_err_en_t; 2206215976Sjmallett 2207215976Sjmallett/** 2208215976Sjmallett * cvmx_sriomaint#_erb_pack_capt_1 2209215976Sjmallett * 2210215976Sjmallett * SRIOMAINT_ERB_PACK_CAPT_1 = SRIO Packet Capture 1 2211215976Sjmallett * 2212215976Sjmallett * Packet Capture 1 2213215976Sjmallett * 2214215976Sjmallett * Notes: 2215215976Sjmallett * Error capture register 1 contains either long symbol capture information or bytes 4 through 7 of 2216215976Sjmallett * the packet header. 2217215976Sjmallett * The HW will not update this register (i.e. this register is locked) while 2218215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2219215976Sjmallett * 2220232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_CAPT_1 hclk hrst_n 2221215976Sjmallett */ 2222232812Sjmallettunion cvmx_sriomaintx_erb_pack_capt_1 { 2223215976Sjmallett uint32_t u32; 2224232812Sjmallett struct cvmx_sriomaintx_erb_pack_capt_1_s { 2225232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2226215976Sjmallett uint32_t capture : 32; /**< Bytes 4 thru 7 of the packet header. */ 2227215976Sjmallett#else 2228215976Sjmallett uint32_t capture : 32; 2229215976Sjmallett#endif 2230215976Sjmallett } s; 2231215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xx; 2232215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xxp1; 2233232812Sjmallett struct cvmx_sriomaintx_erb_pack_capt_1_s cn66xx; 2234215976Sjmallett}; 2235215976Sjmalletttypedef union cvmx_sriomaintx_erb_pack_capt_1 cvmx_sriomaintx_erb_pack_capt_1_t; 2236215976Sjmallett 2237215976Sjmallett/** 2238215976Sjmallett * cvmx_sriomaint#_erb_pack_capt_2 2239215976Sjmallett * 2240215976Sjmallett * SRIOMAINT_ERB_PACK_CAPT_2 = SRIO Packet Capture 2 2241215976Sjmallett * 2242215976Sjmallett * Packet Capture 2 2243215976Sjmallett * 2244215976Sjmallett * Notes: 2245215976Sjmallett * Error capture register 2 contains bytes 8 through 11 of the packet header. 2246215976Sjmallett * The HW will not update this register (i.e. this register is locked) while 2247215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2248215976Sjmallett * 2249232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_CAPT_2 hclk hrst_n 2250215976Sjmallett */ 2251232812Sjmallettunion cvmx_sriomaintx_erb_pack_capt_2 { 2252215976Sjmallett uint32_t u32; 2253232812Sjmallett struct cvmx_sriomaintx_erb_pack_capt_2_s { 2254232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2255215976Sjmallett uint32_t capture : 32; /**< Bytes 8 thru 11 of the packet header. */ 2256215976Sjmallett#else 2257215976Sjmallett uint32_t capture : 32; 2258215976Sjmallett#endif 2259215976Sjmallett } s; 2260215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xx; 2261215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xxp1; 2262232812Sjmallett struct cvmx_sriomaintx_erb_pack_capt_2_s cn66xx; 2263215976Sjmallett}; 2264215976Sjmalletttypedef union cvmx_sriomaintx_erb_pack_capt_2 cvmx_sriomaintx_erb_pack_capt_2_t; 2265215976Sjmallett 2266215976Sjmallett/** 2267215976Sjmallett * cvmx_sriomaint#_erb_pack_capt_3 2268215976Sjmallett * 2269215976Sjmallett * SRIOMAINT_ERB_PACK_CAPT_3 = SRIO Packet Capture 3 2270215976Sjmallett * 2271215976Sjmallett * Packet Capture 3 2272215976Sjmallett * 2273215976Sjmallett * Notes: 2274215976Sjmallett * Error capture register 3 contains bytes 12 through 15 of the packet header. 2275215976Sjmallett * The HW will not update this register (i.e. this register is locked) while 2276215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2277215976Sjmallett * 2278232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_CAPT_3 hclk hrst_n 2279215976Sjmallett */ 2280232812Sjmallettunion cvmx_sriomaintx_erb_pack_capt_3 { 2281215976Sjmallett uint32_t u32; 2282232812Sjmallett struct cvmx_sriomaintx_erb_pack_capt_3_s { 2283232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2284215976Sjmallett uint32_t capture : 32; /**< Bytes 12 thru 15 of the packet header. */ 2285215976Sjmallett#else 2286215976Sjmallett uint32_t capture : 32; 2287215976Sjmallett#endif 2288215976Sjmallett } s; 2289215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xx; 2290215976Sjmallett struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xxp1; 2291232812Sjmallett struct cvmx_sriomaintx_erb_pack_capt_3_s cn66xx; 2292215976Sjmallett}; 2293215976Sjmalletttypedef union cvmx_sriomaintx_erb_pack_capt_3 cvmx_sriomaintx_erb_pack_capt_3_t; 2294215976Sjmallett 2295215976Sjmallett/** 2296215976Sjmallett * cvmx_sriomaint#_erb_pack_sym_capt 2297215976Sjmallett * 2298215976Sjmallett * SRIOMAINT_ERB_PACK_SYM_CAPT = SRIO Packet/Control Symbol Capture 2299215976Sjmallett * 2300215976Sjmallett * Packet/Control Symbol Capture 2301215976Sjmallett * 2302215976Sjmallett * Notes: 2303215976Sjmallett * This register contains either captured control symbol information or the first 4 bytes of captured 2304215976Sjmallett * packet information. The Errors that generate Partial Control Symbols can be found in 2305215976Sjmallett * SRIOMAINT*_ERB_ERR_DET. The HW will not update this register (i.e. this register is locked) while 2306215976Sjmallett * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set. 2307215976Sjmallett * 2308232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT hclk hrst_n 2309215976Sjmallett */ 2310232812Sjmallettunion cvmx_sriomaintx_erb_pack_sym_capt { 2311215976Sjmallett uint32_t u32; 2312232812Sjmallett struct cvmx_sriomaintx_erb_pack_sym_capt_s { 2313232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2314215976Sjmallett uint32_t capture : 32; /**< Control Character and Control Symbol or Bytes 0 to 2315215976Sjmallett 3 of Packet Header 2316215976Sjmallett The Control Symbol consists of 2317215976Sjmallett - 31:24 - SC Character (0 in Partial Symbol) 2318215976Sjmallett - 23:21 - Stype 0 2319215976Sjmallett - 20:16 - Parameter 0 2320215976Sjmallett - 15:11 - Parameter 1 2321215976Sjmallett - 10: 8 - Stype 1 (0 in Partial Symbol) 2322215976Sjmallett - 7: 5 - Command (0 in Partial Symbol) 2323215976Sjmallett - 4: 0 - CRC5 (0 in Partial Symbol) */ 2324215976Sjmallett#else 2325215976Sjmallett uint32_t capture : 32; 2326215976Sjmallett#endif 2327215976Sjmallett } s; 2328215976Sjmallett struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xx; 2329215976Sjmallett struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xxp1; 2330232812Sjmallett struct cvmx_sriomaintx_erb_pack_sym_capt_s cn66xx; 2331215976Sjmallett}; 2332215976Sjmalletttypedef union cvmx_sriomaintx_erb_pack_sym_capt cvmx_sriomaintx_erb_pack_sym_capt_t; 2333215976Sjmallett 2334215976Sjmallett/** 2335215976Sjmallett * cvmx_sriomaint#_hb_dev_id_lock 2336215976Sjmallett * 2337215976Sjmallett * SRIOMAINT_HB_DEV_ID_LOCK = SRIO Host Device ID Lock 2338215976Sjmallett * 2339215976Sjmallett * The Host Base Device ID 2340215976Sjmallett * 2341215976Sjmallett * Notes: 2342215976Sjmallett * This register contains the Device ID of the Host responsible for initializing this SRIO device. 2343215976Sjmallett * The register contains a special write once function that captures the first HOSTID written to it 2344215976Sjmallett * after reset. The function allows several potential hosts to write to this register and then read 2345215976Sjmallett * it to see if they have responsibility for initialization. The register can be unlocked by 2346215976Sjmallett * rewriting the current host value. This will reset the lock and restore the value to 0xFFFF. 2347215976Sjmallett * 2348232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_HB_DEV_ID_LOCK hclk hrst_n 2349215976Sjmallett */ 2350232812Sjmallettunion cvmx_sriomaintx_hb_dev_id_lock { 2351215976Sjmallett uint32_t u32; 2352232812Sjmallett struct cvmx_sriomaintx_hb_dev_id_lock_s { 2353232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2354215976Sjmallett uint32_t reserved_16_31 : 16; 2355215976Sjmallett uint32_t hostid : 16; /**< Primary 16-bit Device ID */ 2356215976Sjmallett#else 2357215976Sjmallett uint32_t hostid : 16; 2358215976Sjmallett uint32_t reserved_16_31 : 16; 2359215976Sjmallett#endif 2360215976Sjmallett } s; 2361215976Sjmallett struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xx; 2362215976Sjmallett struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xxp1; 2363232812Sjmallett struct cvmx_sriomaintx_hb_dev_id_lock_s cn66xx; 2364215976Sjmallett}; 2365215976Sjmalletttypedef union cvmx_sriomaintx_hb_dev_id_lock cvmx_sriomaintx_hb_dev_id_lock_t; 2366215976Sjmallett 2367215976Sjmallett/** 2368215976Sjmallett * cvmx_sriomaint#_ir_buffer_config 2369215976Sjmallett * 2370215976Sjmallett * SRIOMAINT_IR_BUFFER_CONFIG = SRIO Buffer Configuration 2371215976Sjmallett * 2372215976Sjmallett * Buffer Configuration 2373215976Sjmallett * 2374215976Sjmallett * Notes: 2375215976Sjmallett * This register controls the operation of the SRIO Core buffer mux logic. 2376215976Sjmallett * 2377232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG hclk hrst_n 2378215976Sjmallett */ 2379232812Sjmallettunion cvmx_sriomaintx_ir_buffer_config { 2380215976Sjmallett uint32_t u32; 2381232812Sjmallett struct cvmx_sriomaintx_ir_buffer_config_s { 2382232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2383232812Sjmallett uint32_t tx_wm0 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */ 2384232812Sjmallett uint32_t tx_wm1 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */ 2385232812Sjmallett uint32_t tx_wm2 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */ 2386215976Sjmallett uint32_t reserved_3_19 : 17; 2387215976Sjmallett uint32_t tx_flow : 1; /**< Controls whether Transmitter Flow Control is 2388215976Sjmallett permitted on this device. 2389215976Sjmallett 0 - Disabled 2390215976Sjmallett 1 - Permitted 2391215976Sjmallett The reset value of this field is 2392215976Sjmallett SRIO*_IP_FEATURE[TX_FLOW]. */ 2393232812Sjmallett uint32_t tx_sync : 1; /**< Reserved. */ 2394232812Sjmallett uint32_t rx_sync : 1; /**< Reserved. */ 2395215976Sjmallett#else 2396215976Sjmallett uint32_t rx_sync : 1; 2397215976Sjmallett uint32_t tx_sync : 1; 2398215976Sjmallett uint32_t tx_flow : 1; 2399215976Sjmallett uint32_t reserved_3_19 : 17; 2400215976Sjmallett uint32_t tx_wm2 : 4; 2401215976Sjmallett uint32_t tx_wm1 : 4; 2402215976Sjmallett uint32_t tx_wm0 : 4; 2403215976Sjmallett#endif 2404215976Sjmallett } s; 2405215976Sjmallett struct cvmx_sriomaintx_ir_buffer_config_s cn63xx; 2406215976Sjmallett struct cvmx_sriomaintx_ir_buffer_config_s cn63xxp1; 2407232812Sjmallett struct cvmx_sriomaintx_ir_buffer_config_s cn66xx; 2408215976Sjmallett}; 2409215976Sjmalletttypedef union cvmx_sriomaintx_ir_buffer_config cvmx_sriomaintx_ir_buffer_config_t; 2410215976Sjmallett 2411215976Sjmallett/** 2412215976Sjmallett * cvmx_sriomaint#_ir_buffer_config2 2413215976Sjmallett * 2414232812Sjmallett * SRIOMAINT_IR_BUFFER_CONFIG2 = SRIO Buffer Configuration 2 2415215976Sjmallett * 2416215976Sjmallett * Buffer Configuration 2 2417215976Sjmallett * 2418215976Sjmallett * Notes: 2419215976Sjmallett * This register controls the RX and TX Buffer availablility by priority. The typical values are 2420215976Sjmallett * optimized for normal operation. Care must be taken when changing these values to avoid values 2421215976Sjmallett * which can result in deadlocks. Disabling a priority is not recommended and can result in system 2422215976Sjmallett * level failures. 2423215976Sjmallett * 2424232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2 hclk hrst_n 2425215976Sjmallett */ 2426232812Sjmallettunion cvmx_sriomaintx_ir_buffer_config2 { 2427215976Sjmallett uint32_t u32; 2428232812Sjmallett struct cvmx_sriomaintx_ir_buffer_config2_s { 2429232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2430215976Sjmallett uint32_t tx_wm3 : 4; /**< Number of buffers free before a priority 3 packet 2431215976Sjmallett will be transmitted. A value of 9 will disable 2432215976Sjmallett this priority. */ 2433215976Sjmallett uint32_t tx_wm2 : 4; /**< Number of buffers free before a priority 2 packet 2434215976Sjmallett will be transmitted. A value of 9 will disable 2435215976Sjmallett this priority. */ 2436215976Sjmallett uint32_t tx_wm1 : 4; /**< Number of buffers free before a priority 1 packet 2437215976Sjmallett will be transmitted. A value of 9 will disable 2438215976Sjmallett this priority. */ 2439215976Sjmallett uint32_t tx_wm0 : 4; /**< Number of buffers free before a priority 0 packet 2440215976Sjmallett will be transmitted. A value of 9 will disable 2441215976Sjmallett this priority. */ 2442215976Sjmallett uint32_t rx_wm3 : 4; /**< Number of buffers free before a priority 3 packet 2443215976Sjmallett will be accepted. A value of 9 will disable this 2444215976Sjmallett priority and always cause a physical layer RETRY. */ 2445215976Sjmallett uint32_t rx_wm2 : 4; /**< Number of buffers free before a priority 2 packet 2446215976Sjmallett will be accepted. A value of 9 will disable this 2447215976Sjmallett priority and always cause a physical layer RETRY. */ 2448215976Sjmallett uint32_t rx_wm1 : 4; /**< Number of buffers free before a priority 1 packet 2449215976Sjmallett will be accepted. A value of 9 will disable this 2450215976Sjmallett priority and always cause a physical layer RETRY. */ 2451215976Sjmallett uint32_t rx_wm0 : 4; /**< Number of buffers free before a priority 0 packet 2452215976Sjmallett will be accepted. A value of 9 will disable this 2453215976Sjmallett priority and always cause a physical layer RETRY. */ 2454215976Sjmallett#else 2455215976Sjmallett uint32_t rx_wm0 : 4; 2456215976Sjmallett uint32_t rx_wm1 : 4; 2457215976Sjmallett uint32_t rx_wm2 : 4; 2458215976Sjmallett uint32_t rx_wm3 : 4; 2459215976Sjmallett uint32_t tx_wm0 : 4; 2460215976Sjmallett uint32_t tx_wm1 : 4; 2461215976Sjmallett uint32_t tx_wm2 : 4; 2462215976Sjmallett uint32_t tx_wm3 : 4; 2463215976Sjmallett#endif 2464215976Sjmallett } s; 2465215976Sjmallett struct cvmx_sriomaintx_ir_buffer_config2_s cn63xx; 2466232812Sjmallett struct cvmx_sriomaintx_ir_buffer_config2_s cn66xx; 2467215976Sjmallett}; 2468215976Sjmalletttypedef union cvmx_sriomaintx_ir_buffer_config2 cvmx_sriomaintx_ir_buffer_config2_t; 2469215976Sjmallett 2470215976Sjmallett/** 2471215976Sjmallett * cvmx_sriomaint#_ir_pd_phy_ctrl 2472215976Sjmallett * 2473215976Sjmallett * SRIOMAINT_IR_PD_PHY_CTRL = SRIO Platform Dependent PHY Control 2474215976Sjmallett * 2475215976Sjmallett * Platform Dependent PHY Control 2476215976Sjmallett * 2477215976Sjmallett * Notes: 2478215976Sjmallett * This register can be used for testing. The register is otherwise unused by the hardware. 2479215976Sjmallett * 2480232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_PD_PHY_CTRL hclk hrst_n 2481215976Sjmallett */ 2482232812Sjmallettunion cvmx_sriomaintx_ir_pd_phy_ctrl { 2483215976Sjmallett uint32_t u32; 2484232812Sjmallett struct cvmx_sriomaintx_ir_pd_phy_ctrl_s { 2485232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2486215976Sjmallett uint32_t pd_ctrl : 32; /**< Unused Register available for testing */ 2487215976Sjmallett#else 2488215976Sjmallett uint32_t pd_ctrl : 32; 2489215976Sjmallett#endif 2490215976Sjmallett } s; 2491215976Sjmallett struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xx; 2492215976Sjmallett struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xxp1; 2493232812Sjmallett struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn66xx; 2494215976Sjmallett}; 2495215976Sjmalletttypedef union cvmx_sriomaintx_ir_pd_phy_ctrl cvmx_sriomaintx_ir_pd_phy_ctrl_t; 2496215976Sjmallett 2497215976Sjmallett/** 2498215976Sjmallett * cvmx_sriomaint#_ir_pd_phy_stat 2499215976Sjmallett * 2500215976Sjmallett * SRIOMAINT_IR_PD_PHY_STAT = SRIO Platform Dependent PHY Status 2501215976Sjmallett * 2502215976Sjmallett * Platform Dependent PHY Status 2503215976Sjmallett * 2504215976Sjmallett * Notes: 2505215976Sjmallett * This register is used to monitor PHY status on each lane. They are documented here to assist in 2506215976Sjmallett * debugging only. The lane numbers take into account the lane swap pin. 2507215976Sjmallett * 2508232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_PD_PHY_STAT hclk hrst_n 2509215976Sjmallett */ 2510232812Sjmallettunion cvmx_sriomaintx_ir_pd_phy_stat { 2511215976Sjmallett uint32_t u32; 2512232812Sjmallett struct cvmx_sriomaintx_ir_pd_phy_stat_s { 2513232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2514215976Sjmallett uint32_t reserved_16_31 : 16; 2515215976Sjmallett uint32_t ln3_rx : 3; /**< Phy Lane 3 RX Status 2516215976Sjmallett 0XX = Normal Operation 2517215976Sjmallett 100 = 8B/10B Error 2518215976Sjmallett 101 = Elastic Buffer Overflow (Data Lost) 2519215976Sjmallett 110 = Elastic Buffer Underflow (Data Corrupted) 2520215976Sjmallett 111 = Disparity Error */ 2521215976Sjmallett uint32_t ln3_dis : 1; /**< Lane 3 Phy Clock Disabled 2522215976Sjmallett 0 = Phy Clock Valid 2523215976Sjmallett 1 = Phy Clock InValid */ 2524215976Sjmallett uint32_t ln2_rx : 3; /**< Phy Lane 2 RX Status 2525215976Sjmallett 0XX = Normal Operation 2526215976Sjmallett 100 = 8B/10B Error 2527215976Sjmallett 101 = Elastic Buffer Overflow (Data Lost) 2528215976Sjmallett 110 = Elastic Buffer Underflow (Data Corrupted) 2529215976Sjmallett 111 = Disparity Error */ 2530215976Sjmallett uint32_t ln2_dis : 1; /**< Lane 2 Phy Clock Disabled 2531215976Sjmallett 0 = Phy Clock Valid 2532215976Sjmallett 1 = Phy Clock InValid */ 2533215976Sjmallett uint32_t ln1_rx : 3; /**< Phy Lane 1 RX Status 2534215976Sjmallett 0XX = Normal Operation 2535215976Sjmallett 100 = 8B/10B Error 2536215976Sjmallett 101 = Elastic Buffer Overflow (Data Lost) 2537215976Sjmallett 110 = Elastic Buffer Underflow (Data Corrupted) 2538215976Sjmallett 111 = Disparity Error */ 2539215976Sjmallett uint32_t ln1_dis : 1; /**< Lane 1 Phy Clock Disabled 2540215976Sjmallett 0 = Phy Clock Valid 2541215976Sjmallett 1 = Phy Clock InValid */ 2542215976Sjmallett uint32_t ln0_rx : 3; /**< Phy Lane 0 RX Status 2543215976Sjmallett 0XX = Normal Operation 2544215976Sjmallett 100 = 8B/10B Error 2545215976Sjmallett 101 = Elastic Buffer Overflow (Data Lost) 2546215976Sjmallett 110 = Elastic Buffer Underflow (Data Corrupted) 2547215976Sjmallett 111 = Disparity Error */ 2548215976Sjmallett uint32_t ln0_dis : 1; /**< Lane 0 Phy Clock Disabled 2549215976Sjmallett 0 = Phy Clock Valid 2550215976Sjmallett 1 = Phy Clock InValid */ 2551215976Sjmallett#else 2552215976Sjmallett uint32_t ln0_dis : 1; 2553215976Sjmallett uint32_t ln0_rx : 3; 2554215976Sjmallett uint32_t ln1_dis : 1; 2555215976Sjmallett uint32_t ln1_rx : 3; 2556215976Sjmallett uint32_t ln2_dis : 1; 2557215976Sjmallett uint32_t ln2_rx : 3; 2558215976Sjmallett uint32_t ln3_dis : 1; 2559215976Sjmallett uint32_t ln3_rx : 3; 2560215976Sjmallett uint32_t reserved_16_31 : 16; 2561215976Sjmallett#endif 2562215976Sjmallett } s; 2563215976Sjmallett struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xx; 2564215976Sjmallett struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xxp1; 2565232812Sjmallett struct cvmx_sriomaintx_ir_pd_phy_stat_s cn66xx; 2566215976Sjmallett}; 2567215976Sjmalletttypedef union cvmx_sriomaintx_ir_pd_phy_stat cvmx_sriomaintx_ir_pd_phy_stat_t; 2568215976Sjmallett 2569215976Sjmallett/** 2570215976Sjmallett * cvmx_sriomaint#_ir_pi_phy_ctrl 2571215976Sjmallett * 2572215976Sjmallett * SRIOMAINT_IR_PI_PHY_CTRL = SRIO Platform Independent PHY Control 2573215976Sjmallett * 2574215976Sjmallett * Platform Independent PHY Control 2575215976Sjmallett * 2576215976Sjmallett * Notes: 2577215976Sjmallett * This register is used to control platform independent operating modes of the transceivers. These 2578215976Sjmallett * control bits are uniform across all platforms. 2579215976Sjmallett * 2580232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_PI_PHY_CTRL hclk hrst_n 2581215976Sjmallett */ 2582232812Sjmallettunion cvmx_sriomaintx_ir_pi_phy_ctrl { 2583215976Sjmallett uint32_t u32; 2584232812Sjmallett struct cvmx_sriomaintx_ir_pi_phy_ctrl_s { 2585232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2586215976Sjmallett uint32_t tx_reset : 1; /**< Outgoing PHY Logic Reset. 0=Reset, 1=Normal Op */ 2587215976Sjmallett uint32_t rx_reset : 1; /**< Incoming PHY Logic Reset. 0=Reset, 1=Normal Op */ 2588215976Sjmallett uint32_t reserved_29_29 : 1; 2589215976Sjmallett uint32_t loopback : 2; /**< These bits control the state of the loopback 2590215976Sjmallett control vector on the transceiver interface. The 2591215976Sjmallett loopback modes are enumerated as follows: 2592215976Sjmallett 00 - No Loopback 2593215976Sjmallett 01 - Near End PCS Loopback 2594215976Sjmallett 10 - Far End PCS Loopback 2595215976Sjmallett 11 - Both Near and Far End PCS Loopback */ 2596215976Sjmallett uint32_t reserved_0_26 : 27; 2597215976Sjmallett#else 2598215976Sjmallett uint32_t reserved_0_26 : 27; 2599215976Sjmallett uint32_t loopback : 2; 2600215976Sjmallett uint32_t reserved_29_29 : 1; 2601215976Sjmallett uint32_t rx_reset : 1; 2602215976Sjmallett uint32_t tx_reset : 1; 2603215976Sjmallett#endif 2604215976Sjmallett } s; 2605215976Sjmallett struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xx; 2606215976Sjmallett struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xxp1; 2607232812Sjmallett struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn66xx; 2608215976Sjmallett}; 2609215976Sjmalletttypedef union cvmx_sriomaintx_ir_pi_phy_ctrl cvmx_sriomaintx_ir_pi_phy_ctrl_t; 2610215976Sjmallett 2611215976Sjmallett/** 2612215976Sjmallett * cvmx_sriomaint#_ir_pi_phy_stat 2613215976Sjmallett * 2614215976Sjmallett * SRIOMAINT_IR_PI_PHY_STAT = SRIO Platform Independent PHY Status 2615215976Sjmallett * 2616215976Sjmallett * Platform Independent PHY Status 2617215976Sjmallett * 2618215976Sjmallett * Notes: 2619215976Sjmallett * This register displays the status of the link initialization state machine. Changes to this state 2620232812Sjmallett * cause the SRIO(0,2..3)_INT_REG.LINK_UP or SRIO(0,2..3)_INT_REG.LINK_DOWN interrupts. 2621215976Sjmallett * 2622232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_PI_PHY_STAT hclk hrst_n 2623215976Sjmallett */ 2624232812Sjmallettunion cvmx_sriomaintx_ir_pi_phy_stat { 2625215976Sjmallett uint32_t u32; 2626232812Sjmallett struct cvmx_sriomaintx_ir_pi_phy_stat_s { 2627232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2628215976Sjmallett uint32_t reserved_12_31 : 20; 2629232812Sjmallett uint32_t tx_rdy : 1; /**< Minimum number of Status Transmitted */ 2630232812Sjmallett uint32_t rx_rdy : 1; /**< Minimum number of Good Status Received */ 2631215976Sjmallett uint32_t init_sm : 10; /**< Initialization State Machine 2632215976Sjmallett 001 - Silent 2633215976Sjmallett 002 - Seek 2634215976Sjmallett 004 - Discovery 2635215976Sjmallett 008 - 1x_Mode_Lane0 2636215976Sjmallett 010 - 1x_Mode_Lane1 2637215976Sjmallett 020 - 1x_Mode_Lane2 2638215976Sjmallett 040 - 1x_Recovery 2639215976Sjmallett 080 - 2x_Mode 2640215976Sjmallett 100 - 2x_Recovery 2641215976Sjmallett 200 - 4x_Mode 2642215976Sjmallett All others are reserved */ 2643215976Sjmallett#else 2644215976Sjmallett uint32_t init_sm : 10; 2645215976Sjmallett uint32_t rx_rdy : 1; 2646215976Sjmallett uint32_t tx_rdy : 1; 2647215976Sjmallett uint32_t reserved_12_31 : 20; 2648215976Sjmallett#endif 2649215976Sjmallett } s; 2650215976Sjmallett struct cvmx_sriomaintx_ir_pi_phy_stat_s cn63xx; 2651232812Sjmallett struct cvmx_sriomaintx_ir_pi_phy_stat_cn63xxp1 { 2652232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2653215976Sjmallett uint32_t reserved_10_31 : 22; 2654215976Sjmallett uint32_t init_sm : 10; /**< Initialization State Machine 2655215976Sjmallett 001 - Silent 2656215976Sjmallett 002 - Seek 2657215976Sjmallett 004 - Discovery 2658215976Sjmallett 008 - 1x_Mode_Lane0 2659215976Sjmallett 010 - 1x_Mode_Lane1 2660215976Sjmallett 020 - 1x_Mode_Lane2 2661215976Sjmallett 040 - 1x_Recovery 2662215976Sjmallett 080 - 2x_Mode 2663215976Sjmallett 100 - 2x_Recovery 2664215976Sjmallett 200 - 4x_Mode 2665215976Sjmallett All others are reserved */ 2666215976Sjmallett#else 2667215976Sjmallett uint32_t init_sm : 10; 2668215976Sjmallett uint32_t reserved_10_31 : 22; 2669215976Sjmallett#endif 2670215976Sjmallett } cn63xxp1; 2671232812Sjmallett struct cvmx_sriomaintx_ir_pi_phy_stat_s cn66xx; 2672215976Sjmallett}; 2673215976Sjmalletttypedef union cvmx_sriomaintx_ir_pi_phy_stat cvmx_sriomaintx_ir_pi_phy_stat_t; 2674215976Sjmallett 2675215976Sjmallett/** 2676215976Sjmallett * cvmx_sriomaint#_ir_sp_rx_ctrl 2677215976Sjmallett * 2678215976Sjmallett * SRIOMAINT_IR_SP_RX_CTRL = SRIO Soft Packet FIFO Receive Control 2679215976Sjmallett * 2680215976Sjmallett * Soft Packet FIFO Receive Control 2681215976Sjmallett * 2682215976Sjmallett * Notes: 2683215976Sjmallett * This register is used to configure events generated by the reception of packets using the soft 2684215976Sjmallett * packet FIFO. 2685215976Sjmallett * 2686232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_RX_CTRL hclk hrst_n 2687215976Sjmallett */ 2688232812Sjmallettunion cvmx_sriomaintx_ir_sp_rx_ctrl { 2689215976Sjmallett uint32_t u32; 2690232812Sjmallett struct cvmx_sriomaintx_ir_sp_rx_ctrl_s { 2691232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2692215976Sjmallett uint32_t reserved_1_31 : 31; 2693215976Sjmallett uint32_t overwrt : 1; /**< When clear, SRIO drops received packets that should 2694215976Sjmallett enter the soft packet FIFO when the FIFO is full. 2695232812Sjmallett In this case, SRIO also increments 2696232812Sjmallett SRIOMAINT(0,2..3)_IR_SP_RX_STAT.DROP_CNT. When set, SRIO 2697215976Sjmallett stalls received packets that should enter the soft 2698215976Sjmallett packet FIFO when the FIFO is full. SRIO may stop 2699215976Sjmallett receiving any packets in this stall case if 2700215976Sjmallett software does not drain the receive soft packet 2701215976Sjmallett FIFO. */ 2702215976Sjmallett#else 2703215976Sjmallett uint32_t overwrt : 1; 2704215976Sjmallett uint32_t reserved_1_31 : 31; 2705215976Sjmallett#endif 2706215976Sjmallett } s; 2707215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xx; 2708215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xxp1; 2709232812Sjmallett struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn66xx; 2710215976Sjmallett}; 2711215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_rx_ctrl cvmx_sriomaintx_ir_sp_rx_ctrl_t; 2712215976Sjmallett 2713215976Sjmallett/** 2714215976Sjmallett * cvmx_sriomaint#_ir_sp_rx_data 2715215976Sjmallett * 2716215976Sjmallett * SRIOMAINT_IR_SP_RX_DATA = SRIO Soft Packet FIFO Receive Data 2717215976Sjmallett * 2718215976Sjmallett * Soft Packet FIFO Receive Data 2719215976Sjmallett * 2720215976Sjmallett * Notes: 2721215976Sjmallett * This register is used to read data from the soft packet FIFO. The Soft Packet FIFO contains the 2722215976Sjmallett * majority of the packet data received from the SRIO link. The packet does not include the Control 2723215976Sjmallett * Symbols or the initial byte containing AckId, 2 Reserved Bits and the CRF. In the case of packets 2724215976Sjmallett * with less than 80 bytes (including AckId byte) both the trailing CRC and Pad (if present) are 2725215976Sjmallett * included in the FIFO and Octet Count. In the case of a packet with exactly 80 bytes (including 2726215976Sjmallett * the AckId byte) the CRC is removed and the Pad is maintained so the Octet Count will read 81 bytes 2727215976Sjmallett * instead of the expected 83. In cases over 80 bytes the CRC at 80 bytes is removed but the 2728215976Sjmallett * trailing CRC and Pad (if necessary) are present. 2729215976Sjmallett * 2730232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_RX_DATA hclk hrst_n 2731215976Sjmallett */ 2732232812Sjmallettunion cvmx_sriomaintx_ir_sp_rx_data { 2733215976Sjmallett uint32_t u32; 2734232812Sjmallett struct cvmx_sriomaintx_ir_sp_rx_data_s { 2735232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2736215976Sjmallett uint32_t pkt_data : 32; /**< This register is used to read packet data from the 2737215976Sjmallett RX FIFO. */ 2738215976Sjmallett#else 2739215976Sjmallett uint32_t pkt_data : 32; 2740215976Sjmallett#endif 2741215976Sjmallett } s; 2742215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xx; 2743215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xxp1; 2744232812Sjmallett struct cvmx_sriomaintx_ir_sp_rx_data_s cn66xx; 2745215976Sjmallett}; 2746215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_rx_data cvmx_sriomaintx_ir_sp_rx_data_t; 2747215976Sjmallett 2748215976Sjmallett/** 2749215976Sjmallett * cvmx_sriomaint#_ir_sp_rx_stat 2750215976Sjmallett * 2751215976Sjmallett * SRIOMAINT_IR_SP_RX_STAT = SRIO Soft Packet FIFO Receive Status 2752215976Sjmallett * 2753215976Sjmallett * Soft Packet FIFO Receive Status 2754215976Sjmallett * 2755215976Sjmallett * Notes: 2756215976Sjmallett * This register is used to monitor the reception of packets using the soft packet FIFO. 2757215976Sjmallett * The HW sets SRIO_INT_REG[SOFT_RX] every time a packet arrives in the soft packet FIFO. To read 2758215976Sjmallett * out (one or more) packets, the following procedure may be best: 2759215976Sjmallett * (1) clear SRIO_INT_REG[SOFT_RX], 2760215976Sjmallett * (2) read this CSR to determine how many packets there are, 2761215976Sjmallett * (3) read the packets out (via SRIOMAINT*_IR_SP_RX_DATA). 2762215976Sjmallett * This procedure could lead to situations where SOFT_RX will be set even though there are currently 2763215976Sjmallett * no packets - the SW interrupt handler would need to properly handle this case 2764215976Sjmallett * 2765232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_RX_STAT hclk hrst_n 2766215976Sjmallett */ 2767232812Sjmallettunion cvmx_sriomaintx_ir_sp_rx_stat { 2768215976Sjmallett uint32_t u32; 2769232812Sjmallett struct cvmx_sriomaintx_ir_sp_rx_stat_s { 2770232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2771215976Sjmallett uint32_t octets : 16; /**< This field shows how many octets are remaining 2772215976Sjmallett in the current packet in the RX FIFO. */ 2773215976Sjmallett uint32_t buffers : 4; /**< This field indicates how many complete packets are 2774215976Sjmallett stored in the Rx FIFO. */ 2775215976Sjmallett uint32_t drop_cnt : 7; /**< Number of Packets Received when the RX FIFO was 2776232812Sjmallett full and then discarded. */ 2777215976Sjmallett uint32_t full : 1; /**< This bit is set when the value of Buffers Filled 2778232812Sjmallett equals the number of available reception buffers. */ 2779215976Sjmallett uint32_t fifo_st : 4; /**< These bits display the state of the state machine 2780215976Sjmallett that controls loading of packet data into the RX 2781215976Sjmallett FIFO. The enumeration of states are as follows: 2782215976Sjmallett 0000 - Idle 2783215976Sjmallett 0001 - Armed 2784215976Sjmallett 0010 - Active 2785215976Sjmallett All other states are reserved. */ 2786215976Sjmallett#else 2787215976Sjmallett uint32_t fifo_st : 4; 2788215976Sjmallett uint32_t full : 1; 2789215976Sjmallett uint32_t drop_cnt : 7; 2790215976Sjmallett uint32_t buffers : 4; 2791215976Sjmallett uint32_t octets : 16; 2792215976Sjmallett#endif 2793215976Sjmallett } s; 2794215976Sjmallett struct cvmx_sriomaintx_ir_sp_rx_stat_s cn63xx; 2795232812Sjmallett struct cvmx_sriomaintx_ir_sp_rx_stat_cn63xxp1 { 2796232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2797215976Sjmallett uint32_t octets : 16; /**< This field shows how many octets are remaining 2798215976Sjmallett in the current packet in the RX FIFO. */ 2799215976Sjmallett uint32_t buffers : 4; /**< This field indicates how many complete packets are 2800215976Sjmallett stored in the Rx FIFO. */ 2801215976Sjmallett uint32_t reserved_5_11 : 7; 2802215976Sjmallett uint32_t full : 1; /**< This bit is set when the value of Buffers Filled 2803215976Sjmallett equals the number of available reception buffers. 2804215976Sjmallett This bit always reads zero in Pass 1 */ 2805215976Sjmallett uint32_t fifo_st : 4; /**< These bits display the state of the state machine 2806215976Sjmallett that controls loading of packet data into the RX 2807215976Sjmallett FIFO. The enumeration of states are as follows: 2808215976Sjmallett 0000 - Idle 2809215976Sjmallett 0001 - Armed 2810215976Sjmallett 0010 - Active 2811215976Sjmallett All other states are reserved. */ 2812215976Sjmallett#else 2813215976Sjmallett uint32_t fifo_st : 4; 2814215976Sjmallett uint32_t full : 1; 2815215976Sjmallett uint32_t reserved_5_11 : 7; 2816215976Sjmallett uint32_t buffers : 4; 2817215976Sjmallett uint32_t octets : 16; 2818215976Sjmallett#endif 2819215976Sjmallett } cn63xxp1; 2820232812Sjmallett struct cvmx_sriomaintx_ir_sp_rx_stat_s cn66xx; 2821215976Sjmallett}; 2822215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_rx_stat cvmx_sriomaintx_ir_sp_rx_stat_t; 2823215976Sjmallett 2824215976Sjmallett/** 2825215976Sjmallett * cvmx_sriomaint#_ir_sp_tx_ctrl 2826215976Sjmallett * 2827215976Sjmallett * SRIOMAINT_IR_SP_TX_CTRL = SRIO Soft Packet FIFO Transmit Control 2828215976Sjmallett * 2829215976Sjmallett * Soft Packet FIFO Transmit Control 2830215976Sjmallett * 2831215976Sjmallett * Notes: 2832215976Sjmallett * This register is used to configure and control the transmission of packets using the soft packet 2833215976Sjmallett * FIFO. 2834215976Sjmallett * 2835215976Sjmallett * Clk_Rst: SRIOMAINT_IR_SP_TX_CTRL hclk hrst_n 2836215976Sjmallett */ 2837232812Sjmallettunion cvmx_sriomaintx_ir_sp_tx_ctrl { 2838215976Sjmallett uint32_t u32; 2839232812Sjmallett struct cvmx_sriomaintx_ir_sp_tx_ctrl_s { 2840232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2841215976Sjmallett uint32_t octets : 16; /**< Writing a non-zero value (N) to this field arms 2842215976Sjmallett the packet FIFO for packet transmission. The FIFO 2843215976Sjmallett control logic will transmit the next N bytes 2844215976Sjmallett written 4-bytes at a time to the 2845232812Sjmallett SRIOMAINT(0,2..3)_IR_SP_TX_DATA Register and create a 2846215976Sjmallett single RapidIO packet. */ 2847215976Sjmallett uint32_t reserved_0_15 : 16; 2848215976Sjmallett#else 2849215976Sjmallett uint32_t reserved_0_15 : 16; 2850215976Sjmallett uint32_t octets : 16; 2851215976Sjmallett#endif 2852215976Sjmallett } s; 2853215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xx; 2854215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xxp1; 2855232812Sjmallett struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn66xx; 2856215976Sjmallett}; 2857215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_tx_ctrl cvmx_sriomaintx_ir_sp_tx_ctrl_t; 2858215976Sjmallett 2859215976Sjmallett/** 2860215976Sjmallett * cvmx_sriomaint#_ir_sp_tx_data 2861215976Sjmallett * 2862215976Sjmallett * SRIOMAINT_IR_SP_TX_DATA = SRIO Soft Packet FIFO Transmit Data 2863215976Sjmallett * 2864215976Sjmallett * Soft Packet FIFO Transmit Data 2865215976Sjmallett * 2866215976Sjmallett * Notes: 2867215976Sjmallett * This register is used to write data to the soft packet FIFO. The format of the packet follows the 2868215976Sjmallett * Internal Packet Format (add link here). Care must be taken on creating TIDs for the packets which 2869215976Sjmallett * generate a response. Bits [7:6] of the 8 bit TID must be set for all Soft Packet FIFO generated 2870215976Sjmallett * packets. TID values of 0x00 - 0xBF are reserved for hardware generated Tags. The remainer of the 2871215976Sjmallett * TID[5:0] must be unique for each packet in flight and cannot be reused until a response is received 2872232812Sjmallett * in the SRIOMAINT(0,2..3)_IR_SP_RX_DATA register. 2873215976Sjmallett * 2874232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_TX_DATA hclk hrst_n 2875215976Sjmallett */ 2876232812Sjmallettunion cvmx_sriomaintx_ir_sp_tx_data { 2877215976Sjmallett uint32_t u32; 2878232812Sjmallett struct cvmx_sriomaintx_ir_sp_tx_data_s { 2879232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2880215976Sjmallett uint32_t pkt_data : 32; /**< This register is used to write packet data to the 2881215976Sjmallett Tx FIFO. Reads of this register will return zero. */ 2882215976Sjmallett#else 2883215976Sjmallett uint32_t pkt_data : 32; 2884215976Sjmallett#endif 2885215976Sjmallett } s; 2886215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xx; 2887215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xxp1; 2888232812Sjmallett struct cvmx_sriomaintx_ir_sp_tx_data_s cn66xx; 2889215976Sjmallett}; 2890215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_tx_data cvmx_sriomaintx_ir_sp_tx_data_t; 2891215976Sjmallett 2892215976Sjmallett/** 2893215976Sjmallett * cvmx_sriomaint#_ir_sp_tx_stat 2894215976Sjmallett * 2895215976Sjmallett * SRIOMAINT_IR_SP_TX_STAT = SRIO Soft Packet FIFO Transmit Status 2896215976Sjmallett * 2897215976Sjmallett * Soft Packet FIFO Transmit Status 2898215976Sjmallett * 2899215976Sjmallett * Notes: 2900215976Sjmallett * This register is used to monitor the transmission of packets using the soft packet FIFO. 2901215976Sjmallett * 2902232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_TX_STAT hclk hrst_n 2903215976Sjmallett */ 2904232812Sjmallettunion cvmx_sriomaintx_ir_sp_tx_stat { 2905215976Sjmallett uint32_t u32; 2906232812Sjmallett struct cvmx_sriomaintx_ir_sp_tx_stat_s { 2907232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2908215976Sjmallett uint32_t octets : 16; /**< This field shows how many octets are still to be 2909215976Sjmallett loaded in the current packet. */ 2910215976Sjmallett uint32_t buffers : 4; /**< This field indicates how many complete packets are 2911215976Sjmallett stored in the Tx FIFO. The field always reads 2912215976Sjmallett zero in the current hardware. */ 2913215976Sjmallett uint32_t reserved_5_11 : 7; 2914215976Sjmallett uint32_t full : 1; /**< This bit is set when the value of Buffers Filled 2915215976Sjmallett equals the number of available transmission 2916215976Sjmallett buffers. */ 2917215976Sjmallett uint32_t fifo_st : 4; /**< These bits display the state of the state machine 2918215976Sjmallett that controls loading of packet data into the TX 2919215976Sjmallett FIFO. The enumeration of states are as follows: 2920215976Sjmallett 0000 - Idle 2921215976Sjmallett 0001 - Armed 2922215976Sjmallett 0010 - Active 2923215976Sjmallett All other states are reserved. */ 2924215976Sjmallett#else 2925215976Sjmallett uint32_t fifo_st : 4; 2926215976Sjmallett uint32_t full : 1; 2927215976Sjmallett uint32_t reserved_5_11 : 7; 2928215976Sjmallett uint32_t buffers : 4; 2929215976Sjmallett uint32_t octets : 16; 2930215976Sjmallett#endif 2931215976Sjmallett } s; 2932215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xx; 2933215976Sjmallett struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xxp1; 2934232812Sjmallett struct cvmx_sriomaintx_ir_sp_tx_stat_s cn66xx; 2935215976Sjmallett}; 2936215976Sjmalletttypedef union cvmx_sriomaintx_ir_sp_tx_stat cvmx_sriomaintx_ir_sp_tx_stat_t; 2937215976Sjmallett 2938215976Sjmallett/** 2939215976Sjmallett * cvmx_sriomaint#_lane_#_status_0 2940215976Sjmallett * 2941215976Sjmallett * SRIOMAINT_LANE_X_STATUS_0 = SRIO Lane X Status 0 2942215976Sjmallett * 2943215976Sjmallett * SRIO Lane Status 0 2944215976Sjmallett * 2945215976Sjmallett * Notes: 2946215976Sjmallett * This register contains status information about the local lane transceiver. 2947215976Sjmallett * 2948232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_LANE_[0:3]_STATUS_0 hclk hrst_n 2949215976Sjmallett */ 2950232812Sjmallettunion cvmx_sriomaintx_lane_x_status_0 { 2951215976Sjmallett uint32_t u32; 2952232812Sjmallett struct cvmx_sriomaintx_lane_x_status_0_s { 2953232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2954215976Sjmallett uint32_t port : 8; /**< The number of the port within the device to which 2955215976Sjmallett the lane is assigned. */ 2956215976Sjmallett uint32_t lane : 4; /**< Lane Number within the port. */ 2957215976Sjmallett uint32_t tx_type : 1; /**< Transmitter Type 2958215976Sjmallett 0 = Short Run 2959215976Sjmallett 1 = Long Run */ 2960215976Sjmallett uint32_t tx_mode : 1; /**< Transmitter Operating Mode 2961215976Sjmallett 0 = Short Run 2962215976Sjmallett 1 = Long Run */ 2963215976Sjmallett uint32_t rx_type : 2; /**< Receiver Type 2964215976Sjmallett 0 = Short Run 2965215976Sjmallett 1 = Medium Run 2966215976Sjmallett 2 = Long Run 2967215976Sjmallett 3 = Reserved */ 2968215976Sjmallett uint32_t rx_inv : 1; /**< Receiver Input Inverted 2969215976Sjmallett 0 = No Inversion 2970215976Sjmallett 1 = Input Inverted */ 2971215976Sjmallett uint32_t rx_adapt : 1; /**< Receiver Trained 2972215976Sjmallett 0 = One or more adaptive equalizers are 2973215976Sjmallett controlled by the lane receiver and at least 2974215976Sjmallett one is not trained. 2975215976Sjmallett 1 = The lane receiver controls no adaptive 2976215976Sjmallett equalizers or all the equalizers are trained. */ 2977215976Sjmallett uint32_t rx_sync : 1; /**< Receiver Lane Sync'd */ 2978215976Sjmallett uint32_t rx_train : 1; /**< Receiver Lane Trained */ 2979215976Sjmallett uint32_t dec_err : 4; /**< 8Bit/10Bit Decoding Errors 2980215976Sjmallett 0 = No Errors since last read 2981215976Sjmallett 1-14 = Number of Errors since last read 2982215976Sjmallett 15 = Fifteen or more Errors since last read */ 2983215976Sjmallett uint32_t xsync : 1; /**< Receiver Lane Sync Change 2984215976Sjmallett 0 = Lane Sync has not changed since last read 2985215976Sjmallett 1 = Lane Sync has changed since last read */ 2986215976Sjmallett uint32_t xtrain : 1; /**< Receiver Training Change 2987215976Sjmallett 0 = Training has not changed since last read 2988215976Sjmallett 1 = Training has changed since last read */ 2989215976Sjmallett uint32_t reserved_4_5 : 2; 2990215976Sjmallett uint32_t status1 : 1; /**< Status 1 CSR Implemented */ 2991215976Sjmallett uint32_t statusn : 3; /**< Status 2-7 Not Implemented */ 2992215976Sjmallett#else 2993215976Sjmallett uint32_t statusn : 3; 2994215976Sjmallett uint32_t status1 : 1; 2995215976Sjmallett uint32_t reserved_4_5 : 2; 2996215976Sjmallett uint32_t xtrain : 1; 2997215976Sjmallett uint32_t xsync : 1; 2998215976Sjmallett uint32_t dec_err : 4; 2999215976Sjmallett uint32_t rx_train : 1; 3000215976Sjmallett uint32_t rx_sync : 1; 3001215976Sjmallett uint32_t rx_adapt : 1; 3002215976Sjmallett uint32_t rx_inv : 1; 3003215976Sjmallett uint32_t rx_type : 2; 3004215976Sjmallett uint32_t tx_mode : 1; 3005215976Sjmallett uint32_t tx_type : 1; 3006215976Sjmallett uint32_t lane : 4; 3007215976Sjmallett uint32_t port : 8; 3008215976Sjmallett#endif 3009215976Sjmallett } s; 3010215976Sjmallett struct cvmx_sriomaintx_lane_x_status_0_s cn63xx; 3011215976Sjmallett struct cvmx_sriomaintx_lane_x_status_0_s cn63xxp1; 3012232812Sjmallett struct cvmx_sriomaintx_lane_x_status_0_s cn66xx; 3013215976Sjmallett}; 3014215976Sjmalletttypedef union cvmx_sriomaintx_lane_x_status_0 cvmx_sriomaintx_lane_x_status_0_t; 3015215976Sjmallett 3016215976Sjmallett/** 3017215976Sjmallett * cvmx_sriomaint#_lcs_ba0 3018215976Sjmallett * 3019215976Sjmallett * SRIOMAINT_LCS_BA0 = SRIO Local Configuration Space MSB Base Address 3020215976Sjmallett * 3021215976Sjmallett * MSBs of SRIO Address Space mapped to Maintenance BAR. 3022215976Sjmallett * 3023215976Sjmallett * Notes: 3024215976Sjmallett * The double word aligned SRIO address window mapped to the SRIO Maintenance BAR. This window has 3025215976Sjmallett * the highest priority and eclipses matches to the BAR0, BAR1 and BAR2 windows. Note: Address bits 3026215976Sjmallett * not supplied in the transfer are considered zero. For example, SRIO Address 65:35 must be set to 3027215976Sjmallett * zero to match in a 34-bit access. SRIO Address 65:50 must be set to zero to match in a 50-bit 3028215976Sjmallett * access. This coding allows the Maintenance Bar window to appear in specific address spaces. The 3029232812Sjmallett * remaining bits are located in SRIOMAINT(0,2..3)_LCS_BA1. This SRIO maintenance BAR is effectively 3030215976Sjmallett * disabled when LCSBA[30] is set with 34 or 50-bit addressing. 3031215976Sjmallett * 3032232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_LCS_BA0 hclk hrst_n 3033215976Sjmallett */ 3034232812Sjmallettunion cvmx_sriomaintx_lcs_ba0 { 3035215976Sjmallett uint32_t u32; 3036232812Sjmallett struct cvmx_sriomaintx_lcs_ba0_s { 3037232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3038215976Sjmallett uint32_t reserved_31_31 : 1; 3039215976Sjmallett uint32_t lcsba : 31; /**< SRIO Address 65:35 */ 3040215976Sjmallett#else 3041215976Sjmallett uint32_t lcsba : 31; 3042215976Sjmallett uint32_t reserved_31_31 : 1; 3043215976Sjmallett#endif 3044215976Sjmallett } s; 3045215976Sjmallett struct cvmx_sriomaintx_lcs_ba0_s cn63xx; 3046215976Sjmallett struct cvmx_sriomaintx_lcs_ba0_s cn63xxp1; 3047232812Sjmallett struct cvmx_sriomaintx_lcs_ba0_s cn66xx; 3048215976Sjmallett}; 3049215976Sjmalletttypedef union cvmx_sriomaintx_lcs_ba0 cvmx_sriomaintx_lcs_ba0_t; 3050215976Sjmallett 3051215976Sjmallett/** 3052215976Sjmallett * cvmx_sriomaint#_lcs_ba1 3053215976Sjmallett * 3054215976Sjmallett * SRIOMAINT_LCS_BA1 = SRIO Local Configuration Space LSB Base Address 3055215976Sjmallett * 3056215976Sjmallett * LSBs of SRIO Address Space mapped to Maintenance BAR. 3057215976Sjmallett * 3058215976Sjmallett * Notes: 3059215976Sjmallett * The double word aligned SRIO address window mapped to the SRIO Maintenance BAR. This window has 3060215976Sjmallett * the highest priority and eclipses matches to the BAR0, BAR1 and BAR2 windows. Address bits not 3061215976Sjmallett * supplied in the transfer are considered zero. For example, SRIO Address 65:35 must be set to zero 3062215976Sjmallett * to match in a 34-bit access and SRIO Address 65:50 must be set to zero to match in a 50-bit access. 3063215976Sjmallett * This coding allows the Maintenance Bar window to appear in specific address spaces. Accesses 3064215976Sjmallett * through this BAR are limited to single word (32-bit) aligned transfers of one to four bytes. 3065215976Sjmallett * Accesses which violate this rule will return an error response if possible and be otherwise 3066232812Sjmallett * ignored. The remaining bits are located in SRIOMAINT(0,2..3)_LCS_BA0. 3067215976Sjmallett * 3068232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_LCS_BA1 hclk hrst_n 3069215976Sjmallett */ 3070232812Sjmallettunion cvmx_sriomaintx_lcs_ba1 { 3071215976Sjmallett uint32_t u32; 3072232812Sjmallett struct cvmx_sriomaintx_lcs_ba1_s { 3073232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3074215976Sjmallett uint32_t lcsba : 11; /**< SRIO Address 34:24 */ 3075215976Sjmallett uint32_t reserved_0_20 : 21; 3076215976Sjmallett#else 3077215976Sjmallett uint32_t reserved_0_20 : 21; 3078215976Sjmallett uint32_t lcsba : 11; 3079215976Sjmallett#endif 3080215976Sjmallett } s; 3081215976Sjmallett struct cvmx_sriomaintx_lcs_ba1_s cn63xx; 3082215976Sjmallett struct cvmx_sriomaintx_lcs_ba1_s cn63xxp1; 3083232812Sjmallett struct cvmx_sriomaintx_lcs_ba1_s cn66xx; 3084215976Sjmallett}; 3085215976Sjmalletttypedef union cvmx_sriomaintx_lcs_ba1 cvmx_sriomaintx_lcs_ba1_t; 3086215976Sjmallett 3087215976Sjmallett/** 3088215976Sjmallett * cvmx_sriomaint#_m2s_bar0_start0 3089215976Sjmallett * 3090215976Sjmallett * SRIOMAINT_M2S_BAR0_START0 = SRIO Device Access BAR0 MSB Start 3091215976Sjmallett * 3092215976Sjmallett * The starting SRIO address to forwarded to the NPEI Configuration Space. 3093215976Sjmallett * 3094215976Sjmallett * Notes: 3095215976Sjmallett * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR0 Space. See 3096232812Sjmallett * SRIOMAINT(0,2..3)_M2S_BAR0_START1 for more details. This register is only writeable over SRIO if the 3097232812Sjmallett * SRIO(0,2..3)_ACC_CTRL.DENY_BAR0 bit is zero. 3098215976Sjmallett * 3099232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR0_START0 hclk hrst_n 3100215976Sjmallett */ 3101232812Sjmallettunion cvmx_sriomaintx_m2s_bar0_start0 { 3102215976Sjmallett uint32_t u32; 3103232812Sjmallett struct cvmx_sriomaintx_m2s_bar0_start0_s { 3104232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3105215976Sjmallett uint32_t addr64 : 16; /**< SRIO Address 63:48 */ 3106215976Sjmallett uint32_t addr48 : 16; /**< SRIO Address 47:32 */ 3107215976Sjmallett#else 3108215976Sjmallett uint32_t addr48 : 16; 3109215976Sjmallett uint32_t addr64 : 16; 3110215976Sjmallett#endif 3111215976Sjmallett } s; 3112215976Sjmallett struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xx; 3113215976Sjmallett struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xxp1; 3114232812Sjmallett struct cvmx_sriomaintx_m2s_bar0_start0_s cn66xx; 3115215976Sjmallett}; 3116215976Sjmalletttypedef union cvmx_sriomaintx_m2s_bar0_start0 cvmx_sriomaintx_m2s_bar0_start0_t; 3117215976Sjmallett 3118215976Sjmallett/** 3119215976Sjmallett * cvmx_sriomaint#_m2s_bar0_start1 3120215976Sjmallett * 3121215976Sjmallett * SRIOMAINT_M2S_BAR0_START1 = SRIO Device Access BAR0 LSB Start 3122215976Sjmallett * 3123215976Sjmallett * The starting SRIO address to forwarded to the NPEI Configuration Space. 3124215976Sjmallett * 3125215976Sjmallett * Notes: 3126215976Sjmallett * This register specifies the SRIO Address mapped to the BAR0 RSL Space. If the transaction has not 3127215976Sjmallett * already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers, if 3128215976Sjmallett * ENABLE is set and the address bits match then the SRIO Memory transactions will map to Octeon SLI 3129215976Sjmallett * Registers. 34-bit address transactions require a match in SRIO Address 33:14 and require all the 3130215976Sjmallett * other bits in ADDR48, ADDR64 and ADDR66 fields to be zero. 50-bit address transactions a match of 3131215976Sjmallett * SRIO Address 49:14 and require all the other bits of ADDR64 and ADDR66 to be zero. 66-bit address 3132215976Sjmallett * transactions require matches of all valid address field bits. Reads and Writes through Bar0 3133215976Sjmallett * have a size limit of 8 bytes and cannot cross a 64-bit boundry. All accesses with sizes greater 3134215976Sjmallett * than this limit will be ignored and return an error on any SRIO responses. Note: ADDR48 and 3135232812Sjmallett * ADDR64 fields are located in SRIOMAINT(0,2..3)_M2S_BAR0_START0. The ADDR32/66 fields of this register 3136232812Sjmallett * are writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_ADR0 bit is zero. The ENABLE field is 3137232812Sjmallett * writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_BAR0 bit is zero. 3138215976Sjmallett * 3139232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR0_START1 hclk hrst_n 3140215976Sjmallett */ 3141232812Sjmallettunion cvmx_sriomaintx_m2s_bar0_start1 { 3142215976Sjmallett uint32_t u32; 3143232812Sjmallett struct cvmx_sriomaintx_m2s_bar0_start1_s { 3144232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3145215976Sjmallett uint32_t addr32 : 18; /**< SRIO Address 31:14 */ 3146215976Sjmallett uint32_t reserved_3_13 : 11; 3147215976Sjmallett uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3148215976Sjmallett uint32_t enable : 1; /**< Enable BAR0 Access */ 3149215976Sjmallett#else 3150215976Sjmallett uint32_t enable : 1; 3151215976Sjmallett uint32_t addr66 : 2; 3152215976Sjmallett uint32_t reserved_3_13 : 11; 3153215976Sjmallett uint32_t addr32 : 18; 3154215976Sjmallett#endif 3155215976Sjmallett } s; 3156215976Sjmallett struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xx; 3157215976Sjmallett struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xxp1; 3158232812Sjmallett struct cvmx_sriomaintx_m2s_bar0_start1_s cn66xx; 3159215976Sjmallett}; 3160215976Sjmalletttypedef union cvmx_sriomaintx_m2s_bar0_start1 cvmx_sriomaintx_m2s_bar0_start1_t; 3161215976Sjmallett 3162215976Sjmallett/** 3163215976Sjmallett * cvmx_sriomaint#_m2s_bar1_start0 3164215976Sjmallett * 3165215976Sjmallett * SRIOMAINT_M2S_BAR1_START0 = SRIO Device Access BAR1 MSB Start 3166215976Sjmallett * 3167215976Sjmallett * The starting SRIO address to forwarded to the BAR1 Memory Space. 3168215976Sjmallett * 3169215976Sjmallett * Notes: 3170215976Sjmallett * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR1 Space. See 3171232812Sjmallett * SRIOMAINT(0,2..3)_M2S_BAR1_START1 for more details. This register is only writeable over SRIO if the 3172232812Sjmallett * SRIO(0,2..3)_ACC_CTRL.DENY_ADR1 bit is zero. 3173215976Sjmallett * 3174232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR1_START0 hclk hrst_n 3175215976Sjmallett */ 3176232812Sjmallettunion cvmx_sriomaintx_m2s_bar1_start0 { 3177215976Sjmallett uint32_t u32; 3178232812Sjmallett struct cvmx_sriomaintx_m2s_bar1_start0_s { 3179232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3180215976Sjmallett uint32_t addr64 : 16; /**< SRIO Address 63:48 */ 3181232812Sjmallett uint32_t addr48 : 16; /**< SRIO Address 47:32 3182232812Sjmallett The SRIO hardware does not use the low order 3183232812Sjmallett one or two bits of this field when BARSIZE is 12 3184232812Sjmallett or 13, respectively. 3185232812Sjmallett (BARSIZE is SRIOMAINT(0,2..3)_M2S_BAR1_START1[BARSIZE].) */ 3186215976Sjmallett#else 3187215976Sjmallett uint32_t addr48 : 16; 3188215976Sjmallett uint32_t addr64 : 16; 3189215976Sjmallett#endif 3190215976Sjmallett } s; 3191215976Sjmallett struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xx; 3192215976Sjmallett struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xxp1; 3193232812Sjmallett struct cvmx_sriomaintx_m2s_bar1_start0_s cn66xx; 3194215976Sjmallett}; 3195215976Sjmalletttypedef union cvmx_sriomaintx_m2s_bar1_start0 cvmx_sriomaintx_m2s_bar1_start0_t; 3196215976Sjmallett 3197215976Sjmallett/** 3198215976Sjmallett * cvmx_sriomaint#_m2s_bar1_start1 3199215976Sjmallett * 3200215976Sjmallett * SRIOMAINT_M2S_BAR1_START1 = SRIO Device to BAR1 Start 3201215976Sjmallett * 3202215976Sjmallett * The starting SRIO address to forwarded to the BAR1 Memory Space. 3203215976Sjmallett * 3204215976Sjmallett * Notes: 3205215976Sjmallett * This register specifies the SRIO Address mapped to the BAR1 Space. If the transaction has not 3206215976Sjmallett * already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers and the 3207215976Sjmallett * address bits do not match enabled BAR0 addresses and if ENABLE is set and the addresses match the 3208215976Sjmallett * BAR1 addresses then SRIO Memory transactions will map to Octeon Memory Space specified by 3209232812Sjmallett * SRIOMAINT(0,2..3)_BAR1_IDX[31:0] registers. The BARSIZE field determines the size of BAR1, the entry 3210215976Sjmallett * select bits, and the size of each entry. A 34-bit address matches BAR1 when it matches 3211215976Sjmallett * SRIO_Address[33:20+BARSIZE] while all the other bits in ADDR48, ADDR64 and ADDR66 are zero. 3212215976Sjmallett * A 50-bit address matches BAR1 when it matches SRIO_Address[49:20+BARSIZE] while all the 3213215976Sjmallett * other bits of ADDR64 and ADDR66 are zero. A 66-bit address matches BAR1 when all of 3214215976Sjmallett * SRIO_Address[65:20+BARSIZE] match all corresponding address CSR field bits. Note: ADDR48 and 3215232812Sjmallett * ADDR64 fields are located in SRIOMAINT(0,2..3)_M2S_BAR1_START0. The ADDR32/66 fields of this register 3216232812Sjmallett * are writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_ADR1 bit is zero. The remaining fields are 3217232812Sjmallett * writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_BAR1 bit is zero. 3218215976Sjmallett * 3219232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR1_START1 hclk hrst_n 3220215976Sjmallett */ 3221232812Sjmallettunion cvmx_sriomaintx_m2s_bar1_start1 { 3222215976Sjmallett uint32_t u32; 3223232812Sjmallett struct cvmx_sriomaintx_m2s_bar1_start1_s { 3224232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3225215976Sjmallett uint32_t addr32 : 12; /**< SRIO Address 31:20 3226232812Sjmallett This field is not used by the SRIO hardware for 3227232812Sjmallett BARSIZE values 12 or 13. 3228215976Sjmallett With BARSIZE < 12, the upper 12-BARSIZE 3229215976Sjmallett bits of this field are used, and the lower BARSIZE 3230215976Sjmallett bits of this field are unused by the SRIO hardware. */ 3231215976Sjmallett uint32_t reserved_7_19 : 13; 3232215976Sjmallett uint32_t barsize : 4; /**< Bar Size. 3233215976Sjmallett SRIO_Address* 3234215976Sjmallett --------------------- 3235215976Sjmallett / \ 3236215976Sjmallett BARSIZE BAR Entry Entry Entry 3237215976Sjmallett Value BAR compare Select Offset Size 3238215976Sjmallett Size bits bits bits 3239215976Sjmallett 0 1MB 65:20 19:16 15:0 64KB 3240215976Sjmallett 1 2MB 65:21 20:17 16:0 128KB 3241215976Sjmallett 2 4MB 65:22 21:18 17:0 256KB 3242215976Sjmallett 3 8MB 65:23 22:19 18:0 512KB 3243215976Sjmallett 4 16MB 65:24 23:20 19:0 1MB 3244215976Sjmallett 5 32MB 65:25 24:21 20:0 2MB 3245215976Sjmallett 6 64MB 65:26 25:22 21:0 4MB 3246215976Sjmallett 7 128MB 65:27 26:23 22:0 8MB 3247232812Sjmallett 8 256MB 65:28 27:24 23:0 16MB 3248232812Sjmallett 9 512MB 65:29 28:25 24:0 32MB 3249232812Sjmallett 10 1024MB 65:30 29:26 25:0 64MB 3250232812Sjmallett 11 2048MB 65:31 30:27 26:0 128MB 3251232812Sjmallett 12 4096MB 65:32 31:28 27:0 256MB 3252232812Sjmallett 13 8192MB 65:33 32:29 28:0 512MB 3253215976Sjmallett 3254215976Sjmallett *The SRIO Transaction Address 3255215976Sjmallett The entry select bits is the X that select an 3256232812Sjmallett SRIOMAINT(0,2..3)_BAR1_IDXX entry. */ 3257215976Sjmallett uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3258215976Sjmallett uint32_t enable : 1; /**< Enable BAR1 Access */ 3259215976Sjmallett#else 3260215976Sjmallett uint32_t enable : 1; 3261215976Sjmallett uint32_t addr66 : 2; 3262215976Sjmallett uint32_t barsize : 4; 3263215976Sjmallett uint32_t reserved_7_19 : 13; 3264215976Sjmallett uint32_t addr32 : 12; 3265215976Sjmallett#endif 3266215976Sjmallett } s; 3267215976Sjmallett struct cvmx_sriomaintx_m2s_bar1_start1_s cn63xx; 3268232812Sjmallett struct cvmx_sriomaintx_m2s_bar1_start1_cn63xxp1 { 3269232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3270215976Sjmallett uint32_t addr32 : 12; /**< SRIO Address 31:20 3271215976Sjmallett With BARSIZE < 12, the upper 12-BARSIZE 3272215976Sjmallett bits of this field are used, and the lower BARSIZE 3273215976Sjmallett bits of this field are unused by the SRIO hardware. */ 3274215976Sjmallett uint32_t reserved_6_19 : 14; 3275215976Sjmallett uint32_t barsize : 3; /**< Bar Size. 3276215976Sjmallett SRIO_Address* 3277215976Sjmallett --------------------- 3278215976Sjmallett / \ 3279215976Sjmallett BARSIZE BAR Entry Entry Entry 3280215976Sjmallett Value BAR compare Select Offset Size 3281215976Sjmallett Size bits bits bits 3282215976Sjmallett 0 1MB 65:20 19:16 15:0 64KB 3283215976Sjmallett 1 2MB 65:21 20:17 16:0 128KB 3284215976Sjmallett 2 4MB 65:22 21:18 17:0 256KB 3285215976Sjmallett 3 8MB 65:23 22:19 18:0 512KB 3286215976Sjmallett 4 16MB 65:24 23:20 19:0 1MB 3287215976Sjmallett 5 32MB 65:25 24:21 20:0 2MB 3288215976Sjmallett 6 64MB 65:26 25:22 21:0 4MB 3289215976Sjmallett 7 128MB 65:27 26:23 22:0 8MB 3290215976Sjmallett 8 256MB ** not in pass 1 3291215976Sjmallett 9 512MB ** not in pass 1 3292215976Sjmallett 10 1GB ** not in pass 1 3293215976Sjmallett 11 2GB ** not in pass 1 3294215976Sjmallett 12 4GB ** not in pass 1 3295215976Sjmallett 13 8GB ** not in pass 1 3296215976Sjmallett 3297215976Sjmallett *The SRIO Transaction Address 3298215976Sjmallett The entry select bits is the X that select an 3299215976Sjmallett SRIOMAINT(0..1)_BAR1_IDXX entry. 3300215976Sjmallett 3301215976Sjmallett In O63 pass 2, BARSIZE is 4 bits (6:3 in this 3302215976Sjmallett CSR), and BARSIZE values 8-13 are implemented, 3303215976Sjmallett providing a total possible BAR1 size range from 3304215976Sjmallett 1MB up to 8GB. */ 3305215976Sjmallett uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3306215976Sjmallett uint32_t enable : 1; /**< Enable BAR1 Access */ 3307215976Sjmallett#else 3308215976Sjmallett uint32_t enable : 1; 3309215976Sjmallett uint32_t addr66 : 2; 3310215976Sjmallett uint32_t barsize : 3; 3311215976Sjmallett uint32_t reserved_6_19 : 14; 3312215976Sjmallett uint32_t addr32 : 12; 3313215976Sjmallett#endif 3314215976Sjmallett } cn63xxp1; 3315232812Sjmallett struct cvmx_sriomaintx_m2s_bar1_start1_s cn66xx; 3316215976Sjmallett}; 3317215976Sjmalletttypedef union cvmx_sriomaintx_m2s_bar1_start1 cvmx_sriomaintx_m2s_bar1_start1_t; 3318215976Sjmallett 3319215976Sjmallett/** 3320215976Sjmallett * cvmx_sriomaint#_m2s_bar2_start 3321215976Sjmallett * 3322215976Sjmallett * SRIOMAINT_M2S_BAR2_START = SRIO Device to BAR2 Start 3323215976Sjmallett * 3324215976Sjmallett * The starting SRIO address to forwarded to the BAR2 Memory Space. 3325215976Sjmallett * 3326215976Sjmallett * Notes: 3327215976Sjmallett * This register specifies the SRIO Address mapped to the BAR2 Space. If ENABLE is set and the 3328215976Sjmallett * address bits do not match and other enabled BAR address and match the BAR2 addresses then the SRIO 3329215976Sjmallett * Memory transactions will map to Octeon BAR2 Memory Space. 34-bit address transactions require 3330215976Sjmallett * ADDR66, ADDR64 and ADDR48 fields set to zero and supplies zeros for unused addresses 40:34. 3331215976Sjmallett * 50-bit address transactions a match of SRIO Address 49:41 and require all the other bits of ADDR64 3332215976Sjmallett * and ADDR66 to be zero. 66-bit address transactions require matches of all valid address field 3333232812Sjmallett * bits. The ADDR32/48/64/66 fields of this register are writeable over SRIO if the 3334232812Sjmallett * SRIO(0,2..3)_ACC_CTRL.DENY_ADR2 bit is zero. The remaining fields are writeable over SRIO if the 3335232812Sjmallett * SRIO(0,2..3)_ACC_CTRL.DENY_BAR2 bit is zero. 3336215976Sjmallett * 3337232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR2_START hclk hrst_n 3338215976Sjmallett */ 3339232812Sjmallettunion cvmx_sriomaintx_m2s_bar2_start { 3340215976Sjmallett uint32_t u32; 3341232812Sjmallett struct cvmx_sriomaintx_m2s_bar2_start_s { 3342232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3343215976Sjmallett uint32_t addr64 : 16; /**< SRIO Address 63:48 */ 3344215976Sjmallett uint32_t addr48 : 7; /**< SRIO Address 47:41 */ 3345215976Sjmallett uint32_t reserved_6_8 : 3; 3346215976Sjmallett uint32_t esx : 2; /**< Endian Swap Mode used for SRIO 34-bit access. 3347215976Sjmallett For 50/66-bit assesses Endian Swap is determine 3348215976Sjmallett by ESX XOR'd with SRIO Addr 39:38. 3349215976Sjmallett 0 = No Swap 3350215976Sjmallett 1 = 64-bit Swap Bytes [ABCD_EFGH] -> [HGFE_DCBA] 3351215976Sjmallett 2 = 32-bit Swap Words [ABCD_EFGH] -> [DCBA_HGFE] 3352215976Sjmallett 3 = 32-bit Word Exch [ABCD_EFGH] -> [EFGH_ABCD] */ 3353215976Sjmallett uint32_t cax : 1; /**< Cacheable Access Mode. When set transfer is 3354215976Sjmallett cached. This bit is used for SRIO 34-bit access. 3355215976Sjmallett For 50/66-bit accessas NCA is determine by CAX 3356215976Sjmallett XOR'd with SRIO Addr 40. */ 3357215976Sjmallett uint32_t addr66 : 2; /**< SRIO Address 65:64 */ 3358215976Sjmallett uint32_t enable : 1; /**< Enable BAR2 Access */ 3359215976Sjmallett#else 3360215976Sjmallett uint32_t enable : 1; 3361215976Sjmallett uint32_t addr66 : 2; 3362215976Sjmallett uint32_t cax : 1; 3363215976Sjmallett uint32_t esx : 2; 3364215976Sjmallett uint32_t reserved_6_8 : 3; 3365215976Sjmallett uint32_t addr48 : 7; 3366215976Sjmallett uint32_t addr64 : 16; 3367215976Sjmallett#endif 3368215976Sjmallett } s; 3369215976Sjmallett struct cvmx_sriomaintx_m2s_bar2_start_s cn63xx; 3370215976Sjmallett struct cvmx_sriomaintx_m2s_bar2_start_s cn63xxp1; 3371232812Sjmallett struct cvmx_sriomaintx_m2s_bar2_start_s cn66xx; 3372215976Sjmallett}; 3373215976Sjmalletttypedef union cvmx_sriomaintx_m2s_bar2_start cvmx_sriomaintx_m2s_bar2_start_t; 3374215976Sjmallett 3375215976Sjmallett/** 3376215976Sjmallett * cvmx_sriomaint#_mac_ctrl 3377215976Sjmallett * 3378232812Sjmallett * SRIOMAINT_MAC_CTRL = SRIO MAC Control 3379215976Sjmallett * 3380215976Sjmallett * Control for MAC Features 3381215976Sjmallett * 3382215976Sjmallett * Notes: 3383215976Sjmallett * This register enables MAC optimizations that may not be supported by all SRIO devices. The 3384215976Sjmallett * default values should be supported. This register can be changed at any time while the MAC is 3385215976Sjmallett * out of reset. 3386215976Sjmallett * 3387232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_MAC_CTRL hclk hrst_n 3388215976Sjmallett */ 3389232812Sjmallettunion cvmx_sriomaintx_mac_ctrl { 3390215976Sjmallett uint32_t u32; 3391232812Sjmallett struct cvmx_sriomaintx_mac_ctrl_s { 3392232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3393232812Sjmallett uint32_t reserved_21_31 : 11; 3394232812Sjmallett uint32_t sec_spf : 1; /**< Send all Incoming Packets matching Secondary ID to 3395232812Sjmallett RX Soft Packet FIFO. This bit is ignored if 3396232812Sjmallett RX_SPF is set. */ 3397232812Sjmallett uint32_t ack_zero : 1; /**< Generate ACKs for all incoming Zero Byte packets. 3398232812Sjmallett Default behavior is to issue a NACK. Regardless 3399232812Sjmallett of this setting the SRIO(0,2..3)_INT_REG.ZERO_PKT 3400232812Sjmallett interrupt is generated. 3401232812Sjmallett SRIO(0,2..3)_INT_REG. */ 3402215976Sjmallett uint32_t rx_spf : 1; /**< Route all received packets to RX Soft Packet FIFO. 3403215976Sjmallett No logical layer ERB Errors will be reported. 3404215976Sjmallett Used for Diagnostics Only. */ 3405215976Sjmallett uint32_t eop_mrg : 1; /**< Transmitted Packets can eliminate EOP Symbol on 3406215976Sjmallett back to back packets. */ 3407215976Sjmallett uint32_t type_mrg : 1; /**< Allow STYPE Merging on Transmit. */ 3408215976Sjmallett uint32_t lnk_rtry : 16; /**< Number of times MAC will reissue Link Request 3409215976Sjmallett after timeout. If retry count is exceeded Fatal 3410232812Sjmallett Port Error will occur (see SRIO(0,2..3)_INT_REG.F_ERROR) */ 3411232812Sjmallett#else 3412232812Sjmallett uint32_t lnk_rtry : 16; 3413232812Sjmallett uint32_t type_mrg : 1; 3414232812Sjmallett uint32_t eop_mrg : 1; 3415232812Sjmallett uint32_t rx_spf : 1; 3416232812Sjmallett uint32_t ack_zero : 1; 3417232812Sjmallett uint32_t sec_spf : 1; 3418232812Sjmallett uint32_t reserved_21_31 : 11; 3419232812Sjmallett#endif 3420232812Sjmallett } s; 3421232812Sjmallett struct cvmx_sriomaintx_mac_ctrl_cn63xx { 3422232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3423232812Sjmallett uint32_t reserved_20_31 : 12; 3424232812Sjmallett uint32_t ack_zero : 1; /**< Generate ACKs for all incoming Zero Byte packets. 3425232812Sjmallett Default behavior is to issue a NACK. Regardless 3426232812Sjmallett of this setting the SRIO(0..1)_INT_REG.ZERO_PKT 3427232812Sjmallett interrupt is generated. 3428232812Sjmallett SRIO(0..1)_INT_REG. */ 3429232812Sjmallett uint32_t rx_spf : 1; /**< Route all received packets to RX Soft Packet FIFO. 3430232812Sjmallett No logical layer ERB Errors will be reported. 3431232812Sjmallett Used for Diagnostics Only. */ 3432232812Sjmallett uint32_t eop_mrg : 1; /**< Transmitted Packets can eliminate EOP Symbol on 3433232812Sjmallett back to back packets. */ 3434232812Sjmallett uint32_t type_mrg : 1; /**< Allow STYPE Merging on Transmit. */ 3435232812Sjmallett uint32_t lnk_rtry : 16; /**< Number of times MAC will reissue Link Request 3436232812Sjmallett after timeout. If retry count is exceeded Fatal 3437215976Sjmallett Port Error will occur (see SRIO(0..1)_INT_REG.F_ERROR) */ 3438215976Sjmallett#else 3439215976Sjmallett uint32_t lnk_rtry : 16; 3440215976Sjmallett uint32_t type_mrg : 1; 3441215976Sjmallett uint32_t eop_mrg : 1; 3442215976Sjmallett uint32_t rx_spf : 1; 3443232812Sjmallett uint32_t ack_zero : 1; 3444232812Sjmallett uint32_t reserved_20_31 : 12; 3445215976Sjmallett#endif 3446232812Sjmallett } cn63xx; 3447232812Sjmallett struct cvmx_sriomaintx_mac_ctrl_s cn66xx; 3448215976Sjmallett}; 3449215976Sjmalletttypedef union cvmx_sriomaintx_mac_ctrl cvmx_sriomaintx_mac_ctrl_t; 3450215976Sjmallett 3451215976Sjmallett/** 3452215976Sjmallett * cvmx_sriomaint#_pe_feat 3453215976Sjmallett * 3454215976Sjmallett * SRIOMAINT_PE_FEAT = SRIO Processing Element Features 3455215976Sjmallett * 3456215976Sjmallett * The Supported Processing Element Features. 3457215976Sjmallett * 3458215976Sjmallett * Notes: 3459215976Sjmallett * The Processing Element Feature register describes the major functionality provided by the SRIO 3460215976Sjmallett * device. 3461215976Sjmallett * 3462232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PE_FEAT hclk hrst_n 3463215976Sjmallett */ 3464232812Sjmallettunion cvmx_sriomaintx_pe_feat { 3465215976Sjmallett uint32_t u32; 3466232812Sjmallett struct cvmx_sriomaintx_pe_feat_s { 3467232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3468215976Sjmallett uint32_t bridge : 1; /**< Bridge Functions not supported. */ 3469215976Sjmallett uint32_t memory : 1; /**< PE contains addressable memory. */ 3470215976Sjmallett uint32_t proc : 1; /**< PE contains a local processor. */ 3471215976Sjmallett uint32_t switchf : 1; /**< Switch Functions not supported. */ 3472215976Sjmallett uint32_t mult_prt : 1; /**< Multiport Functions not supported. */ 3473215976Sjmallett uint32_t reserved_7_26 : 20; 3474215976Sjmallett uint32_t suppress : 1; /**< Error Recovery Suppression not supported. */ 3475215976Sjmallett uint32_t crf : 1; /**< Critical Request Flow not supported. */ 3476215976Sjmallett uint32_t lg_tran : 1; /**< Large Transport (16-bit Device IDs) supported. */ 3477215976Sjmallett uint32_t ex_feat : 1; /**< Extended Feature Pointer is valid. */ 3478215976Sjmallett uint32_t ex_addr : 3; /**< PE supports 66, 50 and 34-bit addresses. 3479215976Sjmallett [2:1] are a RO copy of SRIO*_IP_FEATURE[A66,A50]. */ 3480215976Sjmallett#else 3481215976Sjmallett uint32_t ex_addr : 3; 3482215976Sjmallett uint32_t ex_feat : 1; 3483215976Sjmallett uint32_t lg_tran : 1; 3484215976Sjmallett uint32_t crf : 1; 3485215976Sjmallett uint32_t suppress : 1; 3486215976Sjmallett uint32_t reserved_7_26 : 20; 3487215976Sjmallett uint32_t mult_prt : 1; 3488215976Sjmallett uint32_t switchf : 1; 3489215976Sjmallett uint32_t proc : 1; 3490215976Sjmallett uint32_t memory : 1; 3491215976Sjmallett uint32_t bridge : 1; 3492215976Sjmallett#endif 3493215976Sjmallett } s; 3494215976Sjmallett struct cvmx_sriomaintx_pe_feat_s cn63xx; 3495215976Sjmallett struct cvmx_sriomaintx_pe_feat_s cn63xxp1; 3496232812Sjmallett struct cvmx_sriomaintx_pe_feat_s cn66xx; 3497215976Sjmallett}; 3498215976Sjmalletttypedef union cvmx_sriomaintx_pe_feat cvmx_sriomaintx_pe_feat_t; 3499215976Sjmallett 3500215976Sjmallett/** 3501215976Sjmallett * cvmx_sriomaint#_pe_llc 3502215976Sjmallett * 3503215976Sjmallett * SRIOMAINT_PE_LLC = SRIO Processing Element Logical Layer Control 3504215976Sjmallett * 3505215976Sjmallett * Addresses supported by the SRIO Device. 3506215976Sjmallett * 3507215976Sjmallett * Notes: 3508215976Sjmallett * The Processing Element Logical Layer is used for general configuration for the logical interface. 3509215976Sjmallett * 3510232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PE_LLC hclk hrst_n 3511215976Sjmallett */ 3512232812Sjmallettunion cvmx_sriomaintx_pe_llc { 3513215976Sjmallett uint32_t u32; 3514232812Sjmallett struct cvmx_sriomaintx_pe_llc_s { 3515232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3516215976Sjmallett uint32_t reserved_3_31 : 29; 3517215976Sjmallett uint32_t ex_addr : 3; /**< Controls the number of address bits generated by 3518215976Sjmallett PE as a source and processed by the PE as a 3519215976Sjmallett target of an operation. 3520215976Sjmallett 001 = 34-bit Addresses 3521215976Sjmallett 010 = 50-bit Addresses 3522215976Sjmallett 100 = 66-bit Addresses 3523215976Sjmallett All other encodings are reserved. */ 3524215976Sjmallett#else 3525215976Sjmallett uint32_t ex_addr : 3; 3526215976Sjmallett uint32_t reserved_3_31 : 29; 3527215976Sjmallett#endif 3528215976Sjmallett } s; 3529215976Sjmallett struct cvmx_sriomaintx_pe_llc_s cn63xx; 3530215976Sjmallett struct cvmx_sriomaintx_pe_llc_s cn63xxp1; 3531232812Sjmallett struct cvmx_sriomaintx_pe_llc_s cn66xx; 3532215976Sjmallett}; 3533215976Sjmalletttypedef union cvmx_sriomaintx_pe_llc cvmx_sriomaintx_pe_llc_t; 3534215976Sjmallett 3535215976Sjmallett/** 3536215976Sjmallett * cvmx_sriomaint#_port_0_ctl 3537215976Sjmallett * 3538215976Sjmallett * SRIOMAINT_PORT_0_CTL = SRIO Port 0 Control 3539215976Sjmallett * 3540215976Sjmallett * Port 0 Control 3541215976Sjmallett * 3542215976Sjmallett * Notes: 3543215976Sjmallett * This register contains assorted control bits. 3544215976Sjmallett * 3545232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_CTL hclk hrst_n 3546215976Sjmallett */ 3547232812Sjmallettunion cvmx_sriomaintx_port_0_ctl { 3548215976Sjmallett uint32_t u32; 3549232812Sjmallett struct cvmx_sriomaintx_port_0_ctl_s { 3550232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3551215976Sjmallett uint32_t pt_width : 2; /**< Hardware Port Width. 3552215976Sjmallett 00 = One Lane supported. 3553232812Sjmallett 01 = One/Four Lanes supported. 3554232812Sjmallett 10 = One/Two Lanes supported. 3555215976Sjmallett 11 = One/Two/Four Lanes supported. 3556232812Sjmallett This value is a copy of SRIO*_IP_FEATURE[PT_WIDTH] 3557232812Sjmallett limited by the number of lanes the MAC has. */ 3558215976Sjmallett uint32_t it_width : 3; /**< Initialized Port Width 3559215976Sjmallett 000 = Single-lane, Lane 0 3560215976Sjmallett 001 = Single-lane, Lane 1 or 2 3561215976Sjmallett 010 = Four-lane 3562215976Sjmallett 011 = Two-lane 3563232812Sjmallett 111 = Link Uninitialized 3564215976Sjmallett Others = Reserved */ 3565215976Sjmallett uint32_t ov_width : 3; /**< Override Port Width. Writing this register causes 3566215976Sjmallett the port to reinitialize. 3567215976Sjmallett 000 = No Override all lanes possible 3568215976Sjmallett 001 = Reserved 3569215976Sjmallett 010 = Force Single-lane, Lane 0 3570232812Sjmallett If Ln 0 is unavailable try Ln 2 then Ln 1 3571215976Sjmallett 011 = Force Single-lane, Lane 2 3572232812Sjmallett If Ln 2 is unavailable try Ln 1 then Ln 0 3573215976Sjmallett 100 = Reserved 3574232812Sjmallett 101 = Enable Two-lane, Disable Four-Lane 3575232812Sjmallett 110 = Enable Four-lane, Disable Two-Lane 3576215976Sjmallett 111 = All lanes sizes enabled */ 3577215976Sjmallett uint32_t disable : 1; /**< Port Disable. Setting this bit disables both 3578215976Sjmallett drivers and receivers. */ 3579215976Sjmallett uint32_t o_enable : 1; /**< Port Output Enable. When cleared, port will 3580215976Sjmallett generate control symbols and respond to 3581215976Sjmallett maintenance transactions only. When set, all 3582215976Sjmallett transactions are allowed. */ 3583215976Sjmallett uint32_t i_enable : 1; /**< Port Input Enable. When cleared, port will 3584215976Sjmallett generate control symbols and respond to 3585215976Sjmallett maintenance packets only. All other packets will 3586215976Sjmallett not be accepted. */ 3587215976Sjmallett uint32_t dis_err : 1; /**< Disable Error Checking. Diagnostic Only. */ 3588215976Sjmallett uint32_t mcast : 1; /**< Reserved. */ 3589215976Sjmallett uint32_t reserved_18_18 : 1; 3590215976Sjmallett uint32_t enumb : 1; /**< Enumeration Boundry. SW can use this bit to 3591215976Sjmallett determine port enumeration. */ 3592215976Sjmallett uint32_t reserved_16_16 : 1; 3593215976Sjmallett uint32_t ex_width : 2; /**< Extended Port Width not supported. */ 3594215976Sjmallett uint32_t ex_stat : 2; /**< Extended Port Width Status. 00 = not supported */ 3595215976Sjmallett uint32_t suppress : 8; /**< Retransmit Suppression Mask. CRF not Supported. */ 3596215976Sjmallett uint32_t stp_port : 1; /**< Stop on Failed Port. This bit is used with the 3597215976Sjmallett DROP_PKT bit to force certain behavior when the 3598215976Sjmallett Error Rate Failed Threshold has been met or 3599215976Sjmallett exceeded. */ 3600215976Sjmallett uint32_t drop_pkt : 1; /**< Drop on Failed Port. This bit is used with the 3601215976Sjmallett STP_PORT bit to force certain behavior when the 3602215976Sjmallett Error Rate Failed Threshold has been met or 3603215976Sjmallett exceeded. */ 3604215976Sjmallett uint32_t prt_lock : 1; /**< When this bit is cleared, the packets that may be 3605215976Sjmallett received and issued are controlled by the state of 3606215976Sjmallett the O_ENABLE and I_ENABLE bits. When this bit is 3607215976Sjmallett set, this port is stopped and is not enabled to 3608215976Sjmallett issue or receive any packets; the input port can 3609215976Sjmallett still follow the training procedure and can still 3610215976Sjmallett send and respond to link-requests; all received 3611215976Sjmallett packets return packet-not-accepted control symbols 3612215976Sjmallett to force an error condition to be signaled by the 3613215976Sjmallett sending device. */ 3614215976Sjmallett uint32_t pt_type : 1; /**< Port Type. 1 = Serial port. */ 3615215976Sjmallett#else 3616215976Sjmallett uint32_t pt_type : 1; 3617215976Sjmallett uint32_t prt_lock : 1; 3618215976Sjmallett uint32_t drop_pkt : 1; 3619215976Sjmallett uint32_t stp_port : 1; 3620215976Sjmallett uint32_t suppress : 8; 3621215976Sjmallett uint32_t ex_stat : 2; 3622215976Sjmallett uint32_t ex_width : 2; 3623215976Sjmallett uint32_t reserved_16_16 : 1; 3624215976Sjmallett uint32_t enumb : 1; 3625215976Sjmallett uint32_t reserved_18_18 : 1; 3626215976Sjmallett uint32_t mcast : 1; 3627215976Sjmallett uint32_t dis_err : 1; 3628215976Sjmallett uint32_t i_enable : 1; 3629215976Sjmallett uint32_t o_enable : 1; 3630215976Sjmallett uint32_t disable : 1; 3631215976Sjmallett uint32_t ov_width : 3; 3632215976Sjmallett uint32_t it_width : 3; 3633215976Sjmallett uint32_t pt_width : 2; 3634215976Sjmallett#endif 3635215976Sjmallett } s; 3636215976Sjmallett struct cvmx_sriomaintx_port_0_ctl_s cn63xx; 3637215976Sjmallett struct cvmx_sriomaintx_port_0_ctl_s cn63xxp1; 3638232812Sjmallett struct cvmx_sriomaintx_port_0_ctl_s cn66xx; 3639215976Sjmallett}; 3640215976Sjmalletttypedef union cvmx_sriomaintx_port_0_ctl cvmx_sriomaintx_port_0_ctl_t; 3641215976Sjmallett 3642215976Sjmallett/** 3643215976Sjmallett * cvmx_sriomaint#_port_0_ctl2 3644215976Sjmallett * 3645215976Sjmallett * SRIOMAINT_PORT_0_CTL2 = SRIO Port 0 Control 2 3646215976Sjmallett * 3647215976Sjmallett * Port 0 Control 2 3648215976Sjmallett * 3649215976Sjmallett * Notes: 3650215976Sjmallett * These registers are accessed when a local processor or an external device wishes to examine the 3651232812Sjmallett * port baudrate information. The Automatic Baud Rate Feature is not available on this device. The 3652232812Sjmallett * SUP_* and ENB_* fields are set directly by the QLM_SPD bits as a reference but otherwise have 3653232812Sjmallett * no effect. WARNING: Writes to this register will reinitialize the SRIO link. 3654215976Sjmallett * 3655232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_CTL2 hclk hrst_n 3656215976Sjmallett */ 3657232812Sjmallettunion cvmx_sriomaintx_port_0_ctl2 { 3658215976Sjmallett uint32_t u32; 3659232812Sjmallett struct cvmx_sriomaintx_port_0_ctl2_s { 3660232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3661215976Sjmallett uint32_t sel_baud : 4; /**< Link Baud Rate Selected. 3662215976Sjmallett 0000 - No rate selected 3663215976Sjmallett 0001 - 1.25 GBaud 3664215976Sjmallett 0010 - 2.5 GBaud 3665215976Sjmallett 0011 - 3.125 GBaud 3666215976Sjmallett 0100 - 5.0 GBaud 3667215976Sjmallett 0101 - 6.25 GBaud (reserved) 3668215976Sjmallett 0110 - 0b1111 - Reserved 3669215976Sjmallett Indicates the speed of the interface SERDES lanes 3670232812Sjmallett (selected by the QLM*_SPD straps). */ 3671215976Sjmallett uint32_t baud_sup : 1; /**< Automatic Baud Rate Discovery not supported. */ 3672215976Sjmallett uint32_t baud_enb : 1; /**< Auto Baud Rate Discovery Enable. */ 3673215976Sjmallett uint32_t sup_125g : 1; /**< 1.25GB Rate Operation supported. 3674215976Sjmallett Set when the interface SERDES lanes are operating 3675215976Sjmallett at 1.25 Gbaud (as selected by QLM*_SPD straps). */ 3676215976Sjmallett uint32_t enb_125g : 1; /**< 1.25GB Rate Operation enable. 3677215976Sjmallett Reset to 1 when the interface SERDES lanes are 3678215976Sjmallett operating at 1.25 Gbaud (as selected by QLM*_SPD 3679215976Sjmallett straps). Reset to 0 otherwise. */ 3680215976Sjmallett uint32_t sup_250g : 1; /**< 2.50GB Rate Operation supported. 3681215976Sjmallett Set when the interface SERDES lanes are operating 3682215976Sjmallett at 2.5 Gbaud (as selected by QLM*_SPD straps). */ 3683215976Sjmallett uint32_t enb_250g : 1; /**< 2.50GB Rate Operation enable. 3684215976Sjmallett Reset to 1 when the interface SERDES lanes are 3685215976Sjmallett operating at 2.5 Gbaud (as selected by QLM*_SPD 3686215976Sjmallett straps). Reset to 0 otherwise. */ 3687215976Sjmallett uint32_t sup_312g : 1; /**< 3.125GB Rate Operation supported. 3688215976Sjmallett Set when the interface SERDES lanes are operating 3689215976Sjmallett at 3.125 Gbaud (as selected by QLM*_SPD straps). */ 3690215976Sjmallett uint32_t enb_312g : 1; /**< 3.125GB Rate Operation enable. 3691215976Sjmallett Reset to 1 when the interface SERDES lanes are 3692215976Sjmallett operating at 3.125 Gbaud (as selected by QLM*_SPD 3693215976Sjmallett straps). Reset to 0 otherwise. */ 3694215976Sjmallett uint32_t sub_500g : 1; /**< 5.0GB Rate Operation supported. 3695215976Sjmallett Set when the interface SERDES lanes are operating 3696215976Sjmallett at 5.0 Gbaud (as selected by QLM*_SPD straps). */ 3697215976Sjmallett uint32_t enb_500g : 1; /**< 5.0GB Rate Operation enable. 3698215976Sjmallett Reset to 1 when the interface SERDES lanes are 3699215976Sjmallett operating at 5.0 Gbaud (as selected by QLM*_SPD 3700215976Sjmallett straps). Reset to 0 otherwise. */ 3701215976Sjmallett uint32_t sup_625g : 1; /**< 6.25GB Rate Operation (not supported). */ 3702215976Sjmallett uint32_t enb_625g : 1; /**< 6.25GB Rate Operation enable. */ 3703215976Sjmallett uint32_t reserved_2_15 : 14; 3704215976Sjmallett uint32_t tx_emph : 1; /**< Indicates whether is port is able to transmit 3705215976Sjmallett commands to control the transmit emphasis in the 3706215976Sjmallett connected port. */ 3707215976Sjmallett uint32_t emph_en : 1; /**< Controls whether a port may adjust the 3708215976Sjmallett transmit emphasis in the connected port. This bit 3709215976Sjmallett should be cleared for normal operation. */ 3710215976Sjmallett#else 3711215976Sjmallett uint32_t emph_en : 1; 3712215976Sjmallett uint32_t tx_emph : 1; 3713215976Sjmallett uint32_t reserved_2_15 : 14; 3714215976Sjmallett uint32_t enb_625g : 1; 3715215976Sjmallett uint32_t sup_625g : 1; 3716215976Sjmallett uint32_t enb_500g : 1; 3717215976Sjmallett uint32_t sub_500g : 1; 3718215976Sjmallett uint32_t enb_312g : 1; 3719215976Sjmallett uint32_t sup_312g : 1; 3720215976Sjmallett uint32_t enb_250g : 1; 3721215976Sjmallett uint32_t sup_250g : 1; 3722215976Sjmallett uint32_t enb_125g : 1; 3723215976Sjmallett uint32_t sup_125g : 1; 3724215976Sjmallett uint32_t baud_enb : 1; 3725215976Sjmallett uint32_t baud_sup : 1; 3726215976Sjmallett uint32_t sel_baud : 4; 3727215976Sjmallett#endif 3728215976Sjmallett } s; 3729215976Sjmallett struct cvmx_sriomaintx_port_0_ctl2_s cn63xx; 3730215976Sjmallett struct cvmx_sriomaintx_port_0_ctl2_s cn63xxp1; 3731232812Sjmallett struct cvmx_sriomaintx_port_0_ctl2_s cn66xx; 3732215976Sjmallett}; 3733215976Sjmalletttypedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t; 3734215976Sjmallett 3735215976Sjmallett/** 3736215976Sjmallett * cvmx_sriomaint#_port_0_err_stat 3737215976Sjmallett * 3738215976Sjmallett * SRIOMAINT_PORT_0_ERR_STAT = SRIO Port 0 Error and Status 3739215976Sjmallett * 3740215976Sjmallett * Port 0 Error and Status 3741215976Sjmallett * 3742215976Sjmallett * Notes: 3743215976Sjmallett * This register displays port error and status information. Several port error conditions are 3744215976Sjmallett * captured here and must be cleared by writing 1's to the individual bits. 3745232812Sjmallett * Bits are R/W on 65/66xx pass 1 and R/W1C on pass 1.2 3746215976Sjmallett * 3747232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_ERR_STAT hclk hrst_n 3748215976Sjmallett */ 3749232812Sjmallettunion cvmx_sriomaintx_port_0_err_stat { 3750215976Sjmallett uint32_t u32; 3751232812Sjmallett struct cvmx_sriomaintx_port_0_err_stat_s { 3752232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3753215976Sjmallett uint32_t reserved_27_31 : 5; 3754215976Sjmallett uint32_t pkt_drop : 1; /**< Output Packet Dropped. */ 3755215976Sjmallett uint32_t o_fail : 1; /**< Output Port has encountered a failure condition, 3756215976Sjmallett meaning the port's failed error threshold has 3757232812Sjmallett reached SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR.ER_FAIL value. */ 3758215976Sjmallett uint32_t o_dgrad : 1; /**< Output Port has encountered a degraded condition, 3759215976Sjmallett meaning the port's degraded threshold has 3760232812Sjmallett reached SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR.ER_DGRAD 3761215976Sjmallett value. */ 3762215976Sjmallett uint32_t reserved_21_23 : 3; 3763215976Sjmallett uint32_t o_retry : 1; /**< Output Retry Encountered. This bit is set when 3764215976Sjmallett bit 18 is set. */ 3765215976Sjmallett uint32_t o_rtried : 1; /**< Output Port has received a packet-retry condition 3766215976Sjmallett and cannot make forward progress. This bit is set 3767215976Sjmallett when bit 18 is set and is cleared when a packet- 3768215976Sjmallett accepted or a packet-not-accepted control symbol 3769215976Sjmallett is received. */ 3770215976Sjmallett uint32_t o_sm_ret : 1; /**< Output Port State Machine has received a 3771215976Sjmallett packet-retry control symbol and is retrying the 3772215976Sjmallett packet. */ 3773215976Sjmallett uint32_t o_error : 1; /**< Output Error Encountered and possibly recovered 3774215976Sjmallett from. This sticky bit is set with bit 16. */ 3775215976Sjmallett uint32_t o_sm_err : 1; /**< Output Port State Machine has encountered an 3776215976Sjmallett error. */ 3777215976Sjmallett uint32_t reserved_11_15 : 5; 3778215976Sjmallett uint32_t i_sm_ret : 1; /**< Input Port State Machine has received a 3779215976Sjmallett packet-retry control symbol and is retrying the 3780215976Sjmallett packet. */ 3781215976Sjmallett uint32_t i_error : 1; /**< Input Error Encountered and possibly recovered 3782215976Sjmallett from. This sticky bit is set with bit 8. */ 3783215976Sjmallett uint32_t i_sm_err : 1; /**< Input Port State Machine has encountered an 3784215976Sjmallett error. */ 3785215976Sjmallett uint32_t reserved_5_7 : 3; 3786215976Sjmallett uint32_t pt_write : 1; /**< Port has encountered a condition which required it 3787232812Sjmallett initiate a Maintenance Port-Write Operation. 3788232812Sjmallett Never set by hardware. */ 3789215976Sjmallett uint32_t reserved_3_3 : 1; 3790215976Sjmallett uint32_t pt_error : 1; /**< Input or Output Port has encountered an 3791215976Sjmallett unrecoverable error condition. */ 3792215976Sjmallett uint32_t pt_ok : 1; /**< Input or Output Port are intitialized and the port 3793215976Sjmallett is exchanging error free control symbols with 3794215976Sjmallett attached device. */ 3795215976Sjmallett uint32_t pt_uinit : 1; /**< Port is uninitialized. This bit and bit 1 are 3796215976Sjmallett mutually exclusive. */ 3797215976Sjmallett#else 3798215976Sjmallett uint32_t pt_uinit : 1; 3799215976Sjmallett uint32_t pt_ok : 1; 3800215976Sjmallett uint32_t pt_error : 1; 3801215976Sjmallett uint32_t reserved_3_3 : 1; 3802215976Sjmallett uint32_t pt_write : 1; 3803215976Sjmallett uint32_t reserved_5_7 : 3; 3804215976Sjmallett uint32_t i_sm_err : 1; 3805215976Sjmallett uint32_t i_error : 1; 3806215976Sjmallett uint32_t i_sm_ret : 1; 3807215976Sjmallett uint32_t reserved_11_15 : 5; 3808215976Sjmallett uint32_t o_sm_err : 1; 3809215976Sjmallett uint32_t o_error : 1; 3810215976Sjmallett uint32_t o_sm_ret : 1; 3811215976Sjmallett uint32_t o_rtried : 1; 3812215976Sjmallett uint32_t o_retry : 1; 3813215976Sjmallett uint32_t reserved_21_23 : 3; 3814215976Sjmallett uint32_t o_dgrad : 1; 3815215976Sjmallett uint32_t o_fail : 1; 3816215976Sjmallett uint32_t pkt_drop : 1; 3817215976Sjmallett uint32_t reserved_27_31 : 5; 3818215976Sjmallett#endif 3819215976Sjmallett } s; 3820215976Sjmallett struct cvmx_sriomaintx_port_0_err_stat_s cn63xx; 3821215976Sjmallett struct cvmx_sriomaintx_port_0_err_stat_s cn63xxp1; 3822232812Sjmallett struct cvmx_sriomaintx_port_0_err_stat_s cn66xx; 3823215976Sjmallett}; 3824215976Sjmalletttypedef union cvmx_sriomaintx_port_0_err_stat cvmx_sriomaintx_port_0_err_stat_t; 3825215976Sjmallett 3826215976Sjmallett/** 3827215976Sjmallett * cvmx_sriomaint#_port_0_link_req 3828215976Sjmallett * 3829232812Sjmallett * SRIOMAINT_PORT_0_LINK_REQ = SRIO Port 0 Link Request 3830215976Sjmallett * 3831215976Sjmallett * Port 0 Manual Link Request 3832215976Sjmallett * 3833215976Sjmallett * Notes: 3834215976Sjmallett * Writing this register generates the link request symbol or eight device reset symbols. The 3835232812Sjmallett * progress of the request can be determined by reading SRIOMAINT(0,2..3)_PORT_0_LINK_RESP. Only a single 3836215976Sjmallett * request should be generated at a time. 3837215976Sjmallett * 3838232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_LINK_REQ hclk hrst_n 3839215976Sjmallett */ 3840232812Sjmallettunion cvmx_sriomaintx_port_0_link_req { 3841215976Sjmallett uint32_t u32; 3842232812Sjmallett struct cvmx_sriomaintx_port_0_link_req_s { 3843232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3844215976Sjmallett uint32_t reserved_3_31 : 29; 3845215976Sjmallett uint32_t cmd : 3; /**< Link Request Command. 3846215976Sjmallett 011 - Reset Device 3847215976Sjmallett 100 - Link Request 3848215976Sjmallett All other values reserved. */ 3849215976Sjmallett#else 3850215976Sjmallett uint32_t cmd : 3; 3851215976Sjmallett uint32_t reserved_3_31 : 29; 3852215976Sjmallett#endif 3853215976Sjmallett } s; 3854215976Sjmallett struct cvmx_sriomaintx_port_0_link_req_s cn63xx; 3855232812Sjmallett struct cvmx_sriomaintx_port_0_link_req_s cn66xx; 3856215976Sjmallett}; 3857215976Sjmalletttypedef union cvmx_sriomaintx_port_0_link_req cvmx_sriomaintx_port_0_link_req_t; 3858215976Sjmallett 3859215976Sjmallett/** 3860215976Sjmallett * cvmx_sriomaint#_port_0_link_resp 3861215976Sjmallett * 3862232812Sjmallett * SRIOMAINT_PORT_0_LINK_RESP = SRIO Port 0 Link Response 3863215976Sjmallett * 3864215976Sjmallett * Port 0 Manual Link Response 3865215976Sjmallett * 3866215976Sjmallett * Notes: 3867232812Sjmallett * This register only returns responses generated by writes to SRIOMAINT(0,2..3)_PORT_0_LINK_REQ. 3868215976Sjmallett * 3869232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_LINK_RESP hclk hrst_n 3870215976Sjmallett */ 3871232812Sjmallettunion cvmx_sriomaintx_port_0_link_resp { 3872215976Sjmallett uint32_t u32; 3873232812Sjmallett struct cvmx_sriomaintx_port_0_link_resp_s { 3874232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3875215976Sjmallett uint32_t valid : 1; /**< Link Response Valid. 3876215976Sjmallett 1 = Link Response Received or Reset Device 3877215976Sjmallett Symbols Transmitted. Value cleared on read. 3878215976Sjmallett 0 = No response received. */ 3879215976Sjmallett uint32_t reserved_11_30 : 20; 3880215976Sjmallett uint32_t ackid : 6; /**< AckID received from link response. 3881215976Sjmallett Reset Device symbol response is always zero. 3882215976Sjmallett Bit 10 is used for IDLE2 and always reads zero. */ 3883215976Sjmallett uint32_t status : 5; /**< Link Response Status. 3884215976Sjmallett Status supplied by link response. 3885215976Sjmallett Reset Device symbol response is always zero. */ 3886215976Sjmallett#else 3887215976Sjmallett uint32_t status : 5; 3888215976Sjmallett uint32_t ackid : 6; 3889215976Sjmallett uint32_t reserved_11_30 : 20; 3890215976Sjmallett uint32_t valid : 1; 3891215976Sjmallett#endif 3892215976Sjmallett } s; 3893215976Sjmallett struct cvmx_sriomaintx_port_0_link_resp_s cn63xx; 3894232812Sjmallett struct cvmx_sriomaintx_port_0_link_resp_s cn66xx; 3895215976Sjmallett}; 3896215976Sjmalletttypedef union cvmx_sriomaintx_port_0_link_resp cvmx_sriomaintx_port_0_link_resp_t; 3897215976Sjmallett 3898215976Sjmallett/** 3899215976Sjmallett * cvmx_sriomaint#_port_0_local_ackid 3900215976Sjmallett * 3901232812Sjmallett * SRIOMAINT_PORT_0_LOCAL_ACKID = SRIO Port 0 Local AckID 3902215976Sjmallett * 3903215976Sjmallett * Port 0 Local AckID Control 3904215976Sjmallett * 3905215976Sjmallett * Notes: 3906215976Sjmallett * This register is typically only written when recovering from a failed link. It may be read at any 3907215976Sjmallett * time the MAC is out of reset. Writes to the O_ACKID field will be used for both the O_ACKID and 3908215976Sjmallett * E_ACKID. Care must be taken to ensure that no packets are pending at the time of a write. The 3909232812Sjmallett * number of pending packets can be read in the TX_INUSE field of SRIO(0,2..3)_MAC_BUFFERS. 3910215976Sjmallett * 3911232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_LOCAL_ACKID hclk hrst_n 3912215976Sjmallett */ 3913232812Sjmallettunion cvmx_sriomaintx_port_0_local_ackid { 3914215976Sjmallett uint32_t u32; 3915232812Sjmallett struct cvmx_sriomaintx_port_0_local_ackid_s { 3916232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3917215976Sjmallett uint32_t reserved_30_31 : 2; 3918215976Sjmallett uint32_t i_ackid : 6; /**< Next Expected Inbound AckID. 3919215976Sjmallett Bit 29 is used for IDLE2 and should be zero. */ 3920215976Sjmallett uint32_t reserved_14_23 : 10; 3921215976Sjmallett uint32_t e_ackid : 6; /**< Next Expected Unacknowledged AckID. 3922215976Sjmallett Bit 13 is used for IDLE2 and should be zero. */ 3923215976Sjmallett uint32_t reserved_6_7 : 2; 3924215976Sjmallett uint32_t o_ackid : 6; /**< Next Outgoing Packet AckID. 3925215976Sjmallett Bit 5 is used for IDLE2 and should be zero. */ 3926215976Sjmallett#else 3927215976Sjmallett uint32_t o_ackid : 6; 3928215976Sjmallett uint32_t reserved_6_7 : 2; 3929215976Sjmallett uint32_t e_ackid : 6; 3930215976Sjmallett uint32_t reserved_14_23 : 10; 3931215976Sjmallett uint32_t i_ackid : 6; 3932215976Sjmallett uint32_t reserved_30_31 : 2; 3933215976Sjmallett#endif 3934215976Sjmallett } s; 3935215976Sjmallett struct cvmx_sriomaintx_port_0_local_ackid_s cn63xx; 3936232812Sjmallett struct cvmx_sriomaintx_port_0_local_ackid_s cn66xx; 3937215976Sjmallett}; 3938215976Sjmalletttypedef union cvmx_sriomaintx_port_0_local_ackid cvmx_sriomaintx_port_0_local_ackid_t; 3939215976Sjmallett 3940215976Sjmallett/** 3941215976Sjmallett * cvmx_sriomaint#_port_gen_ctl 3942215976Sjmallett * 3943215976Sjmallett * SRIOMAINT_PORT_GEN_CTL = SRIO Port General Control 3944215976Sjmallett * 3945215976Sjmallett * Port General Control 3946215976Sjmallett * 3947215976Sjmallett * Notes: 3948232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_GEN_CTL hclk hrst_n 3949215976Sjmallett * 3950215976Sjmallett */ 3951232812Sjmallettunion cvmx_sriomaintx_port_gen_ctl { 3952215976Sjmallett uint32_t u32; 3953232812Sjmallett struct cvmx_sriomaintx_port_gen_ctl_s { 3954232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3955215976Sjmallett uint32_t host : 1; /**< Host Device. 3956215976Sjmallett The HOST reset value is based on corresponding 3957232812Sjmallett MIO_RST_CTL*[PRTMODE]. HOST resets to 1 when 3958232812Sjmallett this field selects RC (i.e. host) mode, else 0. */ 3959215976Sjmallett uint32_t menable : 1; /**< Master Enable. Must be set for device to issue 3960215976Sjmallett read, write, doorbell, message requests. */ 3961215976Sjmallett uint32_t discover : 1; /**< Discovered. The device has been discovered by the 3962215976Sjmallett host responsible for initialization. */ 3963215976Sjmallett uint32_t reserved_0_28 : 29; 3964215976Sjmallett#else 3965215976Sjmallett uint32_t reserved_0_28 : 29; 3966215976Sjmallett uint32_t discover : 1; 3967215976Sjmallett uint32_t menable : 1; 3968215976Sjmallett uint32_t host : 1; 3969215976Sjmallett#endif 3970215976Sjmallett } s; 3971215976Sjmallett struct cvmx_sriomaintx_port_gen_ctl_s cn63xx; 3972215976Sjmallett struct cvmx_sriomaintx_port_gen_ctl_s cn63xxp1; 3973232812Sjmallett struct cvmx_sriomaintx_port_gen_ctl_s cn66xx; 3974215976Sjmallett}; 3975215976Sjmalletttypedef union cvmx_sriomaintx_port_gen_ctl cvmx_sriomaintx_port_gen_ctl_t; 3976215976Sjmallett 3977215976Sjmallett/** 3978215976Sjmallett * cvmx_sriomaint#_port_lt_ctl 3979215976Sjmallett * 3980215976Sjmallett * SRIOMAINT_PORT_LT_CTL = SRIO Link Layer Timeout Control 3981215976Sjmallett * 3982215976Sjmallett * Link Layer Timeout Control 3983215976Sjmallett * 3984215976Sjmallett * Notes: 3985215976Sjmallett * This register controls the timeout for link layer transactions. It is used as the timeout between 3986215976Sjmallett * sending a packet (of any type) or link request to receiving the corresponding link acknowledge or 3987215976Sjmallett * link-response. Each count represents 200ns. The minimum timeout period is the TIMEOUT x 200nS 3988215976Sjmallett * and the maximum is twice that number. A value less than 32 may not guarantee that all timeout 3989215976Sjmallett * errors will be reported correctly. When the timeout period expires the packet or link request is 3990232812Sjmallett * dropped and the error is logged in the LNK_TOUT field of the SRIOMAINT(0,2..3)_ERB_ERR_DET register. A 3991215976Sjmallett * value of 0 in this register will allow the packet or link request to be issued but it will timeout 3992215976Sjmallett * immediately. This value is not recommended for normal operation. 3993215976Sjmallett * 3994232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_LT_CTL hclk hrst_n 3995215976Sjmallett */ 3996232812Sjmallettunion cvmx_sriomaintx_port_lt_ctl { 3997215976Sjmallett uint32_t u32; 3998232812Sjmallett struct cvmx_sriomaintx_port_lt_ctl_s { 3999232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4000215976Sjmallett uint32_t timeout : 24; /**< Timeout Value */ 4001215976Sjmallett uint32_t reserved_0_7 : 8; 4002215976Sjmallett#else 4003215976Sjmallett uint32_t reserved_0_7 : 8; 4004215976Sjmallett uint32_t timeout : 24; 4005215976Sjmallett#endif 4006215976Sjmallett } s; 4007215976Sjmallett struct cvmx_sriomaintx_port_lt_ctl_s cn63xx; 4008215976Sjmallett struct cvmx_sriomaintx_port_lt_ctl_s cn63xxp1; 4009232812Sjmallett struct cvmx_sriomaintx_port_lt_ctl_s cn66xx; 4010215976Sjmallett}; 4011215976Sjmalletttypedef union cvmx_sriomaintx_port_lt_ctl cvmx_sriomaintx_port_lt_ctl_t; 4012215976Sjmallett 4013215976Sjmallett/** 4014215976Sjmallett * cvmx_sriomaint#_port_mbh0 4015215976Sjmallett * 4016215976Sjmallett * SRIOMAINT_PORT_MBH0 = SRIO Port Maintenance Block Header 0 4017215976Sjmallett * 4018215976Sjmallett * Port Maintenance Block Header 0 4019215976Sjmallett * 4020215976Sjmallett * Notes: 4021232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_MBH0 hclk hrst_n 4022215976Sjmallett * 4023215976Sjmallett */ 4024232812Sjmallettunion cvmx_sriomaintx_port_mbh0 { 4025215976Sjmallett uint32_t u32; 4026232812Sjmallett struct cvmx_sriomaintx_port_mbh0_s { 4027232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4028215976Sjmallett uint32_t ef_ptr : 16; /**< Pointer to Error Management Block. */ 4029215976Sjmallett uint32_t ef_id : 16; /**< Extended Feature ID (Generic Endpoint Device) */ 4030215976Sjmallett#else 4031215976Sjmallett uint32_t ef_id : 16; 4032215976Sjmallett uint32_t ef_ptr : 16; 4033215976Sjmallett#endif 4034215976Sjmallett } s; 4035215976Sjmallett struct cvmx_sriomaintx_port_mbh0_s cn63xx; 4036215976Sjmallett struct cvmx_sriomaintx_port_mbh0_s cn63xxp1; 4037232812Sjmallett struct cvmx_sriomaintx_port_mbh0_s cn66xx; 4038215976Sjmallett}; 4039215976Sjmalletttypedef union cvmx_sriomaintx_port_mbh0 cvmx_sriomaintx_port_mbh0_t; 4040215976Sjmallett 4041215976Sjmallett/** 4042215976Sjmallett * cvmx_sriomaint#_port_rt_ctl 4043215976Sjmallett * 4044215976Sjmallett * SRIOMAINT_PORT_RT_CTL = SRIO Logical Layer Timeout Control 4045215976Sjmallett * 4046215976Sjmallett * Logical Layer Timeout Control 4047215976Sjmallett * 4048215976Sjmallett * Notes: 4049215976Sjmallett * This register controls the timeout for logical layer transactions. It is used under two 4050215976Sjmallett * conditions. First, it is used as the timeout period between sending a packet requiring a packet 4051215976Sjmallett * response being sent to receiving the corresponding response. This is used for all outgoing packet 4052215976Sjmallett * types including memory, maintenance, doorbells and message operations. When the timeout period 4053215976Sjmallett * expires the packet is disgarded and the error is logged in the PKT_TOUT field of the 4054232812Sjmallett * SRIOMAINT(0,2..3)_ERB_LT_ERR_DET register. The second use of this register is as a timeout period 4055215976Sjmallett * between incoming message segments of the same message. If a message segment is received then the 4056232812Sjmallett * MSG_TOUT field of the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET register is set if the next segment has not been 4057215976Sjmallett * received before the time expires. In both cases, each count represents 200ns. The minimum 4058215976Sjmallett * timeout period is the TIMEOUT x 200nS and the maximum is twice that number. A value less than 32 4059215976Sjmallett * may not guarantee that all timeout errors will be reported correctly. A value of 0 disables the 4060215976Sjmallett * logical layer timeouts and is not recommended for normal operation. 4061215976Sjmallett * 4062232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_RT_CTL hclk hrst_n 4063215976Sjmallett */ 4064232812Sjmallettunion cvmx_sriomaintx_port_rt_ctl { 4065215976Sjmallett uint32_t u32; 4066232812Sjmallett struct cvmx_sriomaintx_port_rt_ctl_s { 4067232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4068215976Sjmallett uint32_t timeout : 24; /**< Timeout Value */ 4069215976Sjmallett uint32_t reserved_0_7 : 8; 4070215976Sjmallett#else 4071215976Sjmallett uint32_t reserved_0_7 : 8; 4072215976Sjmallett uint32_t timeout : 24; 4073215976Sjmallett#endif 4074215976Sjmallett } s; 4075215976Sjmallett struct cvmx_sriomaintx_port_rt_ctl_s cn63xx; 4076215976Sjmallett struct cvmx_sriomaintx_port_rt_ctl_s cn63xxp1; 4077232812Sjmallett struct cvmx_sriomaintx_port_rt_ctl_s cn66xx; 4078215976Sjmallett}; 4079215976Sjmalletttypedef union cvmx_sriomaintx_port_rt_ctl cvmx_sriomaintx_port_rt_ctl_t; 4080215976Sjmallett 4081215976Sjmallett/** 4082215976Sjmallett * cvmx_sriomaint#_port_ttl_ctl 4083215976Sjmallett * 4084232812Sjmallett * SRIOMAINT_PORT_TTL_CTL = SRIO Packet Time to Live Control 4085215976Sjmallett * 4086215976Sjmallett * Packet Time to Live 4087215976Sjmallett * 4088215976Sjmallett * Notes: 4089215976Sjmallett * This register controls the timeout for outgoing packets. It is used to make sure packets are 4090215976Sjmallett * being transmitted and acknowledged within a reasonable period of time. The timeout value 4091215976Sjmallett * corresponds to TIMEOUT x 200ns and a value of 0 disables the timer. The actualy value of the 4092232812Sjmallett * should be greater than the physical layer timout specified in SRIOMAINT(0,2..3)_PORT_LT_CTL and is 4093232812Sjmallett * typically a less SRIOMAINT(0,2..3)_PORT_LT_CTL timeout than the response timeout specified in 4094232812Sjmallett * SRIOMAINT(0,2..3)_PORT_RT_CTL. A second application of this timer is to remove all the packets waiting 4095232812Sjmallett * to be transmitted including those already in flight. This may necessary in the case of a link 4096232812Sjmallett * going down (see SRIO(0,2..3)_INT_REG.LINK_DWN). This can accomplished by setting the TIMEOUT to small 4097232812Sjmallett * value all so that all TX packets can be dropped. In either case, when the timeout expires the TTL 4098232812Sjmallett * interrupt is asserted, any packets currently being transmitted are dropped, the 4099232812Sjmallett * SRIOMAINT(0,2..3)_TX_DROP.DROP bit is set (causing any scheduled packets to be dropped), the 4100232812Sjmallett * SRIOMAINT(0,2..3)_TX_DROP.DROP_CNT is incremented for each packet and the SRIO output state is set to 4101232812Sjmallett * IDLE (all errors are cleared). Software must clear the SRIOMAINT(0,2..3)_TX_DROP.DROP bit to resume 4102232812Sjmallett * transmitting packets. 4103215976Sjmallett * 4104232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PORT_RT_CTL hclk hrst_n 4105215976Sjmallett */ 4106232812Sjmallettunion cvmx_sriomaintx_port_ttl_ctl { 4107215976Sjmallett uint32_t u32; 4108232812Sjmallett struct cvmx_sriomaintx_port_ttl_ctl_s { 4109232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4110215976Sjmallett uint32_t timeout : 24; /**< Timeout Value */ 4111215976Sjmallett uint32_t reserved_0_7 : 8; 4112215976Sjmallett#else 4113215976Sjmallett uint32_t reserved_0_7 : 8; 4114215976Sjmallett uint32_t timeout : 24; 4115215976Sjmallett#endif 4116215976Sjmallett } s; 4117215976Sjmallett struct cvmx_sriomaintx_port_ttl_ctl_s cn63xx; 4118232812Sjmallett struct cvmx_sriomaintx_port_ttl_ctl_s cn66xx; 4119215976Sjmallett}; 4120215976Sjmalletttypedef union cvmx_sriomaintx_port_ttl_ctl cvmx_sriomaintx_port_ttl_ctl_t; 4121215976Sjmallett 4122215976Sjmallett/** 4123215976Sjmallett * cvmx_sriomaint#_pri_dev_id 4124215976Sjmallett * 4125215976Sjmallett * SRIOMAINT_PRI_DEV_ID = SRIO Primary Device ID 4126215976Sjmallett * 4127215976Sjmallett * Primary 8 and 16 bit Device IDs 4128215976Sjmallett * 4129215976Sjmallett * Notes: 4130215976Sjmallett * This register defines the primary 8 and 16 bit device IDs used for large and small transport. An 4131232812Sjmallett * optional secondary set of device IDs are located in SRIOMAINT(0,2..3)_SEC_DEV_ID. 4132215976Sjmallett * 4133232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_PRI_DEV_ID hclk hrst_n 4134215976Sjmallett */ 4135232812Sjmallettunion cvmx_sriomaintx_pri_dev_id { 4136215976Sjmallett uint32_t u32; 4137232812Sjmallett struct cvmx_sriomaintx_pri_dev_id_s { 4138232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4139215976Sjmallett uint32_t reserved_24_31 : 8; 4140215976Sjmallett uint32_t id8 : 8; /**< Primary 8-bit Device ID */ 4141215976Sjmallett uint32_t id16 : 16; /**< Primary 16-bit Device ID */ 4142215976Sjmallett#else 4143215976Sjmallett uint32_t id16 : 16; 4144215976Sjmallett uint32_t id8 : 8; 4145215976Sjmallett uint32_t reserved_24_31 : 8; 4146215976Sjmallett#endif 4147215976Sjmallett } s; 4148215976Sjmallett struct cvmx_sriomaintx_pri_dev_id_s cn63xx; 4149215976Sjmallett struct cvmx_sriomaintx_pri_dev_id_s cn63xxp1; 4150232812Sjmallett struct cvmx_sriomaintx_pri_dev_id_s cn66xx; 4151215976Sjmallett}; 4152215976Sjmalletttypedef union cvmx_sriomaintx_pri_dev_id cvmx_sriomaintx_pri_dev_id_t; 4153215976Sjmallett 4154215976Sjmallett/** 4155215976Sjmallett * cvmx_sriomaint#_sec_dev_ctrl 4156215976Sjmallett * 4157215976Sjmallett * SRIOMAINT_SEC_DEV_CTRL = SRIO Secondary Device ID Control 4158215976Sjmallett * 4159215976Sjmallett * Control for Secondary Device IDs 4160215976Sjmallett * 4161215976Sjmallett * Notes: 4162215976Sjmallett * This register enables the secondary 8 and 16 bit device IDs used for large and small transport. 4163215976Sjmallett * The corresponding secondary ID must be written before the ID is enabled. The secondary IDs should 4164215976Sjmallett * not be enabled if the values of the primary and secondary IDs are identical. 4165215976Sjmallett * 4166232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_SEC_DEV_CTRL hclk hrst_n 4167215976Sjmallett */ 4168232812Sjmallettunion cvmx_sriomaintx_sec_dev_ctrl { 4169215976Sjmallett uint32_t u32; 4170232812Sjmallett struct cvmx_sriomaintx_sec_dev_ctrl_s { 4171232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4172215976Sjmallett uint32_t reserved_2_31 : 30; 4173215976Sjmallett uint32_t enable8 : 1; /**< Enable matches to secondary 8-bit Device ID */ 4174215976Sjmallett uint32_t enable16 : 1; /**< Enable matches to secondary 16-bit Device ID */ 4175215976Sjmallett#else 4176215976Sjmallett uint32_t enable16 : 1; 4177215976Sjmallett uint32_t enable8 : 1; 4178215976Sjmallett uint32_t reserved_2_31 : 30; 4179215976Sjmallett#endif 4180215976Sjmallett } s; 4181215976Sjmallett struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xx; 4182215976Sjmallett struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xxp1; 4183232812Sjmallett struct cvmx_sriomaintx_sec_dev_ctrl_s cn66xx; 4184215976Sjmallett}; 4185215976Sjmalletttypedef union cvmx_sriomaintx_sec_dev_ctrl cvmx_sriomaintx_sec_dev_ctrl_t; 4186215976Sjmallett 4187215976Sjmallett/** 4188215976Sjmallett * cvmx_sriomaint#_sec_dev_id 4189215976Sjmallett * 4190215976Sjmallett * SRIOMAINT_SEC_DEV_ID = SRIO Secondary Device ID 4191215976Sjmallett * 4192215976Sjmallett * Secondary 8 and 16 bit Device IDs 4193215976Sjmallett * 4194215976Sjmallett * Notes: 4195215976Sjmallett * This register defines the secondary 8 and 16 bit device IDs used for large and small transport. 4196215976Sjmallett * The corresponding secondary ID must be written before the ID is enabled in the 4197232812Sjmallett * SRIOMAINT(0,2..3)_SEC_DEV_CTRL register. The primary set of device IDs are located in 4198232812Sjmallett * SRIOMAINT(0,2..3)_PRI_DEV_ID register. The secondary IDs should not be written to the same values as the 4199215976Sjmallett * corresponding primary IDs. 4200215976Sjmallett * 4201232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_SEC_DEV_ID hclk hrst_n 4202215976Sjmallett */ 4203232812Sjmallettunion cvmx_sriomaintx_sec_dev_id { 4204215976Sjmallett uint32_t u32; 4205232812Sjmallett struct cvmx_sriomaintx_sec_dev_id_s { 4206232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4207215976Sjmallett uint32_t reserved_24_31 : 8; 4208215976Sjmallett uint32_t id8 : 8; /**< Secondary 8-bit Device ID */ 4209215976Sjmallett uint32_t id16 : 16; /**< Secondary 16-bit Device ID */ 4210215976Sjmallett#else 4211215976Sjmallett uint32_t id16 : 16; 4212215976Sjmallett uint32_t id8 : 8; 4213215976Sjmallett uint32_t reserved_24_31 : 8; 4214215976Sjmallett#endif 4215215976Sjmallett } s; 4216215976Sjmallett struct cvmx_sriomaintx_sec_dev_id_s cn63xx; 4217215976Sjmallett struct cvmx_sriomaintx_sec_dev_id_s cn63xxp1; 4218232812Sjmallett struct cvmx_sriomaintx_sec_dev_id_s cn66xx; 4219215976Sjmallett}; 4220215976Sjmalletttypedef union cvmx_sriomaintx_sec_dev_id cvmx_sriomaintx_sec_dev_id_t; 4221215976Sjmallett 4222215976Sjmallett/** 4223215976Sjmallett * cvmx_sriomaint#_serial_lane_hdr 4224215976Sjmallett * 4225215976Sjmallett * SRIOMAINT_SERIAL_LANE_HDR = SRIO Serial Lane Header 4226215976Sjmallett * 4227215976Sjmallett * SRIO Serial Lane Header 4228215976Sjmallett * 4229215976Sjmallett * Notes: 4230215976Sjmallett * The error management extensions block header register contains the EF_PTR to the next EF_BLK and 4231215976Sjmallett * the EF_ID that identifies this as the Serial Lane Status Block. 4232215976Sjmallett * 4233232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_SERIAL_LANE_HDR hclk hrst_n 4234215976Sjmallett */ 4235232812Sjmallettunion cvmx_sriomaintx_serial_lane_hdr { 4236215976Sjmallett uint32_t u32; 4237232812Sjmallett struct cvmx_sriomaintx_serial_lane_hdr_s { 4238232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4239215976Sjmallett uint32_t ef_ptr : 16; /**< Pointer to the next block in the extended features 4240215976Sjmallett data structure. */ 4241215976Sjmallett uint32_t ef_id : 16; 4242215976Sjmallett#else 4243215976Sjmallett uint32_t ef_id : 16; 4244215976Sjmallett uint32_t ef_ptr : 16; 4245215976Sjmallett#endif 4246215976Sjmallett } s; 4247215976Sjmallett struct cvmx_sriomaintx_serial_lane_hdr_s cn63xx; 4248215976Sjmallett struct cvmx_sriomaintx_serial_lane_hdr_s cn63xxp1; 4249232812Sjmallett struct cvmx_sriomaintx_serial_lane_hdr_s cn66xx; 4250215976Sjmallett}; 4251215976Sjmalletttypedef union cvmx_sriomaintx_serial_lane_hdr cvmx_sriomaintx_serial_lane_hdr_t; 4252215976Sjmallett 4253215976Sjmallett/** 4254215976Sjmallett * cvmx_sriomaint#_src_ops 4255215976Sjmallett * 4256215976Sjmallett * SRIOMAINT_SRC_OPS = SRIO Source Operations 4257215976Sjmallett * 4258215976Sjmallett * The logical operations initiated by the Octeon. 4259215976Sjmallett * 4260215976Sjmallett * Notes: 4261215976Sjmallett * The logical operations initiated by the Cores. The Source OPs register shows the operations 4262232812Sjmallett * specified in the SRIO(0,2..3)_IP_FEATURE.OPS register. 4263215976Sjmallett * 4264232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_SRC_OPS hclk hrst_n 4265215976Sjmallett */ 4266232812Sjmallettunion cvmx_sriomaintx_src_ops { 4267215976Sjmallett uint32_t u32; 4268232812Sjmallett struct cvmx_sriomaintx_src_ops_s { 4269232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4270215976Sjmallett uint32_t gsm_read : 1; /**< PE does not support Read Home operations. 4271215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */ 4272215976Sjmallett uint32_t i_read : 1; /**< PE does not support Instruction Read. 4273215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<30>] */ 4274215976Sjmallett uint32_t rd_own : 1; /**< PE does not support Read for Ownership. 4275215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<29>] */ 4276215976Sjmallett uint32_t d_invald : 1; /**< PE does not support Data Cache Invalidate. 4277215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<28>] */ 4278215976Sjmallett uint32_t castout : 1; /**< PE does not support Castout Operations. 4279215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<27>] */ 4280215976Sjmallett uint32_t d_flush : 1; /**< PE does not support Data Cache Flush. 4281215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<26>] */ 4282215976Sjmallett uint32_t io_read : 1; /**< PE does not support IO Read. 4283215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<25>] */ 4284215976Sjmallett uint32_t i_invald : 1; /**< PE does not support Instruction Cache Invalidate. 4285215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<24>] */ 4286215976Sjmallett uint32_t tlb_inv : 1; /**< PE does not support TLB Entry Invalidate. 4287215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<23>] */ 4288215976Sjmallett uint32_t tlb_invs : 1; /**< PE does not support TLB Entry Invalidate Sync. 4289215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<22>] */ 4290215976Sjmallett uint32_t reserved_16_21 : 6; 4291215976Sjmallett uint32_t read : 1; /**< PE can support Nread operations. 4292215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<15>] */ 4293215976Sjmallett uint32_t write : 1; /**< PE can support Nwrite operations. 4294215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<14>] */ 4295215976Sjmallett uint32_t swrite : 1; /**< PE can support Swrite operations. 4296215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<13>] */ 4297215976Sjmallett uint32_t write_r : 1; /**< PE can support Write with Response operations. 4298215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<12>] */ 4299215976Sjmallett uint32_t msg : 1; /**< PE can support Data Message operations. 4300215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<11>] */ 4301215976Sjmallett uint32_t doorbell : 1; /**< PE can support Doorbell operations. 4302215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<10>] */ 4303215976Sjmallett uint32_t compswap : 1; /**< PE does not support Atomic Compare and Swap. 4304215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<9>] */ 4305215976Sjmallett uint32_t testswap : 1; /**< PE does not support Atomic Test and Swap. 4306215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<8>] */ 4307215976Sjmallett uint32_t atom_inc : 1; /**< PE can support Atomic increment operations. 4308215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<7>] */ 4309215976Sjmallett uint32_t atom_dec : 1; /**< PE can support Atomic decrement operations. 4310215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<6>] */ 4311215976Sjmallett uint32_t atom_set : 1; /**< PE can support Atomic set operations. 4312215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<5>] */ 4313215976Sjmallett uint32_t atom_clr : 1; /**< PE can support Atomic clear operations. 4314215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<4>] */ 4315215976Sjmallett uint32_t atom_swp : 1; /**< PE does not support Atomic Swap. 4316215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<3>] */ 4317215976Sjmallett uint32_t port_wr : 1; /**< PE can Port Write operations. 4318215976Sjmallett This is a RO copy of SRIO*_IP_FEATURE[OPS<2>] */ 4319215976Sjmallett uint32_t reserved_0_1 : 2; 4320215976Sjmallett#else 4321215976Sjmallett uint32_t reserved_0_1 : 2; 4322215976Sjmallett uint32_t port_wr : 1; 4323215976Sjmallett uint32_t atom_swp : 1; 4324215976Sjmallett uint32_t atom_clr : 1; 4325215976Sjmallett uint32_t atom_set : 1; 4326215976Sjmallett uint32_t atom_dec : 1; 4327215976Sjmallett uint32_t atom_inc : 1; 4328215976Sjmallett uint32_t testswap : 1; 4329215976Sjmallett uint32_t compswap : 1; 4330215976Sjmallett uint32_t doorbell : 1; 4331215976Sjmallett uint32_t msg : 1; 4332215976Sjmallett uint32_t write_r : 1; 4333215976Sjmallett uint32_t swrite : 1; 4334215976Sjmallett uint32_t write : 1; 4335215976Sjmallett uint32_t read : 1; 4336215976Sjmallett uint32_t reserved_16_21 : 6; 4337215976Sjmallett uint32_t tlb_invs : 1; 4338215976Sjmallett uint32_t tlb_inv : 1; 4339215976Sjmallett uint32_t i_invald : 1; 4340215976Sjmallett uint32_t io_read : 1; 4341215976Sjmallett uint32_t d_flush : 1; 4342215976Sjmallett uint32_t castout : 1; 4343215976Sjmallett uint32_t d_invald : 1; 4344215976Sjmallett uint32_t rd_own : 1; 4345215976Sjmallett uint32_t i_read : 1; 4346215976Sjmallett uint32_t gsm_read : 1; 4347215976Sjmallett#endif 4348215976Sjmallett } s; 4349215976Sjmallett struct cvmx_sriomaintx_src_ops_s cn63xx; 4350215976Sjmallett struct cvmx_sriomaintx_src_ops_s cn63xxp1; 4351232812Sjmallett struct cvmx_sriomaintx_src_ops_s cn66xx; 4352215976Sjmallett}; 4353215976Sjmalletttypedef union cvmx_sriomaintx_src_ops cvmx_sriomaintx_src_ops_t; 4354215976Sjmallett 4355215976Sjmallett/** 4356215976Sjmallett * cvmx_sriomaint#_tx_drop 4357215976Sjmallett * 4358232812Sjmallett * SRIOMAINT_TX_DROP = SRIO MAC Outgoing Packet Drop 4359215976Sjmallett * 4360215976Sjmallett * Outging SRIO Packet Drop Control/Status 4361215976Sjmallett * 4362215976Sjmallett * Notes: 4363215976Sjmallett * This register controls and provides status for dropping outgoing SRIO packets. The DROP bit 4364215976Sjmallett * should only be cleared when no packets are currently being dropped. This can be guaranteed by 4365232812Sjmallett * clearing the SRIOMAINT(0,2..3)_PORT_0_CTL.O_ENABLE bit before changing the DROP bit and restoring the 4366215976Sjmallett * O_ENABLE afterwards. 4367215976Sjmallett * 4368232812Sjmallett * Clk_Rst: SRIOMAINT(0,2..3)_MAC_CTRL hclk hrst_n 4369215976Sjmallett */ 4370232812Sjmallettunion cvmx_sriomaintx_tx_drop { 4371215976Sjmallett uint32_t u32; 4372232812Sjmallett struct cvmx_sriomaintx_tx_drop_s { 4373232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4374215976Sjmallett uint32_t reserved_17_31 : 15; 4375215976Sjmallett uint32_t drop : 1; /**< All outgoing packets are dropped. Any packets 4376215976Sjmallett requiring a response will return 1's after the 4377232812Sjmallett SRIOMAINT(0,2..3)_PORT_RT_CTL Timeout expires. This bit 4378215976Sjmallett is set automatically when the TTL Timeout occurs 4379215976Sjmallett or can be set by software and must always be 4380215976Sjmallett cleared by software. */ 4381215976Sjmallett uint32_t drop_cnt : 16; /**< Number of packets dropped by transmit logic. 4382215976Sjmallett Packets are dropped whenever a packet is ready to 4383215976Sjmallett be transmitted and a TTL Timeouts occur, the DROP 4384232812Sjmallett bit is set or the SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR 4385215976Sjmallett FAIL_TH has been reached and the DROP_PKT bit is 4386232812Sjmallett set in SRIOMAINT(0,2..3)_PORT_0_CTL. This counter wraps 4387232812Sjmallett on overflow and is cleared only on reset. */ 4388215976Sjmallett#else 4389215976Sjmallett uint32_t drop_cnt : 16; 4390215976Sjmallett uint32_t drop : 1; 4391215976Sjmallett uint32_t reserved_17_31 : 15; 4392215976Sjmallett#endif 4393215976Sjmallett } s; 4394215976Sjmallett struct cvmx_sriomaintx_tx_drop_s cn63xx; 4395232812Sjmallett struct cvmx_sriomaintx_tx_drop_s cn66xx; 4396215976Sjmallett}; 4397215976Sjmalletttypedef union cvmx_sriomaintx_tx_drop cvmx_sriomaintx_tx_drop_t; 4398215976Sjmallett 4399215976Sjmallett#endif 4400