1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-smix-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon smix. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_SMIX_DEFS_H__ 53232812Sjmallett#define __CVMX_SMIX_DEFS_H__ 54215976Sjmallett 55215976Sjmallettstatic inline uint64_t CVMX_SMIX_CLK(unsigned long offset) 56215976Sjmallett{ 57232812Sjmallett switch(cvmx_get_octeon_family()) { 58232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 59232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 60232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 61232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 62232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 63232812Sjmallett if ((offset == 0)) 64232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 0) * 256; 65232812Sjmallett break; 66232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 67232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 68232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 69232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 70232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 71232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 72232812Sjmallett if ((offset <= 1)) 73232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256; 74232812Sjmallett break; 75232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 76232812Sjmallett if ((offset <= 3)) 77232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000003818ull) + ((offset) & 3) * 128; 78232812Sjmallett break; 79232812Sjmallett } 80232812Sjmallett cvmx_warn("CVMX_SMIX_CLK (offset = %lu) not supported on this chip\n", offset); 81215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256; 82215976Sjmallett} 83215976Sjmallettstatic inline uint64_t CVMX_SMIX_CMD(unsigned long offset) 84215976Sjmallett{ 85232812Sjmallett switch(cvmx_get_octeon_family()) { 86232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 87232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 88232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 89232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 90232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 91232812Sjmallett if ((offset == 0)) 92232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 0) * 256; 93232812Sjmallett break; 94232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 95232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 96232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 97232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 98232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 99232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 100232812Sjmallett if ((offset <= 1)) 101232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256; 102232812Sjmallett break; 103232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 104232812Sjmallett if ((offset <= 3)) 105232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000003800ull) + ((offset) & 3) * 128; 106232812Sjmallett break; 107232812Sjmallett } 108232812Sjmallett cvmx_warn("CVMX_SMIX_CMD (offset = %lu) not supported on this chip\n", offset); 109215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256; 110215976Sjmallett} 111215976Sjmallettstatic inline uint64_t CVMX_SMIX_EN(unsigned long offset) 112215976Sjmallett{ 113232812Sjmallett switch(cvmx_get_octeon_family()) { 114232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 115232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 116232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 117232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 118232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 119232812Sjmallett if ((offset == 0)) 120232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 0) * 256; 121232812Sjmallett break; 122232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 123232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 124232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 125232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 126232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 127232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 128232812Sjmallett if ((offset <= 1)) 129232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256; 130232812Sjmallett break; 131232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 132232812Sjmallett if ((offset <= 3)) 133232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000003820ull) + ((offset) & 3) * 128; 134232812Sjmallett break; 135232812Sjmallett } 136232812Sjmallett cvmx_warn("CVMX_SMIX_EN (offset = %lu) not supported on this chip\n", offset); 137215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256; 138215976Sjmallett} 139215976Sjmallettstatic inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset) 140215976Sjmallett{ 141232812Sjmallett switch(cvmx_get_octeon_family()) { 142232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 143232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 144232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 145232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 146232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 147232812Sjmallett if ((offset == 0)) 148232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 0) * 256; 149232812Sjmallett break; 150232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 151232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 152232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 153232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 154232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 155232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 156232812Sjmallett if ((offset <= 1)) 157232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256; 158232812Sjmallett break; 159232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 160232812Sjmallett if ((offset <= 3)) 161232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000003810ull) + ((offset) & 3) * 128; 162232812Sjmallett break; 163232812Sjmallett } 164232812Sjmallett cvmx_warn("CVMX_SMIX_RD_DAT (offset = %lu) not supported on this chip\n", offset); 165215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256; 166215976Sjmallett} 167215976Sjmallettstatic inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset) 168215976Sjmallett{ 169232812Sjmallett switch(cvmx_get_octeon_family()) { 170232812Sjmallett case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 171232812Sjmallett case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 172232812Sjmallett case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 173232812Sjmallett case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 174232812Sjmallett case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 175232812Sjmallett if ((offset == 0)) 176232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 0) * 256; 177232812Sjmallett break; 178232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 179232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 180232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 181232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 182232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 183232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 184232812Sjmallett if ((offset <= 1)) 185232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256; 186232812Sjmallett break; 187232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 188232812Sjmallett if ((offset <= 3)) 189232812Sjmallett return CVMX_ADD_IO_SEG(0x0001180000003808ull) + ((offset) & 3) * 128; 190232812Sjmallett break; 191232812Sjmallett } 192232812Sjmallett cvmx_warn("CVMX_SMIX_WR_DAT (offset = %lu) not supported on this chip\n", offset); 193215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256; 194215976Sjmallett} 195215976Sjmallett 196215976Sjmallett/** 197215976Sjmallett * cvmx_smi#_clk 198215976Sjmallett * 199215976Sjmallett * SMI_CLK = Clock Control Register 200215976Sjmallett * 201215976Sjmallett */ 202232812Sjmallettunion cvmx_smix_clk { 203215976Sjmallett uint64_t u64; 204232812Sjmallett struct cvmx_smix_clk_s { 205232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 206215976Sjmallett uint64_t reserved_25_63 : 39; 207215976Sjmallett uint64_t mode : 1; /**< IEEE operating mode 208215976Sjmallett 0=Clause 22 complient 209215976Sjmallett 1=Clause 45 complient */ 210215976Sjmallett uint64_t reserved_21_23 : 3; 211215976Sjmallett uint64_t sample_hi : 5; /**< When to sample read data (extended bits) */ 212215976Sjmallett uint64_t sample_mode : 1; /**< Read Data sampling mode 213215976Sjmallett According to the 802.3 spec, on reads, the STA 214215976Sjmallett transitions MDC and the PHY drives MDIO with 215215976Sjmallett some delay relative to that edge. This is edge1. 216215976Sjmallett The STA then samples MDIO on the next rising edge 217215976Sjmallett of MDC. This is edge2. Octeon can sample the 218215976Sjmallett read data relative to either edge. 219215976Sjmallett 0=[SAMPLE_HI,SAMPLE] specify the sample time 220215976Sjmallett relative to edge2 221215976Sjmallett 1=[SAMPLE_HI,SAMPLE] specify the sample time 222215976Sjmallett relative to edge1 */ 223215976Sjmallett uint64_t reserved_14_14 : 1; 224215976Sjmallett uint64_t clk_idle : 1; /**< Do not toggle MDC on idle cycles */ 225215976Sjmallett uint64_t preamble : 1; /**< Send PREAMBLE on SMI transacton 226215976Sjmallett PREAMBLE must be set 1 when MODE=1 in order 227215976Sjmallett for the receiving PHY to correctly frame the 228215976Sjmallett transaction. */ 229215976Sjmallett uint64_t sample : 4; /**< When to sample read data 230215976Sjmallett (number of eclks after the rising edge of mdc) 231215976Sjmallett ( [SAMPLE_HI,SAMPLE] > 1 ) 232215976Sjmallett ( [SAMPLE_HI, SAMPLE] + 3 <= 2*PHASE ) */ 233215976Sjmallett uint64_t phase : 8; /**< MDC Clock Phase 234215976Sjmallett (number of eclks that make up an mdc phase) 235215976Sjmallett (PHASE > 2) */ 236215976Sjmallett#else 237215976Sjmallett uint64_t phase : 8; 238215976Sjmallett uint64_t sample : 4; 239215976Sjmallett uint64_t preamble : 1; 240215976Sjmallett uint64_t clk_idle : 1; 241215976Sjmallett uint64_t reserved_14_14 : 1; 242215976Sjmallett uint64_t sample_mode : 1; 243215976Sjmallett uint64_t sample_hi : 5; 244215976Sjmallett uint64_t reserved_21_23 : 3; 245215976Sjmallett uint64_t mode : 1; 246215976Sjmallett uint64_t reserved_25_63 : 39; 247215976Sjmallett#endif 248215976Sjmallett } s; 249232812Sjmallett struct cvmx_smix_clk_cn30xx { 250232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 251215976Sjmallett uint64_t reserved_21_63 : 43; 252215976Sjmallett uint64_t sample_hi : 5; /**< When to sample read data (extended bits) */ 253215976Sjmallett uint64_t sample_mode : 1; /**< Read Data sampling mode 254215976Sjmallett According to the 802.3 spec, on reads, the STA 255215976Sjmallett transitions MDC and the PHY drives MDIO with 256215976Sjmallett some delay relative to that edge. This is edge1. 257215976Sjmallett The STA then samples MDIO on the next rising edge 258215976Sjmallett of MDC. This is edge2. Octeon can sample the 259215976Sjmallett read data relative to either edge. 260215976Sjmallett 0=[SAMPLE_HI,SAMPLE] specify the sample time 261215976Sjmallett relative to edge2 262215976Sjmallett 1=[SAMPLE_HI,SAMPLE] specify the sample time 263215976Sjmallett relative to edge1 */ 264215976Sjmallett uint64_t reserved_14_14 : 1; 265215976Sjmallett uint64_t clk_idle : 1; /**< Do not toggle MDC on idle cycles */ 266215976Sjmallett uint64_t preamble : 1; /**< Send PREAMBLE on SMI transacton */ 267215976Sjmallett uint64_t sample : 4; /**< When to sample read data 268215976Sjmallett (number of eclks after the rising edge of mdc) 269215976Sjmallett ( [SAMPLE_HI,SAMPLE] > 1 ) 270215976Sjmallett ( [SAMPLE_HI, SAMPLE] + 3 <= 2*PHASE ) */ 271215976Sjmallett uint64_t phase : 8; /**< MDC Clock Phase 272215976Sjmallett (number of eclks that make up an mdc phase) 273215976Sjmallett (PHASE > 2) */ 274215976Sjmallett#else 275215976Sjmallett uint64_t phase : 8; 276215976Sjmallett uint64_t sample : 4; 277215976Sjmallett uint64_t preamble : 1; 278215976Sjmallett uint64_t clk_idle : 1; 279215976Sjmallett uint64_t reserved_14_14 : 1; 280215976Sjmallett uint64_t sample_mode : 1; 281215976Sjmallett uint64_t sample_hi : 5; 282215976Sjmallett uint64_t reserved_21_63 : 43; 283215976Sjmallett#endif 284215976Sjmallett } cn30xx; 285215976Sjmallett struct cvmx_smix_clk_cn30xx cn31xx; 286215976Sjmallett struct cvmx_smix_clk_cn30xx cn38xx; 287215976Sjmallett struct cvmx_smix_clk_cn30xx cn38xxp2; 288215976Sjmallett struct cvmx_smix_clk_s cn50xx; 289215976Sjmallett struct cvmx_smix_clk_s cn52xx; 290215976Sjmallett struct cvmx_smix_clk_s cn52xxp1; 291215976Sjmallett struct cvmx_smix_clk_s cn56xx; 292215976Sjmallett struct cvmx_smix_clk_s cn56xxp1; 293215976Sjmallett struct cvmx_smix_clk_cn30xx cn58xx; 294215976Sjmallett struct cvmx_smix_clk_cn30xx cn58xxp1; 295232812Sjmallett struct cvmx_smix_clk_s cn61xx; 296215976Sjmallett struct cvmx_smix_clk_s cn63xx; 297215976Sjmallett struct cvmx_smix_clk_s cn63xxp1; 298232812Sjmallett struct cvmx_smix_clk_s cn66xx; 299232812Sjmallett struct cvmx_smix_clk_s cn68xx; 300232812Sjmallett struct cvmx_smix_clk_s cn68xxp1; 301232812Sjmallett struct cvmx_smix_clk_s cnf71xx; 302215976Sjmallett}; 303215976Sjmalletttypedef union cvmx_smix_clk cvmx_smix_clk_t; 304215976Sjmallett 305215976Sjmallett/** 306215976Sjmallett * cvmx_smi#_cmd 307215976Sjmallett * 308215976Sjmallett * SMI_CMD = Force a Read/Write command to the PHY 309215976Sjmallett * 310215976Sjmallett * 311215976Sjmallett * Notes: 312215976Sjmallett * Writes to this register will create SMI xactions. Software will poll on (depending on the xaction type). 313215976Sjmallett * 314215976Sjmallett */ 315232812Sjmallettunion cvmx_smix_cmd { 316215976Sjmallett uint64_t u64; 317232812Sjmallett struct cvmx_smix_cmd_s { 318232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 319215976Sjmallett uint64_t reserved_18_63 : 46; 320215976Sjmallett uint64_t phy_op : 2; /**< PHY Opcode depending on SMI_CLK[MODE] 321215976Sjmallett SMI_CLK[MODE] == 0 (<=1Gbs / Clause 22) 322215976Sjmallett x0=write 323215976Sjmallett x1=read 324215976Sjmallett SMI_CLK[MODE] == 1 (>1Gbs / Clause 45) 325215976Sjmallett 00=address 326215976Sjmallett 01=write 327215976Sjmallett 11=read 328215976Sjmallett 10=post-read-increment-address */ 329215976Sjmallett uint64_t reserved_13_15 : 3; 330215976Sjmallett uint64_t phy_adr : 5; /**< PHY Address */ 331215976Sjmallett uint64_t reserved_5_7 : 3; 332215976Sjmallett uint64_t reg_adr : 5; /**< PHY Register Offset */ 333215976Sjmallett#else 334215976Sjmallett uint64_t reg_adr : 5; 335215976Sjmallett uint64_t reserved_5_7 : 3; 336215976Sjmallett uint64_t phy_adr : 5; 337215976Sjmallett uint64_t reserved_13_15 : 3; 338215976Sjmallett uint64_t phy_op : 2; 339215976Sjmallett uint64_t reserved_18_63 : 46; 340215976Sjmallett#endif 341215976Sjmallett } s; 342232812Sjmallett struct cvmx_smix_cmd_cn30xx { 343232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 344215976Sjmallett uint64_t reserved_17_63 : 47; 345215976Sjmallett uint64_t phy_op : 1; /**< PHY Opcode 346215976Sjmallett 0=write 347215976Sjmallett 1=read */ 348215976Sjmallett uint64_t reserved_13_15 : 3; 349215976Sjmallett uint64_t phy_adr : 5; /**< PHY Address */ 350215976Sjmallett uint64_t reserved_5_7 : 3; 351215976Sjmallett uint64_t reg_adr : 5; /**< PHY Register Offset */ 352215976Sjmallett#else 353215976Sjmallett uint64_t reg_adr : 5; 354215976Sjmallett uint64_t reserved_5_7 : 3; 355215976Sjmallett uint64_t phy_adr : 5; 356215976Sjmallett uint64_t reserved_13_15 : 3; 357215976Sjmallett uint64_t phy_op : 1; 358215976Sjmallett uint64_t reserved_17_63 : 47; 359215976Sjmallett#endif 360215976Sjmallett } cn30xx; 361215976Sjmallett struct cvmx_smix_cmd_cn30xx cn31xx; 362215976Sjmallett struct cvmx_smix_cmd_cn30xx cn38xx; 363215976Sjmallett struct cvmx_smix_cmd_cn30xx cn38xxp2; 364215976Sjmallett struct cvmx_smix_cmd_s cn50xx; 365215976Sjmallett struct cvmx_smix_cmd_s cn52xx; 366215976Sjmallett struct cvmx_smix_cmd_s cn52xxp1; 367215976Sjmallett struct cvmx_smix_cmd_s cn56xx; 368215976Sjmallett struct cvmx_smix_cmd_s cn56xxp1; 369215976Sjmallett struct cvmx_smix_cmd_cn30xx cn58xx; 370215976Sjmallett struct cvmx_smix_cmd_cn30xx cn58xxp1; 371232812Sjmallett struct cvmx_smix_cmd_s cn61xx; 372215976Sjmallett struct cvmx_smix_cmd_s cn63xx; 373215976Sjmallett struct cvmx_smix_cmd_s cn63xxp1; 374232812Sjmallett struct cvmx_smix_cmd_s cn66xx; 375232812Sjmallett struct cvmx_smix_cmd_s cn68xx; 376232812Sjmallett struct cvmx_smix_cmd_s cn68xxp1; 377232812Sjmallett struct cvmx_smix_cmd_s cnf71xx; 378215976Sjmallett}; 379215976Sjmalletttypedef union cvmx_smix_cmd cvmx_smix_cmd_t; 380215976Sjmallett 381215976Sjmallett/** 382215976Sjmallett * cvmx_smi#_en 383215976Sjmallett * 384215976Sjmallett * SMI_EN = Enable the SMI interface 385215976Sjmallett * 386215976Sjmallett */ 387232812Sjmallettunion cvmx_smix_en { 388215976Sjmallett uint64_t u64; 389232812Sjmallett struct cvmx_smix_en_s { 390232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 391215976Sjmallett uint64_t reserved_1_63 : 63; 392215976Sjmallett uint64_t en : 1; /**< Interface enable 393215976Sjmallett 0=SMI Interface is down / no transactions, no MDC 394215976Sjmallett 1=SMI Interface is up */ 395215976Sjmallett#else 396215976Sjmallett uint64_t en : 1; 397215976Sjmallett uint64_t reserved_1_63 : 63; 398215976Sjmallett#endif 399215976Sjmallett } s; 400215976Sjmallett struct cvmx_smix_en_s cn30xx; 401215976Sjmallett struct cvmx_smix_en_s cn31xx; 402215976Sjmallett struct cvmx_smix_en_s cn38xx; 403215976Sjmallett struct cvmx_smix_en_s cn38xxp2; 404215976Sjmallett struct cvmx_smix_en_s cn50xx; 405215976Sjmallett struct cvmx_smix_en_s cn52xx; 406215976Sjmallett struct cvmx_smix_en_s cn52xxp1; 407215976Sjmallett struct cvmx_smix_en_s cn56xx; 408215976Sjmallett struct cvmx_smix_en_s cn56xxp1; 409215976Sjmallett struct cvmx_smix_en_s cn58xx; 410215976Sjmallett struct cvmx_smix_en_s cn58xxp1; 411232812Sjmallett struct cvmx_smix_en_s cn61xx; 412215976Sjmallett struct cvmx_smix_en_s cn63xx; 413215976Sjmallett struct cvmx_smix_en_s cn63xxp1; 414232812Sjmallett struct cvmx_smix_en_s cn66xx; 415232812Sjmallett struct cvmx_smix_en_s cn68xx; 416232812Sjmallett struct cvmx_smix_en_s cn68xxp1; 417232812Sjmallett struct cvmx_smix_en_s cnf71xx; 418215976Sjmallett}; 419215976Sjmalletttypedef union cvmx_smix_en cvmx_smix_en_t; 420215976Sjmallett 421215976Sjmallett/** 422215976Sjmallett * cvmx_smi#_rd_dat 423215976Sjmallett * 424215976Sjmallett * SMI_RD_DAT = SMI Read Data 425215976Sjmallett * 426215976Sjmallett * 427215976Sjmallett * Notes: 428215976Sjmallett * VAL will assert when the read xaction completes. A read to this register 429215976Sjmallett * will clear VAL. PENDING indicates that an SMI RD transaction is in flight. 430215976Sjmallett */ 431232812Sjmallettunion cvmx_smix_rd_dat { 432215976Sjmallett uint64_t u64; 433232812Sjmallett struct cvmx_smix_rd_dat_s { 434232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 435215976Sjmallett uint64_t reserved_18_63 : 46; 436215976Sjmallett uint64_t pending : 1; /**< Read Xaction Pending */ 437215976Sjmallett uint64_t val : 1; /**< Read Data Valid */ 438215976Sjmallett uint64_t dat : 16; /**< Read Data */ 439215976Sjmallett#else 440215976Sjmallett uint64_t dat : 16; 441215976Sjmallett uint64_t val : 1; 442215976Sjmallett uint64_t pending : 1; 443215976Sjmallett uint64_t reserved_18_63 : 46; 444215976Sjmallett#endif 445215976Sjmallett } s; 446215976Sjmallett struct cvmx_smix_rd_dat_s cn30xx; 447215976Sjmallett struct cvmx_smix_rd_dat_s cn31xx; 448215976Sjmallett struct cvmx_smix_rd_dat_s cn38xx; 449215976Sjmallett struct cvmx_smix_rd_dat_s cn38xxp2; 450215976Sjmallett struct cvmx_smix_rd_dat_s cn50xx; 451215976Sjmallett struct cvmx_smix_rd_dat_s cn52xx; 452215976Sjmallett struct cvmx_smix_rd_dat_s cn52xxp1; 453215976Sjmallett struct cvmx_smix_rd_dat_s cn56xx; 454215976Sjmallett struct cvmx_smix_rd_dat_s cn56xxp1; 455215976Sjmallett struct cvmx_smix_rd_dat_s cn58xx; 456215976Sjmallett struct cvmx_smix_rd_dat_s cn58xxp1; 457232812Sjmallett struct cvmx_smix_rd_dat_s cn61xx; 458215976Sjmallett struct cvmx_smix_rd_dat_s cn63xx; 459215976Sjmallett struct cvmx_smix_rd_dat_s cn63xxp1; 460232812Sjmallett struct cvmx_smix_rd_dat_s cn66xx; 461232812Sjmallett struct cvmx_smix_rd_dat_s cn68xx; 462232812Sjmallett struct cvmx_smix_rd_dat_s cn68xxp1; 463232812Sjmallett struct cvmx_smix_rd_dat_s cnf71xx; 464215976Sjmallett}; 465215976Sjmalletttypedef union cvmx_smix_rd_dat cvmx_smix_rd_dat_t; 466215976Sjmallett 467215976Sjmallett/** 468215976Sjmallett * cvmx_smi#_wr_dat 469215976Sjmallett * 470215976Sjmallett * SMI_WR_DAT = SMI Write Data 471215976Sjmallett * 472215976Sjmallett * 473215976Sjmallett * Notes: 474215976Sjmallett * VAL will assert when the write xaction completes. A read to this register 475215976Sjmallett * will clear VAL. PENDING indicates that an SMI WR transaction is in flight. 476215976Sjmallett */ 477232812Sjmallettunion cvmx_smix_wr_dat { 478215976Sjmallett uint64_t u64; 479232812Sjmallett struct cvmx_smix_wr_dat_s { 480232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 481215976Sjmallett uint64_t reserved_18_63 : 46; 482215976Sjmallett uint64_t pending : 1; /**< Write Xaction Pending */ 483215976Sjmallett uint64_t val : 1; /**< Write Data Valid */ 484215976Sjmallett uint64_t dat : 16; /**< Write Data */ 485215976Sjmallett#else 486215976Sjmallett uint64_t dat : 16; 487215976Sjmallett uint64_t val : 1; 488215976Sjmallett uint64_t pending : 1; 489215976Sjmallett uint64_t reserved_18_63 : 46; 490215976Sjmallett#endif 491215976Sjmallett } s; 492215976Sjmallett struct cvmx_smix_wr_dat_s cn30xx; 493215976Sjmallett struct cvmx_smix_wr_dat_s cn31xx; 494215976Sjmallett struct cvmx_smix_wr_dat_s cn38xx; 495215976Sjmallett struct cvmx_smix_wr_dat_s cn38xxp2; 496215976Sjmallett struct cvmx_smix_wr_dat_s cn50xx; 497215976Sjmallett struct cvmx_smix_wr_dat_s cn52xx; 498215976Sjmallett struct cvmx_smix_wr_dat_s cn52xxp1; 499215976Sjmallett struct cvmx_smix_wr_dat_s cn56xx; 500215976Sjmallett struct cvmx_smix_wr_dat_s cn56xxp1; 501215976Sjmallett struct cvmx_smix_wr_dat_s cn58xx; 502215976Sjmallett struct cvmx_smix_wr_dat_s cn58xxp1; 503232812Sjmallett struct cvmx_smix_wr_dat_s cn61xx; 504215976Sjmallett struct cvmx_smix_wr_dat_s cn63xx; 505215976Sjmallett struct cvmx_smix_wr_dat_s cn63xxp1; 506232812Sjmallett struct cvmx_smix_wr_dat_s cn66xx; 507232812Sjmallett struct cvmx_smix_wr_dat_s cn68xx; 508232812Sjmallett struct cvmx_smix_wr_dat_s cn68xxp1; 509232812Sjmallett struct cvmx_smix_wr_dat_s cnf71xx; 510215976Sjmallett}; 511215976Sjmalletttypedef union cvmx_smix_wr_dat cvmx_smix_wr_dat_t; 512215976Sjmallett 513215976Sjmallett#endif 514