cvmx-pip-defs.h revision 215976
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pip-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pip. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PIP_TYPEDEFS_H__ 53#define __CVMX_PIP_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_PIP_BCK_PRS CVMX_PIP_BCK_PRS_FUNC() 57static inline uint64_t CVMX_PIP_BCK_PRS_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 60 cvmx_warn("CVMX_PIP_BCK_PRS not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x00011800A0000038ull); 62} 63#else 64#define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull)) 65#endif 66#define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull)) 67#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 68#define CVMX_PIP_CLKEN CVMX_PIP_CLKEN_FUNC() 69static inline uint64_t CVMX_PIP_CLKEN_FUNC(void) 70{ 71 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 72 cvmx_warn("CVMX_PIP_CLKEN not supported on this chip\n"); 73 return CVMX_ADD_IO_SEG(0x00011800A0000040ull); 74} 75#else 76#define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull)) 77#endif 78#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 79static inline uint64_t CVMX_PIP_CRC_CTLX(unsigned long offset) 80{ 81 if (!( 82 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 83 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 84 cvmx_warn("CVMX_PIP_CRC_CTLX(%lu) is invalid on this chip\n", offset); 85 return CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8; 86} 87#else 88#define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8) 89#endif 90#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 91static inline uint64_t CVMX_PIP_CRC_IVX(unsigned long offset) 92{ 93 if (!( 94 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 95 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 96 cvmx_warn("CVMX_PIP_CRC_IVX(%lu) is invalid on this chip\n", offset); 97 return CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8; 98} 99#else 100#define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8) 101#endif 102#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 103static inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset) 104{ 105 if (!( 106 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 107 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 108 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 109 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 110 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 111 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) || 112 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) || 113 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))))) 114 cvmx_warn("CVMX_PIP_DEC_IPSECX(%lu) is invalid on this chip\n", offset); 115 return CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8; 116} 117#else 118#define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8) 119#endif 120#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121#define CVMX_PIP_DSA_SRC_GRP CVMX_PIP_DSA_SRC_GRP_FUNC() 122static inline uint64_t CVMX_PIP_DSA_SRC_GRP_FUNC(void) 123{ 124 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 125 cvmx_warn("CVMX_PIP_DSA_SRC_GRP not supported on this chip\n"); 126 return CVMX_ADD_IO_SEG(0x00011800A0000190ull); 127} 128#else 129#define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull)) 130#endif 131#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 132#define CVMX_PIP_DSA_VID_GRP CVMX_PIP_DSA_VID_GRP_FUNC() 133static inline uint64_t CVMX_PIP_DSA_VID_GRP_FUNC(void) 134{ 135 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 136 cvmx_warn("CVMX_PIP_DSA_VID_GRP not supported on this chip\n"); 137 return CVMX_ADD_IO_SEG(0x00011800A0000198ull); 138} 139#else 140#define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull)) 141#endif 142#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 143static inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset) 144{ 145 if (!( 146 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 147 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 148 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 149 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))))) 150 cvmx_warn("CVMX_PIP_FRM_LEN_CHKX(%lu) is invalid on this chip\n", offset); 151 return CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8; 152} 153#else 154#define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8) 155#endif 156#define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull)) 157#define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull)) 158#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 159#define CVMX_PIP_HG_PRI_QOS CVMX_PIP_HG_PRI_QOS_FUNC() 160static inline uint64_t CVMX_PIP_HG_PRI_QOS_FUNC(void) 161{ 162 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 163 cvmx_warn("CVMX_PIP_HG_PRI_QOS not supported on this chip\n"); 164 return CVMX_ADD_IO_SEG(0x00011800A00001A0ull); 165} 166#else 167#define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull)) 168#endif 169#define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull)) 170#define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull)) 171#define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull)) 172#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173static inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset) 174{ 175 if (!( 176 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 177 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 178 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 179 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 180 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 181 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 182 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 183 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))))) 184 cvmx_warn("CVMX_PIP_PRT_CFGX(%lu) is invalid on this chip\n", offset); 185 return CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8; 186} 187#else 188#define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8) 189#endif 190#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191static inline uint64_t CVMX_PIP_PRT_TAGX(unsigned long offset) 192{ 193 if (!( 194 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 195 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 196 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 197 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 198 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 199 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 200 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 201 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))))) 202 cvmx_warn("CVMX_PIP_PRT_TAGX(%lu) is invalid on this chip\n", offset); 203 return CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8; 204} 205#else 206#define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8) 207#endif 208#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 209static inline uint64_t CVMX_PIP_QOS_DIFFX(unsigned long offset) 210{ 211 if (!( 212 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) || 213 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) || 214 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) || 215 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) || 216 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) || 217 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) || 218 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) || 219 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63))))) 220 cvmx_warn("CVMX_PIP_QOS_DIFFX(%lu) is invalid on this chip\n", offset); 221 return CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8; 222} 223#else 224#define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8) 225#endif 226#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 227static inline uint64_t CVMX_PIP_QOS_VLANX(unsigned long offset) 228{ 229 if (!( 230 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 231 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 232 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 233 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 234 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 235 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 236 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 237 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 238 cvmx_warn("CVMX_PIP_QOS_VLANX(%lu) is invalid on this chip\n", offset); 239 return CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8; 240} 241#else 242#define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8) 243#endif 244#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 245static inline uint64_t CVMX_PIP_QOS_WATCHX(unsigned long offset) 246{ 247 if (!( 248 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 249 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 250 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 251 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 252 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 253 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 254 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) || 255 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))))) 256 cvmx_warn("CVMX_PIP_QOS_WATCHX(%lu) is invalid on this chip\n", offset); 257 return CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8; 258} 259#else 260#define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8) 261#endif 262#define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull)) 263#define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull)) 264#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265static inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset) 266{ 267 if (!( 268 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 269 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 270 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 271 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 272 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 273 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 274 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 275 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 276 cvmx_warn("CVMX_PIP_STAT0_PRTX(%lu) is invalid on this chip\n", offset); 277 return CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80; 278} 279#else 280#define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80) 281#endif 282#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 283static inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset) 284{ 285 if (!( 286 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 287 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 288 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 289 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 290 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 291 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 292 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 293 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 294 cvmx_warn("CVMX_PIP_STAT1_PRTX(%lu) is invalid on this chip\n", offset); 295 return CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80; 296} 297#else 298#define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80) 299#endif 300#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 301static inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset) 302{ 303 if (!( 304 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 305 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 306 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 307 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 308 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 309 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 310 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 311 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 312 cvmx_warn("CVMX_PIP_STAT2_PRTX(%lu) is invalid on this chip\n", offset); 313 return CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80; 314} 315#else 316#define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80) 317#endif 318#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319static inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset) 320{ 321 if (!( 322 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 323 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 324 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 325 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 326 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 327 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 328 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 329 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 330 cvmx_warn("CVMX_PIP_STAT3_PRTX(%lu) is invalid on this chip\n", offset); 331 return CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80; 332} 333#else 334#define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80) 335#endif 336#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 337static inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset) 338{ 339 if (!( 340 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 341 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 342 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 343 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 344 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 345 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 346 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 347 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 348 cvmx_warn("CVMX_PIP_STAT4_PRTX(%lu) is invalid on this chip\n", offset); 349 return CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80; 350} 351#else 352#define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80) 353#endif 354#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 355static inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset) 356{ 357 if (!( 358 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 359 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 360 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 361 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 362 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 363 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 364 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 365 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 366 cvmx_warn("CVMX_PIP_STAT5_PRTX(%lu) is invalid on this chip\n", offset); 367 return CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80; 368} 369#else 370#define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80) 371#endif 372#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 373static inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset) 374{ 375 if (!( 376 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 377 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 378 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 379 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 380 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 381 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 382 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 383 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 384 cvmx_warn("CVMX_PIP_STAT6_PRTX(%lu) is invalid on this chip\n", offset); 385 return CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80; 386} 387#else 388#define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80) 389#endif 390#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 391static inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset) 392{ 393 if (!( 394 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 395 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 396 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 397 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 398 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 399 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 400 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 401 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 402 cvmx_warn("CVMX_PIP_STAT7_PRTX(%lu) is invalid on this chip\n", offset); 403 return CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80; 404} 405#else 406#define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80) 407#endif 408#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 409static inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset) 410{ 411 if (!( 412 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 413 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 414 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 415 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 416 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 417 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 418 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 419 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 420 cvmx_warn("CVMX_PIP_STAT8_PRTX(%lu) is invalid on this chip\n", offset); 421 return CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80; 422} 423#else 424#define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80) 425#endif 426#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 427static inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset) 428{ 429 if (!( 430 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 431 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 432 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 433 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 434 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 435 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 436 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 437 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 438 cvmx_warn("CVMX_PIP_STAT9_PRTX(%lu) is invalid on this chip\n", offset); 439 return CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80; 440} 441#else 442#define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80) 443#endif 444#define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull)) 445#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446static inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset) 447{ 448 if (!( 449 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 450 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 451 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 452 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 453 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 454 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 455 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 456 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))))) 457 cvmx_warn("CVMX_PIP_STAT_INB_ERRSX(%lu) is invalid on this chip\n", offset); 458 return CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32; 459} 460#else 461#define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32) 462#endif 463#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 464static inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset) 465{ 466 if (!( 467 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 468 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 469 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 470 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 471 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 472 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 473 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 474 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))))) 475 cvmx_warn("CVMX_PIP_STAT_INB_OCTSX(%lu) is invalid on this chip\n", offset); 476 return CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32; 477} 478#else 479#define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32) 480#endif 481#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 482static inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset) 483{ 484 if (!( 485 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 486 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 487 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 488 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 489 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 490 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 491 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 492 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))))) 493 cvmx_warn("CVMX_PIP_STAT_INB_PKTSX(%lu) is invalid on this chip\n", offset); 494 return CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32; 495} 496#else 497#define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32) 498#endif 499#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 500static inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset) 501{ 502 if (!( 503 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) || 504 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) || 505 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) || 506 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) || 507 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) || 508 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) || 509 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) || 510 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63))))) 511 cvmx_warn("CVMX_PIP_TAG_INCX(%lu) is invalid on this chip\n", offset); 512 return CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8; 513} 514#else 515#define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8) 516#endif 517#define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull)) 518#define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull)) 519#define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull)) 520#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 521static inline uint64_t CVMX_PIP_XSTAT0_PRTX(unsigned long offset) 522{ 523 if (!( 524 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 525 cvmx_warn("CVMX_PIP_XSTAT0_PRTX(%lu) is invalid on this chip\n", offset); 526 return CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40; 527} 528#else 529#define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40) 530#endif 531#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 532static inline uint64_t CVMX_PIP_XSTAT1_PRTX(unsigned long offset) 533{ 534 if (!( 535 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 536 cvmx_warn("CVMX_PIP_XSTAT1_PRTX(%lu) is invalid on this chip\n", offset); 537 return CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40; 538} 539#else 540#define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40) 541#endif 542#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 543static inline uint64_t CVMX_PIP_XSTAT2_PRTX(unsigned long offset) 544{ 545 if (!( 546 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 547 cvmx_warn("CVMX_PIP_XSTAT2_PRTX(%lu) is invalid on this chip\n", offset); 548 return CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40; 549} 550#else 551#define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40) 552#endif 553#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 554static inline uint64_t CVMX_PIP_XSTAT3_PRTX(unsigned long offset) 555{ 556 if (!( 557 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 558 cvmx_warn("CVMX_PIP_XSTAT3_PRTX(%lu) is invalid on this chip\n", offset); 559 return CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40; 560} 561#else 562#define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40) 563#endif 564#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 565static inline uint64_t CVMX_PIP_XSTAT4_PRTX(unsigned long offset) 566{ 567 if (!( 568 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 569 cvmx_warn("CVMX_PIP_XSTAT4_PRTX(%lu) is invalid on this chip\n", offset); 570 return CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40; 571} 572#else 573#define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40) 574#endif 575#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 576static inline uint64_t CVMX_PIP_XSTAT5_PRTX(unsigned long offset) 577{ 578 if (!( 579 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 580 cvmx_warn("CVMX_PIP_XSTAT5_PRTX(%lu) is invalid on this chip\n", offset); 581 return CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40; 582} 583#else 584#define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40) 585#endif 586#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 587static inline uint64_t CVMX_PIP_XSTAT6_PRTX(unsigned long offset) 588{ 589 if (!( 590 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 591 cvmx_warn("CVMX_PIP_XSTAT6_PRTX(%lu) is invalid on this chip\n", offset); 592 return CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40; 593} 594#else 595#define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40) 596#endif 597#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 598static inline uint64_t CVMX_PIP_XSTAT7_PRTX(unsigned long offset) 599{ 600 if (!( 601 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 602 cvmx_warn("CVMX_PIP_XSTAT7_PRTX(%lu) is invalid on this chip\n", offset); 603 return CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40; 604} 605#else 606#define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40) 607#endif 608#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 609static inline uint64_t CVMX_PIP_XSTAT8_PRTX(unsigned long offset) 610{ 611 if (!( 612 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 613 cvmx_warn("CVMX_PIP_XSTAT8_PRTX(%lu) is invalid on this chip\n", offset); 614 return CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40; 615} 616#else 617#define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40) 618#endif 619#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 620static inline uint64_t CVMX_PIP_XSTAT9_PRTX(unsigned long offset) 621{ 622 if (!( 623 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))))) 624 cvmx_warn("CVMX_PIP_XSTAT9_PRTX(%lu) is invalid on this chip\n", offset); 625 return CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40; 626} 627#else 628#define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40) 629#endif 630 631/** 632 * cvmx_pip_bck_prs 633 * 634 * PIP_BCK_PRS = PIP's Back Pressure Register 635 * 636 * When to assert backpressure based on the todo list filling up 637 */ 638union cvmx_pip_bck_prs 639{ 640 uint64_t u64; 641 struct cvmx_pip_bck_prs_s 642 { 643#if __BYTE_ORDER == __BIG_ENDIAN 644 uint64_t bckprs : 1; /**< PIP is currently asserting backpressure to IOB 645 Backpressure from PIP will assert when the 646 entries to the todo list exceed HIWATER. 647 Backpressure will be held until the todo entries 648 is less than or equal to LOWATER. */ 649 uint64_t reserved_13_62 : 50; 650 uint64_t hiwater : 5; /**< Water mark in the todo list to assert backpressure 651 Legal values are 1-26. A 0 value will deadlock 652 the machine. A value > 26, will trash memory */ 653 uint64_t reserved_5_7 : 3; 654 uint64_t lowater : 5; /**< Water mark in the todo list to release backpressure 655 The LOWATER value should be < HIWATER. */ 656#else 657 uint64_t lowater : 5; 658 uint64_t reserved_5_7 : 3; 659 uint64_t hiwater : 5; 660 uint64_t reserved_13_62 : 50; 661 uint64_t bckprs : 1; 662#endif 663 } s; 664 struct cvmx_pip_bck_prs_s cn38xx; 665 struct cvmx_pip_bck_prs_s cn38xxp2; 666 struct cvmx_pip_bck_prs_s cn56xx; 667 struct cvmx_pip_bck_prs_s cn56xxp1; 668 struct cvmx_pip_bck_prs_s cn58xx; 669 struct cvmx_pip_bck_prs_s cn58xxp1; 670 struct cvmx_pip_bck_prs_s cn63xx; 671 struct cvmx_pip_bck_prs_s cn63xxp1; 672}; 673typedef union cvmx_pip_bck_prs cvmx_pip_bck_prs_t; 674 675/** 676 * cvmx_pip_bist_status 677 * 678 * PIP_BIST_STATUS = PIP's BIST Results 679 * 680 */ 681union cvmx_pip_bist_status 682{ 683 uint64_t u64; 684 struct cvmx_pip_bist_status_s 685 { 686#if __BYTE_ORDER == __BIG_ENDIAN 687 uint64_t reserved_18_63 : 46; 688 uint64_t bist : 18; /**< BIST Results. 689 HW sets a bit in BIST for for memory that fails 690 BIST. */ 691#else 692 uint64_t bist : 18; 693 uint64_t reserved_18_63 : 46; 694#endif 695 } s; 696 struct cvmx_pip_bist_status_s cn30xx; 697 struct cvmx_pip_bist_status_s cn31xx; 698 struct cvmx_pip_bist_status_s cn38xx; 699 struct cvmx_pip_bist_status_s cn38xxp2; 700 struct cvmx_pip_bist_status_cn50xx 701 { 702#if __BYTE_ORDER == __BIG_ENDIAN 703 uint64_t reserved_17_63 : 47; 704 uint64_t bist : 17; /**< BIST Results. 705 HW sets a bit in BIST for for memory that fails 706 BIST. */ 707#else 708 uint64_t bist : 17; 709 uint64_t reserved_17_63 : 47; 710#endif 711 } cn50xx; 712 struct cvmx_pip_bist_status_s cn52xx; 713 struct cvmx_pip_bist_status_s cn52xxp1; 714 struct cvmx_pip_bist_status_s cn56xx; 715 struct cvmx_pip_bist_status_s cn56xxp1; 716 struct cvmx_pip_bist_status_s cn58xx; 717 struct cvmx_pip_bist_status_s cn58xxp1; 718 struct cvmx_pip_bist_status_s cn63xx; 719 struct cvmx_pip_bist_status_s cn63xxp1; 720}; 721typedef union cvmx_pip_bist_status cvmx_pip_bist_status_t; 722 723/** 724 * cvmx_pip_clken 725 */ 726union cvmx_pip_clken 727{ 728 uint64_t u64; 729 struct cvmx_pip_clken_s 730 { 731#if __BYTE_ORDER == __BIG_ENDIAN 732 uint64_t reserved_1_63 : 63; 733 uint64_t clken : 1; /**< Controls the conditional clocking within PIP 734 0=Allow HW to control the clocks 735 1=Force the clocks to be always on */ 736#else 737 uint64_t clken : 1; 738 uint64_t reserved_1_63 : 63; 739#endif 740 } s; 741 struct cvmx_pip_clken_s cn63xx; 742 struct cvmx_pip_clken_s cn63xxp1; 743}; 744typedef union cvmx_pip_clken cvmx_pip_clken_t; 745 746/** 747 * cvmx_pip_crc_ctl# 748 * 749 * PIP_CRC_CTL = PIP CRC Control Register 750 * 751 * Controls datapath reflection when calculating CRC 752 */ 753union cvmx_pip_crc_ctlx 754{ 755 uint64_t u64; 756 struct cvmx_pip_crc_ctlx_s 757 { 758#if __BYTE_ORDER == __BIG_ENDIAN 759 uint64_t reserved_2_63 : 62; 760 uint64_t invres : 1; /**< Invert the result */ 761 uint64_t reflect : 1; /**< Reflect the bits in each byte. 762 Byte order does not change. 763 - 0: CRC is calculated MSB to LSB 764 - 1: CRC is calculated LSB to MSB */ 765#else 766 uint64_t reflect : 1; 767 uint64_t invres : 1; 768 uint64_t reserved_2_63 : 62; 769#endif 770 } s; 771 struct cvmx_pip_crc_ctlx_s cn38xx; 772 struct cvmx_pip_crc_ctlx_s cn38xxp2; 773 struct cvmx_pip_crc_ctlx_s cn58xx; 774 struct cvmx_pip_crc_ctlx_s cn58xxp1; 775}; 776typedef union cvmx_pip_crc_ctlx cvmx_pip_crc_ctlx_t; 777 778/** 779 * cvmx_pip_crc_iv# 780 * 781 * PIP_CRC_IV = PIP CRC IV Register 782 * 783 * Determines the IV used by the CRC algorithm 784 * 785 * Notes: 786 * * PIP_CRC_IV 787 * PIP_CRC_IV controls the initial state of the CRC algorithm. Octane can 788 * support a wide range of CRC algorithms and as such, the IV must be 789 * carefully constructed to meet the specific algorithm. The code below 790 * determines the value to program into Octane based on the algorthim's IV 791 * and width. In the case of Octane, the width should always be 32. 792 * 793 * PIP_CRC_IV0 sets the IV for ports 0-15 while PIP_CRC_IV1 sets the IV for 794 * ports 16-31. 795 * 796 * unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w) 797 * [ 798 * int i; 799 * int doit; 800 * unsigned int current_val = algorithm_iv; 801 * 802 * for(i = 0; i < w; i++) [ 803 * doit = current_val & 0x1; 804 * 805 * if(doit) current_val ^= poly; 806 * assert(!(current_val & 0x1)); 807 * 808 * current_val = (current_val >> 1) | (doit << (w-1)); 809 * ] 810 * 811 * return current_val; 812 * ] 813 */ 814union cvmx_pip_crc_ivx 815{ 816 uint64_t u64; 817 struct cvmx_pip_crc_ivx_s 818 { 819#if __BYTE_ORDER == __BIG_ENDIAN 820 uint64_t reserved_32_63 : 32; 821 uint64_t iv : 32; /**< IV used by the CRC algorithm. Default is FCS32. */ 822#else 823 uint64_t iv : 32; 824 uint64_t reserved_32_63 : 32; 825#endif 826 } s; 827 struct cvmx_pip_crc_ivx_s cn38xx; 828 struct cvmx_pip_crc_ivx_s cn38xxp2; 829 struct cvmx_pip_crc_ivx_s cn58xx; 830 struct cvmx_pip_crc_ivx_s cn58xxp1; 831}; 832typedef union cvmx_pip_crc_ivx cvmx_pip_crc_ivx_t; 833 834/** 835 * cvmx_pip_dec_ipsec# 836 * 837 * PIP_DEC_IPSEC = UDP or TCP ports to watch for DEC IPSEC 838 * 839 * PIP sets the dec_ipsec based on TCP or UDP destination port. 840 */ 841union cvmx_pip_dec_ipsecx 842{ 843 uint64_t u64; 844 struct cvmx_pip_dec_ipsecx_s 845 { 846#if __BYTE_ORDER == __BIG_ENDIAN 847 uint64_t reserved_18_63 : 46; 848 uint64_t tcp : 1; /**< This DPRT should be used for TCP packets */ 849 uint64_t udp : 1; /**< This DPRT should be used for UDP packets */ 850 uint64_t dprt : 16; /**< UDP or TCP destination port to match on */ 851#else 852 uint64_t dprt : 16; 853 uint64_t udp : 1; 854 uint64_t tcp : 1; 855 uint64_t reserved_18_63 : 46; 856#endif 857 } s; 858 struct cvmx_pip_dec_ipsecx_s cn30xx; 859 struct cvmx_pip_dec_ipsecx_s cn31xx; 860 struct cvmx_pip_dec_ipsecx_s cn38xx; 861 struct cvmx_pip_dec_ipsecx_s cn38xxp2; 862 struct cvmx_pip_dec_ipsecx_s cn50xx; 863 struct cvmx_pip_dec_ipsecx_s cn52xx; 864 struct cvmx_pip_dec_ipsecx_s cn52xxp1; 865 struct cvmx_pip_dec_ipsecx_s cn56xx; 866 struct cvmx_pip_dec_ipsecx_s cn56xxp1; 867 struct cvmx_pip_dec_ipsecx_s cn58xx; 868 struct cvmx_pip_dec_ipsecx_s cn58xxp1; 869 struct cvmx_pip_dec_ipsecx_s cn63xx; 870 struct cvmx_pip_dec_ipsecx_s cn63xxp1; 871}; 872typedef union cvmx_pip_dec_ipsecx cvmx_pip_dec_ipsecx_t; 873 874/** 875 * cvmx_pip_dsa_src_grp 876 */ 877union cvmx_pip_dsa_src_grp 878{ 879 uint64_t u64; 880 struct cvmx_pip_dsa_src_grp_s 881 { 882#if __BYTE_ORDER == __BIG_ENDIAN 883 uint64_t map15 : 4; /**< DSA Group Algorithm */ 884 uint64_t map14 : 4; /**< DSA Group Algorithm */ 885 uint64_t map13 : 4; /**< DSA Group Algorithm */ 886 uint64_t map12 : 4; /**< DSA Group Algorithm */ 887 uint64_t map11 : 4; /**< DSA Group Algorithm */ 888 uint64_t map10 : 4; /**< DSA Group Algorithm */ 889 uint64_t map9 : 4; /**< DSA Group Algorithm */ 890 uint64_t map8 : 4; /**< DSA Group Algorithm */ 891 uint64_t map7 : 4; /**< DSA Group Algorithm */ 892 uint64_t map6 : 4; /**< DSA Group Algorithm */ 893 uint64_t map5 : 4; /**< DSA Group Algorithm */ 894 uint64_t map4 : 4; /**< DSA Group Algorithm */ 895 uint64_t map3 : 4; /**< DSA Group Algorithm */ 896 uint64_t map2 : 4; /**< DSA Group Algorithm */ 897 uint64_t map1 : 4; /**< DSA Group Algorithm */ 898 uint64_t map0 : 4; /**< DSA Group Algorithm 899 Use the DSA source id to compute GRP */ 900#else 901 uint64_t map0 : 4; 902 uint64_t map1 : 4; 903 uint64_t map2 : 4; 904 uint64_t map3 : 4; 905 uint64_t map4 : 4; 906 uint64_t map5 : 4; 907 uint64_t map6 : 4; 908 uint64_t map7 : 4; 909 uint64_t map8 : 4; 910 uint64_t map9 : 4; 911 uint64_t map10 : 4; 912 uint64_t map11 : 4; 913 uint64_t map12 : 4; 914 uint64_t map13 : 4; 915 uint64_t map14 : 4; 916 uint64_t map15 : 4; 917#endif 918 } s; 919 struct cvmx_pip_dsa_src_grp_s cn52xx; 920 struct cvmx_pip_dsa_src_grp_s cn52xxp1; 921 struct cvmx_pip_dsa_src_grp_s cn56xx; 922 struct cvmx_pip_dsa_src_grp_s cn63xx; 923 struct cvmx_pip_dsa_src_grp_s cn63xxp1; 924}; 925typedef union cvmx_pip_dsa_src_grp cvmx_pip_dsa_src_grp_t; 926 927/** 928 * cvmx_pip_dsa_vid_grp 929 */ 930union cvmx_pip_dsa_vid_grp 931{ 932 uint64_t u64; 933 struct cvmx_pip_dsa_vid_grp_s 934 { 935#if __BYTE_ORDER == __BIG_ENDIAN 936 uint64_t map15 : 4; /**< DSA Group Algorithm */ 937 uint64_t map14 : 4; /**< DSA Group Algorithm */ 938 uint64_t map13 : 4; /**< DSA Group Algorithm */ 939 uint64_t map12 : 4; /**< DSA Group Algorithm */ 940 uint64_t map11 : 4; /**< DSA Group Algorithm */ 941 uint64_t map10 : 4; /**< DSA Group Algorithm */ 942 uint64_t map9 : 4; /**< DSA Group Algorithm */ 943 uint64_t map8 : 4; /**< DSA Group Algorithm */ 944 uint64_t map7 : 4; /**< DSA Group Algorithm */ 945 uint64_t map6 : 4; /**< DSA Group Algorithm */ 946 uint64_t map5 : 4; /**< DSA Group Algorithm */ 947 uint64_t map4 : 4; /**< DSA Group Algorithm */ 948 uint64_t map3 : 4; /**< DSA Group Algorithm */ 949 uint64_t map2 : 4; /**< DSA Group Algorithm */ 950 uint64_t map1 : 4; /**< DSA Group Algorithm */ 951 uint64_t map0 : 4; /**< DSA Group Algorithm 952 Use the DSA source id to compute GRP */ 953#else 954 uint64_t map0 : 4; 955 uint64_t map1 : 4; 956 uint64_t map2 : 4; 957 uint64_t map3 : 4; 958 uint64_t map4 : 4; 959 uint64_t map5 : 4; 960 uint64_t map6 : 4; 961 uint64_t map7 : 4; 962 uint64_t map8 : 4; 963 uint64_t map9 : 4; 964 uint64_t map10 : 4; 965 uint64_t map11 : 4; 966 uint64_t map12 : 4; 967 uint64_t map13 : 4; 968 uint64_t map14 : 4; 969 uint64_t map15 : 4; 970#endif 971 } s; 972 struct cvmx_pip_dsa_vid_grp_s cn52xx; 973 struct cvmx_pip_dsa_vid_grp_s cn52xxp1; 974 struct cvmx_pip_dsa_vid_grp_s cn56xx; 975 struct cvmx_pip_dsa_vid_grp_s cn63xx; 976 struct cvmx_pip_dsa_vid_grp_s cn63xxp1; 977}; 978typedef union cvmx_pip_dsa_vid_grp cvmx_pip_dsa_vid_grp_t; 979 980/** 981 * cvmx_pip_frm_len_chk# 982 * 983 * Notes: 984 * PIP_FRM_LEN_CHK0 is used for packets on packet interface0, PCI, PCI RAW, and PKO loopback ports. 985 * PIP_FRM_LEN_CHK1 is unused. 986 */ 987union cvmx_pip_frm_len_chkx 988{ 989 uint64_t u64; 990 struct cvmx_pip_frm_len_chkx_s 991 { 992#if __BYTE_ORDER == __BIG_ENDIAN 993 uint64_t reserved_32_63 : 32; 994 uint64_t maxlen : 16; /**< Byte count for Max-sized frame check 995 PIP_PRT_CFGn[MAXERR_EN] enables the check for 996 port n. 997 If enabled, failing packets set the MAXERR 998 interrupt and work-queue entry WORD2[opcode] is 999 set to OVER_FCS (0x3, if packet has bad FCS) or 1000 OVER_ERR (0x4, if packet has good FCS). 1001 The effective MAXLEN used by HW is 1002 PIP_PRT_CFG[DSA_EN] == 0, 1003 PIP_FRM_LEN_CHK[MAXLEN] + 4*VV + 4*VS 1004 PIP_PRT_CFG[DSA_EN] == 1, 1005 PIP_FRM_LEN_CHK[MAXLEN] + PIP_PRT_CFG[SKIP]+4*VS 1006 If PTP_MODE, the 8B timestamp is prepended to the 1007 packet. MAXLEN should be increased by 8 to 1008 compensate for the additional timestamp field. */ 1009 uint64_t minlen : 16; /**< Byte count for Min-sized frame check 1010 PIP_PRT_CFGn[MINERR_EN] enables the check for 1011 port n. 1012 If enabled, failing packets set the MINERR 1013 interrupt and work-queue entry WORD2[opcode] is 1014 set to UNDER_FCS (0x6, if packet has bad FCS) or 1015 UNDER_ERR (0x8, if packet has good FCS). 1016 If PTP_MODE, the 8B timestamp is prepended to the 1017 packet. MINLEN should be increased by 8 to 1018 compensate for the additional timestamp field. */ 1019#else 1020 uint64_t minlen : 16; 1021 uint64_t maxlen : 16; 1022 uint64_t reserved_32_63 : 32; 1023#endif 1024 } s; 1025 struct cvmx_pip_frm_len_chkx_s cn50xx; 1026 struct cvmx_pip_frm_len_chkx_s cn52xx; 1027 struct cvmx_pip_frm_len_chkx_s cn52xxp1; 1028 struct cvmx_pip_frm_len_chkx_s cn56xx; 1029 struct cvmx_pip_frm_len_chkx_s cn56xxp1; 1030 struct cvmx_pip_frm_len_chkx_s cn63xx; 1031 struct cvmx_pip_frm_len_chkx_s cn63xxp1; 1032}; 1033typedef union cvmx_pip_frm_len_chkx cvmx_pip_frm_len_chkx_t; 1034 1035/** 1036 * cvmx_pip_gbl_cfg 1037 * 1038 * PIP_GBL_CFG = PIP's Global Config Register 1039 * 1040 * Global config information that applies to all ports. 1041 * 1042 * Notes: 1043 * * IP6_UDP 1044 * IPv4 allows optional UDP checksum by sending the all 0's patterns. IPv6 1045 * outlaws this and the spec says to always check UDP checksum. This mode 1046 * bit allows the user to treat IPv6 as IPv4, meaning that the all 0's 1047 * pattern will cause a UDP checksum pass. 1048 */ 1049union cvmx_pip_gbl_cfg 1050{ 1051 uint64_t u64; 1052 struct cvmx_pip_gbl_cfg_s 1053 { 1054#if __BYTE_ORDER == __BIG_ENDIAN 1055 uint64_t reserved_19_63 : 45; 1056 uint64_t tag_syn : 1; /**< Do not include src_crc for TCP/SYN&!ACK packets 1057 0 = include src_crc 1058 1 = tag hash is dst_crc for TCP/SYN&!ACK packets */ 1059 uint64_t ip6_udp : 1; /**< IPv6/UDP checksum is not optional 1060 0 = Allow optional checksum code 1061 1 = Do not allow optional checksum code */ 1062 uint64_t max_l2 : 1; /**< Config bit to choose the largest L2 frame size 1063 Chooses the value of the L2 Type/Length field 1064 to classify the frame as length. 1065 0 = 1500 / 0x5dc 1066 1 = 1535 / 0x5ff */ 1067 uint64_t reserved_11_15 : 5; 1068 uint64_t raw_shf : 3; /**< RAW Packet shift amount 1069 Number of bytes to pad a RAW packet. */ 1070 uint64_t reserved_3_7 : 5; 1071 uint64_t nip_shf : 3; /**< Non-IP shift amount 1072 Number of bytes to pad a packet that has been 1073 classified as not IP. */ 1074#else 1075 uint64_t nip_shf : 3; 1076 uint64_t reserved_3_7 : 5; 1077 uint64_t raw_shf : 3; 1078 uint64_t reserved_11_15 : 5; 1079 uint64_t max_l2 : 1; 1080 uint64_t ip6_udp : 1; 1081 uint64_t tag_syn : 1; 1082 uint64_t reserved_19_63 : 45; 1083#endif 1084 } s; 1085 struct cvmx_pip_gbl_cfg_s cn30xx; 1086 struct cvmx_pip_gbl_cfg_s cn31xx; 1087 struct cvmx_pip_gbl_cfg_s cn38xx; 1088 struct cvmx_pip_gbl_cfg_s cn38xxp2; 1089 struct cvmx_pip_gbl_cfg_s cn50xx; 1090 struct cvmx_pip_gbl_cfg_s cn52xx; 1091 struct cvmx_pip_gbl_cfg_s cn52xxp1; 1092 struct cvmx_pip_gbl_cfg_s cn56xx; 1093 struct cvmx_pip_gbl_cfg_s cn56xxp1; 1094 struct cvmx_pip_gbl_cfg_s cn58xx; 1095 struct cvmx_pip_gbl_cfg_s cn58xxp1; 1096 struct cvmx_pip_gbl_cfg_s cn63xx; 1097 struct cvmx_pip_gbl_cfg_s cn63xxp1; 1098}; 1099typedef union cvmx_pip_gbl_cfg cvmx_pip_gbl_cfg_t; 1100 1101/** 1102 * cvmx_pip_gbl_ctl 1103 * 1104 * PIP_GBL_CTL = PIP's Global Control Register 1105 * 1106 * Global control information. These are the global checker enables for 1107 * IPv4/IPv6 and TCP/UDP parsing. The enables effect all ports. 1108 * 1109 * Notes: 1110 * The following text describes the conditions in which each checker will 1111 * assert and flag an exception. By disabling the checker, the exception will 1112 * not be flagged and the packet will be parsed as best it can. Note, by 1113 * disabling conditions, packets can be parsed incorrectly (.i.e. IP_MAL and 1114 * L4_MAL could cause bits to be seen in the wrong place. IP_CHK and L4_CHK 1115 * means that the packet was corrupted). 1116 * 1117 * * IP_CHK 1118 * Indicates that an IPv4 packet contained an IPv4 header checksum 1119 * violations. Only applies to packets classified as IPv4. 1120 * 1121 * * IP_MAL 1122 * Indicates that the packet was malformed. Malformed packets are defined as 1123 * packets that are not long enough to cover the IP header or not long enough 1124 * to cover the length in the IP header. 1125 * 1126 * * IP_HOP 1127 * Indicates that the IPv4 TTL field or IPv6 HOP field is zero. 1128 * 1129 * * IP4_OPTS 1130 * Indicates the presence of IPv4 options. It is set when the length != 5. 1131 * This only applies to packets classified as IPv4. 1132 * 1133 * * IP6_EEXT 1134 * Indicate the presence of IPv6 early extension headers. These bits only 1135 * apply to packets classified as IPv6. Bit 0 will flag early extensions 1136 * when next_header is any one of the following... 1137 * 1138 * - hop-by-hop (0) 1139 * - destination (60) 1140 * - routing (43) 1141 * 1142 * Bit 1 will flag early extentions when next_header is NOT any of the 1143 * following... 1144 * 1145 * - TCP (6) 1146 * - UDP (17) 1147 * - fragmentation (44) 1148 * - ICMP (58) 1149 * - IPSEC ESP (50) 1150 * - IPSEC AH (51) 1151 * - IPCOMP 1152 * 1153 * * L4_MAL 1154 * Indicates that a TCP or UDP packet is not long enough to cover the TCP or 1155 * UDP header. 1156 * 1157 * * L4_PRT 1158 * Indicates that a TCP or UDP packet has an illegal port number - either the 1159 * source or destination port is zero. 1160 * 1161 * * L4_CHK 1162 * Indicates that a packet classified as either TCP or UDP contains an L4 1163 * checksum failure 1164 * 1165 * * L4_LEN 1166 * Indicates that the TCP or UDP length does not match the the IP length. 1167 * 1168 * * TCP_FLAG 1169 * Indicates any of the following conditions... 1170 * 1171 * [URG, ACK, PSH, RST, SYN, FIN] : tcp_flag 1172 * 6'b000001: (FIN only) 1173 * 6'b000000: (0) 1174 * 6'bxxx1x1: (RST+FIN+*) 1175 * 6'b1xxx1x: (URG+SYN+*) 1176 * 6'bxxx11x: (RST+SYN+*) 1177 * 6'bxxxx11: (SYN+FIN+*) 1178 */ 1179union cvmx_pip_gbl_ctl 1180{ 1181 uint64_t u64; 1182 struct cvmx_pip_gbl_ctl_s 1183 { 1184#if __BYTE_ORDER == __BIG_ENDIAN 1185 uint64_t reserved_28_63 : 36; 1186 uint64_t ihmsk_dis : 1; /**< Instruction Header Mask Disable 1187 0=Allow NTAG,NTT,NGRP,NQOS bits in the 1188 instruction header to control which fields from 1189 the instruction header are used for WQE WORD2. 1190 1=Ignore the NTAG,NTT,NGRP,NQOS bits in the 1191 instruction header and act as if these fields 1192 were zero. Thus always use the TAG,TT,GRP,QOS 1193 (depending on the instruction header length) 1194 from the instruction header for the WQE WORD2. */ 1195 uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm 1196 Use the DSA source id to compute GRP */ 1197 uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm 1198 Use the DSA source id to compute GRP when the 1199 DSA tag command to TO_CPU */ 1200 uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm 1201 Use the DSA VLAN id to compute GRP */ 1202 uint64_t reserved_21_23 : 3; 1203 uint64_t ring_en : 1; /**< Enable PCIe ring information in WQE */ 1204 uint64_t reserved_17_19 : 3; 1205 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 1206 Does not apply to PCI ports (32-35) 1207 When using 2-byte instruction header words, 1208 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 1209 uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking 1210 0=use the 1st (network order) VLAN 1211 1=use the 2nd (network order) VLAN */ 1212 uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking 1213 0=use the 1st (network order) VLAN 1214 1=use the 2nd (network order) VLAN */ 1215 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 1216 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 1217 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 1218 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 1219 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 1220 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 1221 uint64_t reserved_6_7 : 2; 1222 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 1223 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 1224 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 1225 uint64_t ip_mal : 1; /**< Enable malformed check */ 1226 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 1227#else 1228 uint64_t ip_chk : 1; 1229 uint64_t ip_mal : 1; 1230 uint64_t ip_hop : 1; 1231 uint64_t ip4_opts : 1; 1232 uint64_t ip6_eext : 2; 1233 uint64_t reserved_6_7 : 2; 1234 uint64_t l4_mal : 1; 1235 uint64_t l4_prt : 1; 1236 uint64_t l4_chk : 1; 1237 uint64_t l4_len : 1; 1238 uint64_t tcp_flag : 1; 1239 uint64_t l2_mal : 1; 1240 uint64_t vs_qos : 1; 1241 uint64_t vs_wqe : 1; 1242 uint64_t ignrs : 1; 1243 uint64_t reserved_17_19 : 3; 1244 uint64_t ring_en : 1; 1245 uint64_t reserved_21_23 : 3; 1246 uint64_t dsa_grp_sid : 1; 1247 uint64_t dsa_grp_scmd : 1; 1248 uint64_t dsa_grp_tvid : 1; 1249 uint64_t ihmsk_dis : 1; 1250 uint64_t reserved_28_63 : 36; 1251#endif 1252 } s; 1253 struct cvmx_pip_gbl_ctl_cn30xx 1254 { 1255#if __BYTE_ORDER == __BIG_ENDIAN 1256 uint64_t reserved_17_63 : 47; 1257 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 1258 Only applies to the packet interface prts (0-31) 1259 When using 2-byte instruction header words, 1260 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 1261 uint64_t vs_wqe : 1; /**< Which VLAN CFI and ID to use when VLAN Stacking 1262 0=use the 1st (network order) VLAN 1263 1=use the 2nd (network order) VLAN */ 1264 uint64_t vs_qos : 1; /**< Which VLAN priority to use when VLAN Stacking 1265 0=use the 1st (network order) VLAN 1266 1=use the 2nd (network order) VLAN */ 1267 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 1268 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 1269 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 1270 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 1271 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 1272 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 1273 uint64_t reserved_6_7 : 2; 1274 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 1275 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 1276 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 1277 uint64_t ip_mal : 1; /**< Enable malformed check */ 1278 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 1279#else 1280 uint64_t ip_chk : 1; 1281 uint64_t ip_mal : 1; 1282 uint64_t ip_hop : 1; 1283 uint64_t ip4_opts : 1; 1284 uint64_t ip6_eext : 2; 1285 uint64_t reserved_6_7 : 2; 1286 uint64_t l4_mal : 1; 1287 uint64_t l4_prt : 1; 1288 uint64_t l4_chk : 1; 1289 uint64_t l4_len : 1; 1290 uint64_t tcp_flag : 1; 1291 uint64_t l2_mal : 1; 1292 uint64_t vs_qos : 1; 1293 uint64_t vs_wqe : 1; 1294 uint64_t ignrs : 1; 1295 uint64_t reserved_17_63 : 47; 1296#endif 1297 } cn30xx; 1298 struct cvmx_pip_gbl_ctl_cn30xx cn31xx; 1299 struct cvmx_pip_gbl_ctl_cn30xx cn38xx; 1300 struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2; 1301 struct cvmx_pip_gbl_ctl_cn30xx cn50xx; 1302 struct cvmx_pip_gbl_ctl_cn52xx 1303 { 1304#if __BYTE_ORDER == __BIG_ENDIAN 1305 uint64_t reserved_27_63 : 37; 1306 uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm 1307 Use the DSA source id to compute GRP */ 1308 uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm 1309 Use the DSA source id to compute GRP when the 1310 DSA tag command to TO_CPU */ 1311 uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm 1312 Use the DSA VLAN id to compute GRP */ 1313 uint64_t reserved_21_23 : 3; 1314 uint64_t ring_en : 1; /**< Enable PCIe ring information in WQE */ 1315 uint64_t reserved_17_19 : 3; 1316 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 1317 Does not apply to PCI ports (32-35) 1318 When using 2-byte instruction header words, 1319 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 1320 uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking 1321 0=use the 1st (network order) VLAN 1322 1=use the 2nd (network order) VLAN */ 1323 uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking 1324 0=use the 1st (network order) VLAN 1325 1=use the 2nd (network order) VLAN */ 1326 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 1327 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 1328 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 1329 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 1330 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 1331 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 1332 uint64_t reserved_6_7 : 2; 1333 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 1334 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 1335 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 1336 uint64_t ip_mal : 1; /**< Enable malformed check */ 1337 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 1338#else 1339 uint64_t ip_chk : 1; 1340 uint64_t ip_mal : 1; 1341 uint64_t ip_hop : 1; 1342 uint64_t ip4_opts : 1; 1343 uint64_t ip6_eext : 2; 1344 uint64_t reserved_6_7 : 2; 1345 uint64_t l4_mal : 1; 1346 uint64_t l4_prt : 1; 1347 uint64_t l4_chk : 1; 1348 uint64_t l4_len : 1; 1349 uint64_t tcp_flag : 1; 1350 uint64_t l2_mal : 1; 1351 uint64_t vs_qos : 1; 1352 uint64_t vs_wqe : 1; 1353 uint64_t ignrs : 1; 1354 uint64_t reserved_17_19 : 3; 1355 uint64_t ring_en : 1; 1356 uint64_t reserved_21_23 : 3; 1357 uint64_t dsa_grp_sid : 1; 1358 uint64_t dsa_grp_scmd : 1; 1359 uint64_t dsa_grp_tvid : 1; 1360 uint64_t reserved_27_63 : 37; 1361#endif 1362 } cn52xx; 1363 struct cvmx_pip_gbl_ctl_cn52xx cn52xxp1; 1364 struct cvmx_pip_gbl_ctl_cn52xx cn56xx; 1365 struct cvmx_pip_gbl_ctl_cn56xxp1 1366 { 1367#if __BYTE_ORDER == __BIG_ENDIAN 1368 uint64_t reserved_21_63 : 43; 1369 uint64_t ring_en : 1; /**< Enable PCIe ring information in WQE */ 1370 uint64_t reserved_17_19 : 3; 1371 uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 1372 Does not apply to PCI ports (32-35) 1373 When using 2-byte instruction header words, 1374 either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 1375 uint64_t vs_wqe : 1; /**< Which VLAN CFI and ID to use when VLAN Stacking 1376 0=use the 1st (network order) VLAN 1377 1=use the 2nd (network order) VLAN */ 1378 uint64_t vs_qos : 1; /**< Which VLAN priority to use when VLAN Stacking 1379 0=use the 1st (network order) VLAN 1380 1=use the 2nd (network order) VLAN */ 1381 uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 1382 uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 1383 uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 1384 uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 1385 uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 1386 uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 1387 uint64_t reserved_6_7 : 2; 1388 uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 1389 uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 1390 uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 1391 uint64_t ip_mal : 1; /**< Enable malformed check */ 1392 uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 1393#else 1394 uint64_t ip_chk : 1; 1395 uint64_t ip_mal : 1; 1396 uint64_t ip_hop : 1; 1397 uint64_t ip4_opts : 1; 1398 uint64_t ip6_eext : 2; 1399 uint64_t reserved_6_7 : 2; 1400 uint64_t l4_mal : 1; 1401 uint64_t l4_prt : 1; 1402 uint64_t l4_chk : 1; 1403 uint64_t l4_len : 1; 1404 uint64_t tcp_flag : 1; 1405 uint64_t l2_mal : 1; 1406 uint64_t vs_qos : 1; 1407 uint64_t vs_wqe : 1; 1408 uint64_t ignrs : 1; 1409 uint64_t reserved_17_19 : 3; 1410 uint64_t ring_en : 1; 1411 uint64_t reserved_21_63 : 43; 1412#endif 1413 } cn56xxp1; 1414 struct cvmx_pip_gbl_ctl_cn30xx cn58xx; 1415 struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1; 1416 struct cvmx_pip_gbl_ctl_s cn63xx; 1417 struct cvmx_pip_gbl_ctl_s cn63xxp1; 1418}; 1419typedef union cvmx_pip_gbl_ctl cvmx_pip_gbl_ctl_t; 1420 1421/** 1422 * cvmx_pip_hg_pri_qos 1423 * 1424 * Notes: 1425 * This register controls accesses to the HG_QOS_TABLE. To write an entry of 1426 * the table, write PIP_HG_PRI_QOS with PRI=table address, QOS=priority level, 1427 * UP_QOS=1. To read an entry of the table, write PIP_HG_PRI_QOS with 1428 * PRI=table address, QOS=dont_carepriority level, UP_QOS=0 and then read 1429 * PIP_HG_PRI_QOS. The table data will be in PIP_HG_PRI_QOS[QOS]. 1430 */ 1431union cvmx_pip_hg_pri_qos 1432{ 1433 uint64_t u64; 1434 struct cvmx_pip_hg_pri_qos_s 1435 { 1436#if __BYTE_ORDER == __BIG_ENDIAN 1437 uint64_t reserved_13_63 : 51; 1438 uint64_t up_qos : 1; /**< When written to '1', updates the entry in the 1439 HG_QOS_TABLE as specified by PRI to a value of 1440 QOS as follows 1441 HG_QOS_TABLE[PRI] = QOS */ 1442 uint64_t reserved_11_11 : 1; 1443 uint64_t qos : 3; /**< QOS Map level to priority */ 1444 uint64_t reserved_6_7 : 2; 1445 uint64_t pri : 6; /**< The priority level from HiGig header 1446 HiGig/HiGig+ PRI = [1'b0, CNG[1:0], COS[2:0]] 1447 HiGig2 PRI = [DP[1:0], TC[3:0]] */ 1448#else 1449 uint64_t pri : 6; 1450 uint64_t reserved_6_7 : 2; 1451 uint64_t qos : 3; 1452 uint64_t reserved_11_11 : 1; 1453 uint64_t up_qos : 1; 1454 uint64_t reserved_13_63 : 51; 1455#endif 1456 } s; 1457 struct cvmx_pip_hg_pri_qos_s cn52xx; 1458 struct cvmx_pip_hg_pri_qos_s cn52xxp1; 1459 struct cvmx_pip_hg_pri_qos_s cn56xx; 1460 struct cvmx_pip_hg_pri_qos_s cn63xx; 1461 struct cvmx_pip_hg_pri_qos_s cn63xxp1; 1462}; 1463typedef union cvmx_pip_hg_pri_qos cvmx_pip_hg_pri_qos_t; 1464 1465/** 1466 * cvmx_pip_int_en 1467 * 1468 * PIP_INT_EN = PIP's Interrupt Enable Register 1469 * 1470 * Determines if hardward should raise an interrupt to software 1471 * when an exception event occurs. 1472 */ 1473union cvmx_pip_int_en 1474{ 1475 uint64_t u64; 1476 struct cvmx_pip_int_en_s 1477 { 1478#if __BYTE_ORDER == __BIG_ENDIAN 1479 uint64_t reserved_13_63 : 51; 1480 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 1481 stripping in IPD is enable */ 1482 uint64_t lenerr : 1; /**< Frame was received with length error */ 1483 uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1484 uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1485 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1486 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1487 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 1488 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 1489 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1490 uint64_t prtnxa : 1; /**< Non-existent port */ 1491 uint64_t bckprs : 1; /**< PIP asserted backpressure */ 1492 uint64_t crcerr : 1; /**< PIP calculated bad CRC */ 1493 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1494#else 1495 uint64_t pktdrp : 1; 1496 uint64_t crcerr : 1; 1497 uint64_t bckprs : 1; 1498 uint64_t prtnxa : 1; 1499 uint64_t badtag : 1; 1500 uint64_t skprunt : 1; 1501 uint64_t todoovr : 1; 1502 uint64_t feperr : 1; 1503 uint64_t beperr : 1; 1504 uint64_t minerr : 1; 1505 uint64_t maxerr : 1; 1506 uint64_t lenerr : 1; 1507 uint64_t punyerr : 1; 1508 uint64_t reserved_13_63 : 51; 1509#endif 1510 } s; 1511 struct cvmx_pip_int_en_cn30xx 1512 { 1513#if __BYTE_ORDER == __BIG_ENDIAN 1514 uint64_t reserved_9_63 : 55; 1515 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1516 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1517 uint64_t todoovr : 1; /**< Todo list overflow 1518 (not used in O2P) */ 1519 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 1520 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1521 uint64_t prtnxa : 1; /**< Non-existent port */ 1522 uint64_t bckprs : 1; /**< PIP asserted backpressure 1523 (not used in O2P) */ 1524 uint64_t crcerr : 1; /**< PIP calculated bad CRC 1525 (not used in O2P) */ 1526 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1527#else 1528 uint64_t pktdrp : 1; 1529 uint64_t crcerr : 1; 1530 uint64_t bckprs : 1; 1531 uint64_t prtnxa : 1; 1532 uint64_t badtag : 1; 1533 uint64_t skprunt : 1; 1534 uint64_t todoovr : 1; 1535 uint64_t feperr : 1; 1536 uint64_t beperr : 1; 1537 uint64_t reserved_9_63 : 55; 1538#endif 1539 } cn30xx; 1540 struct cvmx_pip_int_en_cn30xx cn31xx; 1541 struct cvmx_pip_int_en_cn30xx cn38xx; 1542 struct cvmx_pip_int_en_cn30xx cn38xxp2; 1543 struct cvmx_pip_int_en_cn50xx 1544 { 1545#if __BYTE_ORDER == __BIG_ENDIAN 1546 uint64_t reserved_12_63 : 52; 1547 uint64_t lenerr : 1; /**< Frame was received with length error */ 1548 uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1549 uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1550 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1551 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1552 uint64_t todoovr : 1; /**< Todo list overflow */ 1553 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 1554 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1555 uint64_t prtnxa : 1; /**< Non-existent port */ 1556 uint64_t bckprs : 1; /**< PIP asserted backpressure */ 1557 uint64_t reserved_1_1 : 1; 1558 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1559#else 1560 uint64_t pktdrp : 1; 1561 uint64_t reserved_1_1 : 1; 1562 uint64_t bckprs : 1; 1563 uint64_t prtnxa : 1; 1564 uint64_t badtag : 1; 1565 uint64_t skprunt : 1; 1566 uint64_t todoovr : 1; 1567 uint64_t feperr : 1; 1568 uint64_t beperr : 1; 1569 uint64_t minerr : 1; 1570 uint64_t maxerr : 1; 1571 uint64_t lenerr : 1; 1572 uint64_t reserved_12_63 : 52; 1573#endif 1574 } cn50xx; 1575 struct cvmx_pip_int_en_cn52xx 1576 { 1577#if __BYTE_ORDER == __BIG_ENDIAN 1578 uint64_t reserved_13_63 : 51; 1579 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 1580 stripping in IPD is enable */ 1581 uint64_t lenerr : 1; /**< Frame was received with length error */ 1582 uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1583 uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1584 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1585 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1586 uint64_t todoovr : 1; /**< Todo list overflow */ 1587 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 1588 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1589 uint64_t prtnxa : 1; /**< Non-existent port */ 1590 uint64_t bckprs : 1; /**< PIP asserted backpressure */ 1591 uint64_t reserved_1_1 : 1; 1592 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1593#else 1594 uint64_t pktdrp : 1; 1595 uint64_t reserved_1_1 : 1; 1596 uint64_t bckprs : 1; 1597 uint64_t prtnxa : 1; 1598 uint64_t badtag : 1; 1599 uint64_t skprunt : 1; 1600 uint64_t todoovr : 1; 1601 uint64_t feperr : 1; 1602 uint64_t beperr : 1; 1603 uint64_t minerr : 1; 1604 uint64_t maxerr : 1; 1605 uint64_t lenerr : 1; 1606 uint64_t punyerr : 1; 1607 uint64_t reserved_13_63 : 51; 1608#endif 1609 } cn52xx; 1610 struct cvmx_pip_int_en_cn52xx cn52xxp1; 1611 struct cvmx_pip_int_en_s cn56xx; 1612 struct cvmx_pip_int_en_cn56xxp1 1613 { 1614#if __BYTE_ORDER == __BIG_ENDIAN 1615 uint64_t reserved_12_63 : 52; 1616 uint64_t lenerr : 1; /**< Frame was received with length error */ 1617 uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1618 uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1619 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1620 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1621 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 1622 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 1623 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1624 uint64_t prtnxa : 1; /**< Non-existent port */ 1625 uint64_t bckprs : 1; /**< PIP asserted backpressure */ 1626 uint64_t crcerr : 1; /**< PIP calculated bad CRC 1627 (Disabled in 56xx) */ 1628 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1629#else 1630 uint64_t pktdrp : 1; 1631 uint64_t crcerr : 1; 1632 uint64_t bckprs : 1; 1633 uint64_t prtnxa : 1; 1634 uint64_t badtag : 1; 1635 uint64_t skprunt : 1; 1636 uint64_t todoovr : 1; 1637 uint64_t feperr : 1; 1638 uint64_t beperr : 1; 1639 uint64_t minerr : 1; 1640 uint64_t maxerr : 1; 1641 uint64_t lenerr : 1; 1642 uint64_t reserved_12_63 : 52; 1643#endif 1644 } cn56xxp1; 1645 struct cvmx_pip_int_en_cn58xx 1646 { 1647#if __BYTE_ORDER == __BIG_ENDIAN 1648 uint64_t reserved_13_63 : 51; 1649 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 1650 stripping in IPD is enable */ 1651 uint64_t reserved_9_11 : 3; 1652 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1653 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1654 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 1655 uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 1656 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1657 uint64_t prtnxa : 1; /**< Non-existent port */ 1658 uint64_t bckprs : 1; /**< PIP asserted backpressure */ 1659 uint64_t crcerr : 1; /**< PIP calculated bad CRC */ 1660 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1661#else 1662 uint64_t pktdrp : 1; 1663 uint64_t crcerr : 1; 1664 uint64_t bckprs : 1; 1665 uint64_t prtnxa : 1; 1666 uint64_t badtag : 1; 1667 uint64_t skprunt : 1; 1668 uint64_t todoovr : 1; 1669 uint64_t feperr : 1; 1670 uint64_t beperr : 1; 1671 uint64_t reserved_9_11 : 3; 1672 uint64_t punyerr : 1; 1673 uint64_t reserved_13_63 : 51; 1674#endif 1675 } cn58xx; 1676 struct cvmx_pip_int_en_cn30xx cn58xxp1; 1677 struct cvmx_pip_int_en_s cn63xx; 1678 struct cvmx_pip_int_en_s cn63xxp1; 1679}; 1680typedef union cvmx_pip_int_en cvmx_pip_int_en_t; 1681 1682/** 1683 * cvmx_pip_int_reg 1684 * 1685 * PIP_INT_REG = PIP's Interrupt Register 1686 * 1687 * Any exception event that occurs is captured in the PIP_INT_REG. 1688 * PIP_INT_REG will set the exception bit regardless of the value 1689 * of PIP_INT_EN. PIP_INT_EN only controls if an interrupt is 1690 * raised to software. 1691 * 1692 * Notes: 1693 * * TODOOVR 1694 * The PIP Todo list stores packets that have been received and require work 1695 * queue entry generation. PIP will normally assert backpressure when the 1696 * list fills up such that any error is normally is result of a programming 1697 * the PIP_BCK_PRS[HIWATER] incorrectly. PIP itself can handle 29M 1698 * packets/sec X500MHz or 15Gbs X 64B packets. 1699 * 1700 * * SKPRUNT 1701 * If a packet size is less then the amount programmed in the per port 1702 * skippers, then there will be nothing to parse and the entire packet will 1703 * basically be skipped over. This is probably not what the user desired, so 1704 * there is an indication to software. 1705 * 1706 * * BADTAG 1707 * A tag is considered bad when it is resued by a new packet before it was 1708 * released by PIP. PIP considers a tag released by one of two methods. 1709 * . QOS dropped so that it is released over the pip__ipd_release bus. 1710 * . WorkQ entry is validated by the pip__ipd_done signal 1711 * 1712 * * PRTNXA 1713 * If PIP receives a packet that is not in the valid port range, the port 1714 * processed will be mapped into the valid port space (the mapping is 1715 * currently unpredictable) and the PRTNXA bit will be set. PRTNXA will be 1716 * set for packets received under the following conditions: 1717 * 1718 * * packet ports (ports 0-31) 1719 * - GMX_INF_MODE[TYPE]==0 (SGMII), received port is 4-15 or 20-31 1720 * - GMX_INF_MODE[TYPE]==1 (XAUI), received port is 1-15 or 17-31 1721 * * upper ports (pci and loopback ports 32-63) 1722 * - received port is 40-47 or 52-63 1723 * 1724 * * BCKPRS 1725 * PIP can assert backpressure to the receive logic when the todo list 1726 * exceeds a high-water mark (see PIP_BCK_PRS for more details). When this 1727 * occurs, PIP can raise an interrupt to software. 1728 * 1729 * * CRCERR 1730 * Octane can compute CRC in two places. Each RGMII port will compute its 1731 * own CRC, but PIP can provide an additional check or check loopback or 1732 * PCI ports. If PIP computes a bad CRC, then PIP will raise an interrupt. 1733 * 1734 * * PKTDRP 1735 * PIP can drop packets based on QOS results received from IPD. If the QOS 1736 * algorithm decides to drop a packet, PIP will assert an interrupt. 1737 */ 1738union cvmx_pip_int_reg 1739{ 1740 uint64_t u64; 1741 struct cvmx_pip_int_reg_s 1742 { 1743#if __BYTE_ORDER == __BIG_ENDIAN 1744 uint64_t reserved_13_63 : 51; 1745 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 1746 stripping in IPD is enable */ 1747 uint64_t lenerr : 1; /**< Frame was received with length error */ 1748 uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1749 uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1750 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1751 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1752 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 1753 uint64_t skprunt : 1; /**< Packet was engulfed by skipper 1754 This interrupt can occur with received PARTIAL 1755 packets that are truncated to SKIP bytes or 1756 smaller. */ 1757 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1758 uint64_t prtnxa : 1; /**< Non-existent port */ 1759 uint64_t bckprs : 1; /**< PIP asserted backpressure */ 1760 uint64_t crcerr : 1; /**< PIP calculated bad CRC */ 1761 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1762#else 1763 uint64_t pktdrp : 1; 1764 uint64_t crcerr : 1; 1765 uint64_t bckprs : 1; 1766 uint64_t prtnxa : 1; 1767 uint64_t badtag : 1; 1768 uint64_t skprunt : 1; 1769 uint64_t todoovr : 1; 1770 uint64_t feperr : 1; 1771 uint64_t beperr : 1; 1772 uint64_t minerr : 1; 1773 uint64_t maxerr : 1; 1774 uint64_t lenerr : 1; 1775 uint64_t punyerr : 1; 1776 uint64_t reserved_13_63 : 51; 1777#endif 1778 } s; 1779 struct cvmx_pip_int_reg_cn30xx 1780 { 1781#if __BYTE_ORDER == __BIG_ENDIAN 1782 uint64_t reserved_9_63 : 55; 1783 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1784 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1785 uint64_t todoovr : 1; /**< Todo list overflow 1786 (not used in O2P) */ 1787 uint64_t skprunt : 1; /**< Packet was engulfed by skipper 1788 This interrupt can occur with received PARTIAL 1789 packets that are truncated to SKIP bytes or 1790 smaller. */ 1791 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1792 uint64_t prtnxa : 1; /**< Non-existent port */ 1793 uint64_t bckprs : 1; /**< PIP asserted backpressure 1794 (not used in O2P) */ 1795 uint64_t crcerr : 1; /**< PIP calculated bad CRC 1796 (not used in O2P) */ 1797 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1798#else 1799 uint64_t pktdrp : 1; 1800 uint64_t crcerr : 1; 1801 uint64_t bckprs : 1; 1802 uint64_t prtnxa : 1; 1803 uint64_t badtag : 1; 1804 uint64_t skprunt : 1; 1805 uint64_t todoovr : 1; 1806 uint64_t feperr : 1; 1807 uint64_t beperr : 1; 1808 uint64_t reserved_9_63 : 55; 1809#endif 1810 } cn30xx; 1811 struct cvmx_pip_int_reg_cn30xx cn31xx; 1812 struct cvmx_pip_int_reg_cn30xx cn38xx; 1813 struct cvmx_pip_int_reg_cn30xx cn38xxp2; 1814 struct cvmx_pip_int_reg_cn50xx 1815 { 1816#if __BYTE_ORDER == __BIG_ENDIAN 1817 uint64_t reserved_12_63 : 52; 1818 uint64_t lenerr : 1; /**< Frame was received with length error */ 1819 uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1820 uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1821 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1822 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1823 uint64_t todoovr : 1; /**< Todo list overflow */ 1824 uint64_t skprunt : 1; /**< Packet was engulfed by skipper 1825 This interrupt can occur with received PARTIAL 1826 packets that are truncated to SKIP bytes or 1827 smaller. */ 1828 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1829 uint64_t prtnxa : 1; /**< Non-existent port */ 1830 uint64_t bckprs : 1; /**< PIP asserted backpressure */ 1831 uint64_t reserved_1_1 : 1; 1832 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1833#else 1834 uint64_t pktdrp : 1; 1835 uint64_t reserved_1_1 : 1; 1836 uint64_t bckprs : 1; 1837 uint64_t prtnxa : 1; 1838 uint64_t badtag : 1; 1839 uint64_t skprunt : 1; 1840 uint64_t todoovr : 1; 1841 uint64_t feperr : 1; 1842 uint64_t beperr : 1; 1843 uint64_t minerr : 1; 1844 uint64_t maxerr : 1; 1845 uint64_t lenerr : 1; 1846 uint64_t reserved_12_63 : 52; 1847#endif 1848 } cn50xx; 1849 struct cvmx_pip_int_reg_cn52xx 1850 { 1851#if __BYTE_ORDER == __BIG_ENDIAN 1852 uint64_t reserved_13_63 : 51; 1853 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 1854 stripping in IPD is enable */ 1855 uint64_t lenerr : 1; /**< Frame was received with length error */ 1856 uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1857 uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1858 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1859 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1860 uint64_t todoovr : 1; /**< Todo list overflow */ 1861 uint64_t skprunt : 1; /**< Packet was engulfed by skipper 1862 This interrupt can occur with received PARTIAL 1863 packets that are truncated to SKIP bytes or 1864 smaller. */ 1865 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1866 uint64_t prtnxa : 1; /**< Non-existent port */ 1867 uint64_t bckprs : 1; /**< PIP asserted backpressure */ 1868 uint64_t reserved_1_1 : 1; 1869 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1870#else 1871 uint64_t pktdrp : 1; 1872 uint64_t reserved_1_1 : 1; 1873 uint64_t bckprs : 1; 1874 uint64_t prtnxa : 1; 1875 uint64_t badtag : 1; 1876 uint64_t skprunt : 1; 1877 uint64_t todoovr : 1; 1878 uint64_t feperr : 1; 1879 uint64_t beperr : 1; 1880 uint64_t minerr : 1; 1881 uint64_t maxerr : 1; 1882 uint64_t lenerr : 1; 1883 uint64_t punyerr : 1; 1884 uint64_t reserved_13_63 : 51; 1885#endif 1886 } cn52xx; 1887 struct cvmx_pip_int_reg_cn52xx cn52xxp1; 1888 struct cvmx_pip_int_reg_s cn56xx; 1889 struct cvmx_pip_int_reg_cn56xxp1 1890 { 1891#if __BYTE_ORDER == __BIG_ENDIAN 1892 uint64_t reserved_12_63 : 52; 1893 uint64_t lenerr : 1; /**< Frame was received with length error */ 1894 uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 1895 uint64_t minerr : 1; /**< Frame was received with length < min_length */ 1896 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1897 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1898 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 1899 uint64_t skprunt : 1; /**< Packet was engulfed by skipper 1900 This interrupt can occur with received PARTIAL 1901 packets that are truncated to SKIP bytes or 1902 smaller. */ 1903 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1904 uint64_t prtnxa : 1; /**< Non-existent port */ 1905 uint64_t bckprs : 1; /**< PIP asserted backpressure */ 1906 uint64_t crcerr : 1; /**< PIP calculated bad CRC 1907 (Disabled in 56xx) */ 1908 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1909#else 1910 uint64_t pktdrp : 1; 1911 uint64_t crcerr : 1; 1912 uint64_t bckprs : 1; 1913 uint64_t prtnxa : 1; 1914 uint64_t badtag : 1; 1915 uint64_t skprunt : 1; 1916 uint64_t todoovr : 1; 1917 uint64_t feperr : 1; 1918 uint64_t beperr : 1; 1919 uint64_t minerr : 1; 1920 uint64_t maxerr : 1; 1921 uint64_t lenerr : 1; 1922 uint64_t reserved_12_63 : 52; 1923#endif 1924 } cn56xxp1; 1925 struct cvmx_pip_int_reg_cn58xx 1926 { 1927#if __BYTE_ORDER == __BIG_ENDIAN 1928 uint64_t reserved_13_63 : 51; 1929 uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 1930 stripping in IPD is enable */ 1931 uint64_t reserved_9_11 : 3; 1932 uint64_t beperr : 1; /**< Parity Error in back end memory */ 1933 uint64_t feperr : 1; /**< Parity Error in front end memory */ 1934 uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 1935 uint64_t skprunt : 1; /**< Packet was engulfed by skipper 1936 This interrupt can occur with received PARTIAL 1937 packets that are truncated to SKIP bytes or 1938 smaller. */ 1939 uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 1940 uint64_t prtnxa : 1; /**< Non-existent port */ 1941 uint64_t bckprs : 1; /**< PIP asserted backpressure */ 1942 uint64_t crcerr : 1; /**< PIP calculated bad CRC */ 1943 uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 1944#else 1945 uint64_t pktdrp : 1; 1946 uint64_t crcerr : 1; 1947 uint64_t bckprs : 1; 1948 uint64_t prtnxa : 1; 1949 uint64_t badtag : 1; 1950 uint64_t skprunt : 1; 1951 uint64_t todoovr : 1; 1952 uint64_t feperr : 1; 1953 uint64_t beperr : 1; 1954 uint64_t reserved_9_11 : 3; 1955 uint64_t punyerr : 1; 1956 uint64_t reserved_13_63 : 51; 1957#endif 1958 } cn58xx; 1959 struct cvmx_pip_int_reg_cn30xx cn58xxp1; 1960 struct cvmx_pip_int_reg_s cn63xx; 1961 struct cvmx_pip_int_reg_s cn63xxp1; 1962}; 1963typedef union cvmx_pip_int_reg cvmx_pip_int_reg_t; 1964 1965/** 1966 * cvmx_pip_ip_offset 1967 * 1968 * PIP_IP_OFFSET = Location of the IP in the workQ entry 1969 * 1970 * An 8-byte offset to find the start of the IP header in the data portion of IP workQ entires 1971 * 1972 * Notes: 1973 * In normal configurations, OFFSET must be set in the 0..4 range to allow the 1974 * entire IP and TCP/UDP headers to be buffered in HW and calculate the L4 1975 * checksum for TCP/UDP packets. 1976 * 1977 * The MAX value of OFFSET is determined by the the types of packets that can 1978 * be sent to PIP as follows... 1979 * 1980 * Packet Type MAX OFFSET 1981 * IPv4/TCP/UDP 7 1982 * IPv6/TCP/UDP 5 1983 * IPv6/without L4 parsing 6 1984 * 1985 * If the L4 can be ignored, then the MAX OFFSET for IPv6 packets can increase 1986 * to 6. Here are the following programming restrictions for IPv6 packets and 1987 * OFFSET==6: 1988 * 1989 * . PIP_GBL_CTL[TCP_FLAG] == 0 1990 * . PIP_GBL_CTL[L4_LEN] == 0 1991 * . PIP_GBL_CTL[L4_CHK] == 0 1992 * . PIP_GBL_CTL[L4_PRT] == 0 1993 * . PIP_GBL_CTL[L4_MAL] == 0 1994 * . PIP_DEC_IPSEC[TCP] == 0 1995 * . PIP_DEC_IPSEC[UDP] == 0 1996 * . PIP_PRT_TAG[IP6_DPRT] == 0 1997 * . PIP_PRT_TAG[IP6_SPRT] == 0 1998 * . PIP_PRT_TAG[TCP6_TAG] == 0 1999 * . PIP_GBL_CFG[TAG_SYN] == 0 2000 */ 2001union cvmx_pip_ip_offset 2002{ 2003 uint64_t u64; 2004 struct cvmx_pip_ip_offset_s 2005 { 2006#if __BYTE_ORDER == __BIG_ENDIAN 2007 uint64_t reserved_3_63 : 61; 2008 uint64_t offset : 3; /**< Number of 8B ticks to include in workQ entry 2009 prior to IP data 2010 - 0: 0 Bytes / IP start at WORD4 of workQ entry 2011 - 1: 8 Bytes / IP start at WORD5 of workQ entry 2012 - 2: 16 Bytes / IP start at WORD6 of workQ entry 2013 - 3: 24 Bytes / IP start at WORD7 of workQ entry 2014 - 4: 32 Bytes / IP start at WORD8 of workQ entry 2015 - 5: 40 Bytes / IP start at WORD9 of workQ entry 2016 - 6: 48 Bytes / IP start at WORD10 of workQ entry 2017 - 7: 56 Bytes / IP start at WORD11 of workQ entry */ 2018#else 2019 uint64_t offset : 3; 2020 uint64_t reserved_3_63 : 61; 2021#endif 2022 } s; 2023 struct cvmx_pip_ip_offset_s cn30xx; 2024 struct cvmx_pip_ip_offset_s cn31xx; 2025 struct cvmx_pip_ip_offset_s cn38xx; 2026 struct cvmx_pip_ip_offset_s cn38xxp2; 2027 struct cvmx_pip_ip_offset_s cn50xx; 2028 struct cvmx_pip_ip_offset_s cn52xx; 2029 struct cvmx_pip_ip_offset_s cn52xxp1; 2030 struct cvmx_pip_ip_offset_s cn56xx; 2031 struct cvmx_pip_ip_offset_s cn56xxp1; 2032 struct cvmx_pip_ip_offset_s cn58xx; 2033 struct cvmx_pip_ip_offset_s cn58xxp1; 2034 struct cvmx_pip_ip_offset_s cn63xx; 2035 struct cvmx_pip_ip_offset_s cn63xxp1; 2036}; 2037typedef union cvmx_pip_ip_offset cvmx_pip_ip_offset_t; 2038 2039/** 2040 * cvmx_pip_prt_cfg# 2041 * 2042 * PIP_PRT_CFGX = Per port config information 2043 * 2044 */ 2045union cvmx_pip_prt_cfgx 2046{ 2047 uint64_t u64; 2048 struct cvmx_pip_prt_cfgx_s 2049 { 2050#if __BYTE_ORDER == __BIG_ENDIAN 2051 uint64_t reserved_53_63 : 11; 2052 uint64_t pad_len : 1; /**< When set, disables the length check for pkts with 2053 padding in the client data */ 2054 uint64_t vlan_len : 1; /**< When set, disables the length check for DSA/VLAN 2055 pkts */ 2056 uint64_t lenerr_en : 1; /**< L2 length error check enable 2057 Frame was received with length error 2058 Typically, this check will not be enabled for 2059 incoming packets on the PCIe ports. */ 2060 uint64_t maxerr_en : 1; /**< Max frame error check enable 2061 Frame was received with length > max_length */ 2062 uint64_t minerr_en : 1; /**< Min frame error check enable 2063 Frame was received with length < min_length 2064 Typically, this check will not be enabled for 2065 incoming packets on the PCIe ports. */ 2066 uint64_t grp_wat_47 : 4; /**< GRP Watcher enable 2067 (Watchers 4-7) */ 2068 uint64_t qos_wat_47 : 4; /**< QOS Watcher enable 2069 (Watchers 4-7) */ 2070 uint64_t reserved_37_39 : 3; 2071 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 2072 Normally, IPD will never drop a packet that PIP 2073 indicates is RAW. 2074 0=never drop RAW packets based on RED algorithm 2075 1=allow RAW packet drops based on RED algorithm */ 2076 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 2077 calculating mask tag hash */ 2078 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 2079 configuration. If DYN_RS is set then 2080 PKT_INST_HDR[RS] is not used. When using 2-byte 2081 instruction header words, either DYN_RS or 2082 PIP_GBL_CTL[IGNRS] should be set. */ 2083 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 2084 (not for PCI prts, 32-35) 2085 Must be zero in DSA mode */ 2086 uint64_t grp_wat : 4; /**< GRP Watcher enable */ 2087 uint64_t hg_qos : 1; /**< When set, uses the HiGig priority bits as a 2088 lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS) 2089 to determine the QOS value 2090 HG_QOS must not be set when HIGIG_EN=0 */ 2091 uint64_t qos : 3; /**< Default QOS level of the port */ 2092 uint64_t qos_wat : 4; /**< QOS Watcher enable 2093 (Watchers 0-3) */ 2094 uint64_t qos_vsel : 1; /**< Which QOS in PIP_QOS_VLAN to use 2095 0 = PIP_QOS_VLAN[QOS] 2096 1 = PIP_QOS_VLAN[QOS1] */ 2097 uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv 2098 if DSA/VLAN exists, it is used 2099 else if IP exists, Diffserv is used 2100 else the per port default is used 2101 Watchers are still highest priority */ 2102 uint64_t qos_diff : 1; /**< QOS Diffserv */ 2103 uint64_t qos_vlan : 1; /**< QOS VLAN */ 2104 uint64_t reserved_13_15 : 3; 2105 uint64_t crc_en : 1; /**< CRC Checking enabled */ 2106 uint64_t higig_en : 1; /**< Enable HiGig parsing 2107 Should not be set for PCIe ports (ports 32-35) 2108 Should not be set for ports in which PTP_MODE=1 2109 When HIGIG_EN=1: 2110 DSA_EN field below must be zero 2111 SKIP field below is both Skip I size and the 2112 size of the HiGig* header (12 or 16 bytes) */ 2113 uint64_t dsa_en : 1; /**< Enable DSA tag parsing 2114 When DSA_EN=1: 2115 HIGIG_EN field above must be zero 2116 SKIP field below is size of DSA tag (4, 8, or 2117 12 bytes) rather than the size of Skip I 2118 total SKIP (Skip I + header + Skip II 2119 must be zero 2120 INST_HDR field above must be zero (non-PCIe 2121 ports) 2122 For PCIe ports, NPEI_PKT*_INSTR_HDR[USE_IHDR] 2123 and PCIE_INST_HDR[R] should be clear 2124 MODE field below must be "skip to L2" */ 2125 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 2126 0 = no packet inspection (Uninterpreted) 2127 1 = L2 parsing / skip to L2 2128 2 = IP parsing / skip to L3 2129 3 = (illegal) 2130 Must be 2 ("skip to L2") when in DSA mode. */ 2131 uint64_t reserved_7_7 : 1; 2132 uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not 2133 apply to packets on PCI ports when a PKT_INST_HDR 2134 is present. See section 7.2.7 - Legal Skip 2135 Values for further details. 2136 In DSA mode, indicates the DSA header length, not 2137 Skip I size. (Must be 4,8,or 12) 2138 In HIGIG mode, indicates both the Skip I size and 2139 the HiGig header size (Must be 12 or 16). 2140 If PTP_MODE, the 8B timestamp is prepended to the 2141 packet. SKIP should be increased by 8 to 2142 compensate for the additional timestamp field. */ 2143#else 2144 uint64_t skip : 7; 2145 uint64_t reserved_7_7 : 1; 2146 cvmx_pip_port_parse_mode_t mode : 2; 2147 uint64_t dsa_en : 1; 2148 uint64_t higig_en : 1; 2149 uint64_t crc_en : 1; 2150 uint64_t reserved_13_15 : 3; 2151 uint64_t qos_vlan : 1; 2152 uint64_t qos_diff : 1; 2153 uint64_t qos_vod : 1; 2154 uint64_t qos_vsel : 1; 2155 uint64_t qos_wat : 4; 2156 uint64_t qos : 3; 2157 uint64_t hg_qos : 1; 2158 uint64_t grp_wat : 4; 2159 uint64_t inst_hdr : 1; 2160 uint64_t dyn_rs : 1; 2161 uint64_t tag_inc : 2; 2162 uint64_t rawdrp : 1; 2163 uint64_t reserved_37_39 : 3; 2164 uint64_t qos_wat_47 : 4; 2165 uint64_t grp_wat_47 : 4; 2166 uint64_t minerr_en : 1; 2167 uint64_t maxerr_en : 1; 2168 uint64_t lenerr_en : 1; 2169 uint64_t vlan_len : 1; 2170 uint64_t pad_len : 1; 2171 uint64_t reserved_53_63 : 11; 2172#endif 2173 } s; 2174 struct cvmx_pip_prt_cfgx_cn30xx 2175 { 2176#if __BYTE_ORDER == __BIG_ENDIAN 2177 uint64_t reserved_37_63 : 27; 2178 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 2179 Normally, IPD will never drop a packet that PIP 2180 indicates is RAW. 2181 0=never drop RAW packets based on RED algorithm 2182 1=allow RAW packet drops based on RED algorithm */ 2183 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 2184 calculating mask tag hash */ 2185 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 2186 configuration. If DYN_RS is set then 2187 PKT_INST_HDR[RS] is not used. When using 2-byte 2188 instruction header words, either DYN_RS or 2189 PIP_GBL_CTL[IGNRS] should be set. */ 2190 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 2191 (not for PCI prts, 32-35) */ 2192 uint64_t grp_wat : 4; /**< GRP Watcher enable */ 2193 uint64_t reserved_27_27 : 1; 2194 uint64_t qos : 3; /**< Default QOS level of the port */ 2195 uint64_t qos_wat : 4; /**< QOS Watcher enable */ 2196 uint64_t reserved_18_19 : 2; 2197 uint64_t qos_diff : 1; /**< QOS Diffserv */ 2198 uint64_t qos_vlan : 1; /**< QOS VLAN */ 2199 uint64_t reserved_10_15 : 6; 2200 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 2201 0 = no packet inspection (Uninterpreted) 2202 1 = L2 parsing / skip to L2 2203 2 = IP parsing / skip to L3 2204 3 = PCI Raw (illegal for software to set) */ 2205 uint64_t reserved_7_7 : 1; 2206 uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not 2207 apply to packets on PCI ports when a PKT_INST_HDR 2208 is present. See section 7.2.7 - Legal Skip 2209 Values for further details. */ 2210#else 2211 uint64_t skip : 7; 2212 uint64_t reserved_7_7 : 1; 2213 cvmx_pip_port_parse_mode_t mode : 2; 2214 uint64_t reserved_10_15 : 6; 2215 uint64_t qos_vlan : 1; 2216 uint64_t qos_diff : 1; 2217 uint64_t reserved_18_19 : 2; 2218 uint64_t qos_wat : 4; 2219 uint64_t qos : 3; 2220 uint64_t reserved_27_27 : 1; 2221 uint64_t grp_wat : 4; 2222 uint64_t inst_hdr : 1; 2223 uint64_t dyn_rs : 1; 2224 uint64_t tag_inc : 2; 2225 uint64_t rawdrp : 1; 2226 uint64_t reserved_37_63 : 27; 2227#endif 2228 } cn30xx; 2229 struct cvmx_pip_prt_cfgx_cn30xx cn31xx; 2230 struct cvmx_pip_prt_cfgx_cn38xx 2231 { 2232#if __BYTE_ORDER == __BIG_ENDIAN 2233 uint64_t reserved_37_63 : 27; 2234 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 2235 Normally, IPD will never drop a packet that PIP 2236 indicates is RAW. 2237 0=never drop RAW packets based on RED algorithm 2238 1=allow RAW packet drops based on RED algorithm */ 2239 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 2240 calculating mask tag hash */ 2241 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 2242 configuration. If DYN_RS is set then 2243 PKT_INST_HDR[RS] is not used. When using 2-byte 2244 instruction header words, either DYN_RS or 2245 PIP_GBL_CTL[IGNRS] should be set. */ 2246 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 2247 (not for PCI prts, 32-35) */ 2248 uint64_t grp_wat : 4; /**< GRP Watcher enable */ 2249 uint64_t reserved_27_27 : 1; 2250 uint64_t qos : 3; /**< Default QOS level of the port */ 2251 uint64_t qos_wat : 4; /**< QOS Watcher enable */ 2252 uint64_t reserved_18_19 : 2; 2253 uint64_t qos_diff : 1; /**< QOS Diffserv */ 2254 uint64_t qos_vlan : 1; /**< QOS VLAN */ 2255 uint64_t reserved_13_15 : 3; 2256 uint64_t crc_en : 1; /**< CRC Checking enabled (for ports 0-31 only) */ 2257 uint64_t reserved_10_11 : 2; 2258 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 2259 0 = no packet inspection (Uninterpreted) 2260 1 = L2 parsing / skip to L2 2261 2 = IP parsing / skip to L3 2262 3 = PCI Raw (illegal for software to set) */ 2263 uint64_t reserved_7_7 : 1; 2264 uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not 2265 apply to packets on PCI ports when a PKT_INST_HDR 2266 is present. See section 7.2.7 - Legal Skip 2267 Values for further details. */ 2268#else 2269 uint64_t skip : 7; 2270 uint64_t reserved_7_7 : 1; 2271 cvmx_pip_port_parse_mode_t mode : 2; 2272 uint64_t reserved_10_11 : 2; 2273 uint64_t crc_en : 1; 2274 uint64_t reserved_13_15 : 3; 2275 uint64_t qos_vlan : 1; 2276 uint64_t qos_diff : 1; 2277 uint64_t reserved_18_19 : 2; 2278 uint64_t qos_wat : 4; 2279 uint64_t qos : 3; 2280 uint64_t reserved_27_27 : 1; 2281 uint64_t grp_wat : 4; 2282 uint64_t inst_hdr : 1; 2283 uint64_t dyn_rs : 1; 2284 uint64_t tag_inc : 2; 2285 uint64_t rawdrp : 1; 2286 uint64_t reserved_37_63 : 27; 2287#endif 2288 } cn38xx; 2289 struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2; 2290 struct cvmx_pip_prt_cfgx_cn50xx 2291 { 2292#if __BYTE_ORDER == __BIG_ENDIAN 2293 uint64_t reserved_53_63 : 11; 2294 uint64_t pad_len : 1; /**< When set, disables the length check for pkts with 2295 padding in the client data */ 2296 uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */ 2297 uint64_t lenerr_en : 1; /**< L2 length error check enable 2298 Frame was received with length error */ 2299 uint64_t maxerr_en : 1; /**< Max frame error check enable 2300 Frame was received with length > max_length */ 2301 uint64_t minerr_en : 1; /**< Min frame error check enable 2302 Frame was received with length < min_length */ 2303 uint64_t grp_wat_47 : 4; /**< GRP Watcher enable 2304 (Watchers 4-7) */ 2305 uint64_t qos_wat_47 : 4; /**< QOS Watcher enable 2306 (Watchers 4-7) */ 2307 uint64_t reserved_37_39 : 3; 2308 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 2309 Normally, IPD will never drop a packet that PIP 2310 indicates is RAW. 2311 0=never drop RAW packets based on RED algorithm 2312 1=allow RAW packet drops based on RED algorithm */ 2313 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 2314 calculating mask tag hash */ 2315 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 2316 configuration. If DYN_RS is set then 2317 PKT_INST_HDR[RS] is not used. When using 2-byte 2318 instruction header words, either DYN_RS or 2319 PIP_GBL_CTL[IGNRS] should be set. */ 2320 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 2321 (not for PCI prts, 32-35) */ 2322 uint64_t grp_wat : 4; /**< GRP Watcher enable */ 2323 uint64_t reserved_27_27 : 1; 2324 uint64_t qos : 3; /**< Default QOS level of the port */ 2325 uint64_t qos_wat : 4; /**< QOS Watcher enable 2326 (Watchers 0-3) */ 2327 uint64_t reserved_19_19 : 1; 2328 uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv 2329 if VLAN exists, it is used 2330 else if IP exists, Diffserv is used 2331 else the per port default is used 2332 Watchers are still highest priority */ 2333 uint64_t qos_diff : 1; /**< QOS Diffserv */ 2334 uint64_t qos_vlan : 1; /**< QOS VLAN */ 2335 uint64_t reserved_13_15 : 3; 2336 uint64_t crc_en : 1; /**< CRC Checking enabled 2337 (Disabled in 5020) */ 2338 uint64_t reserved_10_11 : 2; 2339 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 2340 0 = no packet inspection (Uninterpreted) 2341 1 = L2 parsing / skip to L2 2342 2 = IP parsing / skip to L3 2343 3 = PCI Raw (illegal for software to set) */ 2344 uint64_t reserved_7_7 : 1; 2345 uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not 2346 apply to packets on PCI ports when a PKT_INST_HDR 2347 is present. See section 7.2.7 - Legal Skip 2348 Values for further details. */ 2349#else 2350 uint64_t skip : 7; 2351 uint64_t reserved_7_7 : 1; 2352 cvmx_pip_port_parse_mode_t mode : 2; 2353 uint64_t reserved_10_11 : 2; 2354 uint64_t crc_en : 1; 2355 uint64_t reserved_13_15 : 3; 2356 uint64_t qos_vlan : 1; 2357 uint64_t qos_diff : 1; 2358 uint64_t qos_vod : 1; 2359 uint64_t reserved_19_19 : 1; 2360 uint64_t qos_wat : 4; 2361 uint64_t qos : 3; 2362 uint64_t reserved_27_27 : 1; 2363 uint64_t grp_wat : 4; 2364 uint64_t inst_hdr : 1; 2365 uint64_t dyn_rs : 1; 2366 uint64_t tag_inc : 2; 2367 uint64_t rawdrp : 1; 2368 uint64_t reserved_37_39 : 3; 2369 uint64_t qos_wat_47 : 4; 2370 uint64_t grp_wat_47 : 4; 2371 uint64_t minerr_en : 1; 2372 uint64_t maxerr_en : 1; 2373 uint64_t lenerr_en : 1; 2374 uint64_t vlan_len : 1; 2375 uint64_t pad_len : 1; 2376 uint64_t reserved_53_63 : 11; 2377#endif 2378 } cn50xx; 2379 struct cvmx_pip_prt_cfgx_s cn52xx; 2380 struct cvmx_pip_prt_cfgx_s cn52xxp1; 2381 struct cvmx_pip_prt_cfgx_s cn56xx; 2382 struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1; 2383 struct cvmx_pip_prt_cfgx_cn58xx 2384 { 2385#if __BYTE_ORDER == __BIG_ENDIAN 2386 uint64_t reserved_37_63 : 27; 2387 uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 2388 Normally, IPD will never drop a packet that PIP 2389 indicates is RAW. 2390 0=never drop RAW packets based on RED algorithm 2391 1=allow RAW packet drops based on RED algorithm */ 2392 uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 2393 calculating mask tag hash */ 2394 uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 2395 configuration. If DYN_RS is set then 2396 PKT_INST_HDR[RS] is not used. When using 2-byte 2397 instruction header words, either DYN_RS or 2398 PIP_GBL_CTL[IGNRS] should be set. */ 2399 uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 2400 (not for PCI prts, 32-35) */ 2401 uint64_t grp_wat : 4; /**< GRP Watcher enable */ 2402 uint64_t reserved_27_27 : 1; 2403 uint64_t qos : 3; /**< Default QOS level of the port */ 2404 uint64_t qos_wat : 4; /**< QOS Watcher enable */ 2405 uint64_t reserved_19_19 : 1; 2406 uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv 2407 if VLAN exists, it is used 2408 else if IP exists, Diffserv is used 2409 else the per port default is used 2410 Watchers are still highest priority */ 2411 uint64_t qos_diff : 1; /**< QOS Diffserv */ 2412 uint64_t qos_vlan : 1; /**< QOS VLAN */ 2413 uint64_t reserved_13_15 : 3; 2414 uint64_t crc_en : 1; /**< CRC Checking enabled (for ports 0-31 only) */ 2415 uint64_t reserved_10_11 : 2; 2416 cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 2417 0 = no packet inspection (Uninterpreted) 2418 1 = L2 parsing / skip to L2 2419 2 = IP parsing / skip to L3 2420 3 = PCI Raw (illegal for software to set) */ 2421 uint64_t reserved_7_7 : 1; 2422 uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not 2423 apply to packets on PCI ports when a PKT_INST_HDR 2424 is present. See section 7.2.7 - Legal Skip 2425 Values for further details. */ 2426#else 2427 uint64_t skip : 7; 2428 uint64_t reserved_7_7 : 1; 2429 cvmx_pip_port_parse_mode_t mode : 2; 2430 uint64_t reserved_10_11 : 2; 2431 uint64_t crc_en : 1; 2432 uint64_t reserved_13_15 : 3; 2433 uint64_t qos_vlan : 1; 2434 uint64_t qos_diff : 1; 2435 uint64_t qos_vod : 1; 2436 uint64_t reserved_19_19 : 1; 2437 uint64_t qos_wat : 4; 2438 uint64_t qos : 3; 2439 uint64_t reserved_27_27 : 1; 2440 uint64_t grp_wat : 4; 2441 uint64_t inst_hdr : 1; 2442 uint64_t dyn_rs : 1; 2443 uint64_t tag_inc : 2; 2444 uint64_t rawdrp : 1; 2445 uint64_t reserved_37_63 : 27; 2446#endif 2447 } cn58xx; 2448 struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1; 2449 struct cvmx_pip_prt_cfgx_s cn63xx; 2450 struct cvmx_pip_prt_cfgx_s cn63xxp1; 2451}; 2452typedef union cvmx_pip_prt_cfgx cvmx_pip_prt_cfgx_t; 2453 2454/** 2455 * cvmx_pip_prt_tag# 2456 * 2457 * PIP_PRT_TAGX = Per port config information 2458 * 2459 */ 2460union cvmx_pip_prt_tagx 2461{ 2462 uint64_t u64; 2463 struct cvmx_pip_prt_tagx_s 2464 { 2465#if __BYTE_ORDER == __BIG_ENDIAN 2466 uint64_t reserved_40_63 : 24; 2467 uint64_t grptagbase : 4; /**< Offset to use when computing group from tag bits 2468 when GRPTAG is set. */ 2469 uint64_t grptagmask : 4; /**< Which bits of the tag to exclude when computing 2470 group when GRPTAG is set. */ 2471 uint64_t grptag : 1; /**< When set, use the lower bit of the tag to compute 2472 the group in the work queue entry 2473 GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */ 2474 uint64_t grptag_mskip : 1; /**< When set, GRPTAG will be used regardless if the 2475 packet IS_IP. */ 2476 uint64_t tag_mode : 2; /**< Which tag algorithm to use 2477 0 = always use tuple tag algorithm 2478 1 = always use mask tag algorithm 2479 2 = if packet is IP, use tuple else use mask 2480 3 = tuple XOR mask */ 2481 uint64_t inc_vs : 2; /**< determines the DSA/VLAN ID (VID) to be included in 2482 tuple tag when VLAN stacking is detected 2483 0 = do not include VID in tuple tag generation 2484 1 = include VID (VLAN0) in hash 2485 2 = include VID (VLAN1) in hash 2486 3 = include VID ([VLAN0,VLAN1]) in hash */ 2487 uint64_t inc_vlan : 1; /**< when set, the DSA/VLAN ID is included in tuple tag 2488 when VLAN stacking is not detected 2489 0 = do not include VID in tuple tag generation 2490 1 = include VID in hash */ 2491 uint64_t inc_prt_flag : 1; /**< sets whether the port is included in tuple tag */ 2492 uint64_t ip6_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is 2493 included in tuple tag for IPv6 packets */ 2494 uint64_t ip4_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is 2495 included in tuple tag for IPv4 */ 2496 uint64_t ip6_sprt_flag : 1; /**< sets whether the TCP/UDP src port is 2497 included in tuple tag for IPv6 packets */ 2498 uint64_t ip4_sprt_flag : 1; /**< sets whether the TCP/UDP src port is 2499 included in tuple tag for IPv4 */ 2500 uint64_t ip6_nxth_flag : 1; /**< sets whether ipv6 includes next header in tuple 2501 tag hash */ 2502 uint64_t ip4_pctl_flag : 1; /**< sets whether ipv4 includes protocol in tuple 2503 tag hash */ 2504 uint64_t ip6_dst_flag : 1; /**< sets whether ipv6 includes dst address in tuple 2505 tag hash */ 2506 uint64_t ip4_dst_flag : 1; /**< sets whether ipv4 includes dst address in tuple 2507 tag hash */ 2508 uint64_t ip6_src_flag : 1; /**< sets whether ipv6 includes src address in tuple 2509 tag hash */ 2510 uint64_t ip4_src_flag : 1; /**< sets whether ipv4 includes src address in tuple 2511 tag hash */ 2512 cvmx_pow_tag_type_t tcp6_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv6) 2513 0 = ordered tags 2514 1 = atomic tags 2515 2 = Null tags */ 2516 cvmx_pow_tag_type_t tcp4_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv4) 2517 0 = ordered tags 2518 1 = atomic tags 2519 2 = Null tags */ 2520 cvmx_pow_tag_type_t ip6_tag_type : 2; /**< sets whether IPv6 packet tag type 2521 0 = ordered tags 2522 1 = atomic tags 2523 2 = Null tags */ 2524 cvmx_pow_tag_type_t ip4_tag_type : 2; /**< sets whether IPv4 packet tag type 2525 0 = ordered tags 2526 1 = atomic tags 2527 2 = Null tags */ 2528 cvmx_pow_tag_type_t non_tag_type : 2; /**< sets whether non-IP packet tag type 2529 0 = ordered tags 2530 1 = atomic tags 2531 2 = Null tags */ 2532 uint64_t grp : 4; /**< 4-bit value indicating the group to schedule to */ 2533#else 2534 uint64_t grp : 4; 2535 cvmx_pow_tag_type_t non_tag_type : 2; 2536 cvmx_pow_tag_type_t ip4_tag_type : 2; 2537 cvmx_pow_tag_type_t ip6_tag_type : 2; 2538 cvmx_pow_tag_type_t tcp4_tag_type : 2; 2539 cvmx_pow_tag_type_t tcp6_tag_type : 2; 2540 uint64_t ip4_src_flag : 1; 2541 uint64_t ip6_src_flag : 1; 2542 uint64_t ip4_dst_flag : 1; 2543 uint64_t ip6_dst_flag : 1; 2544 uint64_t ip4_pctl_flag : 1; 2545 uint64_t ip6_nxth_flag : 1; 2546 uint64_t ip4_sprt_flag : 1; 2547 uint64_t ip6_sprt_flag : 1; 2548 uint64_t ip4_dprt_flag : 1; 2549 uint64_t ip6_dprt_flag : 1; 2550 uint64_t inc_prt_flag : 1; 2551 uint64_t inc_vlan : 1; 2552 uint64_t inc_vs : 2; 2553 uint64_t tag_mode : 2; 2554 uint64_t grptag_mskip : 1; 2555 uint64_t grptag : 1; 2556 uint64_t grptagmask : 4; 2557 uint64_t grptagbase : 4; 2558 uint64_t reserved_40_63 : 24; 2559#endif 2560 } s; 2561 struct cvmx_pip_prt_tagx_cn30xx 2562 { 2563#if __BYTE_ORDER == __BIG_ENDIAN 2564 uint64_t reserved_40_63 : 24; 2565 uint64_t grptagbase : 4; /**< Offset to use when computing group from tag bits 2566 when GRPTAG is set. */ 2567 uint64_t grptagmask : 4; /**< Which bits of the tag to exclude when computing 2568 group when GRPTAG is set. */ 2569 uint64_t grptag : 1; /**< When set, use the lower bit of the tag to compute 2570 the group in the work queue entry 2571 GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */ 2572 uint64_t reserved_30_30 : 1; 2573 uint64_t tag_mode : 2; /**< Which tag algorithm to use 2574 0 = always use tuple tag algorithm 2575 1 = always use mask tag algorithm 2576 2 = if packet is IP, use tuple else use mask 2577 3 = tuple XOR mask */ 2578 uint64_t inc_vs : 2; /**< determines the VLAN ID (VID) to be included in 2579 tuple tag when VLAN stacking is detected 2580 0 = do not include VID in tuple tag generation 2581 1 = include VID (VLAN0) in hash 2582 2 = include VID (VLAN1) in hash 2583 3 = include VID ([VLAN0,VLAN1]) in hash */ 2584 uint64_t inc_vlan : 1; /**< when set, the VLAN ID is included in tuple tag 2585 when VLAN stacking is not detected 2586 0 = do not include VID in tuple tag generation 2587 1 = include VID in hash */ 2588 uint64_t inc_prt_flag : 1; /**< sets whether the port is included in tuple tag */ 2589 uint64_t ip6_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is 2590 included in tuple tag for IPv6 packets */ 2591 uint64_t ip4_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is 2592 included in tuple tag for IPv4 */ 2593 uint64_t ip6_sprt_flag : 1; /**< sets whether the TCP/UDP src port is 2594 included in tuple tag for IPv6 packets */ 2595 uint64_t ip4_sprt_flag : 1; /**< sets whether the TCP/UDP src port is 2596 included in tuple tag for IPv4 */ 2597 uint64_t ip6_nxth_flag : 1; /**< sets whether ipv6 includes next header in tuple 2598 tag hash */ 2599 uint64_t ip4_pctl_flag : 1; /**< sets whether ipv4 includes protocol in tuple 2600 tag hash */ 2601 uint64_t ip6_dst_flag : 1; /**< sets whether ipv6 includes dst address in tuple 2602 tag hash */ 2603 uint64_t ip4_dst_flag : 1; /**< sets whether ipv4 includes dst address in tuple 2604 tag hash */ 2605 uint64_t ip6_src_flag : 1; /**< sets whether ipv6 includes src address in tuple 2606 tag hash */ 2607 uint64_t ip4_src_flag : 1; /**< sets whether ipv4 includes src address in tuple 2608 tag hash */ 2609 cvmx_pow_tag_type_t tcp6_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv6) 2610 0 = ordered tags 2611 1 = atomic tags 2612 2 = Null tags */ 2613 cvmx_pow_tag_type_t tcp4_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv4) 2614 0 = ordered tags 2615 1 = atomic tags 2616 2 = Null tags */ 2617 cvmx_pow_tag_type_t ip6_tag_type : 2; /**< sets whether IPv6 packet tag type 2618 0 = ordered tags 2619 1 = atomic tags 2620 2 = Null tags */ 2621 cvmx_pow_tag_type_t ip4_tag_type : 2; /**< sets whether IPv4 packet tag type 2622 0 = ordered tags 2623 1 = atomic tags 2624 2 = Null tags */ 2625 cvmx_pow_tag_type_t non_tag_type : 2; /**< sets whether non-IP packet tag type 2626 0 = ordered tags 2627 1 = atomic tags 2628 2 = Null tags */ 2629 uint64_t grp : 4; /**< 4-bit value indicating the group to schedule to */ 2630#else 2631 uint64_t grp : 4; 2632 cvmx_pow_tag_type_t non_tag_type : 2; 2633 cvmx_pow_tag_type_t ip4_tag_type : 2; 2634 cvmx_pow_tag_type_t ip6_tag_type : 2; 2635 cvmx_pow_tag_type_t tcp4_tag_type : 2; 2636 cvmx_pow_tag_type_t tcp6_tag_type : 2; 2637 uint64_t ip4_src_flag : 1; 2638 uint64_t ip6_src_flag : 1; 2639 uint64_t ip4_dst_flag : 1; 2640 uint64_t ip6_dst_flag : 1; 2641 uint64_t ip4_pctl_flag : 1; 2642 uint64_t ip6_nxth_flag : 1; 2643 uint64_t ip4_sprt_flag : 1; 2644 uint64_t ip6_sprt_flag : 1; 2645 uint64_t ip4_dprt_flag : 1; 2646 uint64_t ip6_dprt_flag : 1; 2647 uint64_t inc_prt_flag : 1; 2648 uint64_t inc_vlan : 1; 2649 uint64_t inc_vs : 2; 2650 uint64_t tag_mode : 2; 2651 uint64_t reserved_30_30 : 1; 2652 uint64_t grptag : 1; 2653 uint64_t grptagmask : 4; 2654 uint64_t grptagbase : 4; 2655 uint64_t reserved_40_63 : 24; 2656#endif 2657 } cn30xx; 2658 struct cvmx_pip_prt_tagx_cn30xx cn31xx; 2659 struct cvmx_pip_prt_tagx_cn30xx cn38xx; 2660 struct cvmx_pip_prt_tagx_cn30xx cn38xxp2; 2661 struct cvmx_pip_prt_tagx_s cn50xx; 2662 struct cvmx_pip_prt_tagx_s cn52xx; 2663 struct cvmx_pip_prt_tagx_s cn52xxp1; 2664 struct cvmx_pip_prt_tagx_s cn56xx; 2665 struct cvmx_pip_prt_tagx_s cn56xxp1; 2666 struct cvmx_pip_prt_tagx_cn30xx cn58xx; 2667 struct cvmx_pip_prt_tagx_cn30xx cn58xxp1; 2668 struct cvmx_pip_prt_tagx_s cn63xx; 2669 struct cvmx_pip_prt_tagx_s cn63xxp1; 2670}; 2671typedef union cvmx_pip_prt_tagx cvmx_pip_prt_tagx_t; 2672 2673/** 2674 * cvmx_pip_qos_diff# 2675 * 2676 * PIP_QOS_DIFFX = QOS Diffserv Tables 2677 * 2678 */ 2679union cvmx_pip_qos_diffx 2680{ 2681 uint64_t u64; 2682 struct cvmx_pip_qos_diffx_s 2683 { 2684#if __BYTE_ORDER == __BIG_ENDIAN 2685 uint64_t reserved_3_63 : 61; 2686 uint64_t qos : 3; /**< Diffserv QOS level */ 2687#else 2688 uint64_t qos : 3; 2689 uint64_t reserved_3_63 : 61; 2690#endif 2691 } s; 2692 struct cvmx_pip_qos_diffx_s cn30xx; 2693 struct cvmx_pip_qos_diffx_s cn31xx; 2694 struct cvmx_pip_qos_diffx_s cn38xx; 2695 struct cvmx_pip_qos_diffx_s cn38xxp2; 2696 struct cvmx_pip_qos_diffx_s cn50xx; 2697 struct cvmx_pip_qos_diffx_s cn52xx; 2698 struct cvmx_pip_qos_diffx_s cn52xxp1; 2699 struct cvmx_pip_qos_diffx_s cn56xx; 2700 struct cvmx_pip_qos_diffx_s cn56xxp1; 2701 struct cvmx_pip_qos_diffx_s cn58xx; 2702 struct cvmx_pip_qos_diffx_s cn58xxp1; 2703 struct cvmx_pip_qos_diffx_s cn63xx; 2704 struct cvmx_pip_qos_diffx_s cn63xxp1; 2705}; 2706typedef union cvmx_pip_qos_diffx cvmx_pip_qos_diffx_t; 2707 2708/** 2709 * cvmx_pip_qos_vlan# 2710 * 2711 * PIP_QOS_VLANX = QOS VLAN Tables 2712 * 2713 * If the PIP indentifies a packet is DSA/VLAN tagged, then the QOS 2714 * can be set based on the DSA/VLAN user priority. These eight register 2715 * comprise the QOS values for all DSA/VLAN user priority values. 2716 */ 2717union cvmx_pip_qos_vlanx 2718{ 2719 uint64_t u64; 2720 struct cvmx_pip_qos_vlanx_s 2721 { 2722#if __BYTE_ORDER == __BIG_ENDIAN 2723 uint64_t reserved_7_63 : 57; 2724 uint64_t qos1 : 3; /**< DSA/VLAN QOS level 2725 Selected when PIP_PRT_CFGx[QOS_VSEL] = 1 */ 2726 uint64_t reserved_3_3 : 1; 2727 uint64_t qos : 3; /**< DSA/VLAN QOS level 2728 Selected when PIP_PRT_CFGx[QOS_VSEL] = 0 */ 2729#else 2730 uint64_t qos : 3; 2731 uint64_t reserved_3_3 : 1; 2732 uint64_t qos1 : 3; 2733 uint64_t reserved_7_63 : 57; 2734#endif 2735 } s; 2736 struct cvmx_pip_qos_vlanx_cn30xx 2737 { 2738#if __BYTE_ORDER == __BIG_ENDIAN 2739 uint64_t reserved_3_63 : 61; 2740 uint64_t qos : 3; /**< VLAN QOS level */ 2741#else 2742 uint64_t qos : 3; 2743 uint64_t reserved_3_63 : 61; 2744#endif 2745 } cn30xx; 2746 struct cvmx_pip_qos_vlanx_cn30xx cn31xx; 2747 struct cvmx_pip_qos_vlanx_cn30xx cn38xx; 2748 struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2; 2749 struct cvmx_pip_qos_vlanx_cn30xx cn50xx; 2750 struct cvmx_pip_qos_vlanx_s cn52xx; 2751 struct cvmx_pip_qos_vlanx_s cn52xxp1; 2752 struct cvmx_pip_qos_vlanx_s cn56xx; 2753 struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1; 2754 struct cvmx_pip_qos_vlanx_cn30xx cn58xx; 2755 struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1; 2756 struct cvmx_pip_qos_vlanx_s cn63xx; 2757 struct cvmx_pip_qos_vlanx_s cn63xxp1; 2758}; 2759typedef union cvmx_pip_qos_vlanx cvmx_pip_qos_vlanx_t; 2760 2761/** 2762 * cvmx_pip_qos_watch# 2763 * 2764 * PIP_QOS_WATCHX = QOS Watcher Tables 2765 * 2766 * Sets up the Configuration CSRs for the four QOS Watchers. 2767 * Each Watcher can be set to look for a specific protocol, 2768 * TCP/UDP destination port, or Ethertype to override the 2769 * default QOS value. 2770 */ 2771union cvmx_pip_qos_watchx 2772{ 2773 uint64_t u64; 2774 struct cvmx_pip_qos_watchx_s 2775 { 2776#if __BYTE_ORDER == __BIG_ENDIAN 2777 uint64_t reserved_48_63 : 16; 2778 uint64_t mask : 16; /**< Mask off a range of values */ 2779 uint64_t reserved_28_31 : 4; 2780 uint64_t grp : 4; /**< The GRP number of the watcher */ 2781 uint64_t reserved_23_23 : 1; 2782 uint64_t qos : 3; /**< The QOS level of the watcher */ 2783 uint64_t reserved_19_19 : 1; 2784 cvmx_pip_qos_watch_types match_type : 3; /**< The field for the watcher match against 2785 0 = disable across all ports 2786 1 = protocol (ipv4) 2787 = next_header (ipv6) 2788 2 = TCP destination port 2789 3 = UDP destination port 2790 4 = Ether type 2791 5-7 = Reserved */ 2792 uint64_t match_value : 16; /**< The value to watch for */ 2793#else 2794 uint64_t match_value : 16; 2795 cvmx_pip_qos_watch_types match_type : 3; 2796 uint64_t reserved_19_19 : 1; 2797 uint64_t qos : 3; 2798 uint64_t reserved_23_23 : 1; 2799 uint64_t grp : 4; 2800 uint64_t reserved_28_31 : 4; 2801 uint64_t mask : 16; 2802 uint64_t reserved_48_63 : 16; 2803#endif 2804 } s; 2805 struct cvmx_pip_qos_watchx_cn30xx 2806 { 2807#if __BYTE_ORDER == __BIG_ENDIAN 2808 uint64_t reserved_48_63 : 16; 2809 uint64_t mask : 16; /**< Mask off a range of values */ 2810 uint64_t reserved_28_31 : 4; 2811 uint64_t grp : 4; /**< The GRP number of the watcher */ 2812 uint64_t reserved_23_23 : 1; 2813 uint64_t qos : 3; /**< The QOS level of the watcher */ 2814 uint64_t reserved_18_19 : 2; 2815 cvmx_pip_qos_watch_types match_type : 2; /**< The field for the watcher match against 2816 0 = disable across all ports 2817 1 = protocol (ipv4) 2818 = next_header (ipv6) 2819 2 = TCP destination port 2820 3 = UDP destination port */ 2821 uint64_t match_value : 16; /**< The value to watch for */ 2822#else 2823 uint64_t match_value : 16; 2824 cvmx_pip_qos_watch_types match_type : 2; 2825 uint64_t reserved_18_19 : 2; 2826 uint64_t qos : 3; 2827 uint64_t reserved_23_23 : 1; 2828 uint64_t grp : 4; 2829 uint64_t reserved_28_31 : 4; 2830 uint64_t mask : 16; 2831 uint64_t reserved_48_63 : 16; 2832#endif 2833 } cn30xx; 2834 struct cvmx_pip_qos_watchx_cn30xx cn31xx; 2835 struct cvmx_pip_qos_watchx_cn30xx cn38xx; 2836 struct cvmx_pip_qos_watchx_cn30xx cn38xxp2; 2837 struct cvmx_pip_qos_watchx_s cn50xx; 2838 struct cvmx_pip_qos_watchx_s cn52xx; 2839 struct cvmx_pip_qos_watchx_s cn52xxp1; 2840 struct cvmx_pip_qos_watchx_s cn56xx; 2841 struct cvmx_pip_qos_watchx_s cn56xxp1; 2842 struct cvmx_pip_qos_watchx_cn30xx cn58xx; 2843 struct cvmx_pip_qos_watchx_cn30xx cn58xxp1; 2844 struct cvmx_pip_qos_watchx_s cn63xx; 2845 struct cvmx_pip_qos_watchx_s cn63xxp1; 2846}; 2847typedef union cvmx_pip_qos_watchx cvmx_pip_qos_watchx_t; 2848 2849/** 2850 * cvmx_pip_raw_word 2851 * 2852 * PIP_RAW_WORD = The RAW Word2 of the workQ entry. 2853 * 2854 * The RAW Word2 to be inserted into the workQ entry of RAWFULL packets. 2855 */ 2856union cvmx_pip_raw_word 2857{ 2858 uint64_t u64; 2859 struct cvmx_pip_raw_word_s 2860 { 2861#if __BYTE_ORDER == __BIG_ENDIAN 2862 uint64_t reserved_56_63 : 8; 2863 uint64_t word : 56; /**< Word2 of the workQ entry 2864 The 8-bit bufs field is still set by HW (IPD) */ 2865#else 2866 uint64_t word : 56; 2867 uint64_t reserved_56_63 : 8; 2868#endif 2869 } s; 2870 struct cvmx_pip_raw_word_s cn30xx; 2871 struct cvmx_pip_raw_word_s cn31xx; 2872 struct cvmx_pip_raw_word_s cn38xx; 2873 struct cvmx_pip_raw_word_s cn38xxp2; 2874 struct cvmx_pip_raw_word_s cn50xx; 2875 struct cvmx_pip_raw_word_s cn52xx; 2876 struct cvmx_pip_raw_word_s cn52xxp1; 2877 struct cvmx_pip_raw_word_s cn56xx; 2878 struct cvmx_pip_raw_word_s cn56xxp1; 2879 struct cvmx_pip_raw_word_s cn58xx; 2880 struct cvmx_pip_raw_word_s cn58xxp1; 2881 struct cvmx_pip_raw_word_s cn63xx; 2882 struct cvmx_pip_raw_word_s cn63xxp1; 2883}; 2884typedef union cvmx_pip_raw_word cvmx_pip_raw_word_t; 2885 2886/** 2887 * cvmx_pip_sft_rst 2888 * 2889 * PIP_SFT_RST = PIP Soft Reset 2890 * 2891 * When written to a '1', resets the pip block 2892 * 2893 * Notes: 2894 * When RST is set to a '1' by SW, PIP will get a short reset pulse (3 cycles 2895 * in duration). Although this will reset much of PIP's internal state, some 2896 * CSRs will not reset. 2897 * 2898 * . PIP_BIST_STATUS 2899 * . PIP_STAT0_PRT* 2900 * . PIP_STAT1_PRT* 2901 * . PIP_STAT2_PRT* 2902 * . PIP_STAT3_PRT* 2903 * . PIP_STAT4_PRT* 2904 * . PIP_STAT5_PRT* 2905 * . PIP_STAT6_PRT* 2906 * . PIP_STAT7_PRT* 2907 * . PIP_STAT8_PRT* 2908 * . PIP_STAT9_PRT* 2909 * . PIP_XSTAT0_PRT* 2910 * . PIP_XSTAT1_PRT* 2911 * . PIP_XSTAT2_PRT* 2912 * . PIP_XSTAT3_PRT* 2913 * . PIP_XSTAT4_PRT* 2914 * . PIP_XSTAT5_PRT* 2915 * . PIP_XSTAT6_PRT* 2916 * . PIP_XSTAT7_PRT* 2917 * . PIP_XSTAT8_PRT* 2918 * . PIP_XSTAT9_PRT* 2919 * . PIP_STAT_INB_PKTS* 2920 * . PIP_STAT_INB_OCTS* 2921 * . PIP_STAT_INB_ERRS* 2922 * . PIP_TAG_INC* 2923 */ 2924union cvmx_pip_sft_rst 2925{ 2926 uint64_t u64; 2927 struct cvmx_pip_sft_rst_s 2928 { 2929#if __BYTE_ORDER == __BIG_ENDIAN 2930 uint64_t reserved_1_63 : 63; 2931 uint64_t rst : 1; /**< Soft Reset */ 2932#else 2933 uint64_t rst : 1; 2934 uint64_t reserved_1_63 : 63; 2935#endif 2936 } s; 2937 struct cvmx_pip_sft_rst_s cn30xx; 2938 struct cvmx_pip_sft_rst_s cn31xx; 2939 struct cvmx_pip_sft_rst_s cn38xx; 2940 struct cvmx_pip_sft_rst_s cn50xx; 2941 struct cvmx_pip_sft_rst_s cn52xx; 2942 struct cvmx_pip_sft_rst_s cn52xxp1; 2943 struct cvmx_pip_sft_rst_s cn56xx; 2944 struct cvmx_pip_sft_rst_s cn56xxp1; 2945 struct cvmx_pip_sft_rst_s cn58xx; 2946 struct cvmx_pip_sft_rst_s cn58xxp1; 2947 struct cvmx_pip_sft_rst_s cn63xx; 2948 struct cvmx_pip_sft_rst_s cn63xxp1; 2949}; 2950typedef union cvmx_pip_sft_rst cvmx_pip_sft_rst_t; 2951 2952/** 2953 * cvmx_pip_stat0_prt# 2954 * 2955 * PIP Statistics Counters 2956 * 2957 * Note: special stat counter behavior 2958 * 2959 * 1) Read and write operations must arbitrate for the statistics resources 2960 * along with the packet engines which are incrementing the counters. 2961 * In order to not drop packet information, the packet HW is always a 2962 * higher priority and the CSR requests will only be satisified when 2963 * there are idle cycles. This can potentially cause long delays if the 2964 * system becomes full. 2965 * 2966 * 2) stat counters can be cleared in two ways. If PIP_STAT_CTL[RDCLR] is 2967 * set, then all read accesses will clear the register. In addition, 2968 * any write to a stats register will also reset the register to zero. 2969 * Please note that the clearing operations must obey rule \#1 above. 2970 * 2971 * 3) all counters are wrapping - software must ensure they are read periodically 2972 * 2973 * 4) The counters accumulate statistics for packets that are sent to PKI. If 2974 * PTP_MODE is enabled, the 8B timestamp is prepended to the packet. This 2975 * additional 8B of data is captured in the octet counts. 2976 * PIP_STAT0_PRT = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS 2977 */ 2978union cvmx_pip_stat0_prtx 2979{ 2980 uint64_t u64; 2981 struct cvmx_pip_stat0_prtx_s 2982 { 2983#if __BYTE_ORDER == __BIG_ENDIAN 2984 uint64_t drp_pkts : 32; /**< Inbound packets marked to be dropped by the IPD 2985 QOS widget per port */ 2986 uint64_t drp_octs : 32; /**< Inbound octets marked to be dropped by the IPD 2987 QOS widget per port */ 2988#else 2989 uint64_t drp_octs : 32; 2990 uint64_t drp_pkts : 32; 2991#endif 2992 } s; 2993 struct cvmx_pip_stat0_prtx_s cn30xx; 2994 struct cvmx_pip_stat0_prtx_s cn31xx; 2995 struct cvmx_pip_stat0_prtx_s cn38xx; 2996 struct cvmx_pip_stat0_prtx_s cn38xxp2; 2997 struct cvmx_pip_stat0_prtx_s cn50xx; 2998 struct cvmx_pip_stat0_prtx_s cn52xx; 2999 struct cvmx_pip_stat0_prtx_s cn52xxp1; 3000 struct cvmx_pip_stat0_prtx_s cn56xx; 3001 struct cvmx_pip_stat0_prtx_s cn56xxp1; 3002 struct cvmx_pip_stat0_prtx_s cn58xx; 3003 struct cvmx_pip_stat0_prtx_s cn58xxp1; 3004 struct cvmx_pip_stat0_prtx_s cn63xx; 3005 struct cvmx_pip_stat0_prtx_s cn63xxp1; 3006}; 3007typedef union cvmx_pip_stat0_prtx cvmx_pip_stat0_prtx_t; 3008 3009/** 3010 * cvmx_pip_stat1_prt# 3011 * 3012 * PIP_STAT1_PRTX = PIP_STAT_OCTS 3013 * 3014 */ 3015union cvmx_pip_stat1_prtx 3016{ 3017 uint64_t u64; 3018 struct cvmx_pip_stat1_prtx_s 3019 { 3020#if __BYTE_ORDER == __BIG_ENDIAN 3021 uint64_t reserved_48_63 : 16; 3022 uint64_t octs : 48; /**< Number of octets received by PIP (good and bad) */ 3023#else 3024 uint64_t octs : 48; 3025 uint64_t reserved_48_63 : 16; 3026#endif 3027 } s; 3028 struct cvmx_pip_stat1_prtx_s cn30xx; 3029 struct cvmx_pip_stat1_prtx_s cn31xx; 3030 struct cvmx_pip_stat1_prtx_s cn38xx; 3031 struct cvmx_pip_stat1_prtx_s cn38xxp2; 3032 struct cvmx_pip_stat1_prtx_s cn50xx; 3033 struct cvmx_pip_stat1_prtx_s cn52xx; 3034 struct cvmx_pip_stat1_prtx_s cn52xxp1; 3035 struct cvmx_pip_stat1_prtx_s cn56xx; 3036 struct cvmx_pip_stat1_prtx_s cn56xxp1; 3037 struct cvmx_pip_stat1_prtx_s cn58xx; 3038 struct cvmx_pip_stat1_prtx_s cn58xxp1; 3039 struct cvmx_pip_stat1_prtx_s cn63xx; 3040 struct cvmx_pip_stat1_prtx_s cn63xxp1; 3041}; 3042typedef union cvmx_pip_stat1_prtx cvmx_pip_stat1_prtx_t; 3043 3044/** 3045 * cvmx_pip_stat2_prt# 3046 * 3047 * PIP_STAT2_PRTX = PIP_STAT_PKTS / PIP_STAT_RAW 3048 * 3049 */ 3050union cvmx_pip_stat2_prtx 3051{ 3052 uint64_t u64; 3053 struct cvmx_pip_stat2_prtx_s 3054 { 3055#if __BYTE_ORDER == __BIG_ENDIAN 3056 uint64_t pkts : 32; /**< Number of packets processed by PIP */ 3057 uint64_t raw : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error 3058 received by PIP per port */ 3059#else 3060 uint64_t raw : 32; 3061 uint64_t pkts : 32; 3062#endif 3063 } s; 3064 struct cvmx_pip_stat2_prtx_s cn30xx; 3065 struct cvmx_pip_stat2_prtx_s cn31xx; 3066 struct cvmx_pip_stat2_prtx_s cn38xx; 3067 struct cvmx_pip_stat2_prtx_s cn38xxp2; 3068 struct cvmx_pip_stat2_prtx_s cn50xx; 3069 struct cvmx_pip_stat2_prtx_s cn52xx; 3070 struct cvmx_pip_stat2_prtx_s cn52xxp1; 3071 struct cvmx_pip_stat2_prtx_s cn56xx; 3072 struct cvmx_pip_stat2_prtx_s cn56xxp1; 3073 struct cvmx_pip_stat2_prtx_s cn58xx; 3074 struct cvmx_pip_stat2_prtx_s cn58xxp1; 3075 struct cvmx_pip_stat2_prtx_s cn63xx; 3076 struct cvmx_pip_stat2_prtx_s cn63xxp1; 3077}; 3078typedef union cvmx_pip_stat2_prtx cvmx_pip_stat2_prtx_t; 3079 3080/** 3081 * cvmx_pip_stat3_prt# 3082 * 3083 * PIP_STAT3_PRTX = PIP_STAT_BCST / PIP_STAT_MCST 3084 * 3085 */ 3086union cvmx_pip_stat3_prtx 3087{ 3088 uint64_t u64; 3089 struct cvmx_pip_stat3_prtx_s 3090 { 3091#if __BYTE_ORDER == __BIG_ENDIAN 3092 uint64_t bcst : 32; /**< Number of indentified L2 broadcast packets 3093 Does not include multicast packets 3094 Only includes packets whose parse mode is 3095 SKIP_TO_L2. */ 3096 uint64_t mcst : 32; /**< Number of indentified L2 multicast packets 3097 Does not include broadcast packets 3098 Only includes packets whose parse mode is 3099 SKIP_TO_L2. */ 3100#else 3101 uint64_t mcst : 32; 3102 uint64_t bcst : 32; 3103#endif 3104 } s; 3105 struct cvmx_pip_stat3_prtx_s cn30xx; 3106 struct cvmx_pip_stat3_prtx_s cn31xx; 3107 struct cvmx_pip_stat3_prtx_s cn38xx; 3108 struct cvmx_pip_stat3_prtx_s cn38xxp2; 3109 struct cvmx_pip_stat3_prtx_s cn50xx; 3110 struct cvmx_pip_stat3_prtx_s cn52xx; 3111 struct cvmx_pip_stat3_prtx_s cn52xxp1; 3112 struct cvmx_pip_stat3_prtx_s cn56xx; 3113 struct cvmx_pip_stat3_prtx_s cn56xxp1; 3114 struct cvmx_pip_stat3_prtx_s cn58xx; 3115 struct cvmx_pip_stat3_prtx_s cn58xxp1; 3116 struct cvmx_pip_stat3_prtx_s cn63xx; 3117 struct cvmx_pip_stat3_prtx_s cn63xxp1; 3118}; 3119typedef union cvmx_pip_stat3_prtx cvmx_pip_stat3_prtx_t; 3120 3121/** 3122 * cvmx_pip_stat4_prt# 3123 * 3124 * PIP_STAT4_PRTX = PIP_STAT_HIST1 / PIP_STAT_HIST0 3125 * 3126 */ 3127union cvmx_pip_stat4_prtx 3128{ 3129 uint64_t u64; 3130 struct cvmx_pip_stat4_prtx_s 3131 { 3132#if __BYTE_ORDER == __BIG_ENDIAN 3133 uint64_t h65to127 : 32; /**< Number of 65-127B packets */ 3134 uint64_t h64 : 32; /**< Number of 1-64B packets */ 3135#else 3136 uint64_t h64 : 32; 3137 uint64_t h65to127 : 32; 3138#endif 3139 } s; 3140 struct cvmx_pip_stat4_prtx_s cn30xx; 3141 struct cvmx_pip_stat4_prtx_s cn31xx; 3142 struct cvmx_pip_stat4_prtx_s cn38xx; 3143 struct cvmx_pip_stat4_prtx_s cn38xxp2; 3144 struct cvmx_pip_stat4_prtx_s cn50xx; 3145 struct cvmx_pip_stat4_prtx_s cn52xx; 3146 struct cvmx_pip_stat4_prtx_s cn52xxp1; 3147 struct cvmx_pip_stat4_prtx_s cn56xx; 3148 struct cvmx_pip_stat4_prtx_s cn56xxp1; 3149 struct cvmx_pip_stat4_prtx_s cn58xx; 3150 struct cvmx_pip_stat4_prtx_s cn58xxp1; 3151 struct cvmx_pip_stat4_prtx_s cn63xx; 3152 struct cvmx_pip_stat4_prtx_s cn63xxp1; 3153}; 3154typedef union cvmx_pip_stat4_prtx cvmx_pip_stat4_prtx_t; 3155 3156/** 3157 * cvmx_pip_stat5_prt# 3158 * 3159 * PIP_STAT5_PRTX = PIP_STAT_HIST3 / PIP_STAT_HIST2 3160 * 3161 */ 3162union cvmx_pip_stat5_prtx 3163{ 3164 uint64_t u64; 3165 struct cvmx_pip_stat5_prtx_s 3166 { 3167#if __BYTE_ORDER == __BIG_ENDIAN 3168 uint64_t h256to511 : 32; /**< Number of 256-511B packets */ 3169 uint64_t h128to255 : 32; /**< Number of 128-255B packets */ 3170#else 3171 uint64_t h128to255 : 32; 3172 uint64_t h256to511 : 32; 3173#endif 3174 } s; 3175 struct cvmx_pip_stat5_prtx_s cn30xx; 3176 struct cvmx_pip_stat5_prtx_s cn31xx; 3177 struct cvmx_pip_stat5_prtx_s cn38xx; 3178 struct cvmx_pip_stat5_prtx_s cn38xxp2; 3179 struct cvmx_pip_stat5_prtx_s cn50xx; 3180 struct cvmx_pip_stat5_prtx_s cn52xx; 3181 struct cvmx_pip_stat5_prtx_s cn52xxp1; 3182 struct cvmx_pip_stat5_prtx_s cn56xx; 3183 struct cvmx_pip_stat5_prtx_s cn56xxp1; 3184 struct cvmx_pip_stat5_prtx_s cn58xx; 3185 struct cvmx_pip_stat5_prtx_s cn58xxp1; 3186 struct cvmx_pip_stat5_prtx_s cn63xx; 3187 struct cvmx_pip_stat5_prtx_s cn63xxp1; 3188}; 3189typedef union cvmx_pip_stat5_prtx cvmx_pip_stat5_prtx_t; 3190 3191/** 3192 * cvmx_pip_stat6_prt# 3193 * 3194 * PIP_STAT6_PRTX = PIP_STAT_HIST5 / PIP_STAT_HIST4 3195 * 3196 */ 3197union cvmx_pip_stat6_prtx 3198{ 3199 uint64_t u64; 3200 struct cvmx_pip_stat6_prtx_s 3201 { 3202#if __BYTE_ORDER == __BIG_ENDIAN 3203 uint64_t h1024to1518 : 32; /**< Number of 1024-1518B packets */ 3204 uint64_t h512to1023 : 32; /**< Number of 512-1023B packets */ 3205#else 3206 uint64_t h512to1023 : 32; 3207 uint64_t h1024to1518 : 32; 3208#endif 3209 } s; 3210 struct cvmx_pip_stat6_prtx_s cn30xx; 3211 struct cvmx_pip_stat6_prtx_s cn31xx; 3212 struct cvmx_pip_stat6_prtx_s cn38xx; 3213 struct cvmx_pip_stat6_prtx_s cn38xxp2; 3214 struct cvmx_pip_stat6_prtx_s cn50xx; 3215 struct cvmx_pip_stat6_prtx_s cn52xx; 3216 struct cvmx_pip_stat6_prtx_s cn52xxp1; 3217 struct cvmx_pip_stat6_prtx_s cn56xx; 3218 struct cvmx_pip_stat6_prtx_s cn56xxp1; 3219 struct cvmx_pip_stat6_prtx_s cn58xx; 3220 struct cvmx_pip_stat6_prtx_s cn58xxp1; 3221 struct cvmx_pip_stat6_prtx_s cn63xx; 3222 struct cvmx_pip_stat6_prtx_s cn63xxp1; 3223}; 3224typedef union cvmx_pip_stat6_prtx cvmx_pip_stat6_prtx_t; 3225 3226/** 3227 * cvmx_pip_stat7_prt# 3228 * 3229 * PIP_STAT7_PRTX = PIP_STAT_FCS / PIP_STAT_HIST6 3230 * 3231 * 3232 * Notes: 3233 * Note: FCS is not checked on the PCI ports 32..35. 3234 * 3235 */ 3236union cvmx_pip_stat7_prtx 3237{ 3238 uint64_t u64; 3239 struct cvmx_pip_stat7_prtx_s 3240 { 3241#if __BYTE_ORDER == __BIG_ENDIAN 3242 uint64_t fcs : 32; /**< Number of packets with FCS or Align opcode errors */ 3243 uint64_t h1519 : 32; /**< Number of 1519-max packets */ 3244#else 3245 uint64_t h1519 : 32; 3246 uint64_t fcs : 32; 3247#endif 3248 } s; 3249 struct cvmx_pip_stat7_prtx_s cn30xx; 3250 struct cvmx_pip_stat7_prtx_s cn31xx; 3251 struct cvmx_pip_stat7_prtx_s cn38xx; 3252 struct cvmx_pip_stat7_prtx_s cn38xxp2; 3253 struct cvmx_pip_stat7_prtx_s cn50xx; 3254 struct cvmx_pip_stat7_prtx_s cn52xx; 3255 struct cvmx_pip_stat7_prtx_s cn52xxp1; 3256 struct cvmx_pip_stat7_prtx_s cn56xx; 3257 struct cvmx_pip_stat7_prtx_s cn56xxp1; 3258 struct cvmx_pip_stat7_prtx_s cn58xx; 3259 struct cvmx_pip_stat7_prtx_s cn58xxp1; 3260 struct cvmx_pip_stat7_prtx_s cn63xx; 3261 struct cvmx_pip_stat7_prtx_s cn63xxp1; 3262}; 3263typedef union cvmx_pip_stat7_prtx cvmx_pip_stat7_prtx_t; 3264 3265/** 3266 * cvmx_pip_stat8_prt# 3267 * 3268 * PIP_STAT8_PRTX = PIP_STAT_FRAG / PIP_STAT_UNDER 3269 * 3270 * 3271 * Notes: 3272 * Note: FCS is not checked on the PCI ports 32..35. 3273 * 3274 */ 3275union cvmx_pip_stat8_prtx 3276{ 3277 uint64_t u64; 3278 struct cvmx_pip_stat8_prtx_s 3279 { 3280#if __BYTE_ORDER == __BIG_ENDIAN 3281 uint64_t frag : 32; /**< Number of packets with length < min and FCS error */ 3282 uint64_t undersz : 32; /**< Number of packets with length < min */ 3283#else 3284 uint64_t undersz : 32; 3285 uint64_t frag : 32; 3286#endif 3287 } s; 3288 struct cvmx_pip_stat8_prtx_s cn30xx; 3289 struct cvmx_pip_stat8_prtx_s cn31xx; 3290 struct cvmx_pip_stat8_prtx_s cn38xx; 3291 struct cvmx_pip_stat8_prtx_s cn38xxp2; 3292 struct cvmx_pip_stat8_prtx_s cn50xx; 3293 struct cvmx_pip_stat8_prtx_s cn52xx; 3294 struct cvmx_pip_stat8_prtx_s cn52xxp1; 3295 struct cvmx_pip_stat8_prtx_s cn56xx; 3296 struct cvmx_pip_stat8_prtx_s cn56xxp1; 3297 struct cvmx_pip_stat8_prtx_s cn58xx; 3298 struct cvmx_pip_stat8_prtx_s cn58xxp1; 3299 struct cvmx_pip_stat8_prtx_s cn63xx; 3300 struct cvmx_pip_stat8_prtx_s cn63xxp1; 3301}; 3302typedef union cvmx_pip_stat8_prtx cvmx_pip_stat8_prtx_t; 3303 3304/** 3305 * cvmx_pip_stat9_prt# 3306 * 3307 * PIP_STAT9_PRTX = PIP_STAT_JABBER / PIP_STAT_OVER 3308 * 3309 * 3310 * Notes: 3311 * Note: FCS is not checked on the PCI ports 32..35. 3312 * 3313 */ 3314union cvmx_pip_stat9_prtx 3315{ 3316 uint64_t u64; 3317 struct cvmx_pip_stat9_prtx_s 3318 { 3319#if __BYTE_ORDER == __BIG_ENDIAN 3320 uint64_t jabber : 32; /**< Number of packets with length > max and FCS error */ 3321 uint64_t oversz : 32; /**< Number of packets with length > max */ 3322#else 3323 uint64_t oversz : 32; 3324 uint64_t jabber : 32; 3325#endif 3326 } s; 3327 struct cvmx_pip_stat9_prtx_s cn30xx; 3328 struct cvmx_pip_stat9_prtx_s cn31xx; 3329 struct cvmx_pip_stat9_prtx_s cn38xx; 3330 struct cvmx_pip_stat9_prtx_s cn38xxp2; 3331 struct cvmx_pip_stat9_prtx_s cn50xx; 3332 struct cvmx_pip_stat9_prtx_s cn52xx; 3333 struct cvmx_pip_stat9_prtx_s cn52xxp1; 3334 struct cvmx_pip_stat9_prtx_s cn56xx; 3335 struct cvmx_pip_stat9_prtx_s cn56xxp1; 3336 struct cvmx_pip_stat9_prtx_s cn58xx; 3337 struct cvmx_pip_stat9_prtx_s cn58xxp1; 3338 struct cvmx_pip_stat9_prtx_s cn63xx; 3339 struct cvmx_pip_stat9_prtx_s cn63xxp1; 3340}; 3341typedef union cvmx_pip_stat9_prtx cvmx_pip_stat9_prtx_t; 3342 3343/** 3344 * cvmx_pip_stat_ctl 3345 * 3346 * PIP_STAT_CTL = PIP's Stat Control Register 3347 * 3348 * Controls how the PIP statistics counters are handled. 3349 */ 3350union cvmx_pip_stat_ctl 3351{ 3352 uint64_t u64; 3353 struct cvmx_pip_stat_ctl_s 3354 { 3355#if __BYTE_ORDER == __BIG_ENDIAN 3356 uint64_t reserved_1_63 : 63; 3357 uint64_t rdclr : 1; /**< Stat registers are read and clear 3358 0 = stat registers hold value when read 3359 1 = stat registers are cleared when read */ 3360#else 3361 uint64_t rdclr : 1; 3362 uint64_t reserved_1_63 : 63; 3363#endif 3364 } s; 3365 struct cvmx_pip_stat_ctl_s cn30xx; 3366 struct cvmx_pip_stat_ctl_s cn31xx; 3367 struct cvmx_pip_stat_ctl_s cn38xx; 3368 struct cvmx_pip_stat_ctl_s cn38xxp2; 3369 struct cvmx_pip_stat_ctl_s cn50xx; 3370 struct cvmx_pip_stat_ctl_s cn52xx; 3371 struct cvmx_pip_stat_ctl_s cn52xxp1; 3372 struct cvmx_pip_stat_ctl_s cn56xx; 3373 struct cvmx_pip_stat_ctl_s cn56xxp1; 3374 struct cvmx_pip_stat_ctl_s cn58xx; 3375 struct cvmx_pip_stat_ctl_s cn58xxp1; 3376 struct cvmx_pip_stat_ctl_s cn63xx; 3377 struct cvmx_pip_stat_ctl_s cn63xxp1; 3378}; 3379typedef union cvmx_pip_stat_ctl cvmx_pip_stat_ctl_t; 3380 3381/** 3382 * cvmx_pip_stat_inb_errs# 3383 * 3384 * PIP_STAT_INB_ERRSX = Inbound error packets received by PIP per port 3385 * 3386 * Inbound stats collect all data sent to PIP from all packet interfaces. 3387 * Its the raw counts of everything that comes into the block. The counts 3388 * will reflect all error packets and packets dropped by the PKI RED engine. 3389 * These counts are intended for system debug, but could convey useful 3390 * information in production systems. 3391 */ 3392union cvmx_pip_stat_inb_errsx 3393{ 3394 uint64_t u64; 3395 struct cvmx_pip_stat_inb_errsx_s 3396 { 3397#if __BYTE_ORDER == __BIG_ENDIAN 3398 uint64_t reserved_16_63 : 48; 3399 uint64_t errs : 16; /**< Number of packets with errors 3400 received by PIP */ 3401#else 3402 uint64_t errs : 16; 3403 uint64_t reserved_16_63 : 48; 3404#endif 3405 } s; 3406 struct cvmx_pip_stat_inb_errsx_s cn30xx; 3407 struct cvmx_pip_stat_inb_errsx_s cn31xx; 3408 struct cvmx_pip_stat_inb_errsx_s cn38xx; 3409 struct cvmx_pip_stat_inb_errsx_s cn38xxp2; 3410 struct cvmx_pip_stat_inb_errsx_s cn50xx; 3411 struct cvmx_pip_stat_inb_errsx_s cn52xx; 3412 struct cvmx_pip_stat_inb_errsx_s cn52xxp1; 3413 struct cvmx_pip_stat_inb_errsx_s cn56xx; 3414 struct cvmx_pip_stat_inb_errsx_s cn56xxp1; 3415 struct cvmx_pip_stat_inb_errsx_s cn58xx; 3416 struct cvmx_pip_stat_inb_errsx_s cn58xxp1; 3417 struct cvmx_pip_stat_inb_errsx_s cn63xx; 3418 struct cvmx_pip_stat_inb_errsx_s cn63xxp1; 3419}; 3420typedef union cvmx_pip_stat_inb_errsx cvmx_pip_stat_inb_errsx_t; 3421 3422/** 3423 * cvmx_pip_stat_inb_octs# 3424 * 3425 * PIP_STAT_INB_OCTSX = Inbound octets received by PIP per port 3426 * 3427 * Inbound stats collect all data sent to PIP from all packet interfaces. 3428 * Its the raw counts of everything that comes into the block. The counts 3429 * will reflect all error packets and packets dropped by the PKI RED engine. 3430 * These counts are intended for system debug, but could convey useful 3431 * information in production systems. The OCTS will include the bytes from 3432 * timestamp fields in PTP_MODE. 3433 */ 3434union cvmx_pip_stat_inb_octsx 3435{ 3436 uint64_t u64; 3437 struct cvmx_pip_stat_inb_octsx_s 3438 { 3439#if __BYTE_ORDER == __BIG_ENDIAN 3440 uint64_t reserved_48_63 : 16; 3441 uint64_t octs : 48; /**< Total number of octets from all packets received 3442 by PIP */ 3443#else 3444 uint64_t octs : 48; 3445 uint64_t reserved_48_63 : 16; 3446#endif 3447 } s; 3448 struct cvmx_pip_stat_inb_octsx_s cn30xx; 3449 struct cvmx_pip_stat_inb_octsx_s cn31xx; 3450 struct cvmx_pip_stat_inb_octsx_s cn38xx; 3451 struct cvmx_pip_stat_inb_octsx_s cn38xxp2; 3452 struct cvmx_pip_stat_inb_octsx_s cn50xx; 3453 struct cvmx_pip_stat_inb_octsx_s cn52xx; 3454 struct cvmx_pip_stat_inb_octsx_s cn52xxp1; 3455 struct cvmx_pip_stat_inb_octsx_s cn56xx; 3456 struct cvmx_pip_stat_inb_octsx_s cn56xxp1; 3457 struct cvmx_pip_stat_inb_octsx_s cn58xx; 3458 struct cvmx_pip_stat_inb_octsx_s cn58xxp1; 3459 struct cvmx_pip_stat_inb_octsx_s cn63xx; 3460 struct cvmx_pip_stat_inb_octsx_s cn63xxp1; 3461}; 3462typedef union cvmx_pip_stat_inb_octsx cvmx_pip_stat_inb_octsx_t; 3463 3464/** 3465 * cvmx_pip_stat_inb_pkts# 3466 * 3467 * PIP_STAT_INB_PKTSX = Inbound packets received by PIP per port 3468 * 3469 * Inbound stats collect all data sent to PIP from all packet interfaces. 3470 * Its the raw counts of everything that comes into the block. The counts 3471 * will reflect all error packets and packets dropped by the PKI RED engine. 3472 * These counts are intended for system debug, but could convey useful 3473 * information in production systems. 3474 */ 3475union cvmx_pip_stat_inb_pktsx 3476{ 3477 uint64_t u64; 3478 struct cvmx_pip_stat_inb_pktsx_s 3479 { 3480#if __BYTE_ORDER == __BIG_ENDIAN 3481 uint64_t reserved_32_63 : 32; 3482 uint64_t pkts : 32; /**< Number of packets without errors 3483 received by PIP */ 3484#else 3485 uint64_t pkts : 32; 3486 uint64_t reserved_32_63 : 32; 3487#endif 3488 } s; 3489 struct cvmx_pip_stat_inb_pktsx_s cn30xx; 3490 struct cvmx_pip_stat_inb_pktsx_s cn31xx; 3491 struct cvmx_pip_stat_inb_pktsx_s cn38xx; 3492 struct cvmx_pip_stat_inb_pktsx_s cn38xxp2; 3493 struct cvmx_pip_stat_inb_pktsx_s cn50xx; 3494 struct cvmx_pip_stat_inb_pktsx_s cn52xx; 3495 struct cvmx_pip_stat_inb_pktsx_s cn52xxp1; 3496 struct cvmx_pip_stat_inb_pktsx_s cn56xx; 3497 struct cvmx_pip_stat_inb_pktsx_s cn56xxp1; 3498 struct cvmx_pip_stat_inb_pktsx_s cn58xx; 3499 struct cvmx_pip_stat_inb_pktsx_s cn58xxp1; 3500 struct cvmx_pip_stat_inb_pktsx_s cn63xx; 3501 struct cvmx_pip_stat_inb_pktsx_s cn63xxp1; 3502}; 3503typedef union cvmx_pip_stat_inb_pktsx cvmx_pip_stat_inb_pktsx_t; 3504 3505/** 3506 * cvmx_pip_tag_inc# 3507 * 3508 * PIP_TAG_INC = Which bytes to include in the new tag hash algorithm 3509 * 3510 * # $PIP_TAG_INCX = 0x300+X X=(0..63) RegType=(RSL) RtlReg=(pip_tag_inc_csr_direct_TestbuilderTask) 3511 */ 3512union cvmx_pip_tag_incx 3513{ 3514 uint64_t u64; 3515 struct cvmx_pip_tag_incx_s 3516 { 3517#if __BYTE_ORDER == __BIG_ENDIAN 3518 uint64_t reserved_8_63 : 56; 3519 uint64_t en : 8; /**< Which bytes to include in mask tag algorithm 3520 Broken into 4, 16-entry masks to cover 128B 3521 PIP_PRT_CFG[TAG_INC] selects 1 of 4 to use 3522 registers 0-15 map to PIP_PRT_CFG[TAG_INC] == 0 3523 registers 16-31 map to PIP_PRT_CFG[TAG_INC] == 1 3524 registers 32-47 map to PIP_PRT_CFG[TAG_INC] == 2 3525 registers 48-63 map to PIP_PRT_CFG[TAG_INC] == 3 3526 [7] coresponds to the MSB of the 8B word 3527 [0] coresponds to the LSB of the 8B word 3528 If PTP_MODE, the 8B timestamp is prepended to the 3529 packet. The EN byte masks should be adjusted to 3530 compensate for the additional timestamp field. */ 3531#else 3532 uint64_t en : 8; 3533 uint64_t reserved_8_63 : 56; 3534#endif 3535 } s; 3536 struct cvmx_pip_tag_incx_s cn30xx; 3537 struct cvmx_pip_tag_incx_s cn31xx; 3538 struct cvmx_pip_tag_incx_s cn38xx; 3539 struct cvmx_pip_tag_incx_s cn38xxp2; 3540 struct cvmx_pip_tag_incx_s cn50xx; 3541 struct cvmx_pip_tag_incx_s cn52xx; 3542 struct cvmx_pip_tag_incx_s cn52xxp1; 3543 struct cvmx_pip_tag_incx_s cn56xx; 3544 struct cvmx_pip_tag_incx_s cn56xxp1; 3545 struct cvmx_pip_tag_incx_s cn58xx; 3546 struct cvmx_pip_tag_incx_s cn58xxp1; 3547 struct cvmx_pip_tag_incx_s cn63xx; 3548 struct cvmx_pip_tag_incx_s cn63xxp1; 3549}; 3550typedef union cvmx_pip_tag_incx cvmx_pip_tag_incx_t; 3551 3552/** 3553 * cvmx_pip_tag_mask 3554 * 3555 * PIP_TAG_MASK = Mask bit in the tag generation 3556 * 3557 */ 3558union cvmx_pip_tag_mask 3559{ 3560 uint64_t u64; 3561 struct cvmx_pip_tag_mask_s 3562 { 3563#if __BYTE_ORDER == __BIG_ENDIAN 3564 uint64_t reserved_16_63 : 48; 3565 uint64_t mask : 16; /**< When set, MASK clears individual bits of lower 16 3566 bits of the computed tag. Does not effect RAW 3567 or INSTR HDR packets. */ 3568#else 3569 uint64_t mask : 16; 3570 uint64_t reserved_16_63 : 48; 3571#endif 3572 } s; 3573 struct cvmx_pip_tag_mask_s cn30xx; 3574 struct cvmx_pip_tag_mask_s cn31xx; 3575 struct cvmx_pip_tag_mask_s cn38xx; 3576 struct cvmx_pip_tag_mask_s cn38xxp2; 3577 struct cvmx_pip_tag_mask_s cn50xx; 3578 struct cvmx_pip_tag_mask_s cn52xx; 3579 struct cvmx_pip_tag_mask_s cn52xxp1; 3580 struct cvmx_pip_tag_mask_s cn56xx; 3581 struct cvmx_pip_tag_mask_s cn56xxp1; 3582 struct cvmx_pip_tag_mask_s cn58xx; 3583 struct cvmx_pip_tag_mask_s cn58xxp1; 3584 struct cvmx_pip_tag_mask_s cn63xx; 3585 struct cvmx_pip_tag_mask_s cn63xxp1; 3586}; 3587typedef union cvmx_pip_tag_mask cvmx_pip_tag_mask_t; 3588 3589/** 3590 * cvmx_pip_tag_secret 3591 * 3592 * PIP_TAG_SECRET = Initial value in tag generation 3593 * 3594 * The source and destination IV's provide a mechanism for each Octeon to be unique. 3595 */ 3596union cvmx_pip_tag_secret 3597{ 3598 uint64_t u64; 3599 struct cvmx_pip_tag_secret_s 3600 { 3601#if __BYTE_ORDER == __BIG_ENDIAN 3602 uint64_t reserved_32_63 : 32; 3603 uint64_t dst : 16; /**< Secret for the destination tuple tag CRC calc */ 3604 uint64_t src : 16; /**< Secret for the source tuple tag CRC calc */ 3605#else 3606 uint64_t src : 16; 3607 uint64_t dst : 16; 3608 uint64_t reserved_32_63 : 32; 3609#endif 3610 } s; 3611 struct cvmx_pip_tag_secret_s cn30xx; 3612 struct cvmx_pip_tag_secret_s cn31xx; 3613 struct cvmx_pip_tag_secret_s cn38xx; 3614 struct cvmx_pip_tag_secret_s cn38xxp2; 3615 struct cvmx_pip_tag_secret_s cn50xx; 3616 struct cvmx_pip_tag_secret_s cn52xx; 3617 struct cvmx_pip_tag_secret_s cn52xxp1; 3618 struct cvmx_pip_tag_secret_s cn56xx; 3619 struct cvmx_pip_tag_secret_s cn56xxp1; 3620 struct cvmx_pip_tag_secret_s cn58xx; 3621 struct cvmx_pip_tag_secret_s cn58xxp1; 3622 struct cvmx_pip_tag_secret_s cn63xx; 3623 struct cvmx_pip_tag_secret_s cn63xxp1; 3624}; 3625typedef union cvmx_pip_tag_secret cvmx_pip_tag_secret_t; 3626 3627/** 3628 * cvmx_pip_todo_entry 3629 * 3630 * PIP_TODO_ENTRY = Head entry of the Todo list (debug only) 3631 * 3632 * Summary of the current packet that has completed and waiting to be processed 3633 */ 3634union cvmx_pip_todo_entry 3635{ 3636 uint64_t u64; 3637 struct cvmx_pip_todo_entry_s 3638 { 3639#if __BYTE_ORDER == __BIG_ENDIAN 3640 uint64_t val : 1; /**< Entry is valid */ 3641 uint64_t reserved_62_62 : 1; 3642 uint64_t entry : 62; /**< Todo list entry summary */ 3643#else 3644 uint64_t entry : 62; 3645 uint64_t reserved_62_62 : 1; 3646 uint64_t val : 1; 3647#endif 3648 } s; 3649 struct cvmx_pip_todo_entry_s cn30xx; 3650 struct cvmx_pip_todo_entry_s cn31xx; 3651 struct cvmx_pip_todo_entry_s cn38xx; 3652 struct cvmx_pip_todo_entry_s cn38xxp2; 3653 struct cvmx_pip_todo_entry_s cn50xx; 3654 struct cvmx_pip_todo_entry_s cn52xx; 3655 struct cvmx_pip_todo_entry_s cn52xxp1; 3656 struct cvmx_pip_todo_entry_s cn56xx; 3657 struct cvmx_pip_todo_entry_s cn56xxp1; 3658 struct cvmx_pip_todo_entry_s cn58xx; 3659 struct cvmx_pip_todo_entry_s cn58xxp1; 3660 struct cvmx_pip_todo_entry_s cn63xx; 3661 struct cvmx_pip_todo_entry_s cn63xxp1; 3662}; 3663typedef union cvmx_pip_todo_entry cvmx_pip_todo_entry_t; 3664 3665/** 3666 * cvmx_pip_xstat0_prt# 3667 * 3668 * PIP_XSTAT0_PRT = PIP_XSTAT_DRP_PKTS / PIP_XSTAT_DRP_OCTS 3669 * 3670 */ 3671union cvmx_pip_xstat0_prtx 3672{ 3673 uint64_t u64; 3674 struct cvmx_pip_xstat0_prtx_s 3675 { 3676#if __BYTE_ORDER == __BIG_ENDIAN 3677 uint64_t drp_pkts : 32; /**< Inbound packets marked to be dropped by the IPD 3678 QOS widget per port */ 3679 uint64_t drp_octs : 32; /**< Inbound octets marked to be dropped by the IPD 3680 QOS widget per port */ 3681#else 3682 uint64_t drp_octs : 32; 3683 uint64_t drp_pkts : 32; 3684#endif 3685 } s; 3686 struct cvmx_pip_xstat0_prtx_s cn63xx; 3687 struct cvmx_pip_xstat0_prtx_s cn63xxp1; 3688}; 3689typedef union cvmx_pip_xstat0_prtx cvmx_pip_xstat0_prtx_t; 3690 3691/** 3692 * cvmx_pip_xstat1_prt# 3693 * 3694 * PIP_XSTAT1_PRTX = PIP_XSTAT_OCTS 3695 * 3696 */ 3697union cvmx_pip_xstat1_prtx 3698{ 3699 uint64_t u64; 3700 struct cvmx_pip_xstat1_prtx_s 3701 { 3702#if __BYTE_ORDER == __BIG_ENDIAN 3703 uint64_t reserved_48_63 : 16; 3704 uint64_t octs : 48; /**< Number of octets received by PIP (good and bad) */ 3705#else 3706 uint64_t octs : 48; 3707 uint64_t reserved_48_63 : 16; 3708#endif 3709 } s; 3710 struct cvmx_pip_xstat1_prtx_s cn63xx; 3711 struct cvmx_pip_xstat1_prtx_s cn63xxp1; 3712}; 3713typedef union cvmx_pip_xstat1_prtx cvmx_pip_xstat1_prtx_t; 3714 3715/** 3716 * cvmx_pip_xstat2_prt# 3717 * 3718 * PIP_XSTAT2_PRTX = PIP_XSTAT_PKTS / PIP_XSTAT_RAW 3719 * 3720 */ 3721union cvmx_pip_xstat2_prtx 3722{ 3723 uint64_t u64; 3724 struct cvmx_pip_xstat2_prtx_s 3725 { 3726#if __BYTE_ORDER == __BIG_ENDIAN 3727 uint64_t pkts : 32; /**< Number of packets processed by PIP */ 3728 uint64_t raw : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error 3729 received by PIP per port */ 3730#else 3731 uint64_t raw : 32; 3732 uint64_t pkts : 32; 3733#endif 3734 } s; 3735 struct cvmx_pip_xstat2_prtx_s cn63xx; 3736 struct cvmx_pip_xstat2_prtx_s cn63xxp1; 3737}; 3738typedef union cvmx_pip_xstat2_prtx cvmx_pip_xstat2_prtx_t; 3739 3740/** 3741 * cvmx_pip_xstat3_prt# 3742 * 3743 * PIP_XSTAT3_PRTX = PIP_XSTAT_BCST / PIP_XSTAT_MCST 3744 * 3745 */ 3746union cvmx_pip_xstat3_prtx 3747{ 3748 uint64_t u64; 3749 struct cvmx_pip_xstat3_prtx_s 3750 { 3751#if __BYTE_ORDER == __BIG_ENDIAN 3752 uint64_t bcst : 32; /**< Number of indentified L2 broadcast packets 3753 Does not include multicast packets 3754 Only includes packets whose parse mode is 3755 SKIP_TO_L2. */ 3756 uint64_t mcst : 32; /**< Number of indentified L2 multicast packets 3757 Does not include broadcast packets 3758 Only includes packets whose parse mode is 3759 SKIP_TO_L2. */ 3760#else 3761 uint64_t mcst : 32; 3762 uint64_t bcst : 32; 3763#endif 3764 } s; 3765 struct cvmx_pip_xstat3_prtx_s cn63xx; 3766 struct cvmx_pip_xstat3_prtx_s cn63xxp1; 3767}; 3768typedef union cvmx_pip_xstat3_prtx cvmx_pip_xstat3_prtx_t; 3769 3770/** 3771 * cvmx_pip_xstat4_prt# 3772 * 3773 * PIP_XSTAT4_PRTX = PIP_XSTAT_HIST1 / PIP_XSTAT_HIST0 3774 * 3775 */ 3776union cvmx_pip_xstat4_prtx 3777{ 3778 uint64_t u64; 3779 struct cvmx_pip_xstat4_prtx_s 3780 { 3781#if __BYTE_ORDER == __BIG_ENDIAN 3782 uint64_t h65to127 : 32; /**< Number of 65-127B packets */ 3783 uint64_t h64 : 32; /**< Number of 1-64B packets */ 3784#else 3785 uint64_t h64 : 32; 3786 uint64_t h65to127 : 32; 3787#endif 3788 } s; 3789 struct cvmx_pip_xstat4_prtx_s cn63xx; 3790 struct cvmx_pip_xstat4_prtx_s cn63xxp1; 3791}; 3792typedef union cvmx_pip_xstat4_prtx cvmx_pip_xstat4_prtx_t; 3793 3794/** 3795 * cvmx_pip_xstat5_prt# 3796 * 3797 * PIP_XSTAT5_PRTX = PIP_XSTAT_HIST3 / PIP_XSTAT_HIST2 3798 * 3799 */ 3800union cvmx_pip_xstat5_prtx 3801{ 3802 uint64_t u64; 3803 struct cvmx_pip_xstat5_prtx_s 3804 { 3805#if __BYTE_ORDER == __BIG_ENDIAN 3806 uint64_t h256to511 : 32; /**< Number of 256-511B packets */ 3807 uint64_t h128to255 : 32; /**< Number of 128-255B packets */ 3808#else 3809 uint64_t h128to255 : 32; 3810 uint64_t h256to511 : 32; 3811#endif 3812 } s; 3813 struct cvmx_pip_xstat5_prtx_s cn63xx; 3814 struct cvmx_pip_xstat5_prtx_s cn63xxp1; 3815}; 3816typedef union cvmx_pip_xstat5_prtx cvmx_pip_xstat5_prtx_t; 3817 3818/** 3819 * cvmx_pip_xstat6_prt# 3820 * 3821 * PIP_XSTAT6_PRTX = PIP_XSTAT_HIST5 / PIP_XSTAT_HIST4 3822 * 3823 */ 3824union cvmx_pip_xstat6_prtx 3825{ 3826 uint64_t u64; 3827 struct cvmx_pip_xstat6_prtx_s 3828 { 3829#if __BYTE_ORDER == __BIG_ENDIAN 3830 uint64_t h1024to1518 : 32; /**< Number of 1024-1518B packets */ 3831 uint64_t h512to1023 : 32; /**< Number of 512-1023B packets */ 3832#else 3833 uint64_t h512to1023 : 32; 3834 uint64_t h1024to1518 : 32; 3835#endif 3836 } s; 3837 struct cvmx_pip_xstat6_prtx_s cn63xx; 3838 struct cvmx_pip_xstat6_prtx_s cn63xxp1; 3839}; 3840typedef union cvmx_pip_xstat6_prtx cvmx_pip_xstat6_prtx_t; 3841 3842/** 3843 * cvmx_pip_xstat7_prt# 3844 * 3845 * PIP_XSTAT7_PRTX = PIP_XSTAT_FCS / PIP_XSTAT_HIST6 3846 * 3847 * 3848 * Notes: 3849 * Note: FCS is not checked on the PCI ports 32..35. 3850 * 3851 */ 3852union cvmx_pip_xstat7_prtx 3853{ 3854 uint64_t u64; 3855 struct cvmx_pip_xstat7_prtx_s 3856 { 3857#if __BYTE_ORDER == __BIG_ENDIAN 3858 uint64_t fcs : 32; /**< Number of packets with FCS or Align opcode errors */ 3859 uint64_t h1519 : 32; /**< Number of 1519-max packets */ 3860#else 3861 uint64_t h1519 : 32; 3862 uint64_t fcs : 32; 3863#endif 3864 } s; 3865 struct cvmx_pip_xstat7_prtx_s cn63xx; 3866 struct cvmx_pip_xstat7_prtx_s cn63xxp1; 3867}; 3868typedef union cvmx_pip_xstat7_prtx cvmx_pip_xstat7_prtx_t; 3869 3870/** 3871 * cvmx_pip_xstat8_prt# 3872 * 3873 * PIP_XSTAT8_PRTX = PIP_XSTAT_FRAG / PIP_XSTAT_UNDER 3874 * 3875 * 3876 * Notes: 3877 * Note: FCS is not checked on the PCI ports 32..35. 3878 * 3879 */ 3880union cvmx_pip_xstat8_prtx 3881{ 3882 uint64_t u64; 3883 struct cvmx_pip_xstat8_prtx_s 3884 { 3885#if __BYTE_ORDER == __BIG_ENDIAN 3886 uint64_t frag : 32; /**< Number of packets with length < min and FCS error */ 3887 uint64_t undersz : 32; /**< Number of packets with length < min */ 3888#else 3889 uint64_t undersz : 32; 3890 uint64_t frag : 32; 3891#endif 3892 } s; 3893 struct cvmx_pip_xstat8_prtx_s cn63xx; 3894 struct cvmx_pip_xstat8_prtx_s cn63xxp1; 3895}; 3896typedef union cvmx_pip_xstat8_prtx cvmx_pip_xstat8_prtx_t; 3897 3898/** 3899 * cvmx_pip_xstat9_prt# 3900 * 3901 * PIP_XSTAT9_PRTX = PIP_XSTAT_JABBER / PIP_XSTAT_OVER 3902 * 3903 * 3904 * Notes: 3905 * Note: FCS is not checked on the PCI ports 32..35. 3906 * 3907 */ 3908union cvmx_pip_xstat9_prtx 3909{ 3910 uint64_t u64; 3911 struct cvmx_pip_xstat9_prtx_s 3912 { 3913#if __BYTE_ORDER == __BIG_ENDIAN 3914 uint64_t jabber : 32; /**< Number of packets with length > max and FCS error */ 3915 uint64_t oversz : 32; /**< Number of packets with length > max */ 3916#else 3917 uint64_t oversz : 32; 3918 uint64_t jabber : 32; 3919#endif 3920 } s; 3921 struct cvmx_pip_xstat9_prtx_s cn63xx; 3922 struct cvmx_pip_xstat9_prtx_s cn63xxp1; 3923}; 3924typedef union cvmx_pip_xstat9_prtx cvmx_pip_xstat9_prtx_t; 3925 3926#endif 3927