1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pip-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pip. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_PIP_DEFS_H__ 53232812Sjmallett#define __CVMX_PIP_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56232812Sjmallettstatic inline uint64_t CVMX_PIP_ALT_SKIP_CFGX(unsigned long offset) 57232812Sjmallett{ 58232812Sjmallett if (!( 59232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 60232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 61232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) || 62232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 63232812Sjmallett cvmx_warn("CVMX_PIP_ALT_SKIP_CFGX(%lu) is invalid on this chip\n", offset); 64232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8; 65232812Sjmallett} 66232812Sjmallett#else 67232812Sjmallett#define CVMX_PIP_ALT_SKIP_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002A00ull) + ((offset) & 3) * 8) 68232812Sjmallett#endif 69232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 70215976Sjmallett#define CVMX_PIP_BCK_PRS CVMX_PIP_BCK_PRS_FUNC() 71215976Sjmallettstatic inline uint64_t CVMX_PIP_BCK_PRS_FUNC(void) 72215976Sjmallett{ 73232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 74215976Sjmallett cvmx_warn("CVMX_PIP_BCK_PRS not supported on this chip\n"); 75215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000038ull); 76215976Sjmallett} 77215976Sjmallett#else 78215976Sjmallett#define CVMX_PIP_BCK_PRS (CVMX_ADD_IO_SEG(0x00011800A0000038ull)) 79215976Sjmallett#endif 80215976Sjmallett#define CVMX_PIP_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800A0000000ull)) 81215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82232812Sjmallettstatic inline uint64_t CVMX_PIP_BSEL_EXT_CFGX(unsigned long offset) 83232812Sjmallett{ 84232812Sjmallett if (!( 85232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 86232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) || 87232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 88232812Sjmallett cvmx_warn("CVMX_PIP_BSEL_EXT_CFGX(%lu) is invalid on this chip\n", offset); 89232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16; 90232812Sjmallett} 91232812Sjmallett#else 92232812Sjmallett#define CVMX_PIP_BSEL_EXT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002800ull) + ((offset) & 3) * 16) 93232812Sjmallett#endif 94232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 95232812Sjmallettstatic inline uint64_t CVMX_PIP_BSEL_EXT_POSX(unsigned long offset) 96232812Sjmallett{ 97232812Sjmallett if (!( 98232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 99232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) || 100232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 101232812Sjmallett cvmx_warn("CVMX_PIP_BSEL_EXT_POSX(%lu) is invalid on this chip\n", offset); 102232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16; 103232812Sjmallett} 104232812Sjmallett#else 105232812Sjmallett#define CVMX_PIP_BSEL_EXT_POSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002808ull) + ((offset) & 3) * 16) 106232812Sjmallett#endif 107232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108232812Sjmallettstatic inline uint64_t CVMX_PIP_BSEL_TBL_ENTX(unsigned long offset) 109232812Sjmallett{ 110232812Sjmallett if (!( 111232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 511))) || 112232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 511))) || 113232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 511))))) 114232812Sjmallett cvmx_warn("CVMX_PIP_BSEL_TBL_ENTX(%lu) is invalid on this chip\n", offset); 115232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8; 116232812Sjmallett} 117232812Sjmallett#else 118232812Sjmallett#define CVMX_PIP_BSEL_TBL_ENTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0003000ull) + ((offset) & 511) * 8) 119232812Sjmallett#endif 120232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121215976Sjmallett#define CVMX_PIP_CLKEN CVMX_PIP_CLKEN_FUNC() 122215976Sjmallettstatic inline uint64_t CVMX_PIP_CLKEN_FUNC(void) 123215976Sjmallett{ 124232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 125215976Sjmallett cvmx_warn("CVMX_PIP_CLKEN not supported on this chip\n"); 126215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000040ull); 127215976Sjmallett} 128215976Sjmallett#else 129215976Sjmallett#define CVMX_PIP_CLKEN (CVMX_ADD_IO_SEG(0x00011800A0000040ull)) 130215976Sjmallett#endif 131215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 132215976Sjmallettstatic inline uint64_t CVMX_PIP_CRC_CTLX(unsigned long offset) 133215976Sjmallett{ 134215976Sjmallett if (!( 135215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 136215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 137215976Sjmallett cvmx_warn("CVMX_PIP_CRC_CTLX(%lu) is invalid on this chip\n", offset); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8; 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_PIP_CRC_CTLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000040ull) + ((offset) & 1) * 8) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallettstatic inline uint64_t CVMX_PIP_CRC_IVX(unsigned long offset) 145215976Sjmallett{ 146215976Sjmallett if (!( 147215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 148215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 149215976Sjmallett cvmx_warn("CVMX_PIP_CRC_IVX(%lu) is invalid on this chip\n", offset); 150215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8; 151215976Sjmallett} 152215976Sjmallett#else 153215976Sjmallett#define CVMX_PIP_CRC_IVX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000050ull) + ((offset) & 1) * 8) 154215976Sjmallett#endif 155215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 156215976Sjmallettstatic inline uint64_t CVMX_PIP_DEC_IPSECX(unsigned long offset) 157215976Sjmallett{ 158215976Sjmallett if (!( 159215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 160215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 161215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 162215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 163215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 164215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) || 165215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) || 166232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) || 168232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 169232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) || 170232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 171215976Sjmallett cvmx_warn("CVMX_PIP_DEC_IPSECX(%lu) is invalid on this chip\n", offset); 172215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8; 173215976Sjmallett} 174215976Sjmallett#else 175215976Sjmallett#define CVMX_PIP_DEC_IPSECX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000080ull) + ((offset) & 3) * 8) 176215976Sjmallett#endif 177215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 178215976Sjmallett#define CVMX_PIP_DSA_SRC_GRP CVMX_PIP_DSA_SRC_GRP_FUNC() 179215976Sjmallettstatic inline uint64_t CVMX_PIP_DSA_SRC_GRP_FUNC(void) 180215976Sjmallett{ 181232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 182215976Sjmallett cvmx_warn("CVMX_PIP_DSA_SRC_GRP not supported on this chip\n"); 183215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000190ull); 184215976Sjmallett} 185215976Sjmallett#else 186215976Sjmallett#define CVMX_PIP_DSA_SRC_GRP (CVMX_ADD_IO_SEG(0x00011800A0000190ull)) 187215976Sjmallett#endif 188215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 189215976Sjmallett#define CVMX_PIP_DSA_VID_GRP CVMX_PIP_DSA_VID_GRP_FUNC() 190215976Sjmallettstatic inline uint64_t CVMX_PIP_DSA_VID_GRP_FUNC(void) 191215976Sjmallett{ 192232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 193215976Sjmallett cvmx_warn("CVMX_PIP_DSA_VID_GRP not supported on this chip\n"); 194215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000198ull); 195215976Sjmallett} 196215976Sjmallett#else 197215976Sjmallett#define CVMX_PIP_DSA_VID_GRP (CVMX_ADD_IO_SEG(0x00011800A0000198ull)) 198215976Sjmallett#endif 199215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 200215976Sjmallettstatic inline uint64_t CVMX_PIP_FRM_LEN_CHKX(unsigned long offset) 201215976Sjmallett{ 202215976Sjmallett if (!( 203215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 204215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) || 205215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 206232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0))) || 207232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0))) || 208232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0))) || 209232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 210232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0))))) 211215976Sjmallett cvmx_warn("CVMX_PIP_FRM_LEN_CHKX(%lu) is invalid on this chip\n", offset); 212215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8; 213215976Sjmallett} 214215976Sjmallett#else 215215976Sjmallett#define CVMX_PIP_FRM_LEN_CHKX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000180ull) + ((offset) & 1) * 8) 216215976Sjmallett#endif 217215976Sjmallett#define CVMX_PIP_GBL_CFG (CVMX_ADD_IO_SEG(0x00011800A0000028ull)) 218215976Sjmallett#define CVMX_PIP_GBL_CTL (CVMX_ADD_IO_SEG(0x00011800A0000020ull)) 219215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 220215976Sjmallett#define CVMX_PIP_HG_PRI_QOS CVMX_PIP_HG_PRI_QOS_FUNC() 221215976Sjmallettstatic inline uint64_t CVMX_PIP_HG_PRI_QOS_FUNC(void) 222215976Sjmallett{ 223232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 224215976Sjmallett cvmx_warn("CVMX_PIP_HG_PRI_QOS not supported on this chip\n"); 225215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A00001A0ull); 226215976Sjmallett} 227215976Sjmallett#else 228215976Sjmallett#define CVMX_PIP_HG_PRI_QOS (CVMX_ADD_IO_SEG(0x00011800A00001A0ull)) 229215976Sjmallett#endif 230215976Sjmallett#define CVMX_PIP_INT_EN (CVMX_ADD_IO_SEG(0x00011800A0000010ull)) 231215976Sjmallett#define CVMX_PIP_INT_REG (CVMX_ADD_IO_SEG(0x00011800A0000008ull)) 232215976Sjmallett#define CVMX_PIP_IP_OFFSET (CVMX_ADD_IO_SEG(0x00011800A0000060ull)) 233215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 234232812Sjmallettstatic inline uint64_t CVMX_PIP_PRI_TBLX(unsigned long offset) 235232812Sjmallett{ 236232812Sjmallett if (!( 237232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 255))))) 238232812Sjmallett cvmx_warn("CVMX_PIP_PRI_TBLX(%lu) is invalid on this chip\n", offset); 239232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8; 240232812Sjmallett} 241232812Sjmallett#else 242232812Sjmallett#define CVMX_PIP_PRI_TBLX(offset) (CVMX_ADD_IO_SEG(0x00011800A0004000ull) + ((offset) & 255) * 8) 243232812Sjmallett#endif 244232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 245232812Sjmallettstatic inline uint64_t CVMX_PIP_PRT_CFGBX(unsigned long offset) 246232812Sjmallett{ 247232812Sjmallett if (!( 248232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 249232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)) || ((offset >= 44) && (offset <= 47)))) || 250232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) || 251232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 252232812Sjmallett cvmx_warn("CVMX_PIP_PRT_CFGBX(%lu) is invalid on this chip\n", offset); 253232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8; 254232812Sjmallett} 255232812Sjmallett#else 256232812Sjmallett#define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8) 257232812Sjmallett#endif 258232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 259215976Sjmallettstatic inline uint64_t CVMX_PIP_PRT_CFGX(unsigned long offset) 260215976Sjmallett{ 261215976Sjmallett if (!( 262215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 263215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 264215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 265215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 266215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 267215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 268215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 269232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 270232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) || 271232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) || 272232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) || 273232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 274215976Sjmallett cvmx_warn("CVMX_PIP_PRT_CFGX(%lu) is invalid on this chip\n", offset); 275215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8; 276215976Sjmallett} 277215976Sjmallett#else 278215976Sjmallett#define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8) 279215976Sjmallett#endif 280215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 281215976Sjmallettstatic inline uint64_t CVMX_PIP_PRT_TAGX(unsigned long offset) 282215976Sjmallett{ 283215976Sjmallett if (!( 284215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 285215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 286215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 287215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 288215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 289215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 290215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 291232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 292232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) || 293232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) || 294232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) || 295232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 296215976Sjmallett cvmx_warn("CVMX_PIP_PRT_TAGX(%lu) is invalid on this chip\n", offset); 297215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8; 298215976Sjmallett} 299215976Sjmallett#else 300215976Sjmallett#define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8) 301215976Sjmallett#endif 302215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 303215976Sjmallettstatic inline uint64_t CVMX_PIP_QOS_DIFFX(unsigned long offset) 304215976Sjmallett{ 305215976Sjmallett if (!( 306215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) || 307215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) || 308215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) || 309215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) || 310215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) || 311215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) || 312215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) || 313232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 63))) || 314232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63))) || 315232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 63))) || 316232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63))))) 317215976Sjmallett cvmx_warn("CVMX_PIP_QOS_DIFFX(%lu) is invalid on this chip\n", offset); 318215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8; 319215976Sjmallett} 320215976Sjmallett#else 321215976Sjmallett#define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8) 322215976Sjmallett#endif 323215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 324215976Sjmallettstatic inline uint64_t CVMX_PIP_QOS_VLANX(unsigned long offset) 325215976Sjmallett{ 326215976Sjmallett if (!( 327215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) || 328215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) || 329215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 330215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 331215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 332215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 333215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) || 334232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 335232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 336232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 337232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 338215976Sjmallett cvmx_warn("CVMX_PIP_QOS_VLANX(%lu) is invalid on this chip\n", offset); 339215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8; 340215976Sjmallett} 341215976Sjmallett#else 342215976Sjmallett#define CVMX_PIP_QOS_VLANX(offset) (CVMX_ADD_IO_SEG(0x00011800A00000C0ull) + ((offset) & 7) * 8) 343215976Sjmallett#endif 344215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 345215976Sjmallettstatic inline uint64_t CVMX_PIP_QOS_WATCHX(unsigned long offset) 346215976Sjmallett{ 347215976Sjmallett if (!( 348215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 349215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 350215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 351215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) || 352215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) || 353215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 354215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) || 355232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) || 356232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) || 357232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) || 358232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) || 359232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7))))) 360215976Sjmallett cvmx_warn("CVMX_PIP_QOS_WATCHX(%lu) is invalid on this chip\n", offset); 361215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8; 362215976Sjmallett} 363215976Sjmallett#else 364215976Sjmallett#define CVMX_PIP_QOS_WATCHX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000100ull) + ((offset) & 7) * 8) 365215976Sjmallett#endif 366215976Sjmallett#define CVMX_PIP_RAW_WORD (CVMX_ADD_IO_SEG(0x00011800A00000B0ull)) 367215976Sjmallett#define CVMX_PIP_SFT_RST (CVMX_ADD_IO_SEG(0x00011800A0000030ull)) 368215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 369215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT0_PRTX(unsigned long offset) 370215976Sjmallett{ 371215976Sjmallett if (!( 372215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 373215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 374215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 375215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 376215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 377215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 378215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 379232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 380232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 381232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 382232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 383215976Sjmallett cvmx_warn("CVMX_PIP_STAT0_PRTX(%lu) is invalid on this chip\n", offset); 384215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80; 385215976Sjmallett} 386215976Sjmallett#else 387215976Sjmallett#define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80) 388215976Sjmallett#endif 389215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 390232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT0_X(unsigned long offset) 391232812Sjmallett{ 392232812Sjmallett if (!( 393232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 394232812Sjmallett cvmx_warn("CVMX_PIP_STAT0_X(%lu) is invalid on this chip\n", offset); 395232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128; 396232812Sjmallett} 397232812Sjmallett#else 398232812Sjmallett#define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128) 399232812Sjmallett#endif 400232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 401232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT10_PRTX(unsigned long offset) 402232812Sjmallett{ 403232812Sjmallett if (!( 404232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 405232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 406232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 407232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 408232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 409232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 410232812Sjmallett cvmx_warn("CVMX_PIP_STAT10_PRTX(%lu) is invalid on this chip\n", offset); 411232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16; 412232812Sjmallett} 413232812Sjmallett#else 414232812Sjmallett#define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16) 415232812Sjmallett#endif 416232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 417232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT10_X(unsigned long offset) 418232812Sjmallett{ 419232812Sjmallett if (!( 420232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 421232812Sjmallett cvmx_warn("CVMX_PIP_STAT10_X(%lu) is invalid on this chip\n", offset); 422232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128; 423232812Sjmallett} 424232812Sjmallett#else 425232812Sjmallett#define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128) 426232812Sjmallett#endif 427232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 428232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT11_PRTX(unsigned long offset) 429232812Sjmallett{ 430232812Sjmallett if (!( 431232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 432232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 433232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 434232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 435232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 436232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 437232812Sjmallett cvmx_warn("CVMX_PIP_STAT11_PRTX(%lu) is invalid on this chip\n", offset); 438232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16; 439232812Sjmallett} 440232812Sjmallett#else 441232812Sjmallett#define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16) 442232812Sjmallett#endif 443232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 444232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT11_X(unsigned long offset) 445232812Sjmallett{ 446232812Sjmallett if (!( 447232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 448232812Sjmallett cvmx_warn("CVMX_PIP_STAT11_X(%lu) is invalid on this chip\n", offset); 449232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128; 450232812Sjmallett} 451232812Sjmallett#else 452232812Sjmallett#define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128) 453232812Sjmallett#endif 454232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 455215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT1_PRTX(unsigned long offset) 456215976Sjmallett{ 457215976Sjmallett if (!( 458215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 459215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 460215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 461215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 462215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 463215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 464215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 465232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 466232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 467232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 468232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 469215976Sjmallett cvmx_warn("CVMX_PIP_STAT1_PRTX(%lu) is invalid on this chip\n", offset); 470215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80; 471215976Sjmallett} 472215976Sjmallett#else 473215976Sjmallett#define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80) 474215976Sjmallett#endif 475215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 476232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT1_X(unsigned long offset) 477232812Sjmallett{ 478232812Sjmallett if (!( 479232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 480232812Sjmallett cvmx_warn("CVMX_PIP_STAT1_X(%lu) is invalid on this chip\n", offset); 481232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128; 482232812Sjmallett} 483232812Sjmallett#else 484232812Sjmallett#define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128) 485232812Sjmallett#endif 486232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 487215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT2_PRTX(unsigned long offset) 488215976Sjmallett{ 489215976Sjmallett if (!( 490215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 491215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 492215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 493215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 494215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 495215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 496215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 497232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 498232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 499232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 500232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 501215976Sjmallett cvmx_warn("CVMX_PIP_STAT2_PRTX(%lu) is invalid on this chip\n", offset); 502215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80; 503215976Sjmallett} 504215976Sjmallett#else 505215976Sjmallett#define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80) 506215976Sjmallett#endif 507215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 508232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT2_X(unsigned long offset) 509232812Sjmallett{ 510232812Sjmallett if (!( 511232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 512232812Sjmallett cvmx_warn("CVMX_PIP_STAT2_X(%lu) is invalid on this chip\n", offset); 513232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128; 514232812Sjmallett} 515232812Sjmallett#else 516232812Sjmallett#define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128) 517232812Sjmallett#endif 518232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 519215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT3_PRTX(unsigned long offset) 520215976Sjmallett{ 521215976Sjmallett if (!( 522215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 523215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 524215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 525215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 526215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 527215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 528215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 529232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 530232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 531232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 532232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 533215976Sjmallett cvmx_warn("CVMX_PIP_STAT3_PRTX(%lu) is invalid on this chip\n", offset); 534215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80; 535215976Sjmallett} 536215976Sjmallett#else 537215976Sjmallett#define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80) 538215976Sjmallett#endif 539215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT3_X(unsigned long offset) 541232812Sjmallett{ 542232812Sjmallett if (!( 543232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 544232812Sjmallett cvmx_warn("CVMX_PIP_STAT3_X(%lu) is invalid on this chip\n", offset); 545232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128; 546232812Sjmallett} 547232812Sjmallett#else 548232812Sjmallett#define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128) 549232812Sjmallett#endif 550232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT4_PRTX(unsigned long offset) 552215976Sjmallett{ 553215976Sjmallett if (!( 554215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 555215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 556215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 557215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 558215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 559215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 560215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 561232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 562232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 563232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 564232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 565215976Sjmallett cvmx_warn("CVMX_PIP_STAT4_PRTX(%lu) is invalid on this chip\n", offset); 566215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80; 567215976Sjmallett} 568215976Sjmallett#else 569215976Sjmallett#define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80) 570215976Sjmallett#endif 571215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 572232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT4_X(unsigned long offset) 573232812Sjmallett{ 574232812Sjmallett if (!( 575232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 576232812Sjmallett cvmx_warn("CVMX_PIP_STAT4_X(%lu) is invalid on this chip\n", offset); 577232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128; 578232812Sjmallett} 579232812Sjmallett#else 580232812Sjmallett#define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128) 581232812Sjmallett#endif 582232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 583215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT5_PRTX(unsigned long offset) 584215976Sjmallett{ 585215976Sjmallett if (!( 586215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 587215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 588215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 589215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 590215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 591215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 592215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 593232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 594232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 595232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 596232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 597215976Sjmallett cvmx_warn("CVMX_PIP_STAT5_PRTX(%lu) is invalid on this chip\n", offset); 598215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80; 599215976Sjmallett} 600215976Sjmallett#else 601215976Sjmallett#define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80) 602215976Sjmallett#endif 603215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 604232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT5_X(unsigned long offset) 605232812Sjmallett{ 606232812Sjmallett if (!( 607232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 608232812Sjmallett cvmx_warn("CVMX_PIP_STAT5_X(%lu) is invalid on this chip\n", offset); 609232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128; 610232812Sjmallett} 611232812Sjmallett#else 612232812Sjmallett#define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128) 613232812Sjmallett#endif 614232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 615215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT6_PRTX(unsigned long offset) 616215976Sjmallett{ 617215976Sjmallett if (!( 618215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 619215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 620215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 621215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 622215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 623215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 624215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 625232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 626232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 627232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 628232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 629215976Sjmallett cvmx_warn("CVMX_PIP_STAT6_PRTX(%lu) is invalid on this chip\n", offset); 630215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80; 631215976Sjmallett} 632215976Sjmallett#else 633215976Sjmallett#define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80) 634215976Sjmallett#endif 635215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 636232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT6_X(unsigned long offset) 637232812Sjmallett{ 638232812Sjmallett if (!( 639232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 640232812Sjmallett cvmx_warn("CVMX_PIP_STAT6_X(%lu) is invalid on this chip\n", offset); 641232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128; 642232812Sjmallett} 643232812Sjmallett#else 644232812Sjmallett#define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128) 645232812Sjmallett#endif 646232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 647215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT7_PRTX(unsigned long offset) 648215976Sjmallett{ 649215976Sjmallett if (!( 650215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 651215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 652215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 653215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 654215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 655215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 656215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 657232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 658232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 659232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 660232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 661215976Sjmallett cvmx_warn("CVMX_PIP_STAT7_PRTX(%lu) is invalid on this chip\n", offset); 662215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80; 663215976Sjmallett} 664215976Sjmallett#else 665215976Sjmallett#define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80) 666215976Sjmallett#endif 667215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 668232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT7_X(unsigned long offset) 669232812Sjmallett{ 670232812Sjmallett if (!( 671232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 672232812Sjmallett cvmx_warn("CVMX_PIP_STAT7_X(%lu) is invalid on this chip\n", offset); 673232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128; 674232812Sjmallett} 675232812Sjmallett#else 676232812Sjmallett#define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128) 677232812Sjmallett#endif 678232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 679215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT8_PRTX(unsigned long offset) 680215976Sjmallett{ 681215976Sjmallett if (!( 682215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 683215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 684215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 685215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 686215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 687215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 688215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 689232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 690232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 691232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 692232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 693215976Sjmallett cvmx_warn("CVMX_PIP_STAT8_PRTX(%lu) is invalid on this chip\n", offset); 694215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80; 695215976Sjmallett} 696215976Sjmallett#else 697215976Sjmallett#define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80) 698215976Sjmallett#endif 699215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 700232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT8_X(unsigned long offset) 701232812Sjmallett{ 702232812Sjmallett if (!( 703232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 704232812Sjmallett cvmx_warn("CVMX_PIP_STAT8_X(%lu) is invalid on this chip\n", offset); 705232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128; 706232812Sjmallett} 707232812Sjmallett#else 708232812Sjmallett#define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128) 709232812Sjmallett#endif 710232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 711215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT9_PRTX(unsigned long offset) 712215976Sjmallett{ 713215976Sjmallett if (!( 714215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 715215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 716215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 717215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 718215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 719215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 720215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 721232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 722232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 723232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 724232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 725215976Sjmallett cvmx_warn("CVMX_PIP_STAT9_PRTX(%lu) is invalid on this chip\n", offset); 726215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80; 727215976Sjmallett} 728215976Sjmallett#else 729215976Sjmallett#define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80) 730215976Sjmallett#endif 731232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 732232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT9_X(unsigned long offset) 733232812Sjmallett{ 734232812Sjmallett if (!( 735232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 736232812Sjmallett cvmx_warn("CVMX_PIP_STAT9_X(%lu) is invalid on this chip\n", offset); 737232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128; 738232812Sjmallett} 739232812Sjmallett#else 740232812Sjmallett#define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128) 741232812Sjmallett#endif 742215976Sjmallett#define CVMX_PIP_STAT_CTL (CVMX_ADD_IO_SEG(0x00011800A0000018ull)) 743215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 744215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT_INB_ERRSX(unsigned long offset) 745215976Sjmallett{ 746215976Sjmallett if (!( 747215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 748215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 749215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 750215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 751215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 752215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 753215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 754232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 755232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) || 756232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) || 757232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 758215976Sjmallett cvmx_warn("CVMX_PIP_STAT_INB_ERRSX(%lu) is invalid on this chip\n", offset); 759215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32; 760215976Sjmallett} 761215976Sjmallett#else 762215976Sjmallett#define CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32) 763215976Sjmallett#endif 764215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 765232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT_INB_ERRS_PKNDX(unsigned long offset) 766232812Sjmallett{ 767232812Sjmallett if (!( 768232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 769232812Sjmallett cvmx_warn("CVMX_PIP_STAT_INB_ERRS_PKNDX(%lu) is invalid on this chip\n", offset); 770232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32; 771232812Sjmallett} 772232812Sjmallett#else 773232812Sjmallett#define CVMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32) 774232812Sjmallett#endif 775232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 776215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT_INB_OCTSX(unsigned long offset) 777215976Sjmallett{ 778215976Sjmallett if (!( 779215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 780215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 781215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 782215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 783215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 784215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 785215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 786232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 787232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) || 788232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) || 789232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 790215976Sjmallett cvmx_warn("CVMX_PIP_STAT_INB_OCTSX(%lu) is invalid on this chip\n", offset); 791215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32; 792215976Sjmallett} 793215976Sjmallett#else 794215976Sjmallett#define CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32) 795215976Sjmallett#endif 796215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 797232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT_INB_OCTS_PKNDX(unsigned long offset) 798232812Sjmallett{ 799232812Sjmallett if (!( 800232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 801232812Sjmallett cvmx_warn("CVMX_PIP_STAT_INB_OCTS_PKNDX(%lu) is invalid on this chip\n", offset); 802232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32; 803232812Sjmallett} 804232812Sjmallett#else 805232812Sjmallett#define CVMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32) 806232812Sjmallett#endif 807232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 808215976Sjmallettstatic inline uint64_t CVMX_PIP_STAT_INB_PKTSX(unsigned long offset) 809215976Sjmallett{ 810215976Sjmallett if (!( 811215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 812215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 813215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) || 814215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) || 815215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 816215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 817215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) || 818232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))) || 819232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 43)))) || 820232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)) || ((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) || 821232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1) || ((offset >= 32) && (offset <= 35)) || ((offset >= 36) && (offset <= 39)))))) 822215976Sjmallett cvmx_warn("CVMX_PIP_STAT_INB_PKTSX(%lu) is invalid on this chip\n", offset); 823215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32; 824215976Sjmallett} 825215976Sjmallett#else 826215976Sjmallett#define CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32) 827215976Sjmallett#endif 828215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 829232812Sjmallettstatic inline uint64_t CVMX_PIP_STAT_INB_PKTS_PKNDX(unsigned long offset) 830232812Sjmallett{ 831232812Sjmallett if (!( 832232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))))) 833232812Sjmallett cvmx_warn("CVMX_PIP_STAT_INB_PKTS_PKNDX(%lu) is invalid on this chip\n", offset); 834232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32; 835232812Sjmallett} 836232812Sjmallett#else 837232812Sjmallett#define CVMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32) 838232812Sjmallett#endif 839232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 840232812Sjmallettstatic inline uint64_t CVMX_PIP_SUB_PKIND_FCSX(unsigned long block_id) 841232812Sjmallett{ 842232812Sjmallett if (!( 843232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))))) 844232812Sjmallett cvmx_warn("CVMX_PIP_SUB_PKIND_FCSX(%lu) is invalid on this chip\n", block_id); 845232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0080000ull); 846232812Sjmallett} 847232812Sjmallett#else 848232812Sjmallett#define CVMX_PIP_SUB_PKIND_FCSX(block_id) (CVMX_ADD_IO_SEG(0x00011800A0080000ull)) 849232812Sjmallett#endif 850232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 851215976Sjmallettstatic inline uint64_t CVMX_PIP_TAG_INCX(unsigned long offset) 852215976Sjmallett{ 853215976Sjmallett if (!( 854215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 63))) || 855215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 63))) || 856215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 63))) || 857215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 63))) || 858215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 63))) || 859215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 63))) || 860215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 63))) || 861232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 63))) || 862232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 63))) || 863232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 63))) || 864232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63))) || 865232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 63))))) 866215976Sjmallett cvmx_warn("CVMX_PIP_TAG_INCX(%lu) is invalid on this chip\n", offset); 867215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8; 868215976Sjmallett} 869215976Sjmallett#else 870215976Sjmallett#define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8) 871215976Sjmallett#endif 872215976Sjmallett#define CVMX_PIP_TAG_MASK (CVMX_ADD_IO_SEG(0x00011800A0000070ull)) 873215976Sjmallett#define CVMX_PIP_TAG_SECRET (CVMX_ADD_IO_SEG(0x00011800A0000068ull)) 874215976Sjmallett#define CVMX_PIP_TODO_ENTRY (CVMX_ADD_IO_SEG(0x00011800A0000078ull)) 875215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 876232812Sjmallettstatic inline uint64_t CVMX_PIP_VLAN_ETYPESX(unsigned long offset) 877232812Sjmallett{ 878232812Sjmallett if (!( 879232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 880232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 881232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 882232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 883232812Sjmallett cvmx_warn("CVMX_PIP_VLAN_ETYPESX(%lu) is invalid on this chip\n", offset); 884232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8; 885232812Sjmallett} 886232812Sjmallett#else 887232812Sjmallett#define CVMX_PIP_VLAN_ETYPESX(offset) (CVMX_ADD_IO_SEG(0x00011800A00001C0ull) + ((offset) & 1) * 8) 888232812Sjmallett#endif 889232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 890215976Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT0_PRTX(unsigned long offset) 891215976Sjmallett{ 892215976Sjmallett if (!( 893232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 894232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 895215976Sjmallett cvmx_warn("CVMX_PIP_XSTAT0_PRTX(%lu) is invalid on this chip\n", offset); 896215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40; 897215976Sjmallett} 898215976Sjmallett#else 899215976Sjmallett#define CVMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40) 900215976Sjmallett#endif 901215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 902232812Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT10_PRTX(unsigned long offset) 903232812Sjmallett{ 904232812Sjmallett if (!( 905232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 906232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 907232812Sjmallett cvmx_warn("CVMX_PIP_XSTAT10_PRTX(%lu) is invalid on this chip\n", offset); 908232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40; 909232812Sjmallett} 910232812Sjmallett#else 911232812Sjmallett#define CVMX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40) 912232812Sjmallett#endif 913232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 914232812Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT11_PRTX(unsigned long offset) 915232812Sjmallett{ 916232812Sjmallett if (!( 917232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 918232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 919232812Sjmallett cvmx_warn("CVMX_PIP_XSTAT11_PRTX(%lu) is invalid on this chip\n", offset); 920232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40; 921232812Sjmallett} 922232812Sjmallett#else 923232812Sjmallett#define CVMX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40) 924232812Sjmallett#endif 925232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 926215976Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT1_PRTX(unsigned long offset) 927215976Sjmallett{ 928215976Sjmallett if (!( 929232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 930232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 931215976Sjmallett cvmx_warn("CVMX_PIP_XSTAT1_PRTX(%lu) is invalid on this chip\n", offset); 932215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40; 933215976Sjmallett} 934215976Sjmallett#else 935215976Sjmallett#define CVMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40) 936215976Sjmallett#endif 937215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 938215976Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT2_PRTX(unsigned long offset) 939215976Sjmallett{ 940215976Sjmallett if (!( 941232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 942232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 943215976Sjmallett cvmx_warn("CVMX_PIP_XSTAT2_PRTX(%lu) is invalid on this chip\n", offset); 944215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40; 945215976Sjmallett} 946215976Sjmallett#else 947215976Sjmallett#define CVMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40) 948215976Sjmallett#endif 949215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 950215976Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT3_PRTX(unsigned long offset) 951215976Sjmallett{ 952215976Sjmallett if (!( 953232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 954232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 955215976Sjmallett cvmx_warn("CVMX_PIP_XSTAT3_PRTX(%lu) is invalid on this chip\n", offset); 956215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40; 957215976Sjmallett} 958215976Sjmallett#else 959215976Sjmallett#define CVMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40) 960215976Sjmallett#endif 961215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 962215976Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT4_PRTX(unsigned long offset) 963215976Sjmallett{ 964215976Sjmallett if (!( 965232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 966232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 967215976Sjmallett cvmx_warn("CVMX_PIP_XSTAT4_PRTX(%lu) is invalid on this chip\n", offset); 968215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40; 969215976Sjmallett} 970215976Sjmallett#else 971215976Sjmallett#define CVMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40) 972215976Sjmallett#endif 973215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 974215976Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT5_PRTX(unsigned long offset) 975215976Sjmallett{ 976215976Sjmallett if (!( 977232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 978232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 979215976Sjmallett cvmx_warn("CVMX_PIP_XSTAT5_PRTX(%lu) is invalid on this chip\n", offset); 980215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40; 981215976Sjmallett} 982215976Sjmallett#else 983215976Sjmallett#define CVMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40) 984215976Sjmallett#endif 985215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 986215976Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT6_PRTX(unsigned long offset) 987215976Sjmallett{ 988215976Sjmallett if (!( 989232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 990232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 991215976Sjmallett cvmx_warn("CVMX_PIP_XSTAT6_PRTX(%lu) is invalid on this chip\n", offset); 992215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40; 993215976Sjmallett} 994215976Sjmallett#else 995215976Sjmallett#define CVMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40) 996215976Sjmallett#endif 997215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 998215976Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT7_PRTX(unsigned long offset) 999215976Sjmallett{ 1000215976Sjmallett if (!( 1001232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 1002232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 1003215976Sjmallett cvmx_warn("CVMX_PIP_XSTAT7_PRTX(%lu) is invalid on this chip\n", offset); 1004215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40; 1005215976Sjmallett} 1006215976Sjmallett#else 1007215976Sjmallett#define CVMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40) 1008215976Sjmallett#endif 1009215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1010215976Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT8_PRTX(unsigned long offset) 1011215976Sjmallett{ 1012215976Sjmallett if (!( 1013232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 1014232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 1015215976Sjmallett cvmx_warn("CVMX_PIP_XSTAT8_PRTX(%lu) is invalid on this chip\n", offset); 1016215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40; 1017215976Sjmallett} 1018215976Sjmallett#else 1019215976Sjmallett#define CVMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40) 1020215976Sjmallett#endif 1021215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1022215976Sjmallettstatic inline uint64_t CVMX_PIP_XSTAT9_PRTX(unsigned long offset) 1023215976Sjmallett{ 1024215976Sjmallett if (!( 1025232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) || 1026232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))))) 1027215976Sjmallett cvmx_warn("CVMX_PIP_XSTAT9_PRTX(%lu) is invalid on this chip\n", offset); 1028215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40; 1029215976Sjmallett} 1030215976Sjmallett#else 1031215976Sjmallett#define CVMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40) 1032215976Sjmallett#endif 1033215976Sjmallett 1034215976Sjmallett/** 1035232812Sjmallett * cvmx_pip_alt_skip_cfg# 1036232812Sjmallett * 1037232812Sjmallett * Notes: 1038232812Sjmallett * The actual SKIP I determined by HW is based on the packet contents. BIT0 and 1039232812Sjmallett * BIT1 make up a two value value that the selects the skip value as follows. 1040232812Sjmallett * 1041232812Sjmallett * lookup_value = LEN ? ( packet_in_bits[BIT1], packet_in_bits[BIT0] ) : ( 0, packet_in_bits[BIT0] ); 1042232812Sjmallett * SKIP I = lookup_value == 3 ? SKIP3 : 1043232812Sjmallett * lookup_value == 2 ? SKIP2 : 1044232812Sjmallett * lookup_value == 1 ? SKIP1 : 1045232812Sjmallett * PIP_PRT_CFG<pknd>[SKIP]; 1046232812Sjmallett */ 1047232812Sjmallettunion cvmx_pip_alt_skip_cfgx { 1048232812Sjmallett uint64_t u64; 1049232812Sjmallett struct cvmx_pip_alt_skip_cfgx_s { 1050232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1051232812Sjmallett uint64_t reserved_57_63 : 7; 1052232812Sjmallett uint64_t len : 1; /**< Indicates the length of the selection field 1053232812Sjmallett 0 = 0, BIT0 1054232812Sjmallett 1 = BIT1, BIT0 */ 1055232812Sjmallett uint64_t reserved_46_55 : 10; 1056232812Sjmallett uint64_t bit1 : 6; /**< Indicates the bit location in the first word of 1057232812Sjmallett the packet to use to select the skip amount. 1058232812Sjmallett BIT1 must be present in the packet. */ 1059232812Sjmallett uint64_t reserved_38_39 : 2; 1060232812Sjmallett uint64_t bit0 : 6; /**< Indicates the bit location in the first word of 1061232812Sjmallett the packet to use to select the skip amount. 1062232812Sjmallett BIT0 must be present in the packet. */ 1063232812Sjmallett uint64_t reserved_23_31 : 9; 1064232812Sjmallett uint64_t skip3 : 7; /**< Indicates number of bytes to skip from start of 1065232812Sjmallett packet 0-64 */ 1066232812Sjmallett uint64_t reserved_15_15 : 1; 1067232812Sjmallett uint64_t skip2 : 7; /**< Indicates number of bytes to skip from start of 1068232812Sjmallett packet 0-64 */ 1069232812Sjmallett uint64_t reserved_7_7 : 1; 1070232812Sjmallett uint64_t skip1 : 7; /**< Indicates number of bytes to skip from start of 1071232812Sjmallett packet 0-64 */ 1072232812Sjmallett#else 1073232812Sjmallett uint64_t skip1 : 7; 1074232812Sjmallett uint64_t reserved_7_7 : 1; 1075232812Sjmallett uint64_t skip2 : 7; 1076232812Sjmallett uint64_t reserved_15_15 : 1; 1077232812Sjmallett uint64_t skip3 : 7; 1078232812Sjmallett uint64_t reserved_23_31 : 9; 1079232812Sjmallett uint64_t bit0 : 6; 1080232812Sjmallett uint64_t reserved_38_39 : 2; 1081232812Sjmallett uint64_t bit1 : 6; 1082232812Sjmallett uint64_t reserved_46_55 : 10; 1083232812Sjmallett uint64_t len : 1; 1084232812Sjmallett uint64_t reserved_57_63 : 7; 1085232812Sjmallett#endif 1086232812Sjmallett } s; 1087232812Sjmallett struct cvmx_pip_alt_skip_cfgx_s cn61xx; 1088232812Sjmallett struct cvmx_pip_alt_skip_cfgx_s cn66xx; 1089232812Sjmallett struct cvmx_pip_alt_skip_cfgx_s cn68xx; 1090232812Sjmallett struct cvmx_pip_alt_skip_cfgx_s cnf71xx; 1091232812Sjmallett}; 1092232812Sjmalletttypedef union cvmx_pip_alt_skip_cfgx cvmx_pip_alt_skip_cfgx_t; 1093232812Sjmallett 1094232812Sjmallett/** 1095215976Sjmallett * cvmx_pip_bck_prs 1096215976Sjmallett * 1097215976Sjmallett * PIP_BCK_PRS = PIP's Back Pressure Register 1098215976Sjmallett * 1099215976Sjmallett * When to assert backpressure based on the todo list filling up 1100215976Sjmallett */ 1101232812Sjmallettunion cvmx_pip_bck_prs { 1102215976Sjmallett uint64_t u64; 1103232812Sjmallett struct cvmx_pip_bck_prs_s { 1104232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1105215976Sjmallett uint64_t bckprs : 1; /**< PIP is currently asserting backpressure to IOB 1106215976Sjmallett Backpressure from PIP will assert when the 1107215976Sjmallett entries to the todo list exceed HIWATER. 1108215976Sjmallett Backpressure will be held until the todo entries 1109215976Sjmallett is less than or equal to LOWATER. */ 1110215976Sjmallett uint64_t reserved_13_62 : 50; 1111215976Sjmallett uint64_t hiwater : 5; /**< Water mark in the todo list to assert backpressure 1112215976Sjmallett Legal values are 1-26. A 0 value will deadlock 1113215976Sjmallett the machine. A value > 26, will trash memory */ 1114215976Sjmallett uint64_t reserved_5_7 : 3; 1115215976Sjmallett uint64_t lowater : 5; /**< Water mark in the todo list to release backpressure 1116215976Sjmallett The LOWATER value should be < HIWATER. */ 1117215976Sjmallett#else 1118215976Sjmallett uint64_t lowater : 5; 1119215976Sjmallett uint64_t reserved_5_7 : 3; 1120215976Sjmallett uint64_t hiwater : 5; 1121215976Sjmallett uint64_t reserved_13_62 : 50; 1122215976Sjmallett uint64_t bckprs : 1; 1123215976Sjmallett#endif 1124215976Sjmallett } s; 1125215976Sjmallett struct cvmx_pip_bck_prs_s cn38xx; 1126215976Sjmallett struct cvmx_pip_bck_prs_s cn38xxp2; 1127215976Sjmallett struct cvmx_pip_bck_prs_s cn56xx; 1128215976Sjmallett struct cvmx_pip_bck_prs_s cn56xxp1; 1129215976Sjmallett struct cvmx_pip_bck_prs_s cn58xx; 1130215976Sjmallett struct cvmx_pip_bck_prs_s cn58xxp1; 1131232812Sjmallett struct cvmx_pip_bck_prs_s cn61xx; 1132215976Sjmallett struct cvmx_pip_bck_prs_s cn63xx; 1133215976Sjmallett struct cvmx_pip_bck_prs_s cn63xxp1; 1134232812Sjmallett struct cvmx_pip_bck_prs_s cn66xx; 1135232812Sjmallett struct cvmx_pip_bck_prs_s cn68xx; 1136232812Sjmallett struct cvmx_pip_bck_prs_s cn68xxp1; 1137232812Sjmallett struct cvmx_pip_bck_prs_s cnf71xx; 1138215976Sjmallett}; 1139215976Sjmalletttypedef union cvmx_pip_bck_prs cvmx_pip_bck_prs_t; 1140215976Sjmallett 1141215976Sjmallett/** 1142215976Sjmallett * cvmx_pip_bist_status 1143215976Sjmallett * 1144215976Sjmallett * PIP_BIST_STATUS = PIP's BIST Results 1145215976Sjmallett * 1146215976Sjmallett */ 1147232812Sjmallettunion cvmx_pip_bist_status { 1148215976Sjmallett uint64_t u64; 1149232812Sjmallett struct cvmx_pip_bist_status_s { 1150232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1151232812Sjmallett uint64_t reserved_22_63 : 42; 1152232812Sjmallett uint64_t bist : 22; /**< BIST Results. 1153232812Sjmallett HW sets a bit in BIST for for memory that fails 1154232812Sjmallett BIST. */ 1155232812Sjmallett#else 1156232812Sjmallett uint64_t bist : 22; 1157232812Sjmallett uint64_t reserved_22_63 : 42; 1158232812Sjmallett#endif 1159232812Sjmallett } s; 1160232812Sjmallett struct cvmx_pip_bist_status_cn30xx { 1161232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1162215976Sjmallett uint64_t reserved_18_63 : 46; 1163215976Sjmallett uint64_t bist : 18; /**< BIST Results. 1164215976Sjmallett HW sets a bit in BIST for for memory that fails 1165215976Sjmallett BIST. */ 1166215976Sjmallett#else 1167215976Sjmallett uint64_t bist : 18; 1168215976Sjmallett uint64_t reserved_18_63 : 46; 1169215976Sjmallett#endif 1170232812Sjmallett } cn30xx; 1171232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn31xx; 1172232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn38xx; 1173232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn38xxp2; 1174232812Sjmallett struct cvmx_pip_bist_status_cn50xx { 1175232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1176215976Sjmallett uint64_t reserved_17_63 : 47; 1177215976Sjmallett uint64_t bist : 17; /**< BIST Results. 1178215976Sjmallett HW sets a bit in BIST for for memory that fails 1179215976Sjmallett BIST. */ 1180215976Sjmallett#else 1181215976Sjmallett uint64_t bist : 17; 1182215976Sjmallett uint64_t reserved_17_63 : 47; 1183215976Sjmallett#endif 1184215976Sjmallett } cn50xx; 1185232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn52xx; 1186232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn52xxp1; 1187232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn56xx; 1188232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn56xxp1; 1189232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn58xx; 1190232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn58xxp1; 1191232812Sjmallett struct cvmx_pip_bist_status_cn61xx { 1192232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1193232812Sjmallett uint64_t reserved_20_63 : 44; 1194232812Sjmallett uint64_t bist : 20; /**< BIST Results. 1195232812Sjmallett HW sets a bit in BIST for for memory that fails 1196232812Sjmallett BIST. */ 1197232812Sjmallett#else 1198232812Sjmallett uint64_t bist : 20; 1199232812Sjmallett uint64_t reserved_20_63 : 44; 1200232812Sjmallett#endif 1201232812Sjmallett } cn61xx; 1202232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn63xx; 1203232812Sjmallett struct cvmx_pip_bist_status_cn30xx cn63xxp1; 1204232812Sjmallett struct cvmx_pip_bist_status_cn61xx cn66xx; 1205232812Sjmallett struct cvmx_pip_bist_status_s cn68xx; 1206232812Sjmallett struct cvmx_pip_bist_status_cn61xx cn68xxp1; 1207232812Sjmallett struct cvmx_pip_bist_status_cn61xx cnf71xx; 1208215976Sjmallett}; 1209215976Sjmalletttypedef union cvmx_pip_bist_status cvmx_pip_bist_status_t; 1210215976Sjmallett 1211215976Sjmallett/** 1212232812Sjmallett * cvmx_pip_bsel_ext_cfg# 1213232812Sjmallett * 1214232812Sjmallett * PIP_BSEL_EXT_CFGX = Bit Select Extractor config register containing the 1215232812Sjmallett * tag, offset, and skip values to be used when using the corresponding extractor. 1216232812Sjmallett */ 1217232812Sjmallettunion cvmx_pip_bsel_ext_cfgx { 1218232812Sjmallett uint64_t u64; 1219232812Sjmallett struct cvmx_pip_bsel_ext_cfgx_s { 1220232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1221232812Sjmallett uint64_t reserved_56_63 : 8; 1222232812Sjmallett uint64_t upper_tag : 16; /**< Extra Tag bits to be added to tag field from table 1223232812Sjmallett Only included when PIP_PRT_TAG[INC_PRT]=0 1224232812Sjmallett WORD2[TAG<31:16>] */ 1225232812Sjmallett uint64_t tag : 8; /**< Extra Tag bits to be added to tag field from table 1226232812Sjmallett WORD2[TAG<15:8>] */ 1227232812Sjmallett uint64_t reserved_25_31 : 7; 1228232812Sjmallett uint64_t offset : 9; /**< Indicates offset to add to extractor mem adr 1229232812Sjmallett to get final address to the lookup table */ 1230232812Sjmallett uint64_t reserved_7_15 : 9; 1231232812Sjmallett uint64_t skip : 7; /**< Indicates number of bytes to skip from start of 1232232812Sjmallett packet 0-64 */ 1233232812Sjmallett#else 1234232812Sjmallett uint64_t skip : 7; 1235232812Sjmallett uint64_t reserved_7_15 : 9; 1236232812Sjmallett uint64_t offset : 9; 1237232812Sjmallett uint64_t reserved_25_31 : 7; 1238232812Sjmallett uint64_t tag : 8; 1239232812Sjmallett uint64_t upper_tag : 16; 1240232812Sjmallett uint64_t reserved_56_63 : 8; 1241232812Sjmallett#endif 1242232812Sjmallett } s; 1243232812Sjmallett struct cvmx_pip_bsel_ext_cfgx_s cn61xx; 1244232812Sjmallett struct cvmx_pip_bsel_ext_cfgx_s cn68xx; 1245232812Sjmallett struct cvmx_pip_bsel_ext_cfgx_s cnf71xx; 1246232812Sjmallett}; 1247232812Sjmalletttypedef union cvmx_pip_bsel_ext_cfgx cvmx_pip_bsel_ext_cfgx_t; 1248232812Sjmallett 1249232812Sjmallett/** 1250232812Sjmallett * cvmx_pip_bsel_ext_pos# 1251232812Sjmallett * 1252232812Sjmallett * PIP_BSEL_EXT_POSX = Bit Select Extractor config register containing the 8 1253232812Sjmallett * bit positions and valids to be used when using the corresponding extractor. 1254232812Sjmallett * 1255232812Sjmallett * Notes: 1256232812Sjmallett * Examples on bit positioning: 1257232812Sjmallett * the most-significant-bit of the 3rd byte ... PIP_BSEL_EXT_CFG*[SKIP]=1 POSn=15 (decimal) or 1258232812Sjmallett * PIP_BSEL_EXT_CFG*[SKIP]=0 POSn=23 (decimal) 1259232812Sjmallett * the least-significant-bit of the 5th byte ... PIP_BSEL_EXT_CFG*[SKIP]=4 POSn=0 1260232812Sjmallett * the second-least-significant bit of the 1st byte ... PIP_BSEL_EXT_CFG*[SKIP]=0 POSn=1 1261232812Sjmallett * 1262232812Sjmallett * POSn_VAL and POSn correspond to <n> in the resultant index into 1263232812Sjmallett * PIP_BSEL_TBL_ENT. When only x bits (0 < x < 7) are to be extracted, 1264232812Sjmallett * POS[7:x] should normally be clear. 1265232812Sjmallett */ 1266232812Sjmallettunion cvmx_pip_bsel_ext_posx { 1267232812Sjmallett uint64_t u64; 1268232812Sjmallett struct cvmx_pip_bsel_ext_posx_s { 1269232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1270232812Sjmallett uint64_t pos7_val : 1; /**< Valid bit for bit position 7 */ 1271232812Sjmallett uint64_t pos7 : 7; /**< Bit position for the 8th bit from 128 bit segment 1272232812Sjmallett of pkt that is defined by the SKIP field of 1273232812Sjmallett PIP_BSEL_EXT_CFG register. */ 1274232812Sjmallett uint64_t pos6_val : 1; /**< Valid bit for bit position 6 */ 1275232812Sjmallett uint64_t pos6 : 7; /**< Bit position for the 7th bit from 128 bit segment 1276232812Sjmallett of pkt that is defined by the SKIP field of 1277232812Sjmallett PIP_BSEL_EXT_CFG register. */ 1278232812Sjmallett uint64_t pos5_val : 1; /**< Valid bit for bit position 5 */ 1279232812Sjmallett uint64_t pos5 : 7; /**< Bit position for the 6th bit from 128 bit segment 1280232812Sjmallett of pkt that is defined by the SKIP field of 1281232812Sjmallett PIP_BSEL_EXT_CFG register. */ 1282232812Sjmallett uint64_t pos4_val : 1; /**< Valid bit for bit position 4 */ 1283232812Sjmallett uint64_t pos4 : 7; /**< Bit position for the 5th bit from 128 bit segment 1284232812Sjmallett of pkt that is defined by the SKIP field of 1285232812Sjmallett PIP_BSEL_EXT_CFG register. */ 1286232812Sjmallett uint64_t pos3_val : 1; /**< Valid bit for bit position 3 */ 1287232812Sjmallett uint64_t pos3 : 7; /**< Bit position for the 4th bit from 128 bit segment 1288232812Sjmallett of pkt that is defined by the SKIP field of 1289232812Sjmallett PIP_BSEL_EXT_CFG register. */ 1290232812Sjmallett uint64_t pos2_val : 1; /**< Valid bit for bit position 2 */ 1291232812Sjmallett uint64_t pos2 : 7; /**< Bit position for the 3rd bit from 128 bit segment 1292232812Sjmallett of pkt that is defined by the SKIP field of 1293232812Sjmallett PIP_BSEL_EXT_CFG register. */ 1294232812Sjmallett uint64_t pos1_val : 1; /**< Valid bit for bit position 1 */ 1295232812Sjmallett uint64_t pos1 : 7; /**< Bit position for the 2nd bit from 128 bit segment 1296232812Sjmallett of pkt that is defined by the SKIP field of 1297232812Sjmallett PIP_BSEL_EXT_CFG register. */ 1298232812Sjmallett uint64_t pos0_val : 1; /**< Valid bit for bit position 0 */ 1299232812Sjmallett uint64_t pos0 : 7; /**< Bit position for the 1st bit from 128 bit segment 1300232812Sjmallett of pkt that is defined by the SKIP field of 1301232812Sjmallett PIP_BSEL_EXT_CFG register. */ 1302232812Sjmallett#else 1303232812Sjmallett uint64_t pos0 : 7; 1304232812Sjmallett uint64_t pos0_val : 1; 1305232812Sjmallett uint64_t pos1 : 7; 1306232812Sjmallett uint64_t pos1_val : 1; 1307232812Sjmallett uint64_t pos2 : 7; 1308232812Sjmallett uint64_t pos2_val : 1; 1309232812Sjmallett uint64_t pos3 : 7; 1310232812Sjmallett uint64_t pos3_val : 1; 1311232812Sjmallett uint64_t pos4 : 7; 1312232812Sjmallett uint64_t pos4_val : 1; 1313232812Sjmallett uint64_t pos5 : 7; 1314232812Sjmallett uint64_t pos5_val : 1; 1315232812Sjmallett uint64_t pos6 : 7; 1316232812Sjmallett uint64_t pos6_val : 1; 1317232812Sjmallett uint64_t pos7 : 7; 1318232812Sjmallett uint64_t pos7_val : 1; 1319232812Sjmallett#endif 1320232812Sjmallett } s; 1321232812Sjmallett struct cvmx_pip_bsel_ext_posx_s cn61xx; 1322232812Sjmallett struct cvmx_pip_bsel_ext_posx_s cn68xx; 1323232812Sjmallett struct cvmx_pip_bsel_ext_posx_s cnf71xx; 1324232812Sjmallett}; 1325232812Sjmalletttypedef union cvmx_pip_bsel_ext_posx cvmx_pip_bsel_ext_posx_t; 1326232812Sjmallett 1327232812Sjmallett/** 1328232812Sjmallett * cvmx_pip_bsel_tbl_ent# 1329232812Sjmallett * 1330232812Sjmallett * PIP_BSEL_TBL_ENTX = Entry for the extractor table 1331232812Sjmallett * 1332232812Sjmallett */ 1333232812Sjmallettunion cvmx_pip_bsel_tbl_entx { 1334232812Sjmallett uint64_t u64; 1335232812Sjmallett struct cvmx_pip_bsel_tbl_entx_s { 1336232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1337232812Sjmallett uint64_t tag_en : 1; /**< Enables the use of the TAG field */ 1338232812Sjmallett uint64_t grp_en : 1; /**< Enables the use of the GRP field */ 1339232812Sjmallett uint64_t tt_en : 1; /**< Enables the use of the TT field */ 1340232812Sjmallett uint64_t qos_en : 1; /**< Enables the use of the QOS field */ 1341232812Sjmallett uint64_t reserved_40_59 : 20; 1342232812Sjmallett uint64_t tag : 8; /**< TAG bits to be used if TAG_EN is set */ 1343232812Sjmallett uint64_t reserved_22_31 : 10; 1344232812Sjmallett uint64_t grp : 6; /**< GRP field to be used if GRP_EN is set */ 1345232812Sjmallett uint64_t reserved_10_15 : 6; 1346232812Sjmallett uint64_t tt : 2; /**< TT field to be used if TT_EN is set */ 1347232812Sjmallett uint64_t reserved_3_7 : 5; 1348232812Sjmallett uint64_t qos : 3; /**< QOS field to be used if QOS_EN is set */ 1349232812Sjmallett#else 1350232812Sjmallett uint64_t qos : 3; 1351232812Sjmallett uint64_t reserved_3_7 : 5; 1352232812Sjmallett uint64_t tt : 2; 1353232812Sjmallett uint64_t reserved_10_15 : 6; 1354232812Sjmallett uint64_t grp : 6; 1355232812Sjmallett uint64_t reserved_22_31 : 10; 1356232812Sjmallett uint64_t tag : 8; 1357232812Sjmallett uint64_t reserved_40_59 : 20; 1358232812Sjmallett uint64_t qos_en : 1; 1359232812Sjmallett uint64_t tt_en : 1; 1360232812Sjmallett uint64_t grp_en : 1; 1361232812Sjmallett uint64_t tag_en : 1; 1362232812Sjmallett#endif 1363232812Sjmallett } s; 1364232812Sjmallett struct cvmx_pip_bsel_tbl_entx_cn61xx { 1365232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1366232812Sjmallett uint64_t tag_en : 1; /**< Enables the use of the TAG field */ 1367232812Sjmallett uint64_t grp_en : 1; /**< Enables the use of the GRP field */ 1368232812Sjmallett uint64_t tt_en : 1; /**< Enables the use of the TT field */ 1369232812Sjmallett uint64_t qos_en : 1; /**< Enables the use of the QOS field */ 1370232812Sjmallett uint64_t reserved_40_59 : 20; 1371232812Sjmallett uint64_t tag : 8; /**< TAG bits to be used if TAG_EN is set */ 1372232812Sjmallett uint64_t reserved_20_31 : 12; 1373232812Sjmallett uint64_t grp : 4; /**< GRP field to be used if GRP_EN is set */ 1374232812Sjmallett uint64_t reserved_10_15 : 6; 1375232812Sjmallett uint64_t tt : 2; /**< TT field to be used if TT_EN is set */ 1376232812Sjmallett uint64_t reserved_3_7 : 5; 1377232812Sjmallett uint64_t qos : 3; /**< QOS field to be used if QOS_EN is set */ 1378232812Sjmallett#else 1379232812Sjmallett uint64_t qos : 3; 1380232812Sjmallett uint64_t reserved_3_7 : 5; 1381232812Sjmallett uint64_t tt : 2; 1382232812Sjmallett uint64_t reserved_10_15 : 6; 1383232812Sjmallett uint64_t grp : 4; 1384232812Sjmallett uint64_t reserved_20_31 : 12; 1385232812Sjmallett uint64_t tag : 8; 1386232812Sjmallett uint64_t reserved_40_59 : 20; 1387232812Sjmallett uint64_t qos_en : 1; 1388232812Sjmallett uint64_t tt_en : 1; 1389232812Sjmallett uint64_t grp_en : 1; 1390232812Sjmallett uint64_t tag_en : 1; 1391232812Sjmallett#endif 1392232812Sjmallett } cn61xx; 1393232812Sjmallett struct cvmx_pip_bsel_tbl_entx_s cn68xx; 1394232812Sjmallett struct cvmx_pip_bsel_tbl_entx_cn61xx cnf71xx; 1395232812Sjmallett}; 1396232812Sjmalletttypedef union cvmx_pip_bsel_tbl_entx cvmx_pip_bsel_tbl_entx_t; 1397232812Sjmallett 1398232812Sjmallett/** 1399215976Sjmallett * cvmx_pip_clken 1400215976Sjmallett */ 1401232812Sjmallettunion cvmx_pip_clken { 1402215976Sjmallett uint64_t u64; 1403232812Sjmallett struct cvmx_pip_clken_s { 1404232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1405215976Sjmallett uint64_t reserved_1_63 : 63; 1406215976Sjmallett uint64_t clken : 1; /**< Controls the conditional clocking within PIP 1407215976Sjmallett 0=Allow HW to control the clocks 1408215976Sjmallett 1=Force the clocks to be always on */ 1409215976Sjmallett#else 1410215976Sjmallett uint64_t clken : 1; 1411215976Sjmallett uint64_t reserved_1_63 : 63; 1412215976Sjmallett#endif 1413215976Sjmallett } s; 1414232812Sjmallett struct cvmx_pip_clken_s cn61xx; 1415215976Sjmallett struct cvmx_pip_clken_s cn63xx; 1416215976Sjmallett struct cvmx_pip_clken_s cn63xxp1; 1417232812Sjmallett struct cvmx_pip_clken_s cn66xx; 1418232812Sjmallett struct cvmx_pip_clken_s cn68xx; 1419232812Sjmallett struct cvmx_pip_clken_s cn68xxp1; 1420232812Sjmallett struct cvmx_pip_clken_s cnf71xx; 1421215976Sjmallett}; 1422215976Sjmalletttypedef union cvmx_pip_clken cvmx_pip_clken_t; 1423215976Sjmallett 1424215976Sjmallett/** 1425215976Sjmallett * cvmx_pip_crc_ctl# 1426215976Sjmallett * 1427215976Sjmallett * PIP_CRC_CTL = PIP CRC Control Register 1428215976Sjmallett * 1429215976Sjmallett * Controls datapath reflection when calculating CRC 1430215976Sjmallett */ 1431232812Sjmallettunion cvmx_pip_crc_ctlx { 1432215976Sjmallett uint64_t u64; 1433232812Sjmallett struct cvmx_pip_crc_ctlx_s { 1434232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1435215976Sjmallett uint64_t reserved_2_63 : 62; 1436215976Sjmallett uint64_t invres : 1; /**< Invert the result */ 1437215976Sjmallett uint64_t reflect : 1; /**< Reflect the bits in each byte. 1438215976Sjmallett Byte order does not change. 1439215976Sjmallett - 0: CRC is calculated MSB to LSB 1440215976Sjmallett - 1: CRC is calculated LSB to MSB */ 1441215976Sjmallett#else 1442215976Sjmallett uint64_t reflect : 1; 1443215976Sjmallett uint64_t invres : 1; 1444215976Sjmallett uint64_t reserved_2_63 : 62; 1445215976Sjmallett#endif 1446215976Sjmallett } s; 1447215976Sjmallett struct cvmx_pip_crc_ctlx_s cn38xx; 1448215976Sjmallett struct cvmx_pip_crc_ctlx_s cn38xxp2; 1449215976Sjmallett struct cvmx_pip_crc_ctlx_s cn58xx; 1450215976Sjmallett struct cvmx_pip_crc_ctlx_s cn58xxp1; 1451215976Sjmallett}; 1452215976Sjmalletttypedef union cvmx_pip_crc_ctlx cvmx_pip_crc_ctlx_t; 1453215976Sjmallett 1454215976Sjmallett/** 1455215976Sjmallett * cvmx_pip_crc_iv# 1456215976Sjmallett * 1457215976Sjmallett * PIP_CRC_IV = PIP CRC IV Register 1458215976Sjmallett * 1459215976Sjmallett * Determines the IV used by the CRC algorithm 1460215976Sjmallett * 1461215976Sjmallett * Notes: 1462215976Sjmallett * * PIP_CRC_IV 1463215976Sjmallett * PIP_CRC_IV controls the initial state of the CRC algorithm. Octane can 1464215976Sjmallett * support a wide range of CRC algorithms and as such, the IV must be 1465215976Sjmallett * carefully constructed to meet the specific algorithm. The code below 1466215976Sjmallett * determines the value to program into Octane based on the algorthim's IV 1467215976Sjmallett * and width. In the case of Octane, the width should always be 32. 1468215976Sjmallett * 1469215976Sjmallett * PIP_CRC_IV0 sets the IV for ports 0-15 while PIP_CRC_IV1 sets the IV for 1470215976Sjmallett * ports 16-31. 1471215976Sjmallett * 1472215976Sjmallett * unsigned octane_crc_iv(unsigned algorithm_iv, unsigned poly, unsigned w) 1473215976Sjmallett * [ 1474215976Sjmallett * int i; 1475215976Sjmallett * int doit; 1476215976Sjmallett * unsigned int current_val = algorithm_iv; 1477215976Sjmallett * 1478215976Sjmallett * for(i = 0; i < w; i++) [ 1479215976Sjmallett * doit = current_val & 0x1; 1480215976Sjmallett * 1481215976Sjmallett * if(doit) current_val ^= poly; 1482215976Sjmallett * assert(!(current_val & 0x1)); 1483215976Sjmallett * 1484215976Sjmallett * current_val = (current_val >> 1) | (doit << (w-1)); 1485215976Sjmallett * ] 1486215976Sjmallett * 1487215976Sjmallett * return current_val; 1488215976Sjmallett * ] 1489215976Sjmallett */ 1490232812Sjmallettunion cvmx_pip_crc_ivx { 1491215976Sjmallett uint64_t u64; 1492232812Sjmallett struct cvmx_pip_crc_ivx_s { 1493232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1494215976Sjmallett uint64_t reserved_32_63 : 32; 1495215976Sjmallett uint64_t iv : 32; /**< IV used by the CRC algorithm. Default is FCS32. */ 1496215976Sjmallett#else 1497215976Sjmallett uint64_t iv : 32; 1498215976Sjmallett uint64_t reserved_32_63 : 32; 1499215976Sjmallett#endif 1500215976Sjmallett } s; 1501215976Sjmallett struct cvmx_pip_crc_ivx_s cn38xx; 1502215976Sjmallett struct cvmx_pip_crc_ivx_s cn38xxp2; 1503215976Sjmallett struct cvmx_pip_crc_ivx_s cn58xx; 1504215976Sjmallett struct cvmx_pip_crc_ivx_s cn58xxp1; 1505215976Sjmallett}; 1506215976Sjmalletttypedef union cvmx_pip_crc_ivx cvmx_pip_crc_ivx_t; 1507215976Sjmallett 1508215976Sjmallett/** 1509215976Sjmallett * cvmx_pip_dec_ipsec# 1510215976Sjmallett * 1511215976Sjmallett * PIP_DEC_IPSEC = UDP or TCP ports to watch for DEC IPSEC 1512215976Sjmallett * 1513215976Sjmallett * PIP sets the dec_ipsec based on TCP or UDP destination port. 1514215976Sjmallett */ 1515232812Sjmallettunion cvmx_pip_dec_ipsecx { 1516215976Sjmallett uint64_t u64; 1517232812Sjmallett struct cvmx_pip_dec_ipsecx_s { 1518232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1519215976Sjmallett uint64_t reserved_18_63 : 46; 1520215976Sjmallett uint64_t tcp : 1; /**< This DPRT should be used for TCP packets */ 1521215976Sjmallett uint64_t udp : 1; /**< This DPRT should be used for UDP packets */ 1522215976Sjmallett uint64_t dprt : 16; /**< UDP or TCP destination port to match on */ 1523215976Sjmallett#else 1524215976Sjmallett uint64_t dprt : 16; 1525215976Sjmallett uint64_t udp : 1; 1526215976Sjmallett uint64_t tcp : 1; 1527215976Sjmallett uint64_t reserved_18_63 : 46; 1528215976Sjmallett#endif 1529215976Sjmallett } s; 1530215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn30xx; 1531215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn31xx; 1532215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn38xx; 1533215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn38xxp2; 1534215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn50xx; 1535215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn52xx; 1536215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn52xxp1; 1537215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn56xx; 1538215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn56xxp1; 1539215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn58xx; 1540215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn58xxp1; 1541232812Sjmallett struct cvmx_pip_dec_ipsecx_s cn61xx; 1542215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn63xx; 1543215976Sjmallett struct cvmx_pip_dec_ipsecx_s cn63xxp1; 1544232812Sjmallett struct cvmx_pip_dec_ipsecx_s cn66xx; 1545232812Sjmallett struct cvmx_pip_dec_ipsecx_s cn68xx; 1546232812Sjmallett struct cvmx_pip_dec_ipsecx_s cn68xxp1; 1547232812Sjmallett struct cvmx_pip_dec_ipsecx_s cnf71xx; 1548215976Sjmallett}; 1549215976Sjmalletttypedef union cvmx_pip_dec_ipsecx cvmx_pip_dec_ipsecx_t; 1550215976Sjmallett 1551215976Sjmallett/** 1552215976Sjmallett * cvmx_pip_dsa_src_grp 1553215976Sjmallett */ 1554232812Sjmallettunion cvmx_pip_dsa_src_grp { 1555215976Sjmallett uint64_t u64; 1556232812Sjmallett struct cvmx_pip_dsa_src_grp_s { 1557232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1558215976Sjmallett uint64_t map15 : 4; /**< DSA Group Algorithm */ 1559215976Sjmallett uint64_t map14 : 4; /**< DSA Group Algorithm */ 1560215976Sjmallett uint64_t map13 : 4; /**< DSA Group Algorithm */ 1561215976Sjmallett uint64_t map12 : 4; /**< DSA Group Algorithm */ 1562215976Sjmallett uint64_t map11 : 4; /**< DSA Group Algorithm */ 1563215976Sjmallett uint64_t map10 : 4; /**< DSA Group Algorithm */ 1564215976Sjmallett uint64_t map9 : 4; /**< DSA Group Algorithm */ 1565215976Sjmallett uint64_t map8 : 4; /**< DSA Group Algorithm */ 1566215976Sjmallett uint64_t map7 : 4; /**< DSA Group Algorithm */ 1567215976Sjmallett uint64_t map6 : 4; /**< DSA Group Algorithm */ 1568215976Sjmallett uint64_t map5 : 4; /**< DSA Group Algorithm */ 1569215976Sjmallett uint64_t map4 : 4; /**< DSA Group Algorithm */ 1570215976Sjmallett uint64_t map3 : 4; /**< DSA Group Algorithm */ 1571215976Sjmallett uint64_t map2 : 4; /**< DSA Group Algorithm */ 1572215976Sjmallett uint64_t map1 : 4; /**< DSA Group Algorithm */ 1573215976Sjmallett uint64_t map0 : 4; /**< DSA Group Algorithm 1574215976Sjmallett Use the DSA source id to compute GRP */ 1575215976Sjmallett#else 1576215976Sjmallett uint64_t map0 : 4; 1577215976Sjmallett uint64_t map1 : 4; 1578215976Sjmallett uint64_t map2 : 4; 1579215976Sjmallett uint64_t map3 : 4; 1580215976Sjmallett uint64_t map4 : 4; 1581215976Sjmallett uint64_t map5 : 4; 1582215976Sjmallett uint64_t map6 : 4; 1583215976Sjmallett uint64_t map7 : 4; 1584215976Sjmallett uint64_t map8 : 4; 1585215976Sjmallett uint64_t map9 : 4; 1586215976Sjmallett uint64_t map10 : 4; 1587215976Sjmallett uint64_t map11 : 4; 1588215976Sjmallett uint64_t map12 : 4; 1589215976Sjmallett uint64_t map13 : 4; 1590215976Sjmallett uint64_t map14 : 4; 1591215976Sjmallett uint64_t map15 : 4; 1592215976Sjmallett#endif 1593215976Sjmallett } s; 1594215976Sjmallett struct cvmx_pip_dsa_src_grp_s cn52xx; 1595215976Sjmallett struct cvmx_pip_dsa_src_grp_s cn52xxp1; 1596215976Sjmallett struct cvmx_pip_dsa_src_grp_s cn56xx; 1597232812Sjmallett struct cvmx_pip_dsa_src_grp_s cn61xx; 1598215976Sjmallett struct cvmx_pip_dsa_src_grp_s cn63xx; 1599215976Sjmallett struct cvmx_pip_dsa_src_grp_s cn63xxp1; 1600232812Sjmallett struct cvmx_pip_dsa_src_grp_s cn66xx; 1601232812Sjmallett struct cvmx_pip_dsa_src_grp_s cn68xx; 1602232812Sjmallett struct cvmx_pip_dsa_src_grp_s cn68xxp1; 1603232812Sjmallett struct cvmx_pip_dsa_src_grp_s cnf71xx; 1604215976Sjmallett}; 1605215976Sjmalletttypedef union cvmx_pip_dsa_src_grp cvmx_pip_dsa_src_grp_t; 1606215976Sjmallett 1607215976Sjmallett/** 1608215976Sjmallett * cvmx_pip_dsa_vid_grp 1609215976Sjmallett */ 1610232812Sjmallettunion cvmx_pip_dsa_vid_grp { 1611215976Sjmallett uint64_t u64; 1612232812Sjmallett struct cvmx_pip_dsa_vid_grp_s { 1613232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1614215976Sjmallett uint64_t map15 : 4; /**< DSA Group Algorithm */ 1615215976Sjmallett uint64_t map14 : 4; /**< DSA Group Algorithm */ 1616215976Sjmallett uint64_t map13 : 4; /**< DSA Group Algorithm */ 1617215976Sjmallett uint64_t map12 : 4; /**< DSA Group Algorithm */ 1618215976Sjmallett uint64_t map11 : 4; /**< DSA Group Algorithm */ 1619215976Sjmallett uint64_t map10 : 4; /**< DSA Group Algorithm */ 1620215976Sjmallett uint64_t map9 : 4; /**< DSA Group Algorithm */ 1621215976Sjmallett uint64_t map8 : 4; /**< DSA Group Algorithm */ 1622215976Sjmallett uint64_t map7 : 4; /**< DSA Group Algorithm */ 1623215976Sjmallett uint64_t map6 : 4; /**< DSA Group Algorithm */ 1624215976Sjmallett uint64_t map5 : 4; /**< DSA Group Algorithm */ 1625215976Sjmallett uint64_t map4 : 4; /**< DSA Group Algorithm */ 1626215976Sjmallett uint64_t map3 : 4; /**< DSA Group Algorithm */ 1627215976Sjmallett uint64_t map2 : 4; /**< DSA Group Algorithm */ 1628215976Sjmallett uint64_t map1 : 4; /**< DSA Group Algorithm */ 1629215976Sjmallett uint64_t map0 : 4; /**< DSA Group Algorithm 1630215976Sjmallett Use the DSA source id to compute GRP */ 1631215976Sjmallett#else 1632215976Sjmallett uint64_t map0 : 4; 1633215976Sjmallett uint64_t map1 : 4; 1634215976Sjmallett uint64_t map2 : 4; 1635215976Sjmallett uint64_t map3 : 4; 1636215976Sjmallett uint64_t map4 : 4; 1637215976Sjmallett uint64_t map5 : 4; 1638215976Sjmallett uint64_t map6 : 4; 1639215976Sjmallett uint64_t map7 : 4; 1640215976Sjmallett uint64_t map8 : 4; 1641215976Sjmallett uint64_t map9 : 4; 1642215976Sjmallett uint64_t map10 : 4; 1643215976Sjmallett uint64_t map11 : 4; 1644215976Sjmallett uint64_t map12 : 4; 1645215976Sjmallett uint64_t map13 : 4; 1646215976Sjmallett uint64_t map14 : 4; 1647215976Sjmallett uint64_t map15 : 4; 1648215976Sjmallett#endif 1649215976Sjmallett } s; 1650215976Sjmallett struct cvmx_pip_dsa_vid_grp_s cn52xx; 1651215976Sjmallett struct cvmx_pip_dsa_vid_grp_s cn52xxp1; 1652215976Sjmallett struct cvmx_pip_dsa_vid_grp_s cn56xx; 1653232812Sjmallett struct cvmx_pip_dsa_vid_grp_s cn61xx; 1654215976Sjmallett struct cvmx_pip_dsa_vid_grp_s cn63xx; 1655215976Sjmallett struct cvmx_pip_dsa_vid_grp_s cn63xxp1; 1656232812Sjmallett struct cvmx_pip_dsa_vid_grp_s cn66xx; 1657232812Sjmallett struct cvmx_pip_dsa_vid_grp_s cn68xx; 1658232812Sjmallett struct cvmx_pip_dsa_vid_grp_s cn68xxp1; 1659232812Sjmallett struct cvmx_pip_dsa_vid_grp_s cnf71xx; 1660215976Sjmallett}; 1661215976Sjmalletttypedef union cvmx_pip_dsa_vid_grp cvmx_pip_dsa_vid_grp_t; 1662215976Sjmallett 1663215976Sjmallett/** 1664215976Sjmallett * cvmx_pip_frm_len_chk# 1665215976Sjmallett * 1666215976Sjmallett * Notes: 1667215976Sjmallett * PIP_FRM_LEN_CHK0 is used for packets on packet interface0, PCI, PCI RAW, and PKO loopback ports. 1668215976Sjmallett * PIP_FRM_LEN_CHK1 is unused. 1669215976Sjmallett */ 1670232812Sjmallettunion cvmx_pip_frm_len_chkx { 1671215976Sjmallett uint64_t u64; 1672232812Sjmallett struct cvmx_pip_frm_len_chkx_s { 1673232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1674215976Sjmallett uint64_t reserved_32_63 : 32; 1675215976Sjmallett uint64_t maxlen : 16; /**< Byte count for Max-sized frame check 1676215976Sjmallett PIP_PRT_CFGn[MAXERR_EN] enables the check for 1677215976Sjmallett port n. 1678215976Sjmallett If enabled, failing packets set the MAXERR 1679215976Sjmallett interrupt and work-queue entry WORD2[opcode] is 1680215976Sjmallett set to OVER_FCS (0x3, if packet has bad FCS) or 1681215976Sjmallett OVER_ERR (0x4, if packet has good FCS). 1682215976Sjmallett The effective MAXLEN used by HW is 1683215976Sjmallett PIP_PRT_CFG[DSA_EN] == 0, 1684215976Sjmallett PIP_FRM_LEN_CHK[MAXLEN] + 4*VV + 4*VS 1685215976Sjmallett PIP_PRT_CFG[DSA_EN] == 1, 1686215976Sjmallett PIP_FRM_LEN_CHK[MAXLEN] + PIP_PRT_CFG[SKIP]+4*VS 1687215976Sjmallett If PTP_MODE, the 8B timestamp is prepended to the 1688215976Sjmallett packet. MAXLEN should be increased by 8 to 1689215976Sjmallett compensate for the additional timestamp field. */ 1690215976Sjmallett uint64_t minlen : 16; /**< Byte count for Min-sized frame check 1691215976Sjmallett PIP_PRT_CFGn[MINERR_EN] enables the check for 1692215976Sjmallett port n. 1693215976Sjmallett If enabled, failing packets set the MINERR 1694215976Sjmallett interrupt and work-queue entry WORD2[opcode] is 1695215976Sjmallett set to UNDER_FCS (0x6, if packet has bad FCS) or 1696215976Sjmallett UNDER_ERR (0x8, if packet has good FCS). 1697215976Sjmallett If PTP_MODE, the 8B timestamp is prepended to the 1698215976Sjmallett packet. MINLEN should be increased by 8 to 1699215976Sjmallett compensate for the additional timestamp field. */ 1700215976Sjmallett#else 1701215976Sjmallett uint64_t minlen : 16; 1702215976Sjmallett uint64_t maxlen : 16; 1703215976Sjmallett uint64_t reserved_32_63 : 32; 1704215976Sjmallett#endif 1705215976Sjmallett } s; 1706215976Sjmallett struct cvmx_pip_frm_len_chkx_s cn50xx; 1707215976Sjmallett struct cvmx_pip_frm_len_chkx_s cn52xx; 1708215976Sjmallett struct cvmx_pip_frm_len_chkx_s cn52xxp1; 1709215976Sjmallett struct cvmx_pip_frm_len_chkx_s cn56xx; 1710215976Sjmallett struct cvmx_pip_frm_len_chkx_s cn56xxp1; 1711232812Sjmallett struct cvmx_pip_frm_len_chkx_s cn61xx; 1712215976Sjmallett struct cvmx_pip_frm_len_chkx_s cn63xx; 1713215976Sjmallett struct cvmx_pip_frm_len_chkx_s cn63xxp1; 1714232812Sjmallett struct cvmx_pip_frm_len_chkx_s cn66xx; 1715232812Sjmallett struct cvmx_pip_frm_len_chkx_s cn68xx; 1716232812Sjmallett struct cvmx_pip_frm_len_chkx_s cn68xxp1; 1717232812Sjmallett struct cvmx_pip_frm_len_chkx_s cnf71xx; 1718215976Sjmallett}; 1719215976Sjmalletttypedef union cvmx_pip_frm_len_chkx cvmx_pip_frm_len_chkx_t; 1720215976Sjmallett 1721215976Sjmallett/** 1722215976Sjmallett * cvmx_pip_gbl_cfg 1723215976Sjmallett * 1724215976Sjmallett * PIP_GBL_CFG = PIP's Global Config Register 1725215976Sjmallett * 1726215976Sjmallett * Global config information that applies to all ports. 1727215976Sjmallett * 1728215976Sjmallett * Notes: 1729215976Sjmallett * * IP6_UDP 1730215976Sjmallett * IPv4 allows optional UDP checksum by sending the all 0's patterns. IPv6 1731215976Sjmallett * outlaws this and the spec says to always check UDP checksum. This mode 1732215976Sjmallett * bit allows the user to treat IPv6 as IPv4, meaning that the all 0's 1733215976Sjmallett * pattern will cause a UDP checksum pass. 1734215976Sjmallett */ 1735232812Sjmallettunion cvmx_pip_gbl_cfg { 1736215976Sjmallett uint64_t u64; 1737232812Sjmallett struct cvmx_pip_gbl_cfg_s { 1738232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1739215976Sjmallett uint64_t reserved_19_63 : 45; 1740215976Sjmallett uint64_t tag_syn : 1; /**< Do not include src_crc for TCP/SYN&!ACK packets 1741215976Sjmallett 0 = include src_crc 1742215976Sjmallett 1 = tag hash is dst_crc for TCP/SYN&!ACK packets */ 1743215976Sjmallett uint64_t ip6_udp : 1; /**< IPv6/UDP checksum is not optional 1744215976Sjmallett 0 = Allow optional checksum code 1745215976Sjmallett 1 = Do not allow optional checksum code */ 1746215976Sjmallett uint64_t max_l2 : 1; /**< Config bit to choose the largest L2 frame size 1747215976Sjmallett Chooses the value of the L2 Type/Length field 1748215976Sjmallett to classify the frame as length. 1749215976Sjmallett 0 = 1500 / 0x5dc 1750215976Sjmallett 1 = 1535 / 0x5ff */ 1751215976Sjmallett uint64_t reserved_11_15 : 5; 1752215976Sjmallett uint64_t raw_shf : 3; /**< RAW Packet shift amount 1753215976Sjmallett Number of bytes to pad a RAW packet. */ 1754215976Sjmallett uint64_t reserved_3_7 : 5; 1755215976Sjmallett uint64_t nip_shf : 3; /**< Non-IP shift amount 1756215976Sjmallett Number of bytes to pad a packet that has been 1757215976Sjmallett classified as not IP. */ 1758215976Sjmallett#else 1759215976Sjmallett uint64_t nip_shf : 3; 1760215976Sjmallett uint64_t reserved_3_7 : 5; 1761215976Sjmallett uint64_t raw_shf : 3; 1762215976Sjmallett uint64_t reserved_11_15 : 5; 1763215976Sjmallett uint64_t max_l2 : 1; 1764215976Sjmallett uint64_t ip6_udp : 1; 1765215976Sjmallett uint64_t tag_syn : 1; 1766215976Sjmallett uint64_t reserved_19_63 : 45; 1767215976Sjmallett#endif 1768215976Sjmallett } s; 1769215976Sjmallett struct cvmx_pip_gbl_cfg_s cn30xx; 1770215976Sjmallett struct cvmx_pip_gbl_cfg_s cn31xx; 1771215976Sjmallett struct cvmx_pip_gbl_cfg_s cn38xx; 1772215976Sjmallett struct cvmx_pip_gbl_cfg_s cn38xxp2; 1773215976Sjmallett struct cvmx_pip_gbl_cfg_s cn50xx; 1774215976Sjmallett struct cvmx_pip_gbl_cfg_s cn52xx; 1775215976Sjmallett struct cvmx_pip_gbl_cfg_s cn52xxp1; 1776215976Sjmallett struct cvmx_pip_gbl_cfg_s cn56xx; 1777215976Sjmallett struct cvmx_pip_gbl_cfg_s cn56xxp1; 1778215976Sjmallett struct cvmx_pip_gbl_cfg_s cn58xx; 1779215976Sjmallett struct cvmx_pip_gbl_cfg_s cn58xxp1; 1780232812Sjmallett struct cvmx_pip_gbl_cfg_s cn61xx; 1781215976Sjmallett struct cvmx_pip_gbl_cfg_s cn63xx; 1782215976Sjmallett struct cvmx_pip_gbl_cfg_s cn63xxp1; 1783232812Sjmallett struct cvmx_pip_gbl_cfg_s cn66xx; 1784232812Sjmallett struct cvmx_pip_gbl_cfg_s cn68xx; 1785232812Sjmallett struct cvmx_pip_gbl_cfg_s cn68xxp1; 1786232812Sjmallett struct cvmx_pip_gbl_cfg_s cnf71xx; 1787215976Sjmallett}; 1788215976Sjmalletttypedef union cvmx_pip_gbl_cfg cvmx_pip_gbl_cfg_t; 1789215976Sjmallett 1790215976Sjmallett/** 1791215976Sjmallett * cvmx_pip_gbl_ctl 1792215976Sjmallett * 1793215976Sjmallett * PIP_GBL_CTL = PIP's Global Control Register 1794215976Sjmallett * 1795215976Sjmallett * Global control information. These are the global checker enables for 1796215976Sjmallett * IPv4/IPv6 and TCP/UDP parsing. The enables effect all ports. 1797215976Sjmallett * 1798215976Sjmallett * Notes: 1799215976Sjmallett * The following text describes the conditions in which each checker will 1800215976Sjmallett * assert and flag an exception. By disabling the checker, the exception will 1801215976Sjmallett * not be flagged and the packet will be parsed as best it can. Note, by 1802215976Sjmallett * disabling conditions, packets can be parsed incorrectly (.i.e. IP_MAL and 1803215976Sjmallett * L4_MAL could cause bits to be seen in the wrong place. IP_CHK and L4_CHK 1804215976Sjmallett * means that the packet was corrupted). 1805215976Sjmallett * 1806215976Sjmallett * * IP_CHK 1807215976Sjmallett * Indicates that an IPv4 packet contained an IPv4 header checksum 1808215976Sjmallett * violations. Only applies to packets classified as IPv4. 1809215976Sjmallett * 1810215976Sjmallett * * IP_MAL 1811215976Sjmallett * Indicates that the packet was malformed. Malformed packets are defined as 1812215976Sjmallett * packets that are not long enough to cover the IP header or not long enough 1813215976Sjmallett * to cover the length in the IP header. 1814215976Sjmallett * 1815215976Sjmallett * * IP_HOP 1816215976Sjmallett * Indicates that the IPv4 TTL field or IPv6 HOP field is zero. 1817215976Sjmallett * 1818215976Sjmallett * * IP4_OPTS 1819215976Sjmallett * Indicates the presence of IPv4 options. It is set when the length != 5. 1820215976Sjmallett * This only applies to packets classified as IPv4. 1821215976Sjmallett * 1822215976Sjmallett * * IP6_EEXT 1823215976Sjmallett * Indicate the presence of IPv6 early extension headers. These bits only 1824215976Sjmallett * apply to packets classified as IPv6. Bit 0 will flag early extensions 1825215976Sjmallett * when next_header is any one of the following... 1826215976Sjmallett * 1827215976Sjmallett * - hop-by-hop (0) 1828215976Sjmallett * - destination (60) 1829215976Sjmallett * - routing (43) 1830215976Sjmallett * 1831215976Sjmallett * Bit 1 will flag early extentions when next_header is NOT any of the 1832215976Sjmallett * following... 1833215976Sjmallett * 1834215976Sjmallett * - TCP (6) 1835215976Sjmallett * - UDP (17) 1836215976Sjmallett * - fragmentation (44) 1837215976Sjmallett * - ICMP (58) 1838215976Sjmallett * - IPSEC ESP (50) 1839215976Sjmallett * - IPSEC AH (51) 1840215976Sjmallett * - IPCOMP 1841215976Sjmallett * 1842215976Sjmallett * * L4_MAL 1843215976Sjmallett * Indicates that a TCP or UDP packet is not long enough to cover the TCP or 1844215976Sjmallett * UDP header. 1845215976Sjmallett * 1846215976Sjmallett * * L4_PRT 1847215976Sjmallett * Indicates that a TCP or UDP packet has an illegal port number - either the 1848215976Sjmallett * source or destination port is zero. 1849215976Sjmallett * 1850215976Sjmallett * * L4_CHK 1851215976Sjmallett * Indicates that a packet classified as either TCP or UDP contains an L4 1852215976Sjmallett * checksum failure 1853215976Sjmallett * 1854215976Sjmallett * * L4_LEN 1855215976Sjmallett * Indicates that the TCP or UDP length does not match the the IP length. 1856215976Sjmallett * 1857215976Sjmallett * * TCP_FLAG 1858215976Sjmallett * Indicates any of the following conditions... 1859215976Sjmallett * 1860215976Sjmallett * [URG, ACK, PSH, RST, SYN, FIN] : tcp_flag 1861215976Sjmallett * 6'b000001: (FIN only) 1862215976Sjmallett * 6'b000000: (0) 1863215976Sjmallett * 6'bxxx1x1: (RST+FIN+*) 1864215976Sjmallett * 6'b1xxx1x: (URG+SYN+*) 1865215976Sjmallett * 6'bxxx11x: (RST+SYN+*) 1866215976Sjmallett * 6'bxxxx11: (SYN+FIN+*) 1867215976Sjmallett */ 1868232812Sjmallettunion cvmx_pip_gbl_ctl { 1869215976Sjmallett uint64_t u64; 1870232812Sjmallett struct cvmx_pip_gbl_ctl_s { 1871232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1872232812Sjmallett uint64_t reserved_29_63 : 35; 1873232812Sjmallett uint64_t egrp_dis : 1; /**< PKT_INST_HDR extended group field disable 1874232812Sjmallett When set, HW will ignore the EGRP field of the 1875232812Sjmallett PKT_INST_HDR - bits 47:46. */ 1876215976Sjmallett uint64_t ihmsk_dis : 1; /**< Instruction Header Mask Disable 1877215976Sjmallett 0=Allow NTAG,NTT,NGRP,NQOS bits in the 1878215976Sjmallett instruction header to control which fields from 1879215976Sjmallett the instruction header are used for WQE WORD2. 1880215976Sjmallett 1=Ignore the NTAG,NTT,NGRP,NQOS bits in the 1881215976Sjmallett instruction header and act as if these fields 1882215976Sjmallett were zero. Thus always use the TAG,TT,GRP,QOS 1883215976Sjmallett (depending on the instruction header length) 1884215976Sjmallett from the instruction header for the WQE WORD2. */ 1885215976Sjmallett uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm 1886215976Sjmallett Use the DSA source id to compute GRP */ 1887215976Sjmallett uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm 1888215976Sjmallett Use the DSA source id to compute GRP when the 1889215976Sjmallett DSA tag command to TO_CPU */ 1890215976Sjmallett uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm 1891215976Sjmallett Use the DSA VLAN id to compute GRP */ 1892215976Sjmallett uint64_t reserved_21_23 : 3; 1893232812Sjmallett uint64_t ring_en : 1; /**< Enable DPI ring information in WQE */ 1894215976Sjmallett uint64_t reserved_17_19 : 3; 1895215976Sjmallett uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 1896232812Sjmallett Does not apply to DPI ports (32-35) 1897215976Sjmallett When using 2-byte instruction header words, 1898215976Sjmallett either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 1899215976Sjmallett uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking 1900215976Sjmallett 0=use the 1st (network order) VLAN 1901215976Sjmallett 1=use the 2nd (network order) VLAN */ 1902215976Sjmallett uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking 1903215976Sjmallett 0=use the 1st (network order) VLAN 1904215976Sjmallett 1=use the 2nd (network order) VLAN */ 1905215976Sjmallett uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 1906215976Sjmallett uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 1907215976Sjmallett uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 1908215976Sjmallett uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 1909215976Sjmallett uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 1910215976Sjmallett uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 1911215976Sjmallett uint64_t reserved_6_7 : 2; 1912215976Sjmallett uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 1913215976Sjmallett uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 1914215976Sjmallett uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 1915215976Sjmallett uint64_t ip_mal : 1; /**< Enable malformed check */ 1916215976Sjmallett uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 1917215976Sjmallett#else 1918215976Sjmallett uint64_t ip_chk : 1; 1919215976Sjmallett uint64_t ip_mal : 1; 1920215976Sjmallett uint64_t ip_hop : 1; 1921215976Sjmallett uint64_t ip4_opts : 1; 1922215976Sjmallett uint64_t ip6_eext : 2; 1923215976Sjmallett uint64_t reserved_6_7 : 2; 1924215976Sjmallett uint64_t l4_mal : 1; 1925215976Sjmallett uint64_t l4_prt : 1; 1926215976Sjmallett uint64_t l4_chk : 1; 1927215976Sjmallett uint64_t l4_len : 1; 1928215976Sjmallett uint64_t tcp_flag : 1; 1929215976Sjmallett uint64_t l2_mal : 1; 1930215976Sjmallett uint64_t vs_qos : 1; 1931215976Sjmallett uint64_t vs_wqe : 1; 1932215976Sjmallett uint64_t ignrs : 1; 1933215976Sjmallett uint64_t reserved_17_19 : 3; 1934215976Sjmallett uint64_t ring_en : 1; 1935215976Sjmallett uint64_t reserved_21_23 : 3; 1936215976Sjmallett uint64_t dsa_grp_sid : 1; 1937215976Sjmallett uint64_t dsa_grp_scmd : 1; 1938215976Sjmallett uint64_t dsa_grp_tvid : 1; 1939215976Sjmallett uint64_t ihmsk_dis : 1; 1940232812Sjmallett uint64_t egrp_dis : 1; 1941232812Sjmallett uint64_t reserved_29_63 : 35; 1942215976Sjmallett#endif 1943215976Sjmallett } s; 1944232812Sjmallett struct cvmx_pip_gbl_ctl_cn30xx { 1945232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1946215976Sjmallett uint64_t reserved_17_63 : 47; 1947215976Sjmallett uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 1948215976Sjmallett Only applies to the packet interface prts (0-31) 1949215976Sjmallett When using 2-byte instruction header words, 1950215976Sjmallett either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 1951215976Sjmallett uint64_t vs_wqe : 1; /**< Which VLAN CFI and ID to use when VLAN Stacking 1952215976Sjmallett 0=use the 1st (network order) VLAN 1953215976Sjmallett 1=use the 2nd (network order) VLAN */ 1954215976Sjmallett uint64_t vs_qos : 1; /**< Which VLAN priority to use when VLAN Stacking 1955215976Sjmallett 0=use the 1st (network order) VLAN 1956215976Sjmallett 1=use the 2nd (network order) VLAN */ 1957215976Sjmallett uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 1958215976Sjmallett uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 1959215976Sjmallett uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 1960215976Sjmallett uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 1961215976Sjmallett uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 1962215976Sjmallett uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 1963215976Sjmallett uint64_t reserved_6_7 : 2; 1964215976Sjmallett uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 1965215976Sjmallett uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 1966215976Sjmallett uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 1967215976Sjmallett uint64_t ip_mal : 1; /**< Enable malformed check */ 1968215976Sjmallett uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 1969215976Sjmallett#else 1970215976Sjmallett uint64_t ip_chk : 1; 1971215976Sjmallett uint64_t ip_mal : 1; 1972215976Sjmallett uint64_t ip_hop : 1; 1973215976Sjmallett uint64_t ip4_opts : 1; 1974215976Sjmallett uint64_t ip6_eext : 2; 1975215976Sjmallett uint64_t reserved_6_7 : 2; 1976215976Sjmallett uint64_t l4_mal : 1; 1977215976Sjmallett uint64_t l4_prt : 1; 1978215976Sjmallett uint64_t l4_chk : 1; 1979215976Sjmallett uint64_t l4_len : 1; 1980215976Sjmallett uint64_t tcp_flag : 1; 1981215976Sjmallett uint64_t l2_mal : 1; 1982215976Sjmallett uint64_t vs_qos : 1; 1983215976Sjmallett uint64_t vs_wqe : 1; 1984215976Sjmallett uint64_t ignrs : 1; 1985215976Sjmallett uint64_t reserved_17_63 : 47; 1986215976Sjmallett#endif 1987215976Sjmallett } cn30xx; 1988215976Sjmallett struct cvmx_pip_gbl_ctl_cn30xx cn31xx; 1989215976Sjmallett struct cvmx_pip_gbl_ctl_cn30xx cn38xx; 1990215976Sjmallett struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2; 1991215976Sjmallett struct cvmx_pip_gbl_ctl_cn30xx cn50xx; 1992232812Sjmallett struct cvmx_pip_gbl_ctl_cn52xx { 1993232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1994215976Sjmallett uint64_t reserved_27_63 : 37; 1995215976Sjmallett uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm 1996215976Sjmallett Use the DSA source id to compute GRP */ 1997215976Sjmallett uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm 1998215976Sjmallett Use the DSA source id to compute GRP when the 1999215976Sjmallett DSA tag command to TO_CPU */ 2000215976Sjmallett uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm 2001215976Sjmallett Use the DSA VLAN id to compute GRP */ 2002215976Sjmallett uint64_t reserved_21_23 : 3; 2003215976Sjmallett uint64_t ring_en : 1; /**< Enable PCIe ring information in WQE */ 2004215976Sjmallett uint64_t reserved_17_19 : 3; 2005215976Sjmallett uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 2006215976Sjmallett Does not apply to PCI ports (32-35) 2007215976Sjmallett When using 2-byte instruction header words, 2008215976Sjmallett either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 2009215976Sjmallett uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking 2010215976Sjmallett 0=use the 1st (network order) VLAN 2011215976Sjmallett 1=use the 2nd (network order) VLAN */ 2012215976Sjmallett uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking 2013215976Sjmallett 0=use the 1st (network order) VLAN 2014215976Sjmallett 1=use the 2nd (network order) VLAN */ 2015215976Sjmallett uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 2016215976Sjmallett uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 2017215976Sjmallett uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 2018215976Sjmallett uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 2019215976Sjmallett uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 2020215976Sjmallett uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 2021215976Sjmallett uint64_t reserved_6_7 : 2; 2022215976Sjmallett uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 2023215976Sjmallett uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 2024215976Sjmallett uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 2025215976Sjmallett uint64_t ip_mal : 1; /**< Enable malformed check */ 2026215976Sjmallett uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 2027215976Sjmallett#else 2028215976Sjmallett uint64_t ip_chk : 1; 2029215976Sjmallett uint64_t ip_mal : 1; 2030215976Sjmallett uint64_t ip_hop : 1; 2031215976Sjmallett uint64_t ip4_opts : 1; 2032215976Sjmallett uint64_t ip6_eext : 2; 2033215976Sjmallett uint64_t reserved_6_7 : 2; 2034215976Sjmallett uint64_t l4_mal : 1; 2035215976Sjmallett uint64_t l4_prt : 1; 2036215976Sjmallett uint64_t l4_chk : 1; 2037215976Sjmallett uint64_t l4_len : 1; 2038215976Sjmallett uint64_t tcp_flag : 1; 2039215976Sjmallett uint64_t l2_mal : 1; 2040215976Sjmallett uint64_t vs_qos : 1; 2041215976Sjmallett uint64_t vs_wqe : 1; 2042215976Sjmallett uint64_t ignrs : 1; 2043215976Sjmallett uint64_t reserved_17_19 : 3; 2044215976Sjmallett uint64_t ring_en : 1; 2045215976Sjmallett uint64_t reserved_21_23 : 3; 2046215976Sjmallett uint64_t dsa_grp_sid : 1; 2047215976Sjmallett uint64_t dsa_grp_scmd : 1; 2048215976Sjmallett uint64_t dsa_grp_tvid : 1; 2049215976Sjmallett uint64_t reserved_27_63 : 37; 2050215976Sjmallett#endif 2051215976Sjmallett } cn52xx; 2052215976Sjmallett struct cvmx_pip_gbl_ctl_cn52xx cn52xxp1; 2053215976Sjmallett struct cvmx_pip_gbl_ctl_cn52xx cn56xx; 2054232812Sjmallett struct cvmx_pip_gbl_ctl_cn56xxp1 { 2055232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2056215976Sjmallett uint64_t reserved_21_63 : 43; 2057215976Sjmallett uint64_t ring_en : 1; /**< Enable PCIe ring information in WQE */ 2058215976Sjmallett uint64_t reserved_17_19 : 3; 2059215976Sjmallett uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 2060215976Sjmallett Does not apply to PCI ports (32-35) 2061215976Sjmallett When using 2-byte instruction header words, 2062215976Sjmallett either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 2063215976Sjmallett uint64_t vs_wqe : 1; /**< Which VLAN CFI and ID to use when VLAN Stacking 2064215976Sjmallett 0=use the 1st (network order) VLAN 2065215976Sjmallett 1=use the 2nd (network order) VLAN */ 2066215976Sjmallett uint64_t vs_qos : 1; /**< Which VLAN priority to use when VLAN Stacking 2067215976Sjmallett 0=use the 1st (network order) VLAN 2068215976Sjmallett 1=use the 2nd (network order) VLAN */ 2069215976Sjmallett uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 2070215976Sjmallett uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 2071215976Sjmallett uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 2072215976Sjmallett uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 2073215976Sjmallett uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 2074215976Sjmallett uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 2075215976Sjmallett uint64_t reserved_6_7 : 2; 2076215976Sjmallett uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 2077215976Sjmallett uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 2078215976Sjmallett uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 2079215976Sjmallett uint64_t ip_mal : 1; /**< Enable malformed check */ 2080215976Sjmallett uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 2081215976Sjmallett#else 2082215976Sjmallett uint64_t ip_chk : 1; 2083215976Sjmallett uint64_t ip_mal : 1; 2084215976Sjmallett uint64_t ip_hop : 1; 2085215976Sjmallett uint64_t ip4_opts : 1; 2086215976Sjmallett uint64_t ip6_eext : 2; 2087215976Sjmallett uint64_t reserved_6_7 : 2; 2088215976Sjmallett uint64_t l4_mal : 1; 2089215976Sjmallett uint64_t l4_prt : 1; 2090215976Sjmallett uint64_t l4_chk : 1; 2091215976Sjmallett uint64_t l4_len : 1; 2092215976Sjmallett uint64_t tcp_flag : 1; 2093215976Sjmallett uint64_t l2_mal : 1; 2094215976Sjmallett uint64_t vs_qos : 1; 2095215976Sjmallett uint64_t vs_wqe : 1; 2096215976Sjmallett uint64_t ignrs : 1; 2097215976Sjmallett uint64_t reserved_17_19 : 3; 2098215976Sjmallett uint64_t ring_en : 1; 2099215976Sjmallett uint64_t reserved_21_63 : 43; 2100215976Sjmallett#endif 2101215976Sjmallett } cn56xxp1; 2102215976Sjmallett struct cvmx_pip_gbl_ctl_cn30xx cn58xx; 2103215976Sjmallett struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1; 2104232812Sjmallett struct cvmx_pip_gbl_ctl_cn61xx { 2105232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2106232812Sjmallett uint64_t reserved_28_63 : 36; 2107232812Sjmallett uint64_t ihmsk_dis : 1; /**< Instruction Header Mask Disable 2108232812Sjmallett 0=Allow NTAG,NTT,NGRP,NQOS bits in the 2109232812Sjmallett instruction header to control which fields from 2110232812Sjmallett the instruction header are used for WQE WORD2. 2111232812Sjmallett 1=Ignore the NTAG,NTT,NGRP,NQOS bits in the 2112232812Sjmallett instruction header and act as if these fields 2113232812Sjmallett were zero. Thus always use the TAG,TT,GRP,QOS 2114232812Sjmallett (depending on the instruction header length) 2115232812Sjmallett from the instruction header for the WQE WORD2. */ 2116232812Sjmallett uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm 2117232812Sjmallett Use the DSA source id to compute GRP */ 2118232812Sjmallett uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm 2119232812Sjmallett Use the DSA source id to compute GRP when the 2120232812Sjmallett DSA tag command to TO_CPU */ 2121232812Sjmallett uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm 2122232812Sjmallett Use the DSA VLAN id to compute GRP */ 2123232812Sjmallett uint64_t reserved_21_23 : 3; 2124232812Sjmallett uint64_t ring_en : 1; /**< Enable DPI ring information in WQE */ 2125232812Sjmallett uint64_t reserved_17_19 : 3; 2126232812Sjmallett uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 2127232812Sjmallett Does not apply to DPI ports (32-35) 2128232812Sjmallett When using 2-byte instruction header words, 2129232812Sjmallett either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 2130232812Sjmallett uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking 2131232812Sjmallett 0=use the 1st (network order) VLAN 2132232812Sjmallett 1=use the 2nd (network order) VLAN */ 2133232812Sjmallett uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking 2134232812Sjmallett 0=use the 1st (network order) VLAN 2135232812Sjmallett 1=use the 2nd (network order) VLAN */ 2136232812Sjmallett uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 2137232812Sjmallett uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 2138232812Sjmallett uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 2139232812Sjmallett uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 2140232812Sjmallett uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 2141232812Sjmallett uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 2142232812Sjmallett uint64_t reserved_6_7 : 2; 2143232812Sjmallett uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 2144232812Sjmallett uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 2145232812Sjmallett uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 2146232812Sjmallett uint64_t ip_mal : 1; /**< Enable malformed check */ 2147232812Sjmallett uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 2148232812Sjmallett#else 2149232812Sjmallett uint64_t ip_chk : 1; 2150232812Sjmallett uint64_t ip_mal : 1; 2151232812Sjmallett uint64_t ip_hop : 1; 2152232812Sjmallett uint64_t ip4_opts : 1; 2153232812Sjmallett uint64_t ip6_eext : 2; 2154232812Sjmallett uint64_t reserved_6_7 : 2; 2155232812Sjmallett uint64_t l4_mal : 1; 2156232812Sjmallett uint64_t l4_prt : 1; 2157232812Sjmallett uint64_t l4_chk : 1; 2158232812Sjmallett uint64_t l4_len : 1; 2159232812Sjmallett uint64_t tcp_flag : 1; 2160232812Sjmallett uint64_t l2_mal : 1; 2161232812Sjmallett uint64_t vs_qos : 1; 2162232812Sjmallett uint64_t vs_wqe : 1; 2163232812Sjmallett uint64_t ignrs : 1; 2164232812Sjmallett uint64_t reserved_17_19 : 3; 2165232812Sjmallett uint64_t ring_en : 1; 2166232812Sjmallett uint64_t reserved_21_23 : 3; 2167232812Sjmallett uint64_t dsa_grp_sid : 1; 2168232812Sjmallett uint64_t dsa_grp_scmd : 1; 2169232812Sjmallett uint64_t dsa_grp_tvid : 1; 2170232812Sjmallett uint64_t ihmsk_dis : 1; 2171232812Sjmallett uint64_t reserved_28_63 : 36; 2172232812Sjmallett#endif 2173232812Sjmallett } cn61xx; 2174232812Sjmallett struct cvmx_pip_gbl_ctl_cn61xx cn63xx; 2175232812Sjmallett struct cvmx_pip_gbl_ctl_cn61xx cn63xxp1; 2176232812Sjmallett struct cvmx_pip_gbl_ctl_cn61xx cn66xx; 2177232812Sjmallett struct cvmx_pip_gbl_ctl_cn68xx { 2178232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2179232812Sjmallett uint64_t reserved_29_63 : 35; 2180232812Sjmallett uint64_t egrp_dis : 1; /**< PKT_INST_HDR extended group field disable 2181232812Sjmallett When set, HW will ignore the EGRP field of the 2182232812Sjmallett PKT_INST_HDR - bits 47:46. */ 2183232812Sjmallett uint64_t ihmsk_dis : 1; /**< Instruction Header Mask Disable 2184232812Sjmallett 0=Allow NTAG,NTT,NGRP,NQOS bits in the 2185232812Sjmallett instruction header to control which fields from 2186232812Sjmallett the instruction header are used for WQE WORD2. 2187232812Sjmallett 1=Ignore the NTAG,NTT,NGRP,NQOS bits in the 2188232812Sjmallett instruction header and act as if these fields 2189232812Sjmallett were zero. Thus always use the TAG,TT,GRP,QOS 2190232812Sjmallett (depending on the instruction header length) 2191232812Sjmallett from the instruction header for the WQE WORD2. */ 2192232812Sjmallett uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm 2193232812Sjmallett Use the DSA source id to compute GRP */ 2194232812Sjmallett uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm 2195232812Sjmallett Use the DSA source id to compute GRP when the 2196232812Sjmallett DSA tag command to TO_CPU */ 2197232812Sjmallett uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm 2198232812Sjmallett Use the DSA VLAN id to compute GRP */ 2199232812Sjmallett uint64_t reserved_17_23 : 7; 2200232812Sjmallett uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 2201232812Sjmallett When using 2-byte instruction header words, 2202232812Sjmallett either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 2203232812Sjmallett uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking 2204232812Sjmallett 0=use the 1st (network order) VLAN 2205232812Sjmallett 1=use the 2nd (network order) VLAN */ 2206232812Sjmallett uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking 2207232812Sjmallett 0=use the 1st (network order) VLAN 2208232812Sjmallett 1=use the 2nd (network order) VLAN */ 2209232812Sjmallett uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 2210232812Sjmallett uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 2211232812Sjmallett uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 2212232812Sjmallett uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 2213232812Sjmallett uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 2214232812Sjmallett uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 2215232812Sjmallett uint64_t reserved_6_7 : 2; 2216232812Sjmallett uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 2217232812Sjmallett uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 2218232812Sjmallett uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 2219232812Sjmallett uint64_t ip_mal : 1; /**< Enable malformed check */ 2220232812Sjmallett uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 2221232812Sjmallett#else 2222232812Sjmallett uint64_t ip_chk : 1; 2223232812Sjmallett uint64_t ip_mal : 1; 2224232812Sjmallett uint64_t ip_hop : 1; 2225232812Sjmallett uint64_t ip4_opts : 1; 2226232812Sjmallett uint64_t ip6_eext : 2; 2227232812Sjmallett uint64_t reserved_6_7 : 2; 2228232812Sjmallett uint64_t l4_mal : 1; 2229232812Sjmallett uint64_t l4_prt : 1; 2230232812Sjmallett uint64_t l4_chk : 1; 2231232812Sjmallett uint64_t l4_len : 1; 2232232812Sjmallett uint64_t tcp_flag : 1; 2233232812Sjmallett uint64_t l2_mal : 1; 2234232812Sjmallett uint64_t vs_qos : 1; 2235232812Sjmallett uint64_t vs_wqe : 1; 2236232812Sjmallett uint64_t ignrs : 1; 2237232812Sjmallett uint64_t reserved_17_23 : 7; 2238232812Sjmallett uint64_t dsa_grp_sid : 1; 2239232812Sjmallett uint64_t dsa_grp_scmd : 1; 2240232812Sjmallett uint64_t dsa_grp_tvid : 1; 2241232812Sjmallett uint64_t ihmsk_dis : 1; 2242232812Sjmallett uint64_t egrp_dis : 1; 2243232812Sjmallett uint64_t reserved_29_63 : 35; 2244232812Sjmallett#endif 2245232812Sjmallett } cn68xx; 2246232812Sjmallett struct cvmx_pip_gbl_ctl_cn68xxp1 { 2247232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2248232812Sjmallett uint64_t reserved_28_63 : 36; 2249232812Sjmallett uint64_t ihmsk_dis : 1; /**< Instruction Header Mask Disable 2250232812Sjmallett 0=Allow NTAG,NTT,NGRP,NQOS bits in the 2251232812Sjmallett instruction header to control which fields from 2252232812Sjmallett the instruction header are used for WQE WORD2. 2253232812Sjmallett 1=Ignore the NTAG,NTT,NGRP,NQOS bits in the 2254232812Sjmallett instruction header and act as if these fields 2255232812Sjmallett were zero. Thus always use the TAG,TT,GRP,QOS 2256232812Sjmallett (depending on the instruction header length) 2257232812Sjmallett from the instruction header for the WQE WORD2. */ 2258232812Sjmallett uint64_t dsa_grp_tvid : 1; /**< DSA Group Algorithm 2259232812Sjmallett Use the DSA source id to compute GRP */ 2260232812Sjmallett uint64_t dsa_grp_scmd : 1; /**< DSA Group Algorithm 2261232812Sjmallett Use the DSA source id to compute GRP when the 2262232812Sjmallett DSA tag command to TO_CPU */ 2263232812Sjmallett uint64_t dsa_grp_sid : 1; /**< DSA Group Algorithm 2264232812Sjmallett Use the DSA VLAN id to compute GRP */ 2265232812Sjmallett uint64_t reserved_17_23 : 7; 2266232812Sjmallett uint64_t ignrs : 1; /**< Ignore the PKT_INST_HDR[RS] bit when set 2267232812Sjmallett When using 2-byte instruction header words, 2268232812Sjmallett either PIP_PRT_CFG[DYN_RS] or IGNRS should be set */ 2269232812Sjmallett uint64_t vs_wqe : 1; /**< Which DSA/VLAN CFI/ID to use when VLAN Stacking 2270232812Sjmallett 0=use the 1st (network order) VLAN 2271232812Sjmallett 1=use the 2nd (network order) VLAN */ 2272232812Sjmallett uint64_t vs_qos : 1; /**< Which DSA/VLAN priority to use when VLAN Stacking 2273232812Sjmallett 0=use the 1st (network order) VLAN 2274232812Sjmallett 1=use the 2nd (network order) VLAN */ 2275232812Sjmallett uint64_t l2_mal : 1; /**< Enable L2 malformed packet check */ 2276232812Sjmallett uint64_t tcp_flag : 1; /**< Enable TCP flags checks */ 2277232812Sjmallett uint64_t l4_len : 1; /**< Enable TCP/UDP length check */ 2278232812Sjmallett uint64_t l4_chk : 1; /**< Enable TCP/UDP checksum check */ 2279232812Sjmallett uint64_t l4_prt : 1; /**< Enable TCP/UDP illegal port check */ 2280232812Sjmallett uint64_t l4_mal : 1; /**< Enable TCP/UDP malformed packet check */ 2281232812Sjmallett uint64_t reserved_6_7 : 2; 2282232812Sjmallett uint64_t ip6_eext : 2; /**< Enable IPv6 early extension headers */ 2283232812Sjmallett uint64_t ip4_opts : 1; /**< Enable IPv4 options check */ 2284232812Sjmallett uint64_t ip_hop : 1; /**< Enable TTL (IPv4) / hop (IPv6) check */ 2285232812Sjmallett uint64_t ip_mal : 1; /**< Enable malformed check */ 2286232812Sjmallett uint64_t ip_chk : 1; /**< Enable IPv4 header checksum check */ 2287232812Sjmallett#else 2288232812Sjmallett uint64_t ip_chk : 1; 2289232812Sjmallett uint64_t ip_mal : 1; 2290232812Sjmallett uint64_t ip_hop : 1; 2291232812Sjmallett uint64_t ip4_opts : 1; 2292232812Sjmallett uint64_t ip6_eext : 2; 2293232812Sjmallett uint64_t reserved_6_7 : 2; 2294232812Sjmallett uint64_t l4_mal : 1; 2295232812Sjmallett uint64_t l4_prt : 1; 2296232812Sjmallett uint64_t l4_chk : 1; 2297232812Sjmallett uint64_t l4_len : 1; 2298232812Sjmallett uint64_t tcp_flag : 1; 2299232812Sjmallett uint64_t l2_mal : 1; 2300232812Sjmallett uint64_t vs_qos : 1; 2301232812Sjmallett uint64_t vs_wqe : 1; 2302232812Sjmallett uint64_t ignrs : 1; 2303232812Sjmallett uint64_t reserved_17_23 : 7; 2304232812Sjmallett uint64_t dsa_grp_sid : 1; 2305232812Sjmallett uint64_t dsa_grp_scmd : 1; 2306232812Sjmallett uint64_t dsa_grp_tvid : 1; 2307232812Sjmallett uint64_t ihmsk_dis : 1; 2308232812Sjmallett uint64_t reserved_28_63 : 36; 2309232812Sjmallett#endif 2310232812Sjmallett } cn68xxp1; 2311232812Sjmallett struct cvmx_pip_gbl_ctl_cn61xx cnf71xx; 2312215976Sjmallett}; 2313215976Sjmalletttypedef union cvmx_pip_gbl_ctl cvmx_pip_gbl_ctl_t; 2314215976Sjmallett 2315215976Sjmallett/** 2316215976Sjmallett * cvmx_pip_hg_pri_qos 2317215976Sjmallett * 2318215976Sjmallett * Notes: 2319215976Sjmallett * This register controls accesses to the HG_QOS_TABLE. To write an entry of 2320215976Sjmallett * the table, write PIP_HG_PRI_QOS with PRI=table address, QOS=priority level, 2321215976Sjmallett * UP_QOS=1. To read an entry of the table, write PIP_HG_PRI_QOS with 2322215976Sjmallett * PRI=table address, QOS=dont_carepriority level, UP_QOS=0 and then read 2323215976Sjmallett * PIP_HG_PRI_QOS. The table data will be in PIP_HG_PRI_QOS[QOS]. 2324215976Sjmallett */ 2325232812Sjmallettunion cvmx_pip_hg_pri_qos { 2326215976Sjmallett uint64_t u64; 2327232812Sjmallett struct cvmx_pip_hg_pri_qos_s { 2328232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2329215976Sjmallett uint64_t reserved_13_63 : 51; 2330215976Sjmallett uint64_t up_qos : 1; /**< When written to '1', updates the entry in the 2331215976Sjmallett HG_QOS_TABLE as specified by PRI to a value of 2332215976Sjmallett QOS as follows 2333215976Sjmallett HG_QOS_TABLE[PRI] = QOS */ 2334215976Sjmallett uint64_t reserved_11_11 : 1; 2335215976Sjmallett uint64_t qos : 3; /**< QOS Map level to priority */ 2336215976Sjmallett uint64_t reserved_6_7 : 2; 2337215976Sjmallett uint64_t pri : 6; /**< The priority level from HiGig header 2338215976Sjmallett HiGig/HiGig+ PRI = [1'b0, CNG[1:0], COS[2:0]] 2339215976Sjmallett HiGig2 PRI = [DP[1:0], TC[3:0]] */ 2340215976Sjmallett#else 2341215976Sjmallett uint64_t pri : 6; 2342215976Sjmallett uint64_t reserved_6_7 : 2; 2343215976Sjmallett uint64_t qos : 3; 2344215976Sjmallett uint64_t reserved_11_11 : 1; 2345215976Sjmallett uint64_t up_qos : 1; 2346215976Sjmallett uint64_t reserved_13_63 : 51; 2347215976Sjmallett#endif 2348215976Sjmallett } s; 2349215976Sjmallett struct cvmx_pip_hg_pri_qos_s cn52xx; 2350215976Sjmallett struct cvmx_pip_hg_pri_qos_s cn52xxp1; 2351215976Sjmallett struct cvmx_pip_hg_pri_qos_s cn56xx; 2352232812Sjmallett struct cvmx_pip_hg_pri_qos_s cn61xx; 2353215976Sjmallett struct cvmx_pip_hg_pri_qos_s cn63xx; 2354215976Sjmallett struct cvmx_pip_hg_pri_qos_s cn63xxp1; 2355232812Sjmallett struct cvmx_pip_hg_pri_qos_s cn66xx; 2356232812Sjmallett struct cvmx_pip_hg_pri_qos_s cnf71xx; 2357215976Sjmallett}; 2358215976Sjmalletttypedef union cvmx_pip_hg_pri_qos cvmx_pip_hg_pri_qos_t; 2359215976Sjmallett 2360215976Sjmallett/** 2361215976Sjmallett * cvmx_pip_int_en 2362215976Sjmallett * 2363215976Sjmallett * PIP_INT_EN = PIP's Interrupt Enable Register 2364215976Sjmallett * 2365215976Sjmallett * Determines if hardward should raise an interrupt to software 2366215976Sjmallett * when an exception event occurs. 2367215976Sjmallett */ 2368232812Sjmallettunion cvmx_pip_int_en { 2369215976Sjmallett uint64_t u64; 2370232812Sjmallett struct cvmx_pip_int_en_s { 2371232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2372215976Sjmallett uint64_t reserved_13_63 : 51; 2373215976Sjmallett uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 2374215976Sjmallett stripping in IPD is enable */ 2375215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2376215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2377215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2378215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2379215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2380215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 2381215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 2382215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2383215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2384215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure */ 2385215976Sjmallett uint64_t crcerr : 1; /**< PIP calculated bad CRC */ 2386215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2387215976Sjmallett#else 2388215976Sjmallett uint64_t pktdrp : 1; 2389215976Sjmallett uint64_t crcerr : 1; 2390215976Sjmallett uint64_t bckprs : 1; 2391215976Sjmallett uint64_t prtnxa : 1; 2392215976Sjmallett uint64_t badtag : 1; 2393215976Sjmallett uint64_t skprunt : 1; 2394215976Sjmallett uint64_t todoovr : 1; 2395215976Sjmallett uint64_t feperr : 1; 2396215976Sjmallett uint64_t beperr : 1; 2397215976Sjmallett uint64_t minerr : 1; 2398215976Sjmallett uint64_t maxerr : 1; 2399215976Sjmallett uint64_t lenerr : 1; 2400215976Sjmallett uint64_t punyerr : 1; 2401215976Sjmallett uint64_t reserved_13_63 : 51; 2402215976Sjmallett#endif 2403215976Sjmallett } s; 2404232812Sjmallett struct cvmx_pip_int_en_cn30xx { 2405232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2406215976Sjmallett uint64_t reserved_9_63 : 55; 2407215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2408215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2409215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow 2410215976Sjmallett (not used in O2P) */ 2411215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 2412215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2413215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2414215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure 2415215976Sjmallett (not used in O2P) */ 2416215976Sjmallett uint64_t crcerr : 1; /**< PIP calculated bad CRC 2417215976Sjmallett (not used in O2P) */ 2418215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2419215976Sjmallett#else 2420215976Sjmallett uint64_t pktdrp : 1; 2421215976Sjmallett uint64_t crcerr : 1; 2422215976Sjmallett uint64_t bckprs : 1; 2423215976Sjmallett uint64_t prtnxa : 1; 2424215976Sjmallett uint64_t badtag : 1; 2425215976Sjmallett uint64_t skprunt : 1; 2426215976Sjmallett uint64_t todoovr : 1; 2427215976Sjmallett uint64_t feperr : 1; 2428215976Sjmallett uint64_t beperr : 1; 2429215976Sjmallett uint64_t reserved_9_63 : 55; 2430215976Sjmallett#endif 2431215976Sjmallett } cn30xx; 2432215976Sjmallett struct cvmx_pip_int_en_cn30xx cn31xx; 2433215976Sjmallett struct cvmx_pip_int_en_cn30xx cn38xx; 2434215976Sjmallett struct cvmx_pip_int_en_cn30xx cn38xxp2; 2435232812Sjmallett struct cvmx_pip_int_en_cn50xx { 2436232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2437215976Sjmallett uint64_t reserved_12_63 : 52; 2438215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2439215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2440215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2441215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2442215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2443215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow */ 2444215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 2445215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2446215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2447215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure */ 2448215976Sjmallett uint64_t reserved_1_1 : 1; 2449215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2450215976Sjmallett#else 2451215976Sjmallett uint64_t pktdrp : 1; 2452215976Sjmallett uint64_t reserved_1_1 : 1; 2453215976Sjmallett uint64_t bckprs : 1; 2454215976Sjmallett uint64_t prtnxa : 1; 2455215976Sjmallett uint64_t badtag : 1; 2456215976Sjmallett uint64_t skprunt : 1; 2457215976Sjmallett uint64_t todoovr : 1; 2458215976Sjmallett uint64_t feperr : 1; 2459215976Sjmallett uint64_t beperr : 1; 2460215976Sjmallett uint64_t minerr : 1; 2461215976Sjmallett uint64_t maxerr : 1; 2462215976Sjmallett uint64_t lenerr : 1; 2463215976Sjmallett uint64_t reserved_12_63 : 52; 2464215976Sjmallett#endif 2465215976Sjmallett } cn50xx; 2466232812Sjmallett struct cvmx_pip_int_en_cn52xx { 2467232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2468215976Sjmallett uint64_t reserved_13_63 : 51; 2469215976Sjmallett uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 2470215976Sjmallett stripping in IPD is enable */ 2471215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2472215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2473215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2474215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2475215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2476215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow */ 2477215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 2478215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2479215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2480215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure */ 2481215976Sjmallett uint64_t reserved_1_1 : 1; 2482215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2483215976Sjmallett#else 2484215976Sjmallett uint64_t pktdrp : 1; 2485215976Sjmallett uint64_t reserved_1_1 : 1; 2486215976Sjmallett uint64_t bckprs : 1; 2487215976Sjmallett uint64_t prtnxa : 1; 2488215976Sjmallett uint64_t badtag : 1; 2489215976Sjmallett uint64_t skprunt : 1; 2490215976Sjmallett uint64_t todoovr : 1; 2491215976Sjmallett uint64_t feperr : 1; 2492215976Sjmallett uint64_t beperr : 1; 2493215976Sjmallett uint64_t minerr : 1; 2494215976Sjmallett uint64_t maxerr : 1; 2495215976Sjmallett uint64_t lenerr : 1; 2496215976Sjmallett uint64_t punyerr : 1; 2497215976Sjmallett uint64_t reserved_13_63 : 51; 2498215976Sjmallett#endif 2499215976Sjmallett } cn52xx; 2500215976Sjmallett struct cvmx_pip_int_en_cn52xx cn52xxp1; 2501215976Sjmallett struct cvmx_pip_int_en_s cn56xx; 2502232812Sjmallett struct cvmx_pip_int_en_cn56xxp1 { 2503232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2504215976Sjmallett uint64_t reserved_12_63 : 52; 2505215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2506215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2507215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2508215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2509215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2510215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 2511215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 2512215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2513215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2514215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure */ 2515215976Sjmallett uint64_t crcerr : 1; /**< PIP calculated bad CRC 2516215976Sjmallett (Disabled in 56xx) */ 2517215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2518215976Sjmallett#else 2519215976Sjmallett uint64_t pktdrp : 1; 2520215976Sjmallett uint64_t crcerr : 1; 2521215976Sjmallett uint64_t bckprs : 1; 2522215976Sjmallett uint64_t prtnxa : 1; 2523215976Sjmallett uint64_t badtag : 1; 2524215976Sjmallett uint64_t skprunt : 1; 2525215976Sjmallett uint64_t todoovr : 1; 2526215976Sjmallett uint64_t feperr : 1; 2527215976Sjmallett uint64_t beperr : 1; 2528215976Sjmallett uint64_t minerr : 1; 2529215976Sjmallett uint64_t maxerr : 1; 2530215976Sjmallett uint64_t lenerr : 1; 2531215976Sjmallett uint64_t reserved_12_63 : 52; 2532215976Sjmallett#endif 2533215976Sjmallett } cn56xxp1; 2534232812Sjmallett struct cvmx_pip_int_en_cn58xx { 2535232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2536215976Sjmallett uint64_t reserved_13_63 : 51; 2537215976Sjmallett uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 2538215976Sjmallett stripping in IPD is enable */ 2539215976Sjmallett uint64_t reserved_9_11 : 3; 2540215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2541215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2542215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 2543215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper */ 2544215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2545215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2546215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure */ 2547215976Sjmallett uint64_t crcerr : 1; /**< PIP calculated bad CRC */ 2548215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2549215976Sjmallett#else 2550215976Sjmallett uint64_t pktdrp : 1; 2551215976Sjmallett uint64_t crcerr : 1; 2552215976Sjmallett uint64_t bckprs : 1; 2553215976Sjmallett uint64_t prtnxa : 1; 2554215976Sjmallett uint64_t badtag : 1; 2555215976Sjmallett uint64_t skprunt : 1; 2556215976Sjmallett uint64_t todoovr : 1; 2557215976Sjmallett uint64_t feperr : 1; 2558215976Sjmallett uint64_t beperr : 1; 2559215976Sjmallett uint64_t reserved_9_11 : 3; 2560215976Sjmallett uint64_t punyerr : 1; 2561215976Sjmallett uint64_t reserved_13_63 : 51; 2562215976Sjmallett#endif 2563215976Sjmallett } cn58xx; 2564215976Sjmallett struct cvmx_pip_int_en_cn30xx cn58xxp1; 2565232812Sjmallett struct cvmx_pip_int_en_s cn61xx; 2566215976Sjmallett struct cvmx_pip_int_en_s cn63xx; 2567215976Sjmallett struct cvmx_pip_int_en_s cn63xxp1; 2568232812Sjmallett struct cvmx_pip_int_en_s cn66xx; 2569232812Sjmallett struct cvmx_pip_int_en_s cn68xx; 2570232812Sjmallett struct cvmx_pip_int_en_s cn68xxp1; 2571232812Sjmallett struct cvmx_pip_int_en_s cnf71xx; 2572215976Sjmallett}; 2573215976Sjmalletttypedef union cvmx_pip_int_en cvmx_pip_int_en_t; 2574215976Sjmallett 2575215976Sjmallett/** 2576215976Sjmallett * cvmx_pip_int_reg 2577215976Sjmallett * 2578215976Sjmallett * PIP_INT_REG = PIP's Interrupt Register 2579215976Sjmallett * 2580215976Sjmallett * Any exception event that occurs is captured in the PIP_INT_REG. 2581215976Sjmallett * PIP_INT_REG will set the exception bit regardless of the value 2582215976Sjmallett * of PIP_INT_EN. PIP_INT_EN only controls if an interrupt is 2583215976Sjmallett * raised to software. 2584215976Sjmallett * 2585215976Sjmallett * Notes: 2586215976Sjmallett * * TODOOVR 2587215976Sjmallett * The PIP Todo list stores packets that have been received and require work 2588215976Sjmallett * queue entry generation. PIP will normally assert backpressure when the 2589215976Sjmallett * list fills up such that any error is normally is result of a programming 2590215976Sjmallett * the PIP_BCK_PRS[HIWATER] incorrectly. PIP itself can handle 29M 2591215976Sjmallett * packets/sec X500MHz or 15Gbs X 64B packets. 2592215976Sjmallett * 2593215976Sjmallett * * SKPRUNT 2594215976Sjmallett * If a packet size is less then the amount programmed in the per port 2595215976Sjmallett * skippers, then there will be nothing to parse and the entire packet will 2596215976Sjmallett * basically be skipped over. This is probably not what the user desired, so 2597215976Sjmallett * there is an indication to software. 2598215976Sjmallett * 2599215976Sjmallett * * BADTAG 2600215976Sjmallett * A tag is considered bad when it is resued by a new packet before it was 2601215976Sjmallett * released by PIP. PIP considers a tag released by one of two methods. 2602215976Sjmallett * . QOS dropped so that it is released over the pip__ipd_release bus. 2603215976Sjmallett * . WorkQ entry is validated by the pip__ipd_done signal 2604215976Sjmallett * 2605215976Sjmallett * * PRTNXA 2606215976Sjmallett * If PIP receives a packet that is not in the valid port range, the port 2607215976Sjmallett * processed will be mapped into the valid port space (the mapping is 2608215976Sjmallett * currently unpredictable) and the PRTNXA bit will be set. PRTNXA will be 2609215976Sjmallett * set for packets received under the following conditions: 2610215976Sjmallett * 2611215976Sjmallett * * packet ports (ports 0-31) 2612215976Sjmallett * - GMX_INF_MODE[TYPE]==0 (SGMII), received port is 4-15 or 20-31 2613215976Sjmallett * - GMX_INF_MODE[TYPE]==1 (XAUI), received port is 1-15 or 17-31 2614215976Sjmallett * * upper ports (pci and loopback ports 32-63) 2615215976Sjmallett * - received port is 40-47 or 52-63 2616215976Sjmallett * 2617215976Sjmallett * * BCKPRS 2618215976Sjmallett * PIP can assert backpressure to the receive logic when the todo list 2619215976Sjmallett * exceeds a high-water mark (see PIP_BCK_PRS for more details). When this 2620215976Sjmallett * occurs, PIP can raise an interrupt to software. 2621215976Sjmallett * 2622215976Sjmallett * * CRCERR 2623215976Sjmallett * Octane can compute CRC in two places. Each RGMII port will compute its 2624215976Sjmallett * own CRC, but PIP can provide an additional check or check loopback or 2625215976Sjmallett * PCI ports. If PIP computes a bad CRC, then PIP will raise an interrupt. 2626215976Sjmallett * 2627215976Sjmallett * * PKTDRP 2628215976Sjmallett * PIP can drop packets based on QOS results received from IPD. If the QOS 2629215976Sjmallett * algorithm decides to drop a packet, PIP will assert an interrupt. 2630215976Sjmallett */ 2631232812Sjmallettunion cvmx_pip_int_reg { 2632215976Sjmallett uint64_t u64; 2633232812Sjmallett struct cvmx_pip_int_reg_s { 2634232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2635215976Sjmallett uint64_t reserved_13_63 : 51; 2636215976Sjmallett uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 2637215976Sjmallett stripping in IPD is enable */ 2638215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2639215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2640215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2641215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2642215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2643215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 2644215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper 2645215976Sjmallett This interrupt can occur with received PARTIAL 2646215976Sjmallett packets that are truncated to SKIP bytes or 2647215976Sjmallett smaller. */ 2648215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2649215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2650215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure */ 2651215976Sjmallett uint64_t crcerr : 1; /**< PIP calculated bad CRC */ 2652215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2653215976Sjmallett#else 2654215976Sjmallett uint64_t pktdrp : 1; 2655215976Sjmallett uint64_t crcerr : 1; 2656215976Sjmallett uint64_t bckprs : 1; 2657215976Sjmallett uint64_t prtnxa : 1; 2658215976Sjmallett uint64_t badtag : 1; 2659215976Sjmallett uint64_t skprunt : 1; 2660215976Sjmallett uint64_t todoovr : 1; 2661215976Sjmallett uint64_t feperr : 1; 2662215976Sjmallett uint64_t beperr : 1; 2663215976Sjmallett uint64_t minerr : 1; 2664215976Sjmallett uint64_t maxerr : 1; 2665215976Sjmallett uint64_t lenerr : 1; 2666215976Sjmallett uint64_t punyerr : 1; 2667215976Sjmallett uint64_t reserved_13_63 : 51; 2668215976Sjmallett#endif 2669215976Sjmallett } s; 2670232812Sjmallett struct cvmx_pip_int_reg_cn30xx { 2671232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2672215976Sjmallett uint64_t reserved_9_63 : 55; 2673215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2674215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2675215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow 2676215976Sjmallett (not used in O2P) */ 2677215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper 2678215976Sjmallett This interrupt can occur with received PARTIAL 2679215976Sjmallett packets that are truncated to SKIP bytes or 2680215976Sjmallett smaller. */ 2681215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2682215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2683215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure 2684215976Sjmallett (not used in O2P) */ 2685215976Sjmallett uint64_t crcerr : 1; /**< PIP calculated bad CRC 2686215976Sjmallett (not used in O2P) */ 2687215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2688215976Sjmallett#else 2689215976Sjmallett uint64_t pktdrp : 1; 2690215976Sjmallett uint64_t crcerr : 1; 2691215976Sjmallett uint64_t bckprs : 1; 2692215976Sjmallett uint64_t prtnxa : 1; 2693215976Sjmallett uint64_t badtag : 1; 2694215976Sjmallett uint64_t skprunt : 1; 2695215976Sjmallett uint64_t todoovr : 1; 2696215976Sjmallett uint64_t feperr : 1; 2697215976Sjmallett uint64_t beperr : 1; 2698215976Sjmallett uint64_t reserved_9_63 : 55; 2699215976Sjmallett#endif 2700215976Sjmallett } cn30xx; 2701215976Sjmallett struct cvmx_pip_int_reg_cn30xx cn31xx; 2702215976Sjmallett struct cvmx_pip_int_reg_cn30xx cn38xx; 2703215976Sjmallett struct cvmx_pip_int_reg_cn30xx cn38xxp2; 2704232812Sjmallett struct cvmx_pip_int_reg_cn50xx { 2705232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2706215976Sjmallett uint64_t reserved_12_63 : 52; 2707215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2708215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2709215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2710215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2711215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2712215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow */ 2713215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper 2714215976Sjmallett This interrupt can occur with received PARTIAL 2715215976Sjmallett packets that are truncated to SKIP bytes or 2716215976Sjmallett smaller. */ 2717215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2718215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2719215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure */ 2720215976Sjmallett uint64_t reserved_1_1 : 1; 2721215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2722215976Sjmallett#else 2723215976Sjmallett uint64_t pktdrp : 1; 2724215976Sjmallett uint64_t reserved_1_1 : 1; 2725215976Sjmallett uint64_t bckprs : 1; 2726215976Sjmallett uint64_t prtnxa : 1; 2727215976Sjmallett uint64_t badtag : 1; 2728215976Sjmallett uint64_t skprunt : 1; 2729215976Sjmallett uint64_t todoovr : 1; 2730215976Sjmallett uint64_t feperr : 1; 2731215976Sjmallett uint64_t beperr : 1; 2732215976Sjmallett uint64_t minerr : 1; 2733215976Sjmallett uint64_t maxerr : 1; 2734215976Sjmallett uint64_t lenerr : 1; 2735215976Sjmallett uint64_t reserved_12_63 : 52; 2736215976Sjmallett#endif 2737215976Sjmallett } cn50xx; 2738232812Sjmallett struct cvmx_pip_int_reg_cn52xx { 2739232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2740215976Sjmallett uint64_t reserved_13_63 : 51; 2741215976Sjmallett uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 2742215976Sjmallett stripping in IPD is enable */ 2743215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2744215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2745215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2746215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2747215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2748215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow */ 2749215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper 2750215976Sjmallett This interrupt can occur with received PARTIAL 2751215976Sjmallett packets that are truncated to SKIP bytes or 2752215976Sjmallett smaller. */ 2753215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2754215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2755215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure */ 2756215976Sjmallett uint64_t reserved_1_1 : 1; 2757215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2758215976Sjmallett#else 2759215976Sjmallett uint64_t pktdrp : 1; 2760215976Sjmallett uint64_t reserved_1_1 : 1; 2761215976Sjmallett uint64_t bckprs : 1; 2762215976Sjmallett uint64_t prtnxa : 1; 2763215976Sjmallett uint64_t badtag : 1; 2764215976Sjmallett uint64_t skprunt : 1; 2765215976Sjmallett uint64_t todoovr : 1; 2766215976Sjmallett uint64_t feperr : 1; 2767215976Sjmallett uint64_t beperr : 1; 2768215976Sjmallett uint64_t minerr : 1; 2769215976Sjmallett uint64_t maxerr : 1; 2770215976Sjmallett uint64_t lenerr : 1; 2771215976Sjmallett uint64_t punyerr : 1; 2772215976Sjmallett uint64_t reserved_13_63 : 51; 2773215976Sjmallett#endif 2774215976Sjmallett } cn52xx; 2775215976Sjmallett struct cvmx_pip_int_reg_cn52xx cn52xxp1; 2776215976Sjmallett struct cvmx_pip_int_reg_s cn56xx; 2777232812Sjmallett struct cvmx_pip_int_reg_cn56xxp1 { 2778232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2779215976Sjmallett uint64_t reserved_12_63 : 52; 2780215976Sjmallett uint64_t lenerr : 1; /**< Frame was received with length error */ 2781215976Sjmallett uint64_t maxerr : 1; /**< Frame was received with length > max_length */ 2782215976Sjmallett uint64_t minerr : 1; /**< Frame was received with length < min_length */ 2783215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2784215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2785215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 2786215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper 2787215976Sjmallett This interrupt can occur with received PARTIAL 2788215976Sjmallett packets that are truncated to SKIP bytes or 2789215976Sjmallett smaller. */ 2790215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2791215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2792215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure */ 2793215976Sjmallett uint64_t crcerr : 1; /**< PIP calculated bad CRC 2794215976Sjmallett (Disabled in 56xx) */ 2795215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2796215976Sjmallett#else 2797215976Sjmallett uint64_t pktdrp : 1; 2798215976Sjmallett uint64_t crcerr : 1; 2799215976Sjmallett uint64_t bckprs : 1; 2800215976Sjmallett uint64_t prtnxa : 1; 2801215976Sjmallett uint64_t badtag : 1; 2802215976Sjmallett uint64_t skprunt : 1; 2803215976Sjmallett uint64_t todoovr : 1; 2804215976Sjmallett uint64_t feperr : 1; 2805215976Sjmallett uint64_t beperr : 1; 2806215976Sjmallett uint64_t minerr : 1; 2807215976Sjmallett uint64_t maxerr : 1; 2808215976Sjmallett uint64_t lenerr : 1; 2809215976Sjmallett uint64_t reserved_12_63 : 52; 2810215976Sjmallett#endif 2811215976Sjmallett } cn56xxp1; 2812232812Sjmallett struct cvmx_pip_int_reg_cn58xx { 2813232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2814215976Sjmallett uint64_t reserved_13_63 : 51; 2815215976Sjmallett uint64_t punyerr : 1; /**< Frame was received with length <=4B when CRC 2816215976Sjmallett stripping in IPD is enable */ 2817215976Sjmallett uint64_t reserved_9_11 : 3; 2818215976Sjmallett uint64_t beperr : 1; /**< Parity Error in back end memory */ 2819215976Sjmallett uint64_t feperr : 1; /**< Parity Error in front end memory */ 2820215976Sjmallett uint64_t todoovr : 1; /**< Todo list overflow (see PIP_BCK_PRS[HIWATER]) */ 2821215976Sjmallett uint64_t skprunt : 1; /**< Packet was engulfed by skipper 2822215976Sjmallett This interrupt can occur with received PARTIAL 2823215976Sjmallett packets that are truncated to SKIP bytes or 2824215976Sjmallett smaller. */ 2825215976Sjmallett uint64_t badtag : 1; /**< A bad tag was sent from IPD */ 2826215976Sjmallett uint64_t prtnxa : 1; /**< Non-existent port */ 2827215976Sjmallett uint64_t bckprs : 1; /**< PIP asserted backpressure */ 2828215976Sjmallett uint64_t crcerr : 1; /**< PIP calculated bad CRC */ 2829215976Sjmallett uint64_t pktdrp : 1; /**< Packet Dropped due to QOS */ 2830215976Sjmallett#else 2831215976Sjmallett uint64_t pktdrp : 1; 2832215976Sjmallett uint64_t crcerr : 1; 2833215976Sjmallett uint64_t bckprs : 1; 2834215976Sjmallett uint64_t prtnxa : 1; 2835215976Sjmallett uint64_t badtag : 1; 2836215976Sjmallett uint64_t skprunt : 1; 2837215976Sjmallett uint64_t todoovr : 1; 2838215976Sjmallett uint64_t feperr : 1; 2839215976Sjmallett uint64_t beperr : 1; 2840215976Sjmallett uint64_t reserved_9_11 : 3; 2841215976Sjmallett uint64_t punyerr : 1; 2842215976Sjmallett uint64_t reserved_13_63 : 51; 2843215976Sjmallett#endif 2844215976Sjmallett } cn58xx; 2845215976Sjmallett struct cvmx_pip_int_reg_cn30xx cn58xxp1; 2846232812Sjmallett struct cvmx_pip_int_reg_s cn61xx; 2847215976Sjmallett struct cvmx_pip_int_reg_s cn63xx; 2848215976Sjmallett struct cvmx_pip_int_reg_s cn63xxp1; 2849232812Sjmallett struct cvmx_pip_int_reg_s cn66xx; 2850232812Sjmallett struct cvmx_pip_int_reg_s cn68xx; 2851232812Sjmallett struct cvmx_pip_int_reg_s cn68xxp1; 2852232812Sjmallett struct cvmx_pip_int_reg_s cnf71xx; 2853215976Sjmallett}; 2854215976Sjmalletttypedef union cvmx_pip_int_reg cvmx_pip_int_reg_t; 2855215976Sjmallett 2856215976Sjmallett/** 2857215976Sjmallett * cvmx_pip_ip_offset 2858215976Sjmallett * 2859215976Sjmallett * PIP_IP_OFFSET = Location of the IP in the workQ entry 2860215976Sjmallett * 2861215976Sjmallett * An 8-byte offset to find the start of the IP header in the data portion of IP workQ entires 2862215976Sjmallett * 2863215976Sjmallett * Notes: 2864215976Sjmallett * In normal configurations, OFFSET must be set in the 0..4 range to allow the 2865215976Sjmallett * entire IP and TCP/UDP headers to be buffered in HW and calculate the L4 2866215976Sjmallett * checksum for TCP/UDP packets. 2867215976Sjmallett * 2868215976Sjmallett * The MAX value of OFFSET is determined by the the types of packets that can 2869215976Sjmallett * be sent to PIP as follows... 2870215976Sjmallett * 2871215976Sjmallett * Packet Type MAX OFFSET 2872215976Sjmallett * IPv4/TCP/UDP 7 2873215976Sjmallett * IPv6/TCP/UDP 5 2874215976Sjmallett * IPv6/without L4 parsing 6 2875215976Sjmallett * 2876215976Sjmallett * If the L4 can be ignored, then the MAX OFFSET for IPv6 packets can increase 2877215976Sjmallett * to 6. Here are the following programming restrictions for IPv6 packets and 2878215976Sjmallett * OFFSET==6: 2879215976Sjmallett * 2880215976Sjmallett * . PIP_GBL_CTL[TCP_FLAG] == 0 2881215976Sjmallett * . PIP_GBL_CTL[L4_LEN] == 0 2882215976Sjmallett * . PIP_GBL_CTL[L4_CHK] == 0 2883215976Sjmallett * . PIP_GBL_CTL[L4_PRT] == 0 2884215976Sjmallett * . PIP_GBL_CTL[L4_MAL] == 0 2885215976Sjmallett * . PIP_DEC_IPSEC[TCP] == 0 2886215976Sjmallett * . PIP_DEC_IPSEC[UDP] == 0 2887215976Sjmallett * . PIP_PRT_TAG[IP6_DPRT] == 0 2888215976Sjmallett * . PIP_PRT_TAG[IP6_SPRT] == 0 2889215976Sjmallett * . PIP_PRT_TAG[TCP6_TAG] == 0 2890215976Sjmallett * . PIP_GBL_CFG[TAG_SYN] == 0 2891215976Sjmallett */ 2892232812Sjmallettunion cvmx_pip_ip_offset { 2893215976Sjmallett uint64_t u64; 2894232812Sjmallett struct cvmx_pip_ip_offset_s { 2895232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2896215976Sjmallett uint64_t reserved_3_63 : 61; 2897215976Sjmallett uint64_t offset : 3; /**< Number of 8B ticks to include in workQ entry 2898215976Sjmallett prior to IP data 2899215976Sjmallett - 0: 0 Bytes / IP start at WORD4 of workQ entry 2900215976Sjmallett - 1: 8 Bytes / IP start at WORD5 of workQ entry 2901215976Sjmallett - 2: 16 Bytes / IP start at WORD6 of workQ entry 2902215976Sjmallett - 3: 24 Bytes / IP start at WORD7 of workQ entry 2903215976Sjmallett - 4: 32 Bytes / IP start at WORD8 of workQ entry 2904215976Sjmallett - 5: 40 Bytes / IP start at WORD9 of workQ entry 2905215976Sjmallett - 6: 48 Bytes / IP start at WORD10 of workQ entry 2906215976Sjmallett - 7: 56 Bytes / IP start at WORD11 of workQ entry */ 2907215976Sjmallett#else 2908215976Sjmallett uint64_t offset : 3; 2909215976Sjmallett uint64_t reserved_3_63 : 61; 2910215976Sjmallett#endif 2911215976Sjmallett } s; 2912215976Sjmallett struct cvmx_pip_ip_offset_s cn30xx; 2913215976Sjmallett struct cvmx_pip_ip_offset_s cn31xx; 2914215976Sjmallett struct cvmx_pip_ip_offset_s cn38xx; 2915215976Sjmallett struct cvmx_pip_ip_offset_s cn38xxp2; 2916215976Sjmallett struct cvmx_pip_ip_offset_s cn50xx; 2917215976Sjmallett struct cvmx_pip_ip_offset_s cn52xx; 2918215976Sjmallett struct cvmx_pip_ip_offset_s cn52xxp1; 2919215976Sjmallett struct cvmx_pip_ip_offset_s cn56xx; 2920215976Sjmallett struct cvmx_pip_ip_offset_s cn56xxp1; 2921215976Sjmallett struct cvmx_pip_ip_offset_s cn58xx; 2922215976Sjmallett struct cvmx_pip_ip_offset_s cn58xxp1; 2923232812Sjmallett struct cvmx_pip_ip_offset_s cn61xx; 2924215976Sjmallett struct cvmx_pip_ip_offset_s cn63xx; 2925215976Sjmallett struct cvmx_pip_ip_offset_s cn63xxp1; 2926232812Sjmallett struct cvmx_pip_ip_offset_s cn66xx; 2927232812Sjmallett struct cvmx_pip_ip_offset_s cn68xx; 2928232812Sjmallett struct cvmx_pip_ip_offset_s cn68xxp1; 2929232812Sjmallett struct cvmx_pip_ip_offset_s cnf71xx; 2930215976Sjmallett}; 2931215976Sjmalletttypedef union cvmx_pip_ip_offset cvmx_pip_ip_offset_t; 2932215976Sjmallett 2933215976Sjmallett/** 2934232812Sjmallett * cvmx_pip_pri_tbl# 2935232812Sjmallett * 2936232812Sjmallett * Notes: 2937232812Sjmallett * The priority level from HiGig header is as follows 2938232812Sjmallett * 2939232812Sjmallett * HiGig/HiGig+ PRI = [1'b0, CNG[1:0], COS[2:0]] 2940232812Sjmallett * HiGig2 PRI = [DP[1:0], TC[3:0]] 2941232812Sjmallett * 2942232812Sjmallett * DSA PRI = WORD0[15:13] 2943232812Sjmallett * 2944232812Sjmallett * VLAN PRI = VLAN[15:13] 2945232812Sjmallett * 2946232812Sjmallett * DIFFSERV = IP.TOS/CLASS<7:2> 2947232812Sjmallett */ 2948232812Sjmallettunion cvmx_pip_pri_tblx { 2949232812Sjmallett uint64_t u64; 2950232812Sjmallett struct cvmx_pip_pri_tblx_s { 2951232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2952232812Sjmallett uint64_t diff2_padd : 8; /**< Diffserv port-add */ 2953232812Sjmallett uint64_t hg2_padd : 8; /**< HG_PRI port-add */ 2954232812Sjmallett uint64_t vlan2_padd : 8; /**< VLAN port-add */ 2955232812Sjmallett uint64_t reserved_38_39 : 2; 2956232812Sjmallett uint64_t diff2_bpid : 6; /**< Diffserv backpressure ID */ 2957232812Sjmallett uint64_t reserved_30_31 : 2; 2958232812Sjmallett uint64_t hg2_bpid : 6; /**< HG_PRI backpressure ID */ 2959232812Sjmallett uint64_t reserved_22_23 : 2; 2960232812Sjmallett uint64_t vlan2_bpid : 6; /**< VLAN backpressure ID */ 2961232812Sjmallett uint64_t reserved_11_15 : 5; 2962232812Sjmallett uint64_t diff2_qos : 3; /**< Diffserv QOS level */ 2963232812Sjmallett uint64_t reserved_7_7 : 1; 2964232812Sjmallett uint64_t hg2_qos : 3; /**< HG_PRI QOS level */ 2965232812Sjmallett uint64_t reserved_3_3 : 1; 2966232812Sjmallett uint64_t vlan2_qos : 3; /**< VLAN QOS level */ 2967232812Sjmallett#else 2968232812Sjmallett uint64_t vlan2_qos : 3; 2969232812Sjmallett uint64_t reserved_3_3 : 1; 2970232812Sjmallett uint64_t hg2_qos : 3; 2971232812Sjmallett uint64_t reserved_7_7 : 1; 2972232812Sjmallett uint64_t diff2_qos : 3; 2973232812Sjmallett uint64_t reserved_11_15 : 5; 2974232812Sjmallett uint64_t vlan2_bpid : 6; 2975232812Sjmallett uint64_t reserved_22_23 : 2; 2976232812Sjmallett uint64_t hg2_bpid : 6; 2977232812Sjmallett uint64_t reserved_30_31 : 2; 2978232812Sjmallett uint64_t diff2_bpid : 6; 2979232812Sjmallett uint64_t reserved_38_39 : 2; 2980232812Sjmallett uint64_t vlan2_padd : 8; 2981232812Sjmallett uint64_t hg2_padd : 8; 2982232812Sjmallett uint64_t diff2_padd : 8; 2983232812Sjmallett#endif 2984232812Sjmallett } s; 2985232812Sjmallett struct cvmx_pip_pri_tblx_s cn68xx; 2986232812Sjmallett struct cvmx_pip_pri_tblx_s cn68xxp1; 2987232812Sjmallett}; 2988232812Sjmalletttypedef union cvmx_pip_pri_tblx cvmx_pip_pri_tblx_t; 2989232812Sjmallett 2990232812Sjmallett/** 2991215976Sjmallett * cvmx_pip_prt_cfg# 2992215976Sjmallett * 2993215976Sjmallett * PIP_PRT_CFGX = Per port config information 2994215976Sjmallett * 2995215976Sjmallett */ 2996232812Sjmallettunion cvmx_pip_prt_cfgx { 2997215976Sjmallett uint64_t u64; 2998232812Sjmallett struct cvmx_pip_prt_cfgx_s { 2999232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3000232812Sjmallett uint64_t reserved_55_63 : 9; 3001232812Sjmallett uint64_t ih_pri : 1; /**< Use the PRI/QOS field in the instruction header 3002232812Sjmallett as the PRIORITY in BPID calculations. */ 3003232812Sjmallett uint64_t len_chk_sel : 1; /**< Selects which PIP_FRM_LEN_CHK register is used 3004232812Sjmallett for this port-kind for MINERR and MAXERR checks. 3005232812Sjmallett LEN_CHK_SEL=0, use PIP_FRM_LEN_CHK0 3006232812Sjmallett LEN_CHK_SEL=1, use PIP_FRM_LEN_CHK1 */ 3007215976Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for pkts with 3008215976Sjmallett padding in the client data */ 3009215976Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for DSA/VLAN 3010215976Sjmallett pkts */ 3011215976Sjmallett uint64_t lenerr_en : 1; /**< L2 length error check enable 3012215976Sjmallett Frame was received with length error 3013215976Sjmallett Typically, this check will not be enabled for 3014232812Sjmallett incoming packets on the DPI and sRIO ports 3015232812Sjmallett because the CRC bytes may not normally be 3016232812Sjmallett present. */ 3017215976Sjmallett uint64_t maxerr_en : 1; /**< Max frame error check enable 3018232812Sjmallett Frame was received with length > max_length 3019232812Sjmallett max_length is defined by PIP_FRM_LEN_CHK[MAXLEN] */ 3020215976Sjmallett uint64_t minerr_en : 1; /**< Min frame error check enable 3021215976Sjmallett Frame was received with length < min_length 3022215976Sjmallett Typically, this check will not be enabled for 3023232812Sjmallett incoming packets on the DPI and sRIO ports 3024232812Sjmallett because the CRC bytes may not normally be 3025232812Sjmallett present. 3026232812Sjmallett min_length is defined by PIP_FRM_LEN_CHK[MINLEN] */ 3027215976Sjmallett uint64_t grp_wat_47 : 4; /**< GRP Watcher enable 3028215976Sjmallett (Watchers 4-7) */ 3029215976Sjmallett uint64_t qos_wat_47 : 4; /**< QOS Watcher enable 3030215976Sjmallett (Watchers 4-7) */ 3031215976Sjmallett uint64_t reserved_37_39 : 3; 3032215976Sjmallett uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 3033215976Sjmallett Normally, IPD will never drop a packet that PIP 3034215976Sjmallett indicates is RAW. 3035215976Sjmallett 0=never drop RAW packets based on RED algorithm 3036215976Sjmallett 1=allow RAW packet drops based on RED algorithm */ 3037215976Sjmallett uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 3038215976Sjmallett calculating mask tag hash */ 3039215976Sjmallett uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 3040215976Sjmallett configuration. If DYN_RS is set then 3041215976Sjmallett PKT_INST_HDR[RS] is not used. When using 2-byte 3042215976Sjmallett instruction header words, either DYN_RS or 3043215976Sjmallett PIP_GBL_CTL[IGNRS] should be set. */ 3044215976Sjmallett uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 3045232812Sjmallett Internally set for RAWFULL/RAWSCHED packets 3046232812Sjmallett on the DPI ports (32-35). 3047232812Sjmallett Internally cleared for all other packets on the 3048232812Sjmallett DPI ports (32-35). 3049215976Sjmallett Must be zero in DSA mode */ 3050215976Sjmallett uint64_t grp_wat : 4; /**< GRP Watcher enable */ 3051215976Sjmallett uint64_t hg_qos : 1; /**< When set, uses the HiGig priority bits as a 3052215976Sjmallett lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS) 3053215976Sjmallett to determine the QOS value 3054215976Sjmallett HG_QOS must not be set when HIGIG_EN=0 */ 3055215976Sjmallett uint64_t qos : 3; /**< Default QOS level of the port */ 3056215976Sjmallett uint64_t qos_wat : 4; /**< QOS Watcher enable 3057215976Sjmallett (Watchers 0-3) */ 3058215976Sjmallett uint64_t qos_vsel : 1; /**< Which QOS in PIP_QOS_VLAN to use 3059215976Sjmallett 0 = PIP_QOS_VLAN[QOS] 3060215976Sjmallett 1 = PIP_QOS_VLAN[QOS1] */ 3061215976Sjmallett uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv 3062215976Sjmallett if DSA/VLAN exists, it is used 3063215976Sjmallett else if IP exists, Diffserv is used 3064215976Sjmallett else the per port default is used 3065215976Sjmallett Watchers are still highest priority */ 3066215976Sjmallett uint64_t qos_diff : 1; /**< QOS Diffserv */ 3067215976Sjmallett uint64_t qos_vlan : 1; /**< QOS VLAN */ 3068215976Sjmallett uint64_t reserved_13_15 : 3; 3069215976Sjmallett uint64_t crc_en : 1; /**< CRC Checking enabled */ 3070215976Sjmallett uint64_t higig_en : 1; /**< Enable HiGig parsing 3071232812Sjmallett Should not be set for DPI ports (ports 32-35) 3072232812Sjmallett Should not be set for sRIO ports (ports 40-47) 3073215976Sjmallett Should not be set for ports in which PTP_MODE=1 3074215976Sjmallett When HIGIG_EN=1: 3075215976Sjmallett DSA_EN field below must be zero 3076232812Sjmallett PIP_PRT_CFGB[ALT_SKP_EN] must be zero. 3077215976Sjmallett SKIP field below is both Skip I size and the 3078215976Sjmallett size of the HiGig* header (12 or 16 bytes) */ 3079215976Sjmallett uint64_t dsa_en : 1; /**< Enable DSA tag parsing 3080232812Sjmallett Should not be set for sRIO (ports 40-47) 3081232812Sjmallett Should not be set for ports in which PTP_MODE=1 3082215976Sjmallett When DSA_EN=1: 3083215976Sjmallett HIGIG_EN field above must be zero 3084215976Sjmallett SKIP field below is size of DSA tag (4, 8, or 3085215976Sjmallett 12 bytes) rather than the size of Skip I 3086215976Sjmallett total SKIP (Skip I + header + Skip II 3087215976Sjmallett must be zero 3088232812Sjmallett INST_HDR field above must be zero (non-DPI 3089215976Sjmallett ports) 3090232812Sjmallett PIP_PRT_CFGB[ALT_SKP_EN] must be zero. 3091232812Sjmallett For DPI ports, SLI_PKT*_INSTR_HEADER[USE_IHDR] 3092232812Sjmallett and DPI_INST_HDR[R] should be clear 3093215976Sjmallett MODE field below must be "skip to L2" */ 3094215976Sjmallett cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 3095215976Sjmallett 0 = no packet inspection (Uninterpreted) 3096215976Sjmallett 1 = L2 parsing / skip to L2 3097215976Sjmallett 2 = IP parsing / skip to L3 3098215976Sjmallett 3 = (illegal) 3099215976Sjmallett Must be 2 ("skip to L2") when in DSA mode. */ 3100215976Sjmallett uint64_t reserved_7_7 : 1; 3101232812Sjmallett uint64_t skip : 7; /**< Optional Skip I amount for packets. 3102232812Sjmallett HW forces the SKIP to zero for packets on DPI 3103232812Sjmallett ports (32-35) when a PKT_INST_HDR is present. 3104232812Sjmallett See PIP_PRT_CFGB[ALT_SKP*] and PIP_ALT_SKIP_CFG. 3105232812Sjmallett See HRM sections "Parse Mode and Skip Length 3106232812Sjmallett Selection" and "Legal Skip Values" 3107232812Sjmallett for further details. 3108215976Sjmallett In DSA mode, indicates the DSA header length, not 3109215976Sjmallett Skip I size. (Must be 4,8,or 12) 3110215976Sjmallett In HIGIG mode, indicates both the Skip I size and 3111215976Sjmallett the HiGig header size (Must be 12 or 16). 3112215976Sjmallett If PTP_MODE, the 8B timestamp is prepended to the 3113215976Sjmallett packet. SKIP should be increased by 8 to 3114215976Sjmallett compensate for the additional timestamp field. */ 3115215976Sjmallett#else 3116215976Sjmallett uint64_t skip : 7; 3117215976Sjmallett uint64_t reserved_7_7 : 1; 3118215976Sjmallett cvmx_pip_port_parse_mode_t mode : 2; 3119215976Sjmallett uint64_t dsa_en : 1; 3120215976Sjmallett uint64_t higig_en : 1; 3121215976Sjmallett uint64_t crc_en : 1; 3122215976Sjmallett uint64_t reserved_13_15 : 3; 3123215976Sjmallett uint64_t qos_vlan : 1; 3124215976Sjmallett uint64_t qos_diff : 1; 3125215976Sjmallett uint64_t qos_vod : 1; 3126215976Sjmallett uint64_t qos_vsel : 1; 3127215976Sjmallett uint64_t qos_wat : 4; 3128215976Sjmallett uint64_t qos : 3; 3129215976Sjmallett uint64_t hg_qos : 1; 3130215976Sjmallett uint64_t grp_wat : 4; 3131215976Sjmallett uint64_t inst_hdr : 1; 3132215976Sjmallett uint64_t dyn_rs : 1; 3133215976Sjmallett uint64_t tag_inc : 2; 3134215976Sjmallett uint64_t rawdrp : 1; 3135215976Sjmallett uint64_t reserved_37_39 : 3; 3136215976Sjmallett uint64_t qos_wat_47 : 4; 3137215976Sjmallett uint64_t grp_wat_47 : 4; 3138215976Sjmallett uint64_t minerr_en : 1; 3139215976Sjmallett uint64_t maxerr_en : 1; 3140215976Sjmallett uint64_t lenerr_en : 1; 3141215976Sjmallett uint64_t vlan_len : 1; 3142215976Sjmallett uint64_t pad_len : 1; 3143232812Sjmallett uint64_t len_chk_sel : 1; 3144232812Sjmallett uint64_t ih_pri : 1; 3145232812Sjmallett uint64_t reserved_55_63 : 9; 3146215976Sjmallett#endif 3147215976Sjmallett } s; 3148232812Sjmallett struct cvmx_pip_prt_cfgx_cn30xx { 3149232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3150215976Sjmallett uint64_t reserved_37_63 : 27; 3151215976Sjmallett uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 3152215976Sjmallett Normally, IPD will never drop a packet that PIP 3153215976Sjmallett indicates is RAW. 3154215976Sjmallett 0=never drop RAW packets based on RED algorithm 3155215976Sjmallett 1=allow RAW packet drops based on RED algorithm */ 3156215976Sjmallett uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 3157215976Sjmallett calculating mask tag hash */ 3158215976Sjmallett uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 3159215976Sjmallett configuration. If DYN_RS is set then 3160215976Sjmallett PKT_INST_HDR[RS] is not used. When using 2-byte 3161215976Sjmallett instruction header words, either DYN_RS or 3162215976Sjmallett PIP_GBL_CTL[IGNRS] should be set. */ 3163215976Sjmallett uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 3164215976Sjmallett (not for PCI prts, 32-35) */ 3165215976Sjmallett uint64_t grp_wat : 4; /**< GRP Watcher enable */ 3166215976Sjmallett uint64_t reserved_27_27 : 1; 3167215976Sjmallett uint64_t qos : 3; /**< Default QOS level of the port */ 3168215976Sjmallett uint64_t qos_wat : 4; /**< QOS Watcher enable */ 3169215976Sjmallett uint64_t reserved_18_19 : 2; 3170215976Sjmallett uint64_t qos_diff : 1; /**< QOS Diffserv */ 3171215976Sjmallett uint64_t qos_vlan : 1; /**< QOS VLAN */ 3172215976Sjmallett uint64_t reserved_10_15 : 6; 3173215976Sjmallett cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 3174215976Sjmallett 0 = no packet inspection (Uninterpreted) 3175215976Sjmallett 1 = L2 parsing / skip to L2 3176215976Sjmallett 2 = IP parsing / skip to L3 3177215976Sjmallett 3 = PCI Raw (illegal for software to set) */ 3178215976Sjmallett uint64_t reserved_7_7 : 1; 3179215976Sjmallett uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not 3180215976Sjmallett apply to packets on PCI ports when a PKT_INST_HDR 3181215976Sjmallett is present. See section 7.2.7 - Legal Skip 3182215976Sjmallett Values for further details. */ 3183215976Sjmallett#else 3184215976Sjmallett uint64_t skip : 7; 3185215976Sjmallett uint64_t reserved_7_7 : 1; 3186215976Sjmallett cvmx_pip_port_parse_mode_t mode : 2; 3187215976Sjmallett uint64_t reserved_10_15 : 6; 3188215976Sjmallett uint64_t qos_vlan : 1; 3189215976Sjmallett uint64_t qos_diff : 1; 3190215976Sjmallett uint64_t reserved_18_19 : 2; 3191215976Sjmallett uint64_t qos_wat : 4; 3192215976Sjmallett uint64_t qos : 3; 3193215976Sjmallett uint64_t reserved_27_27 : 1; 3194215976Sjmallett uint64_t grp_wat : 4; 3195215976Sjmallett uint64_t inst_hdr : 1; 3196215976Sjmallett uint64_t dyn_rs : 1; 3197215976Sjmallett uint64_t tag_inc : 2; 3198215976Sjmallett uint64_t rawdrp : 1; 3199215976Sjmallett uint64_t reserved_37_63 : 27; 3200215976Sjmallett#endif 3201215976Sjmallett } cn30xx; 3202215976Sjmallett struct cvmx_pip_prt_cfgx_cn30xx cn31xx; 3203232812Sjmallett struct cvmx_pip_prt_cfgx_cn38xx { 3204232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3205215976Sjmallett uint64_t reserved_37_63 : 27; 3206215976Sjmallett uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 3207215976Sjmallett Normally, IPD will never drop a packet that PIP 3208215976Sjmallett indicates is RAW. 3209215976Sjmallett 0=never drop RAW packets based on RED algorithm 3210215976Sjmallett 1=allow RAW packet drops based on RED algorithm */ 3211215976Sjmallett uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 3212215976Sjmallett calculating mask tag hash */ 3213215976Sjmallett uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 3214215976Sjmallett configuration. If DYN_RS is set then 3215215976Sjmallett PKT_INST_HDR[RS] is not used. When using 2-byte 3216215976Sjmallett instruction header words, either DYN_RS or 3217215976Sjmallett PIP_GBL_CTL[IGNRS] should be set. */ 3218215976Sjmallett uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 3219215976Sjmallett (not for PCI prts, 32-35) */ 3220215976Sjmallett uint64_t grp_wat : 4; /**< GRP Watcher enable */ 3221215976Sjmallett uint64_t reserved_27_27 : 1; 3222215976Sjmallett uint64_t qos : 3; /**< Default QOS level of the port */ 3223215976Sjmallett uint64_t qos_wat : 4; /**< QOS Watcher enable */ 3224215976Sjmallett uint64_t reserved_18_19 : 2; 3225215976Sjmallett uint64_t qos_diff : 1; /**< QOS Diffserv */ 3226215976Sjmallett uint64_t qos_vlan : 1; /**< QOS VLAN */ 3227215976Sjmallett uint64_t reserved_13_15 : 3; 3228215976Sjmallett uint64_t crc_en : 1; /**< CRC Checking enabled (for ports 0-31 only) */ 3229215976Sjmallett uint64_t reserved_10_11 : 2; 3230215976Sjmallett cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 3231215976Sjmallett 0 = no packet inspection (Uninterpreted) 3232215976Sjmallett 1 = L2 parsing / skip to L2 3233215976Sjmallett 2 = IP parsing / skip to L3 3234215976Sjmallett 3 = PCI Raw (illegal for software to set) */ 3235215976Sjmallett uint64_t reserved_7_7 : 1; 3236215976Sjmallett uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not 3237215976Sjmallett apply to packets on PCI ports when a PKT_INST_HDR 3238215976Sjmallett is present. See section 7.2.7 - Legal Skip 3239215976Sjmallett Values for further details. */ 3240215976Sjmallett#else 3241215976Sjmallett uint64_t skip : 7; 3242215976Sjmallett uint64_t reserved_7_7 : 1; 3243215976Sjmallett cvmx_pip_port_parse_mode_t mode : 2; 3244215976Sjmallett uint64_t reserved_10_11 : 2; 3245215976Sjmallett uint64_t crc_en : 1; 3246215976Sjmallett uint64_t reserved_13_15 : 3; 3247215976Sjmallett uint64_t qos_vlan : 1; 3248215976Sjmallett uint64_t qos_diff : 1; 3249215976Sjmallett uint64_t reserved_18_19 : 2; 3250215976Sjmallett uint64_t qos_wat : 4; 3251215976Sjmallett uint64_t qos : 3; 3252215976Sjmallett uint64_t reserved_27_27 : 1; 3253215976Sjmallett uint64_t grp_wat : 4; 3254215976Sjmallett uint64_t inst_hdr : 1; 3255215976Sjmallett uint64_t dyn_rs : 1; 3256215976Sjmallett uint64_t tag_inc : 2; 3257215976Sjmallett uint64_t rawdrp : 1; 3258215976Sjmallett uint64_t reserved_37_63 : 27; 3259215976Sjmallett#endif 3260215976Sjmallett } cn38xx; 3261215976Sjmallett struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2; 3262232812Sjmallett struct cvmx_pip_prt_cfgx_cn50xx { 3263232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3264215976Sjmallett uint64_t reserved_53_63 : 11; 3265215976Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for pkts with 3266215976Sjmallett padding in the client data */ 3267215976Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for VLAN pkts */ 3268215976Sjmallett uint64_t lenerr_en : 1; /**< L2 length error check enable 3269215976Sjmallett Frame was received with length error */ 3270215976Sjmallett uint64_t maxerr_en : 1; /**< Max frame error check enable 3271215976Sjmallett Frame was received with length > max_length */ 3272215976Sjmallett uint64_t minerr_en : 1; /**< Min frame error check enable 3273215976Sjmallett Frame was received with length < min_length */ 3274215976Sjmallett uint64_t grp_wat_47 : 4; /**< GRP Watcher enable 3275215976Sjmallett (Watchers 4-7) */ 3276215976Sjmallett uint64_t qos_wat_47 : 4; /**< QOS Watcher enable 3277215976Sjmallett (Watchers 4-7) */ 3278215976Sjmallett uint64_t reserved_37_39 : 3; 3279215976Sjmallett uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 3280215976Sjmallett Normally, IPD will never drop a packet that PIP 3281215976Sjmallett indicates is RAW. 3282215976Sjmallett 0=never drop RAW packets based on RED algorithm 3283215976Sjmallett 1=allow RAW packet drops based on RED algorithm */ 3284215976Sjmallett uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 3285215976Sjmallett calculating mask tag hash */ 3286215976Sjmallett uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 3287215976Sjmallett configuration. If DYN_RS is set then 3288215976Sjmallett PKT_INST_HDR[RS] is not used. When using 2-byte 3289215976Sjmallett instruction header words, either DYN_RS or 3290215976Sjmallett PIP_GBL_CTL[IGNRS] should be set. */ 3291215976Sjmallett uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 3292215976Sjmallett (not for PCI prts, 32-35) */ 3293215976Sjmallett uint64_t grp_wat : 4; /**< GRP Watcher enable */ 3294215976Sjmallett uint64_t reserved_27_27 : 1; 3295215976Sjmallett uint64_t qos : 3; /**< Default QOS level of the port */ 3296215976Sjmallett uint64_t qos_wat : 4; /**< QOS Watcher enable 3297215976Sjmallett (Watchers 0-3) */ 3298215976Sjmallett uint64_t reserved_19_19 : 1; 3299215976Sjmallett uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv 3300215976Sjmallett if VLAN exists, it is used 3301215976Sjmallett else if IP exists, Diffserv is used 3302215976Sjmallett else the per port default is used 3303215976Sjmallett Watchers are still highest priority */ 3304215976Sjmallett uint64_t qos_diff : 1; /**< QOS Diffserv */ 3305215976Sjmallett uint64_t qos_vlan : 1; /**< QOS VLAN */ 3306215976Sjmallett uint64_t reserved_13_15 : 3; 3307215976Sjmallett uint64_t crc_en : 1; /**< CRC Checking enabled 3308215976Sjmallett (Disabled in 5020) */ 3309215976Sjmallett uint64_t reserved_10_11 : 2; 3310215976Sjmallett cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 3311215976Sjmallett 0 = no packet inspection (Uninterpreted) 3312215976Sjmallett 1 = L2 parsing / skip to L2 3313215976Sjmallett 2 = IP parsing / skip to L3 3314215976Sjmallett 3 = PCI Raw (illegal for software to set) */ 3315215976Sjmallett uint64_t reserved_7_7 : 1; 3316215976Sjmallett uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not 3317215976Sjmallett apply to packets on PCI ports when a PKT_INST_HDR 3318215976Sjmallett is present. See section 7.2.7 - Legal Skip 3319215976Sjmallett Values for further details. */ 3320215976Sjmallett#else 3321215976Sjmallett uint64_t skip : 7; 3322215976Sjmallett uint64_t reserved_7_7 : 1; 3323215976Sjmallett cvmx_pip_port_parse_mode_t mode : 2; 3324215976Sjmallett uint64_t reserved_10_11 : 2; 3325215976Sjmallett uint64_t crc_en : 1; 3326215976Sjmallett uint64_t reserved_13_15 : 3; 3327215976Sjmallett uint64_t qos_vlan : 1; 3328215976Sjmallett uint64_t qos_diff : 1; 3329215976Sjmallett uint64_t qos_vod : 1; 3330215976Sjmallett uint64_t reserved_19_19 : 1; 3331215976Sjmallett uint64_t qos_wat : 4; 3332215976Sjmallett uint64_t qos : 3; 3333215976Sjmallett uint64_t reserved_27_27 : 1; 3334215976Sjmallett uint64_t grp_wat : 4; 3335215976Sjmallett uint64_t inst_hdr : 1; 3336215976Sjmallett uint64_t dyn_rs : 1; 3337215976Sjmallett uint64_t tag_inc : 2; 3338215976Sjmallett uint64_t rawdrp : 1; 3339215976Sjmallett uint64_t reserved_37_39 : 3; 3340215976Sjmallett uint64_t qos_wat_47 : 4; 3341215976Sjmallett uint64_t grp_wat_47 : 4; 3342215976Sjmallett uint64_t minerr_en : 1; 3343215976Sjmallett uint64_t maxerr_en : 1; 3344215976Sjmallett uint64_t lenerr_en : 1; 3345215976Sjmallett uint64_t vlan_len : 1; 3346215976Sjmallett uint64_t pad_len : 1; 3347215976Sjmallett uint64_t reserved_53_63 : 11; 3348215976Sjmallett#endif 3349215976Sjmallett } cn50xx; 3350232812Sjmallett struct cvmx_pip_prt_cfgx_cn52xx { 3351232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3352232812Sjmallett uint64_t reserved_53_63 : 11; 3353232812Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for pkts with 3354232812Sjmallett padding in the client data */ 3355232812Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for DSA/VLAN 3356232812Sjmallett pkts */ 3357232812Sjmallett uint64_t lenerr_en : 1; /**< L2 length error check enable 3358232812Sjmallett Frame was received with length error 3359232812Sjmallett Typically, this check will not be enabled for 3360232812Sjmallett incoming packets on the PCIe ports. */ 3361232812Sjmallett uint64_t maxerr_en : 1; /**< Max frame error check enable 3362232812Sjmallett Frame was received with length > max_length */ 3363232812Sjmallett uint64_t minerr_en : 1; /**< Min frame error check enable 3364232812Sjmallett Frame was received with length < min_length 3365232812Sjmallett Typically, this check will not be enabled for 3366232812Sjmallett incoming packets on the PCIe ports. */ 3367232812Sjmallett uint64_t grp_wat_47 : 4; /**< GRP Watcher enable 3368232812Sjmallett (Watchers 4-7) */ 3369232812Sjmallett uint64_t qos_wat_47 : 4; /**< QOS Watcher enable 3370232812Sjmallett (Watchers 4-7) */ 3371232812Sjmallett uint64_t reserved_37_39 : 3; 3372232812Sjmallett uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 3373232812Sjmallett Normally, IPD will never drop a packet that PIP 3374232812Sjmallett indicates is RAW. 3375232812Sjmallett 0=never drop RAW packets based on RED algorithm 3376232812Sjmallett 1=allow RAW packet drops based on RED algorithm */ 3377232812Sjmallett uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 3378232812Sjmallett calculating mask tag hash */ 3379232812Sjmallett uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 3380232812Sjmallett configuration. If DYN_RS is set then 3381232812Sjmallett PKT_INST_HDR[RS] is not used. When using 2-byte 3382232812Sjmallett instruction header words, either DYN_RS or 3383232812Sjmallett PIP_GBL_CTL[IGNRS] should be set. */ 3384232812Sjmallett uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 3385232812Sjmallett (not for PCI ports, 32-35) 3386232812Sjmallett Must be zero in DSA mode */ 3387232812Sjmallett uint64_t grp_wat : 4; /**< GRP Watcher enable */ 3388232812Sjmallett uint64_t hg_qos : 1; /**< When set, uses the HiGig priority bits as a 3389232812Sjmallett lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS) 3390232812Sjmallett to determine the QOS value 3391232812Sjmallett HG_QOS must not be set when HIGIG_EN=0 */ 3392232812Sjmallett uint64_t qos : 3; /**< Default QOS level of the port */ 3393232812Sjmallett uint64_t qos_wat : 4; /**< QOS Watcher enable 3394232812Sjmallett (Watchers 0-3) */ 3395232812Sjmallett uint64_t qos_vsel : 1; /**< Which QOS in PIP_QOS_VLAN to use 3396232812Sjmallett 0 = PIP_QOS_VLAN[QOS] 3397232812Sjmallett 1 = PIP_QOS_VLAN[QOS1] */ 3398232812Sjmallett uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv 3399232812Sjmallett if DSA/VLAN exists, it is used 3400232812Sjmallett else if IP exists, Diffserv is used 3401232812Sjmallett else the per port default is used 3402232812Sjmallett Watchers are still highest priority */ 3403232812Sjmallett uint64_t qos_diff : 1; /**< QOS Diffserv */ 3404232812Sjmallett uint64_t qos_vlan : 1; /**< QOS VLAN */ 3405232812Sjmallett uint64_t reserved_13_15 : 3; 3406232812Sjmallett uint64_t crc_en : 1; /**< CRC Checking enabled 3407232812Sjmallett (Disabled in 52xx) */ 3408232812Sjmallett uint64_t higig_en : 1; /**< Enable HiGig parsing 3409232812Sjmallett When HIGIG_EN=1: 3410232812Sjmallett DSA_EN field below must be zero 3411232812Sjmallett SKIP field below is both Skip I size and the 3412232812Sjmallett size of the HiGig* header (12 or 16 bytes) */ 3413232812Sjmallett uint64_t dsa_en : 1; /**< Enable DSA tag parsing 3414232812Sjmallett When DSA_EN=1: 3415232812Sjmallett HIGIG_EN field above must be zero 3416232812Sjmallett SKIP field below is size of DSA tag (4, 8, or 3417232812Sjmallett 12 bytes) rather than the size of Skip I 3418232812Sjmallett total SKIP (Skip I + header + Skip II 3419232812Sjmallett must be zero 3420232812Sjmallett INST_HDR field above must be zero 3421232812Sjmallett MODE field below must be "skip to L2" */ 3422232812Sjmallett cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 3423232812Sjmallett 0 = no packet inspection (Uninterpreted) 3424232812Sjmallett 1 = L2 parsing / skip to L2 3425232812Sjmallett 2 = IP parsing / skip to L3 3426232812Sjmallett 3 = (illegal) 3427232812Sjmallett Must be 2 ("skip to L2") when in DSA mode. */ 3428232812Sjmallett uint64_t reserved_7_7 : 1; 3429232812Sjmallett uint64_t skip : 7; /**< Optional Skip I amount for packets. 3430232812Sjmallett See section 7.2.7 - Legal Skip 3431232812Sjmallett Values for further details. 3432232812Sjmallett In DSA mode, indicates the DSA header length, not 3433232812Sjmallett Skip I size. (Must be 4,8,or 12) 3434232812Sjmallett In HIGIG mode, indicates both the Skip I size and 3435232812Sjmallett the HiGig header size (Must be 12 or 16). */ 3436232812Sjmallett#else 3437232812Sjmallett uint64_t skip : 7; 3438232812Sjmallett uint64_t reserved_7_7 : 1; 3439232812Sjmallett cvmx_pip_port_parse_mode_t mode : 2; 3440232812Sjmallett uint64_t dsa_en : 1; 3441232812Sjmallett uint64_t higig_en : 1; 3442232812Sjmallett uint64_t crc_en : 1; 3443232812Sjmallett uint64_t reserved_13_15 : 3; 3444232812Sjmallett uint64_t qos_vlan : 1; 3445232812Sjmallett uint64_t qos_diff : 1; 3446232812Sjmallett uint64_t qos_vod : 1; 3447232812Sjmallett uint64_t qos_vsel : 1; 3448232812Sjmallett uint64_t qos_wat : 4; 3449232812Sjmallett uint64_t qos : 3; 3450232812Sjmallett uint64_t hg_qos : 1; 3451232812Sjmallett uint64_t grp_wat : 4; 3452232812Sjmallett uint64_t inst_hdr : 1; 3453232812Sjmallett uint64_t dyn_rs : 1; 3454232812Sjmallett uint64_t tag_inc : 2; 3455232812Sjmallett uint64_t rawdrp : 1; 3456232812Sjmallett uint64_t reserved_37_39 : 3; 3457232812Sjmallett uint64_t qos_wat_47 : 4; 3458232812Sjmallett uint64_t grp_wat_47 : 4; 3459232812Sjmallett uint64_t minerr_en : 1; 3460232812Sjmallett uint64_t maxerr_en : 1; 3461232812Sjmallett uint64_t lenerr_en : 1; 3462232812Sjmallett uint64_t vlan_len : 1; 3463232812Sjmallett uint64_t pad_len : 1; 3464232812Sjmallett uint64_t reserved_53_63 : 11; 3465232812Sjmallett#endif 3466232812Sjmallett } cn52xx; 3467232812Sjmallett struct cvmx_pip_prt_cfgx_cn52xx cn52xxp1; 3468232812Sjmallett struct cvmx_pip_prt_cfgx_cn52xx cn56xx; 3469215976Sjmallett struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1; 3470232812Sjmallett struct cvmx_pip_prt_cfgx_cn58xx { 3471232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3472215976Sjmallett uint64_t reserved_37_63 : 27; 3473215976Sjmallett uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 3474215976Sjmallett Normally, IPD will never drop a packet that PIP 3475215976Sjmallett indicates is RAW. 3476215976Sjmallett 0=never drop RAW packets based on RED algorithm 3477215976Sjmallett 1=allow RAW packet drops based on RED algorithm */ 3478215976Sjmallett uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 3479215976Sjmallett calculating mask tag hash */ 3480215976Sjmallett uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 3481215976Sjmallett configuration. If DYN_RS is set then 3482215976Sjmallett PKT_INST_HDR[RS] is not used. When using 2-byte 3483215976Sjmallett instruction header words, either DYN_RS or 3484215976Sjmallett PIP_GBL_CTL[IGNRS] should be set. */ 3485215976Sjmallett uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 3486215976Sjmallett (not for PCI prts, 32-35) */ 3487215976Sjmallett uint64_t grp_wat : 4; /**< GRP Watcher enable */ 3488215976Sjmallett uint64_t reserved_27_27 : 1; 3489215976Sjmallett uint64_t qos : 3; /**< Default QOS level of the port */ 3490215976Sjmallett uint64_t qos_wat : 4; /**< QOS Watcher enable */ 3491215976Sjmallett uint64_t reserved_19_19 : 1; 3492215976Sjmallett uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv 3493215976Sjmallett if VLAN exists, it is used 3494215976Sjmallett else if IP exists, Diffserv is used 3495215976Sjmallett else the per port default is used 3496215976Sjmallett Watchers are still highest priority */ 3497215976Sjmallett uint64_t qos_diff : 1; /**< QOS Diffserv */ 3498215976Sjmallett uint64_t qos_vlan : 1; /**< QOS VLAN */ 3499215976Sjmallett uint64_t reserved_13_15 : 3; 3500215976Sjmallett uint64_t crc_en : 1; /**< CRC Checking enabled (for ports 0-31 only) */ 3501215976Sjmallett uint64_t reserved_10_11 : 2; 3502215976Sjmallett cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 3503215976Sjmallett 0 = no packet inspection (Uninterpreted) 3504215976Sjmallett 1 = L2 parsing / skip to L2 3505215976Sjmallett 2 = IP parsing / skip to L3 3506215976Sjmallett 3 = PCI Raw (illegal for software to set) */ 3507215976Sjmallett uint64_t reserved_7_7 : 1; 3508215976Sjmallett uint64_t skip : 7; /**< Optional Skip I amount for packets. Does not 3509215976Sjmallett apply to packets on PCI ports when a PKT_INST_HDR 3510215976Sjmallett is present. See section 7.2.7 - Legal Skip 3511215976Sjmallett Values for further details. */ 3512215976Sjmallett#else 3513215976Sjmallett uint64_t skip : 7; 3514215976Sjmallett uint64_t reserved_7_7 : 1; 3515215976Sjmallett cvmx_pip_port_parse_mode_t mode : 2; 3516215976Sjmallett uint64_t reserved_10_11 : 2; 3517215976Sjmallett uint64_t crc_en : 1; 3518215976Sjmallett uint64_t reserved_13_15 : 3; 3519215976Sjmallett uint64_t qos_vlan : 1; 3520215976Sjmallett uint64_t qos_diff : 1; 3521215976Sjmallett uint64_t qos_vod : 1; 3522215976Sjmallett uint64_t reserved_19_19 : 1; 3523215976Sjmallett uint64_t qos_wat : 4; 3524215976Sjmallett uint64_t qos : 3; 3525215976Sjmallett uint64_t reserved_27_27 : 1; 3526215976Sjmallett uint64_t grp_wat : 4; 3527215976Sjmallett uint64_t inst_hdr : 1; 3528215976Sjmallett uint64_t dyn_rs : 1; 3529215976Sjmallett uint64_t tag_inc : 2; 3530215976Sjmallett uint64_t rawdrp : 1; 3531215976Sjmallett uint64_t reserved_37_63 : 27; 3532215976Sjmallett#endif 3533215976Sjmallett } cn58xx; 3534215976Sjmallett struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1; 3535232812Sjmallett struct cvmx_pip_prt_cfgx_cn52xx cn61xx; 3536232812Sjmallett struct cvmx_pip_prt_cfgx_cn52xx cn63xx; 3537232812Sjmallett struct cvmx_pip_prt_cfgx_cn52xx cn63xxp1; 3538232812Sjmallett struct cvmx_pip_prt_cfgx_cn52xx cn66xx; 3539232812Sjmallett struct cvmx_pip_prt_cfgx_cn68xx { 3540232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3541232812Sjmallett uint64_t reserved_55_63 : 9; 3542232812Sjmallett uint64_t ih_pri : 1; /**< Use the PRI/QOS field in the instruction header 3543232812Sjmallett as the PRIORITY in BPID calculations. */ 3544232812Sjmallett uint64_t len_chk_sel : 1; /**< Selects which PIP_FRM_LEN_CHK register is used 3545232812Sjmallett for this port-kind for MINERR and MAXERR checks. 3546232812Sjmallett LEN_CHK_SEL=0, use PIP_FRM_LEN_CHK0 3547232812Sjmallett LEN_CHK_SEL=1, use PIP_FRM_LEN_CHK1 */ 3548232812Sjmallett uint64_t pad_len : 1; /**< When set, disables the length check for pkts with 3549232812Sjmallett padding in the client data */ 3550232812Sjmallett uint64_t vlan_len : 1; /**< When set, disables the length check for DSA/VLAN 3551232812Sjmallett pkts */ 3552232812Sjmallett uint64_t lenerr_en : 1; /**< L2 length error check enable 3553232812Sjmallett Frame was received with length error 3554232812Sjmallett Typically, this check will not be enabled for 3555232812Sjmallett incoming packets on the DPI rings 3556232812Sjmallett because the CRC bytes may not normally be 3557232812Sjmallett present. */ 3558232812Sjmallett uint64_t maxerr_en : 1; /**< Max frame error check enable 3559232812Sjmallett Frame was received with length > max_length 3560232812Sjmallett max_length is defined by PIP_FRM_LEN_CHK[MAXLEN] */ 3561232812Sjmallett uint64_t minerr_en : 1; /**< Min frame error check enable 3562232812Sjmallett Frame was received with length < min_length 3563232812Sjmallett Typically, this check will not be enabled for 3564232812Sjmallett incoming packets on the DPI rings 3565232812Sjmallett because the CRC bytes may not normally be 3566232812Sjmallett present. 3567232812Sjmallett min_length is defined by PIP_FRM_LEN_CHK[MINLEN] */ 3568232812Sjmallett uint64_t grp_wat_47 : 4; /**< GRP Watcher enable 3569232812Sjmallett (Watchers 4-7) */ 3570232812Sjmallett uint64_t qos_wat_47 : 4; /**< QOS Watcher enable 3571232812Sjmallett (Watchers 4-7) */ 3572232812Sjmallett uint64_t reserved_37_39 : 3; 3573232812Sjmallett uint64_t rawdrp : 1; /**< Allow the IPD to RED drop a packet. 3574232812Sjmallett Normally, IPD will never drop a packet in which 3575232812Sjmallett PKT_INST_HDR[R] is set. 3576232812Sjmallett 0=never drop RAW packets based on RED algorithm 3577232812Sjmallett 1=allow RAW packet drops based on RED algorithm */ 3578232812Sjmallett uint64_t tag_inc : 2; /**< Which of the 4 PIP_TAG_INC to use when 3579232812Sjmallett calculating mask tag hash */ 3580232812Sjmallett uint64_t dyn_rs : 1; /**< Dynamically calculate RS based on pkt size and 3581232812Sjmallett configuration. If DYN_RS is set then 3582232812Sjmallett PKT_INST_HDR[RS] is not used. When using 2-byte 3583232812Sjmallett instruction header words, either DYN_RS or 3584232812Sjmallett PIP_GBL_CTL[IGNRS] should be set. */ 3585232812Sjmallett uint64_t inst_hdr : 1; /**< 8-byte INST_HDR is present on all packets 3586232812Sjmallett Normally INST_HDR should be set for packets that 3587232812Sjmallett include a PKT_INST_HDR prepended by DPI hardware. 3588232812Sjmallett (If SLI_PORTx_PKIND[RPK_ENB]=0, for packets that 3589232812Sjmallett include a PKT_INST_HDR prepended by DPI, 3590232812Sjmallett PIP internally sets INST_HDR before using it.) 3591232812Sjmallett Must be zero in DSA mode */ 3592232812Sjmallett uint64_t grp_wat : 4; /**< GRP Watcher enable */ 3593232812Sjmallett uint64_t hg_qos : 1; /**< When set, uses the HiGig priority bits as a 3594232812Sjmallett lookup into the HG_QOS_TABLE (PIP_HG_PRI_QOS) 3595232812Sjmallett to determine the QOS value 3596232812Sjmallett HG_QOS must not be set when HIGIG_EN=0 */ 3597232812Sjmallett uint64_t qos : 3; /**< Default QOS level of the port */ 3598232812Sjmallett uint64_t qos_wat : 4; /**< QOS Watcher enable 3599232812Sjmallett (Watchers 0-3) */ 3600232812Sjmallett uint64_t reserved_19_19 : 1; 3601232812Sjmallett uint64_t qos_vod : 1; /**< QOS VLAN over Diffserv 3602232812Sjmallett if DSA/VLAN exists, it is used 3603232812Sjmallett else if IP exists, Diffserv is used 3604232812Sjmallett else the per port default is used 3605232812Sjmallett Watchers are still highest priority */ 3606232812Sjmallett uint64_t qos_diff : 1; /**< QOS Diffserv */ 3607232812Sjmallett uint64_t qos_vlan : 1; /**< QOS VLAN */ 3608232812Sjmallett uint64_t reserved_13_15 : 3; 3609232812Sjmallett uint64_t crc_en : 1; /**< CRC Checking enabled */ 3610232812Sjmallett uint64_t higig_en : 1; /**< Enable HiGig parsing 3611232812Sjmallett Normally HIGIG_EN should be clear for packets that 3612232812Sjmallett include a PKT_INST_HDR prepended by DPI hardware. 3613232812Sjmallett (If SLI_PORTx_PKIND[RPK_ENB]=0, for packets that 3614232812Sjmallett include a PKT_INST_HDR prepended by DPI, 3615232812Sjmallett PIP internally clears HIGIG_EN before using it.) 3616232812Sjmallett Should not be set for ports in which PTP_MODE=1 3617232812Sjmallett When HIGIG_EN=1: 3618232812Sjmallett DSA_EN field below must be zero 3619232812Sjmallett PIP_PRT_CFGB[ALT_SKP_EN] must be zero. 3620232812Sjmallett SKIP field below is both Skip I size and the 3621232812Sjmallett size of the HiGig* header (12 or 16 bytes) */ 3622232812Sjmallett uint64_t dsa_en : 1; /**< Enable DSA tag parsing 3623232812Sjmallett Should not be set for ports in which PTP_MODE=1 3624232812Sjmallett When DSA_EN=1: 3625232812Sjmallett HIGIG_EN field above must be zero 3626232812Sjmallett SKIP field below is size of DSA tag (4, 8, or 3627232812Sjmallett 12 bytes) rather than the size of Skip I 3628232812Sjmallett total SKIP (Skip I + header + Skip II 3629232812Sjmallett must be zero 3630232812Sjmallett INST_HDR field above must be zero 3631232812Sjmallett PIP_PRT_CFGB[ALT_SKP_EN] must be zero. 3632232812Sjmallett For DPI rings, DPI hardware must not prepend 3633232812Sjmallett a PKT_INST_HDR when DSA_EN=1. 3634232812Sjmallett MODE field below must be "skip to L2" */ 3635232812Sjmallett cvmx_pip_port_parse_mode_t mode : 2; /**< Parse Mode 3636232812Sjmallett 0 = no packet inspection (Uninterpreted) 3637232812Sjmallett 1 = L2 parsing / skip to L2 3638232812Sjmallett 2 = IP parsing / skip to L3 3639232812Sjmallett 3 = (illegal) 3640232812Sjmallett Must be 2 ("skip to L2") when in DSA mode. */ 3641232812Sjmallett uint64_t reserved_7_7 : 1; 3642232812Sjmallett uint64_t skip : 7; /**< Optional Skip I amount for packets. 3643232812Sjmallett Should normally be zero for packets on 3644232812Sjmallett DPI rings when a PKT_INST_HDR is prepended by DPI 3645232812Sjmallett hardware. 3646232812Sjmallett See PIP_PRT_CFGB[ALT_SKP*] and PIP_ALT_SKIP_CFG. 3647232812Sjmallett See HRM sections "Parse Mode and Skip Length 3648232812Sjmallett Selection" and "Legal Skip Values" 3649232812Sjmallett for further details. 3650232812Sjmallett In DSA mode, indicates the DSA header length, not 3651232812Sjmallett Skip I size. (Must be 4,8,or 12) 3652232812Sjmallett In HIGIG mode, indicates both the Skip I size and 3653232812Sjmallett the HiGig header size (Must be 12 or 16). 3654232812Sjmallett If PTP_MODE, the 8B timestamp is prepended to the 3655232812Sjmallett packet. SKIP should be increased by 8 to 3656232812Sjmallett compensate for the additional timestamp field. */ 3657232812Sjmallett#else 3658232812Sjmallett uint64_t skip : 7; 3659232812Sjmallett uint64_t reserved_7_7 : 1; 3660232812Sjmallett cvmx_pip_port_parse_mode_t mode : 2; 3661232812Sjmallett uint64_t dsa_en : 1; 3662232812Sjmallett uint64_t higig_en : 1; 3663232812Sjmallett uint64_t crc_en : 1; 3664232812Sjmallett uint64_t reserved_13_15 : 3; 3665232812Sjmallett uint64_t qos_vlan : 1; 3666232812Sjmallett uint64_t qos_diff : 1; 3667232812Sjmallett uint64_t qos_vod : 1; 3668232812Sjmallett uint64_t reserved_19_19 : 1; 3669232812Sjmallett uint64_t qos_wat : 4; 3670232812Sjmallett uint64_t qos : 3; 3671232812Sjmallett uint64_t hg_qos : 1; 3672232812Sjmallett uint64_t grp_wat : 4; 3673232812Sjmallett uint64_t inst_hdr : 1; 3674232812Sjmallett uint64_t dyn_rs : 1; 3675232812Sjmallett uint64_t tag_inc : 2; 3676232812Sjmallett uint64_t rawdrp : 1; 3677232812Sjmallett uint64_t reserved_37_39 : 3; 3678232812Sjmallett uint64_t qos_wat_47 : 4; 3679232812Sjmallett uint64_t grp_wat_47 : 4; 3680232812Sjmallett uint64_t minerr_en : 1; 3681232812Sjmallett uint64_t maxerr_en : 1; 3682232812Sjmallett uint64_t lenerr_en : 1; 3683232812Sjmallett uint64_t vlan_len : 1; 3684232812Sjmallett uint64_t pad_len : 1; 3685232812Sjmallett uint64_t len_chk_sel : 1; 3686232812Sjmallett uint64_t ih_pri : 1; 3687232812Sjmallett uint64_t reserved_55_63 : 9; 3688232812Sjmallett#endif 3689232812Sjmallett } cn68xx; 3690232812Sjmallett struct cvmx_pip_prt_cfgx_cn68xx cn68xxp1; 3691232812Sjmallett struct cvmx_pip_prt_cfgx_cn52xx cnf71xx; 3692215976Sjmallett}; 3693215976Sjmalletttypedef union cvmx_pip_prt_cfgx cvmx_pip_prt_cfgx_t; 3694215976Sjmallett 3695215976Sjmallett/** 3696232812Sjmallett * cvmx_pip_prt_cfgb# 3697232812Sjmallett * 3698232812Sjmallett * Notes: 3699232812Sjmallett * PIP_PRT_CFGB* does not exist prior to pass 1.2. 3700232812Sjmallett * 3701232812Sjmallett */ 3702232812Sjmallettunion cvmx_pip_prt_cfgbx { 3703232812Sjmallett uint64_t u64; 3704232812Sjmallett struct cvmx_pip_prt_cfgbx_s { 3705232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3706232812Sjmallett uint64_t reserved_39_63 : 25; 3707232812Sjmallett uint64_t alt_skp_sel : 2; /**< Alternate skip selector 3708232812Sjmallett When enabled (ALT_SKP_EN), selects which of the 3709232812Sjmallett four PIP_ALT_SKIP_CFGx to use with the packets 3710232812Sjmallett arriving on the port-kind. */ 3711232812Sjmallett uint64_t alt_skp_en : 1; /**< Enable the alternate skip selector 3712232812Sjmallett When enabled, the HW is able to recompute the 3713232812Sjmallett SKIP I value based on the packet contents. 3714232812Sjmallett Up to two of the initial 64 bits of the header 3715232812Sjmallett are used along with four PIP_ALT_SKIP_CFGx to 3716232812Sjmallett determine the updated SKIP I value. 3717232812Sjmallett The bits of the packet used should be present in 3718232812Sjmallett all packets. 3719232812Sjmallett PIP_PRT_CFG[DSA_EN,HIGIG_EN] must be disabled 3720232812Sjmallett when ALT_SKP_EN is set. 3721232812Sjmallett ALT_SKP_EN must not be set for DPI ports (32-35) 3722232812Sjmallett when a PKT_INST_HDR is present. 3723232812Sjmallett ALT_SKP_EN should not be enabled for ports which 3724232812Sjmallett have GMX_RX_FRM_CTL[PTP_MODE] set as the timestamp 3725232812Sjmallett will be prepended onto the initial 64 bits of the 3726232812Sjmallett packet. */ 3727232812Sjmallett uint64_t reserved_35_35 : 1; 3728232812Sjmallett uint64_t bsel_num : 2; /**< Which of the 4 bit select extractors to use 3729232812Sjmallett (Alias to PIP_PRT_CFG) */ 3730232812Sjmallett uint64_t bsel_en : 1; /**< Enable to turn on/off use of bit select extractor 3731232812Sjmallett (Alias to PIP_PRT_CFG) */ 3732232812Sjmallett uint64_t reserved_24_31 : 8; 3733232812Sjmallett uint64_t base : 8; /**< Base priority address into the table */ 3734232812Sjmallett uint64_t reserved_6_15 : 10; 3735232812Sjmallett uint64_t bpid : 6; /**< Default BPID to use for packets on this port-kind. */ 3736232812Sjmallett#else 3737232812Sjmallett uint64_t bpid : 6; 3738232812Sjmallett uint64_t reserved_6_15 : 10; 3739232812Sjmallett uint64_t base : 8; 3740232812Sjmallett uint64_t reserved_24_31 : 8; 3741232812Sjmallett uint64_t bsel_en : 1; 3742232812Sjmallett uint64_t bsel_num : 2; 3743232812Sjmallett uint64_t reserved_35_35 : 1; 3744232812Sjmallett uint64_t alt_skp_en : 1; 3745232812Sjmallett uint64_t alt_skp_sel : 2; 3746232812Sjmallett uint64_t reserved_39_63 : 25; 3747232812Sjmallett#endif 3748232812Sjmallett } s; 3749232812Sjmallett struct cvmx_pip_prt_cfgbx_cn61xx { 3750232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3751232812Sjmallett uint64_t reserved_39_63 : 25; 3752232812Sjmallett uint64_t alt_skp_sel : 2; /**< Alternate skip selector 3753232812Sjmallett When enabled (ALT_SKP_EN), selects which of the 3754232812Sjmallett four PIP_ALT_SKIP_CFGx to use with the packets 3755232812Sjmallett arriving on the port-kind. */ 3756232812Sjmallett uint64_t alt_skp_en : 1; /**< Enable the alternate skip selector 3757232812Sjmallett When enabled, the HW is able to recompute the 3758232812Sjmallett SKIP I value based on the packet contents. 3759232812Sjmallett Up to two of the initial 64 bits of the header 3760232812Sjmallett are used along with four PIP_ALT_SKIP_CFGx to 3761232812Sjmallett determine the updated SKIP I value. 3762232812Sjmallett The bits of the packet used should be present in 3763232812Sjmallett all packets. 3764232812Sjmallett PIP_PRT_CFG[DSA_EN,HIGIG_EN] must be disabled 3765232812Sjmallett when ALT_SKP_EN is set. 3766232812Sjmallett ALT_SKP_EN must not be set for DPI ports (32-35) 3767232812Sjmallett when a PKT_INST_HDR is present. 3768232812Sjmallett ALT_SKP_EN should not be enabled for ports which 3769232812Sjmallett have GMX_RX_FRM_CTL[PTP_MODE] set as the timestamp 3770232812Sjmallett will be prepended onto the initial 64 bits of the 3771232812Sjmallett packet. */ 3772232812Sjmallett uint64_t reserved_35_35 : 1; 3773232812Sjmallett uint64_t bsel_num : 2; /**< Which of the 4 bit select extractors to use 3774232812Sjmallett (Alias to PIP_PRT_CFG) */ 3775232812Sjmallett uint64_t bsel_en : 1; /**< Enable to turn on/off use of bit select extractor 3776232812Sjmallett (Alias to PIP_PRT_CFG) */ 3777232812Sjmallett uint64_t reserved_0_31 : 32; 3778232812Sjmallett#else 3779232812Sjmallett uint64_t reserved_0_31 : 32; 3780232812Sjmallett uint64_t bsel_en : 1; 3781232812Sjmallett uint64_t bsel_num : 2; 3782232812Sjmallett uint64_t reserved_35_35 : 1; 3783232812Sjmallett uint64_t alt_skp_en : 1; 3784232812Sjmallett uint64_t alt_skp_sel : 2; 3785232812Sjmallett uint64_t reserved_39_63 : 25; 3786232812Sjmallett#endif 3787232812Sjmallett } cn61xx; 3788232812Sjmallett struct cvmx_pip_prt_cfgbx_cn66xx { 3789232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3790232812Sjmallett uint64_t reserved_39_63 : 25; 3791232812Sjmallett uint64_t alt_skp_sel : 2; /**< Alternate skip selector 3792232812Sjmallett When enabled (ALT_SKP_EN), selects which of the 3793232812Sjmallett four PIP_ALT_SKIP_CFGx to use with the packets 3794232812Sjmallett arriving on the port-kind. */ 3795232812Sjmallett uint64_t alt_skp_en : 1; /**< Enable the alternate skip selector 3796232812Sjmallett When enabled, the HW is able to recompute the 3797232812Sjmallett SKIP I value based on the packet contents. 3798232812Sjmallett Up to two of the initial 64 bits of the header 3799232812Sjmallett are used along with four PIP_ALT_SKIP_CFGx to 3800232812Sjmallett determine the updated SKIP I value. 3801232812Sjmallett The bits of the packet used should be present in 3802232812Sjmallett all packets. 3803232812Sjmallett PIP_PRT_CFG[DSA_EN,HIGIG_EN] must be disabled 3804232812Sjmallett when ALT_SKP_EN is set. 3805232812Sjmallett ALT_SKP_EN must not be set for DPI ports (32-35) 3806232812Sjmallett when a PKT_INST_HDR is present. */ 3807232812Sjmallett uint64_t reserved_0_35 : 36; 3808232812Sjmallett#else 3809232812Sjmallett uint64_t reserved_0_35 : 36; 3810232812Sjmallett uint64_t alt_skp_en : 1; 3811232812Sjmallett uint64_t alt_skp_sel : 2; 3812232812Sjmallett uint64_t reserved_39_63 : 25; 3813232812Sjmallett#endif 3814232812Sjmallett } cn66xx; 3815232812Sjmallett struct cvmx_pip_prt_cfgbx_s cn68xx; 3816232812Sjmallett struct cvmx_pip_prt_cfgbx_cn68xxp1 { 3817232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3818232812Sjmallett uint64_t reserved_24_63 : 40; 3819232812Sjmallett uint64_t base : 8; /**< Base priority address into the table */ 3820232812Sjmallett uint64_t reserved_6_15 : 10; 3821232812Sjmallett uint64_t bpid : 6; /**< Default BPID to use for packets on this port-kind. */ 3822232812Sjmallett#else 3823232812Sjmallett uint64_t bpid : 6; 3824232812Sjmallett uint64_t reserved_6_15 : 10; 3825232812Sjmallett uint64_t base : 8; 3826232812Sjmallett uint64_t reserved_24_63 : 40; 3827232812Sjmallett#endif 3828232812Sjmallett } cn68xxp1; 3829232812Sjmallett struct cvmx_pip_prt_cfgbx_cn61xx cnf71xx; 3830232812Sjmallett}; 3831232812Sjmalletttypedef union cvmx_pip_prt_cfgbx cvmx_pip_prt_cfgbx_t; 3832232812Sjmallett 3833232812Sjmallett/** 3834215976Sjmallett * cvmx_pip_prt_tag# 3835215976Sjmallett * 3836215976Sjmallett * PIP_PRT_TAGX = Per port config information 3837215976Sjmallett * 3838215976Sjmallett */ 3839232812Sjmallettunion cvmx_pip_prt_tagx { 3840215976Sjmallett uint64_t u64; 3841232812Sjmallett struct cvmx_pip_prt_tagx_s { 3842232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3843232812Sjmallett uint64_t reserved_54_63 : 10; 3844232812Sjmallett uint64_t portadd_en : 1; /**< Enables PIP to optionally increment the incoming 3845232812Sjmallett port from the MACs based on port-kind 3846232812Sjmallett configuration and packet contents. */ 3847232812Sjmallett uint64_t inc_hwchk : 1; /**< Include the HW_checksum into WORD0 of the WQE 3848232812Sjmallett instead of the L4PTR. This mode will be 3849232812Sjmallett deprecated in future products. */ 3850232812Sjmallett uint64_t reserved_50_51 : 2; 3851232812Sjmallett uint64_t grptagbase_msb : 2; /**< Most significant 2 bits of the GRPTAGBASE value. */ 3852232812Sjmallett uint64_t reserved_46_47 : 2; 3853232812Sjmallett uint64_t grptagmask_msb : 2; /**< Most significant 2 bits of the GRPTAGMASK value. 3854232812Sjmallett group when GRPTAG is set. */ 3855232812Sjmallett uint64_t reserved_42_43 : 2; 3856232812Sjmallett uint64_t grp_msb : 2; /**< Most significant 2 bits of the 6-bit value 3857232812Sjmallett indicating the group to schedule to. */ 3858215976Sjmallett uint64_t grptagbase : 4; /**< Offset to use when computing group from tag bits 3859215976Sjmallett when GRPTAG is set. */ 3860215976Sjmallett uint64_t grptagmask : 4; /**< Which bits of the tag to exclude when computing 3861215976Sjmallett group when GRPTAG is set. */ 3862215976Sjmallett uint64_t grptag : 1; /**< When set, use the lower bit of the tag to compute 3863215976Sjmallett the group in the work queue entry 3864215976Sjmallett GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */ 3865215976Sjmallett uint64_t grptag_mskip : 1; /**< When set, GRPTAG will be used regardless if the 3866215976Sjmallett packet IS_IP. */ 3867215976Sjmallett uint64_t tag_mode : 2; /**< Which tag algorithm to use 3868215976Sjmallett 0 = always use tuple tag algorithm 3869215976Sjmallett 1 = always use mask tag algorithm 3870215976Sjmallett 2 = if packet is IP, use tuple else use mask 3871215976Sjmallett 3 = tuple XOR mask */ 3872215976Sjmallett uint64_t inc_vs : 2; /**< determines the DSA/VLAN ID (VID) to be included in 3873215976Sjmallett tuple tag when VLAN stacking is detected 3874215976Sjmallett 0 = do not include VID in tuple tag generation 3875215976Sjmallett 1 = include VID (VLAN0) in hash 3876215976Sjmallett 2 = include VID (VLAN1) in hash 3877215976Sjmallett 3 = include VID ([VLAN0,VLAN1]) in hash */ 3878215976Sjmallett uint64_t inc_vlan : 1; /**< when set, the DSA/VLAN ID is included in tuple tag 3879215976Sjmallett when VLAN stacking is not detected 3880215976Sjmallett 0 = do not include VID in tuple tag generation 3881215976Sjmallett 1 = include VID in hash */ 3882215976Sjmallett uint64_t inc_prt_flag : 1; /**< sets whether the port is included in tuple tag */ 3883215976Sjmallett uint64_t ip6_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is 3884215976Sjmallett included in tuple tag for IPv6 packets */ 3885215976Sjmallett uint64_t ip4_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is 3886215976Sjmallett included in tuple tag for IPv4 */ 3887215976Sjmallett uint64_t ip6_sprt_flag : 1; /**< sets whether the TCP/UDP src port is 3888215976Sjmallett included in tuple tag for IPv6 packets */ 3889215976Sjmallett uint64_t ip4_sprt_flag : 1; /**< sets whether the TCP/UDP src port is 3890215976Sjmallett included in tuple tag for IPv4 */ 3891215976Sjmallett uint64_t ip6_nxth_flag : 1; /**< sets whether ipv6 includes next header in tuple 3892215976Sjmallett tag hash */ 3893215976Sjmallett uint64_t ip4_pctl_flag : 1; /**< sets whether ipv4 includes protocol in tuple 3894215976Sjmallett tag hash */ 3895215976Sjmallett uint64_t ip6_dst_flag : 1; /**< sets whether ipv6 includes dst address in tuple 3896215976Sjmallett tag hash */ 3897215976Sjmallett uint64_t ip4_dst_flag : 1; /**< sets whether ipv4 includes dst address in tuple 3898215976Sjmallett tag hash */ 3899215976Sjmallett uint64_t ip6_src_flag : 1; /**< sets whether ipv6 includes src address in tuple 3900215976Sjmallett tag hash */ 3901215976Sjmallett uint64_t ip4_src_flag : 1; /**< sets whether ipv4 includes src address in tuple 3902215976Sjmallett tag hash */ 3903215976Sjmallett cvmx_pow_tag_type_t tcp6_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv6) 3904215976Sjmallett 0 = ordered tags 3905215976Sjmallett 1 = atomic tags 3906215976Sjmallett 2 = Null tags */ 3907215976Sjmallett cvmx_pow_tag_type_t tcp4_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv4) 3908215976Sjmallett 0 = ordered tags 3909215976Sjmallett 1 = atomic tags 3910215976Sjmallett 2 = Null tags */ 3911215976Sjmallett cvmx_pow_tag_type_t ip6_tag_type : 2; /**< sets whether IPv6 packet tag type 3912215976Sjmallett 0 = ordered tags 3913215976Sjmallett 1 = atomic tags 3914215976Sjmallett 2 = Null tags */ 3915215976Sjmallett cvmx_pow_tag_type_t ip4_tag_type : 2; /**< sets whether IPv4 packet tag type 3916215976Sjmallett 0 = ordered tags 3917215976Sjmallett 1 = atomic tags 3918215976Sjmallett 2 = Null tags */ 3919215976Sjmallett cvmx_pow_tag_type_t non_tag_type : 2; /**< sets whether non-IP packet tag type 3920215976Sjmallett 0 = ordered tags 3921215976Sjmallett 1 = atomic tags 3922215976Sjmallett 2 = Null tags */ 3923215976Sjmallett uint64_t grp : 4; /**< 4-bit value indicating the group to schedule to */ 3924215976Sjmallett#else 3925215976Sjmallett uint64_t grp : 4; 3926215976Sjmallett cvmx_pow_tag_type_t non_tag_type : 2; 3927215976Sjmallett cvmx_pow_tag_type_t ip4_tag_type : 2; 3928215976Sjmallett cvmx_pow_tag_type_t ip6_tag_type : 2; 3929215976Sjmallett cvmx_pow_tag_type_t tcp4_tag_type : 2; 3930215976Sjmallett cvmx_pow_tag_type_t tcp6_tag_type : 2; 3931215976Sjmallett uint64_t ip4_src_flag : 1; 3932215976Sjmallett uint64_t ip6_src_flag : 1; 3933215976Sjmallett uint64_t ip4_dst_flag : 1; 3934215976Sjmallett uint64_t ip6_dst_flag : 1; 3935215976Sjmallett uint64_t ip4_pctl_flag : 1; 3936215976Sjmallett uint64_t ip6_nxth_flag : 1; 3937215976Sjmallett uint64_t ip4_sprt_flag : 1; 3938215976Sjmallett uint64_t ip6_sprt_flag : 1; 3939215976Sjmallett uint64_t ip4_dprt_flag : 1; 3940215976Sjmallett uint64_t ip6_dprt_flag : 1; 3941215976Sjmallett uint64_t inc_prt_flag : 1; 3942215976Sjmallett uint64_t inc_vlan : 1; 3943215976Sjmallett uint64_t inc_vs : 2; 3944215976Sjmallett uint64_t tag_mode : 2; 3945215976Sjmallett uint64_t grptag_mskip : 1; 3946215976Sjmallett uint64_t grptag : 1; 3947215976Sjmallett uint64_t grptagmask : 4; 3948215976Sjmallett uint64_t grptagbase : 4; 3949232812Sjmallett uint64_t grp_msb : 2; 3950232812Sjmallett uint64_t reserved_42_43 : 2; 3951232812Sjmallett uint64_t grptagmask_msb : 2; 3952232812Sjmallett uint64_t reserved_46_47 : 2; 3953232812Sjmallett uint64_t grptagbase_msb : 2; 3954232812Sjmallett uint64_t reserved_50_51 : 2; 3955232812Sjmallett uint64_t inc_hwchk : 1; 3956232812Sjmallett uint64_t portadd_en : 1; 3957232812Sjmallett uint64_t reserved_54_63 : 10; 3958215976Sjmallett#endif 3959215976Sjmallett } s; 3960232812Sjmallett struct cvmx_pip_prt_tagx_cn30xx { 3961232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3962215976Sjmallett uint64_t reserved_40_63 : 24; 3963215976Sjmallett uint64_t grptagbase : 4; /**< Offset to use when computing group from tag bits 3964215976Sjmallett when GRPTAG is set. */ 3965215976Sjmallett uint64_t grptagmask : 4; /**< Which bits of the tag to exclude when computing 3966215976Sjmallett group when GRPTAG is set. */ 3967215976Sjmallett uint64_t grptag : 1; /**< When set, use the lower bit of the tag to compute 3968215976Sjmallett the group in the work queue entry 3969215976Sjmallett GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */ 3970215976Sjmallett uint64_t reserved_30_30 : 1; 3971215976Sjmallett uint64_t tag_mode : 2; /**< Which tag algorithm to use 3972215976Sjmallett 0 = always use tuple tag algorithm 3973215976Sjmallett 1 = always use mask tag algorithm 3974215976Sjmallett 2 = if packet is IP, use tuple else use mask 3975215976Sjmallett 3 = tuple XOR mask */ 3976215976Sjmallett uint64_t inc_vs : 2; /**< determines the VLAN ID (VID) to be included in 3977215976Sjmallett tuple tag when VLAN stacking is detected 3978215976Sjmallett 0 = do not include VID in tuple tag generation 3979215976Sjmallett 1 = include VID (VLAN0) in hash 3980215976Sjmallett 2 = include VID (VLAN1) in hash 3981215976Sjmallett 3 = include VID ([VLAN0,VLAN1]) in hash */ 3982215976Sjmallett uint64_t inc_vlan : 1; /**< when set, the VLAN ID is included in tuple tag 3983215976Sjmallett when VLAN stacking is not detected 3984215976Sjmallett 0 = do not include VID in tuple tag generation 3985215976Sjmallett 1 = include VID in hash */ 3986215976Sjmallett uint64_t inc_prt_flag : 1; /**< sets whether the port is included in tuple tag */ 3987215976Sjmallett uint64_t ip6_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is 3988215976Sjmallett included in tuple tag for IPv6 packets */ 3989215976Sjmallett uint64_t ip4_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is 3990215976Sjmallett included in tuple tag for IPv4 */ 3991215976Sjmallett uint64_t ip6_sprt_flag : 1; /**< sets whether the TCP/UDP src port is 3992215976Sjmallett included in tuple tag for IPv6 packets */ 3993215976Sjmallett uint64_t ip4_sprt_flag : 1; /**< sets whether the TCP/UDP src port is 3994215976Sjmallett included in tuple tag for IPv4 */ 3995215976Sjmallett uint64_t ip6_nxth_flag : 1; /**< sets whether ipv6 includes next header in tuple 3996215976Sjmallett tag hash */ 3997215976Sjmallett uint64_t ip4_pctl_flag : 1; /**< sets whether ipv4 includes protocol in tuple 3998215976Sjmallett tag hash */ 3999215976Sjmallett uint64_t ip6_dst_flag : 1; /**< sets whether ipv6 includes dst address in tuple 4000215976Sjmallett tag hash */ 4001215976Sjmallett uint64_t ip4_dst_flag : 1; /**< sets whether ipv4 includes dst address in tuple 4002215976Sjmallett tag hash */ 4003215976Sjmallett uint64_t ip6_src_flag : 1; /**< sets whether ipv6 includes src address in tuple 4004215976Sjmallett tag hash */ 4005215976Sjmallett uint64_t ip4_src_flag : 1; /**< sets whether ipv4 includes src address in tuple 4006215976Sjmallett tag hash */ 4007215976Sjmallett cvmx_pow_tag_type_t tcp6_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv6) 4008215976Sjmallett 0 = ordered tags 4009215976Sjmallett 1 = atomic tags 4010215976Sjmallett 2 = Null tags */ 4011215976Sjmallett cvmx_pow_tag_type_t tcp4_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv4) 4012215976Sjmallett 0 = ordered tags 4013215976Sjmallett 1 = atomic tags 4014215976Sjmallett 2 = Null tags */ 4015215976Sjmallett cvmx_pow_tag_type_t ip6_tag_type : 2; /**< sets whether IPv6 packet tag type 4016215976Sjmallett 0 = ordered tags 4017215976Sjmallett 1 = atomic tags 4018215976Sjmallett 2 = Null tags */ 4019215976Sjmallett cvmx_pow_tag_type_t ip4_tag_type : 2; /**< sets whether IPv4 packet tag type 4020215976Sjmallett 0 = ordered tags 4021215976Sjmallett 1 = atomic tags 4022215976Sjmallett 2 = Null tags */ 4023215976Sjmallett cvmx_pow_tag_type_t non_tag_type : 2; /**< sets whether non-IP packet tag type 4024215976Sjmallett 0 = ordered tags 4025215976Sjmallett 1 = atomic tags 4026215976Sjmallett 2 = Null tags */ 4027215976Sjmallett uint64_t grp : 4; /**< 4-bit value indicating the group to schedule to */ 4028215976Sjmallett#else 4029215976Sjmallett uint64_t grp : 4; 4030215976Sjmallett cvmx_pow_tag_type_t non_tag_type : 2; 4031215976Sjmallett cvmx_pow_tag_type_t ip4_tag_type : 2; 4032215976Sjmallett cvmx_pow_tag_type_t ip6_tag_type : 2; 4033215976Sjmallett cvmx_pow_tag_type_t tcp4_tag_type : 2; 4034215976Sjmallett cvmx_pow_tag_type_t tcp6_tag_type : 2; 4035215976Sjmallett uint64_t ip4_src_flag : 1; 4036215976Sjmallett uint64_t ip6_src_flag : 1; 4037215976Sjmallett uint64_t ip4_dst_flag : 1; 4038215976Sjmallett uint64_t ip6_dst_flag : 1; 4039215976Sjmallett uint64_t ip4_pctl_flag : 1; 4040215976Sjmallett uint64_t ip6_nxth_flag : 1; 4041215976Sjmallett uint64_t ip4_sprt_flag : 1; 4042215976Sjmallett uint64_t ip6_sprt_flag : 1; 4043215976Sjmallett uint64_t ip4_dprt_flag : 1; 4044215976Sjmallett uint64_t ip6_dprt_flag : 1; 4045215976Sjmallett uint64_t inc_prt_flag : 1; 4046215976Sjmallett uint64_t inc_vlan : 1; 4047215976Sjmallett uint64_t inc_vs : 2; 4048215976Sjmallett uint64_t tag_mode : 2; 4049215976Sjmallett uint64_t reserved_30_30 : 1; 4050215976Sjmallett uint64_t grptag : 1; 4051215976Sjmallett uint64_t grptagmask : 4; 4052215976Sjmallett uint64_t grptagbase : 4; 4053215976Sjmallett uint64_t reserved_40_63 : 24; 4054215976Sjmallett#endif 4055215976Sjmallett } cn30xx; 4056215976Sjmallett struct cvmx_pip_prt_tagx_cn30xx cn31xx; 4057215976Sjmallett struct cvmx_pip_prt_tagx_cn30xx cn38xx; 4058215976Sjmallett struct cvmx_pip_prt_tagx_cn30xx cn38xxp2; 4059232812Sjmallett struct cvmx_pip_prt_tagx_cn50xx { 4060232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4061232812Sjmallett uint64_t reserved_40_63 : 24; 4062232812Sjmallett uint64_t grptagbase : 4; /**< Offset to use when computing group from tag bits 4063232812Sjmallett when GRPTAG is set. */ 4064232812Sjmallett uint64_t grptagmask : 4; /**< Which bits of the tag to exclude when computing 4065232812Sjmallett group when GRPTAG is set. */ 4066232812Sjmallett uint64_t grptag : 1; /**< When set, use the lower bit of the tag to compute 4067232812Sjmallett the group in the work queue entry 4068232812Sjmallett GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE */ 4069232812Sjmallett uint64_t grptag_mskip : 1; /**< When set, GRPTAG will be used regardless if the 4070232812Sjmallett packet IS_IP. */ 4071232812Sjmallett uint64_t tag_mode : 2; /**< Which tag algorithm to use 4072232812Sjmallett 0 = always use tuple tag algorithm 4073232812Sjmallett 1 = always use mask tag algorithm 4074232812Sjmallett 2 = if packet is IP, use tuple else use mask 4075232812Sjmallett 3 = tuple XOR mask */ 4076232812Sjmallett uint64_t inc_vs : 2; /**< determines the VLAN ID (VID) to be included in 4077232812Sjmallett tuple tag when VLAN stacking is detected 4078232812Sjmallett 0 = do not include VID in tuple tag generation 4079232812Sjmallett 1 = include VID (VLAN0) in hash 4080232812Sjmallett 2 = include VID (VLAN1) in hash 4081232812Sjmallett 3 = include VID ([VLAN0,VLAN1]) in hash */ 4082232812Sjmallett uint64_t inc_vlan : 1; /**< when set, the VLAN ID is included in tuple tag 4083232812Sjmallett when VLAN stacking is not detected 4084232812Sjmallett 0 = do not include VID in tuple tag generation 4085232812Sjmallett 1 = include VID in hash */ 4086232812Sjmallett uint64_t inc_prt_flag : 1; /**< sets whether the port is included in tuple tag */ 4087232812Sjmallett uint64_t ip6_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is 4088232812Sjmallett included in tuple tag for IPv6 packets */ 4089232812Sjmallett uint64_t ip4_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is 4090232812Sjmallett included in tuple tag for IPv4 */ 4091232812Sjmallett uint64_t ip6_sprt_flag : 1; /**< sets whether the TCP/UDP src port is 4092232812Sjmallett included in tuple tag for IPv6 packets */ 4093232812Sjmallett uint64_t ip4_sprt_flag : 1; /**< sets whether the TCP/UDP src port is 4094232812Sjmallett included in tuple tag for IPv4 */ 4095232812Sjmallett uint64_t ip6_nxth_flag : 1; /**< sets whether ipv6 includes next header in tuple 4096232812Sjmallett tag hash */ 4097232812Sjmallett uint64_t ip4_pctl_flag : 1; /**< sets whether ipv4 includes protocol in tuple 4098232812Sjmallett tag hash */ 4099232812Sjmallett uint64_t ip6_dst_flag : 1; /**< sets whether ipv6 includes dst address in tuple 4100232812Sjmallett tag hash */ 4101232812Sjmallett uint64_t ip4_dst_flag : 1; /**< sets whether ipv4 includes dst address in tuple 4102232812Sjmallett tag hash */ 4103232812Sjmallett uint64_t ip6_src_flag : 1; /**< sets whether ipv6 includes src address in tuple 4104232812Sjmallett tag hash */ 4105232812Sjmallett uint64_t ip4_src_flag : 1; /**< sets whether ipv4 includes src address in tuple 4106232812Sjmallett tag hash */ 4107232812Sjmallett cvmx_pow_tag_type_t tcp6_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv6) 4108232812Sjmallett 0 = ordered tags 4109232812Sjmallett 1 = atomic tags 4110232812Sjmallett 2 = Null tags */ 4111232812Sjmallett cvmx_pow_tag_type_t tcp4_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv4) 4112232812Sjmallett 0 = ordered tags 4113232812Sjmallett 1 = atomic tags 4114232812Sjmallett 2 = Null tags */ 4115232812Sjmallett cvmx_pow_tag_type_t ip6_tag_type : 2; /**< sets whether IPv6 packet tag type 4116232812Sjmallett 0 = ordered tags 4117232812Sjmallett 1 = atomic tags 4118232812Sjmallett 2 = Null tags */ 4119232812Sjmallett cvmx_pow_tag_type_t ip4_tag_type : 2; /**< sets whether IPv4 packet tag type 4120232812Sjmallett 0 = ordered tags 4121232812Sjmallett 1 = atomic tags 4122232812Sjmallett 2 = Null tags */ 4123232812Sjmallett cvmx_pow_tag_type_t non_tag_type : 2; /**< sets whether non-IP packet tag type 4124232812Sjmallett 0 = ordered tags 4125232812Sjmallett 1 = atomic tags 4126232812Sjmallett 2 = Null tags */ 4127232812Sjmallett uint64_t grp : 4; /**< 4-bit value indicating the group to schedule to */ 4128232812Sjmallett#else 4129232812Sjmallett uint64_t grp : 4; 4130232812Sjmallett cvmx_pow_tag_type_t non_tag_type : 2; 4131232812Sjmallett cvmx_pow_tag_type_t ip4_tag_type : 2; 4132232812Sjmallett cvmx_pow_tag_type_t ip6_tag_type : 2; 4133232812Sjmallett cvmx_pow_tag_type_t tcp4_tag_type : 2; 4134232812Sjmallett cvmx_pow_tag_type_t tcp6_tag_type : 2; 4135232812Sjmallett uint64_t ip4_src_flag : 1; 4136232812Sjmallett uint64_t ip6_src_flag : 1; 4137232812Sjmallett uint64_t ip4_dst_flag : 1; 4138232812Sjmallett uint64_t ip6_dst_flag : 1; 4139232812Sjmallett uint64_t ip4_pctl_flag : 1; 4140232812Sjmallett uint64_t ip6_nxth_flag : 1; 4141232812Sjmallett uint64_t ip4_sprt_flag : 1; 4142232812Sjmallett uint64_t ip6_sprt_flag : 1; 4143232812Sjmallett uint64_t ip4_dprt_flag : 1; 4144232812Sjmallett uint64_t ip6_dprt_flag : 1; 4145232812Sjmallett uint64_t inc_prt_flag : 1; 4146232812Sjmallett uint64_t inc_vlan : 1; 4147232812Sjmallett uint64_t inc_vs : 2; 4148232812Sjmallett uint64_t tag_mode : 2; 4149232812Sjmallett uint64_t grptag_mskip : 1; 4150232812Sjmallett uint64_t grptag : 1; 4151232812Sjmallett uint64_t grptagmask : 4; 4152232812Sjmallett uint64_t grptagbase : 4; 4153232812Sjmallett uint64_t reserved_40_63 : 24; 4154232812Sjmallett#endif 4155232812Sjmallett } cn50xx; 4156232812Sjmallett struct cvmx_pip_prt_tagx_cn50xx cn52xx; 4157232812Sjmallett struct cvmx_pip_prt_tagx_cn50xx cn52xxp1; 4158232812Sjmallett struct cvmx_pip_prt_tagx_cn50xx cn56xx; 4159232812Sjmallett struct cvmx_pip_prt_tagx_cn50xx cn56xxp1; 4160215976Sjmallett struct cvmx_pip_prt_tagx_cn30xx cn58xx; 4161215976Sjmallett struct cvmx_pip_prt_tagx_cn30xx cn58xxp1; 4162232812Sjmallett struct cvmx_pip_prt_tagx_cn50xx cn61xx; 4163232812Sjmallett struct cvmx_pip_prt_tagx_cn50xx cn63xx; 4164232812Sjmallett struct cvmx_pip_prt_tagx_cn50xx cn63xxp1; 4165232812Sjmallett struct cvmx_pip_prt_tagx_cn50xx cn66xx; 4166232812Sjmallett struct cvmx_pip_prt_tagx_s cn68xx; 4167232812Sjmallett struct cvmx_pip_prt_tagx_s cn68xxp1; 4168232812Sjmallett struct cvmx_pip_prt_tagx_cn50xx cnf71xx; 4169215976Sjmallett}; 4170215976Sjmalletttypedef union cvmx_pip_prt_tagx cvmx_pip_prt_tagx_t; 4171215976Sjmallett 4172215976Sjmallett/** 4173215976Sjmallett * cvmx_pip_qos_diff# 4174215976Sjmallett * 4175215976Sjmallett * PIP_QOS_DIFFX = QOS Diffserv Tables 4176215976Sjmallett * 4177215976Sjmallett */ 4178232812Sjmallettunion cvmx_pip_qos_diffx { 4179215976Sjmallett uint64_t u64; 4180232812Sjmallett struct cvmx_pip_qos_diffx_s { 4181232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4182215976Sjmallett uint64_t reserved_3_63 : 61; 4183215976Sjmallett uint64_t qos : 3; /**< Diffserv QOS level */ 4184215976Sjmallett#else 4185215976Sjmallett uint64_t qos : 3; 4186215976Sjmallett uint64_t reserved_3_63 : 61; 4187215976Sjmallett#endif 4188215976Sjmallett } s; 4189215976Sjmallett struct cvmx_pip_qos_diffx_s cn30xx; 4190215976Sjmallett struct cvmx_pip_qos_diffx_s cn31xx; 4191215976Sjmallett struct cvmx_pip_qos_diffx_s cn38xx; 4192215976Sjmallett struct cvmx_pip_qos_diffx_s cn38xxp2; 4193215976Sjmallett struct cvmx_pip_qos_diffx_s cn50xx; 4194215976Sjmallett struct cvmx_pip_qos_diffx_s cn52xx; 4195215976Sjmallett struct cvmx_pip_qos_diffx_s cn52xxp1; 4196215976Sjmallett struct cvmx_pip_qos_diffx_s cn56xx; 4197215976Sjmallett struct cvmx_pip_qos_diffx_s cn56xxp1; 4198215976Sjmallett struct cvmx_pip_qos_diffx_s cn58xx; 4199215976Sjmallett struct cvmx_pip_qos_diffx_s cn58xxp1; 4200232812Sjmallett struct cvmx_pip_qos_diffx_s cn61xx; 4201215976Sjmallett struct cvmx_pip_qos_diffx_s cn63xx; 4202215976Sjmallett struct cvmx_pip_qos_diffx_s cn63xxp1; 4203232812Sjmallett struct cvmx_pip_qos_diffx_s cn66xx; 4204232812Sjmallett struct cvmx_pip_qos_diffx_s cnf71xx; 4205215976Sjmallett}; 4206215976Sjmalletttypedef union cvmx_pip_qos_diffx cvmx_pip_qos_diffx_t; 4207215976Sjmallett 4208215976Sjmallett/** 4209215976Sjmallett * cvmx_pip_qos_vlan# 4210215976Sjmallett * 4211215976Sjmallett * PIP_QOS_VLANX = QOS VLAN Tables 4212215976Sjmallett * 4213215976Sjmallett * If the PIP indentifies a packet is DSA/VLAN tagged, then the QOS 4214215976Sjmallett * can be set based on the DSA/VLAN user priority. These eight register 4215215976Sjmallett * comprise the QOS values for all DSA/VLAN user priority values. 4216215976Sjmallett */ 4217232812Sjmallettunion cvmx_pip_qos_vlanx { 4218215976Sjmallett uint64_t u64; 4219232812Sjmallett struct cvmx_pip_qos_vlanx_s { 4220232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4221215976Sjmallett uint64_t reserved_7_63 : 57; 4222215976Sjmallett uint64_t qos1 : 3; /**< DSA/VLAN QOS level 4223215976Sjmallett Selected when PIP_PRT_CFGx[QOS_VSEL] = 1 */ 4224215976Sjmallett uint64_t reserved_3_3 : 1; 4225215976Sjmallett uint64_t qos : 3; /**< DSA/VLAN QOS level 4226215976Sjmallett Selected when PIP_PRT_CFGx[QOS_VSEL] = 0 */ 4227215976Sjmallett#else 4228215976Sjmallett uint64_t qos : 3; 4229215976Sjmallett uint64_t reserved_3_3 : 1; 4230215976Sjmallett uint64_t qos1 : 3; 4231215976Sjmallett uint64_t reserved_7_63 : 57; 4232215976Sjmallett#endif 4233215976Sjmallett } s; 4234232812Sjmallett struct cvmx_pip_qos_vlanx_cn30xx { 4235232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4236215976Sjmallett uint64_t reserved_3_63 : 61; 4237215976Sjmallett uint64_t qos : 3; /**< VLAN QOS level */ 4238215976Sjmallett#else 4239215976Sjmallett uint64_t qos : 3; 4240215976Sjmallett uint64_t reserved_3_63 : 61; 4241215976Sjmallett#endif 4242215976Sjmallett } cn30xx; 4243215976Sjmallett struct cvmx_pip_qos_vlanx_cn30xx cn31xx; 4244215976Sjmallett struct cvmx_pip_qos_vlanx_cn30xx cn38xx; 4245215976Sjmallett struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2; 4246215976Sjmallett struct cvmx_pip_qos_vlanx_cn30xx cn50xx; 4247215976Sjmallett struct cvmx_pip_qos_vlanx_s cn52xx; 4248215976Sjmallett struct cvmx_pip_qos_vlanx_s cn52xxp1; 4249215976Sjmallett struct cvmx_pip_qos_vlanx_s cn56xx; 4250215976Sjmallett struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1; 4251215976Sjmallett struct cvmx_pip_qos_vlanx_cn30xx cn58xx; 4252215976Sjmallett struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1; 4253232812Sjmallett struct cvmx_pip_qos_vlanx_s cn61xx; 4254215976Sjmallett struct cvmx_pip_qos_vlanx_s cn63xx; 4255215976Sjmallett struct cvmx_pip_qos_vlanx_s cn63xxp1; 4256232812Sjmallett struct cvmx_pip_qos_vlanx_s cn66xx; 4257232812Sjmallett struct cvmx_pip_qos_vlanx_s cnf71xx; 4258215976Sjmallett}; 4259215976Sjmalletttypedef union cvmx_pip_qos_vlanx cvmx_pip_qos_vlanx_t; 4260215976Sjmallett 4261215976Sjmallett/** 4262215976Sjmallett * cvmx_pip_qos_watch# 4263215976Sjmallett * 4264215976Sjmallett * PIP_QOS_WATCHX = QOS Watcher Tables 4265215976Sjmallett * 4266215976Sjmallett * Sets up the Configuration CSRs for the four QOS Watchers. 4267215976Sjmallett * Each Watcher can be set to look for a specific protocol, 4268215976Sjmallett * TCP/UDP destination port, or Ethertype to override the 4269215976Sjmallett * default QOS value. 4270215976Sjmallett */ 4271232812Sjmallettunion cvmx_pip_qos_watchx { 4272215976Sjmallett uint64_t u64; 4273232812Sjmallett struct cvmx_pip_qos_watchx_s { 4274232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4275215976Sjmallett uint64_t reserved_48_63 : 16; 4276215976Sjmallett uint64_t mask : 16; /**< Mask off a range of values */ 4277232812Sjmallett uint64_t reserved_30_31 : 2; 4278232812Sjmallett uint64_t grp : 6; /**< The GRP number of the watcher */ 4279215976Sjmallett uint64_t reserved_23_23 : 1; 4280215976Sjmallett uint64_t qos : 3; /**< The QOS level of the watcher */ 4281215976Sjmallett uint64_t reserved_19_19 : 1; 4282215976Sjmallett cvmx_pip_qos_watch_types match_type : 3; /**< The field for the watcher match against 4283215976Sjmallett 0 = disable across all ports 4284215976Sjmallett 1 = protocol (ipv4) 4285215976Sjmallett = next_header (ipv6) 4286215976Sjmallett 2 = TCP destination port 4287215976Sjmallett 3 = UDP destination port 4288215976Sjmallett 4 = Ether type 4289215976Sjmallett 5-7 = Reserved */ 4290215976Sjmallett uint64_t match_value : 16; /**< The value to watch for */ 4291215976Sjmallett#else 4292215976Sjmallett uint64_t match_value : 16; 4293215976Sjmallett cvmx_pip_qos_watch_types match_type : 3; 4294215976Sjmallett uint64_t reserved_19_19 : 1; 4295215976Sjmallett uint64_t qos : 3; 4296215976Sjmallett uint64_t reserved_23_23 : 1; 4297232812Sjmallett uint64_t grp : 6; 4298232812Sjmallett uint64_t reserved_30_31 : 2; 4299215976Sjmallett uint64_t mask : 16; 4300215976Sjmallett uint64_t reserved_48_63 : 16; 4301215976Sjmallett#endif 4302215976Sjmallett } s; 4303232812Sjmallett struct cvmx_pip_qos_watchx_cn30xx { 4304232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4305215976Sjmallett uint64_t reserved_48_63 : 16; 4306215976Sjmallett uint64_t mask : 16; /**< Mask off a range of values */ 4307215976Sjmallett uint64_t reserved_28_31 : 4; 4308215976Sjmallett uint64_t grp : 4; /**< The GRP number of the watcher */ 4309215976Sjmallett uint64_t reserved_23_23 : 1; 4310215976Sjmallett uint64_t qos : 3; /**< The QOS level of the watcher */ 4311215976Sjmallett uint64_t reserved_18_19 : 2; 4312215976Sjmallett cvmx_pip_qos_watch_types match_type : 2; /**< The field for the watcher match against 4313215976Sjmallett 0 = disable across all ports 4314215976Sjmallett 1 = protocol (ipv4) 4315215976Sjmallett = next_header (ipv6) 4316215976Sjmallett 2 = TCP destination port 4317215976Sjmallett 3 = UDP destination port */ 4318215976Sjmallett uint64_t match_value : 16; /**< The value to watch for */ 4319215976Sjmallett#else 4320215976Sjmallett uint64_t match_value : 16; 4321215976Sjmallett cvmx_pip_qos_watch_types match_type : 2; 4322215976Sjmallett uint64_t reserved_18_19 : 2; 4323215976Sjmallett uint64_t qos : 3; 4324215976Sjmallett uint64_t reserved_23_23 : 1; 4325215976Sjmallett uint64_t grp : 4; 4326215976Sjmallett uint64_t reserved_28_31 : 4; 4327215976Sjmallett uint64_t mask : 16; 4328215976Sjmallett uint64_t reserved_48_63 : 16; 4329215976Sjmallett#endif 4330215976Sjmallett } cn30xx; 4331215976Sjmallett struct cvmx_pip_qos_watchx_cn30xx cn31xx; 4332215976Sjmallett struct cvmx_pip_qos_watchx_cn30xx cn38xx; 4333215976Sjmallett struct cvmx_pip_qos_watchx_cn30xx cn38xxp2; 4334232812Sjmallett struct cvmx_pip_qos_watchx_cn50xx { 4335232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4336232812Sjmallett uint64_t reserved_48_63 : 16; 4337232812Sjmallett uint64_t mask : 16; /**< Mask off a range of values */ 4338232812Sjmallett uint64_t reserved_28_31 : 4; 4339232812Sjmallett uint64_t grp : 4; /**< The GRP number of the watcher */ 4340232812Sjmallett uint64_t reserved_23_23 : 1; 4341232812Sjmallett uint64_t qos : 3; /**< The QOS level of the watcher */ 4342232812Sjmallett uint64_t reserved_19_19 : 1; 4343232812Sjmallett cvmx_pip_qos_watch_types match_type : 3; /**< The field for the watcher match against 4344232812Sjmallett 0 = disable across all ports 4345232812Sjmallett 1 = protocol (ipv4) 4346232812Sjmallett = next_header (ipv6) 4347232812Sjmallett 2 = TCP destination port 4348232812Sjmallett 3 = UDP destination port 4349232812Sjmallett 4 = Ether type 4350232812Sjmallett 5-7 = Reserved */ 4351232812Sjmallett uint64_t match_value : 16; /**< The value to watch for */ 4352232812Sjmallett#else 4353232812Sjmallett uint64_t match_value : 16; 4354232812Sjmallett cvmx_pip_qos_watch_types match_type : 3; 4355232812Sjmallett uint64_t reserved_19_19 : 1; 4356232812Sjmallett uint64_t qos : 3; 4357232812Sjmallett uint64_t reserved_23_23 : 1; 4358232812Sjmallett uint64_t grp : 4; 4359232812Sjmallett uint64_t reserved_28_31 : 4; 4360232812Sjmallett uint64_t mask : 16; 4361232812Sjmallett uint64_t reserved_48_63 : 16; 4362232812Sjmallett#endif 4363232812Sjmallett } cn50xx; 4364232812Sjmallett struct cvmx_pip_qos_watchx_cn50xx cn52xx; 4365232812Sjmallett struct cvmx_pip_qos_watchx_cn50xx cn52xxp1; 4366232812Sjmallett struct cvmx_pip_qos_watchx_cn50xx cn56xx; 4367232812Sjmallett struct cvmx_pip_qos_watchx_cn50xx cn56xxp1; 4368215976Sjmallett struct cvmx_pip_qos_watchx_cn30xx cn58xx; 4369215976Sjmallett struct cvmx_pip_qos_watchx_cn30xx cn58xxp1; 4370232812Sjmallett struct cvmx_pip_qos_watchx_cn50xx cn61xx; 4371232812Sjmallett struct cvmx_pip_qos_watchx_cn50xx cn63xx; 4372232812Sjmallett struct cvmx_pip_qos_watchx_cn50xx cn63xxp1; 4373232812Sjmallett struct cvmx_pip_qos_watchx_cn50xx cn66xx; 4374232812Sjmallett struct cvmx_pip_qos_watchx_s cn68xx; 4375232812Sjmallett struct cvmx_pip_qos_watchx_s cn68xxp1; 4376232812Sjmallett struct cvmx_pip_qos_watchx_cn50xx cnf71xx; 4377215976Sjmallett}; 4378215976Sjmalletttypedef union cvmx_pip_qos_watchx cvmx_pip_qos_watchx_t; 4379215976Sjmallett 4380215976Sjmallett/** 4381215976Sjmallett * cvmx_pip_raw_word 4382215976Sjmallett * 4383215976Sjmallett * PIP_RAW_WORD = The RAW Word2 of the workQ entry. 4384215976Sjmallett * 4385215976Sjmallett * The RAW Word2 to be inserted into the workQ entry of RAWFULL packets. 4386215976Sjmallett */ 4387232812Sjmallettunion cvmx_pip_raw_word { 4388215976Sjmallett uint64_t u64; 4389232812Sjmallett struct cvmx_pip_raw_word_s { 4390232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4391215976Sjmallett uint64_t reserved_56_63 : 8; 4392215976Sjmallett uint64_t word : 56; /**< Word2 of the workQ entry 4393215976Sjmallett The 8-bit bufs field is still set by HW (IPD) */ 4394215976Sjmallett#else 4395215976Sjmallett uint64_t word : 56; 4396215976Sjmallett uint64_t reserved_56_63 : 8; 4397215976Sjmallett#endif 4398215976Sjmallett } s; 4399215976Sjmallett struct cvmx_pip_raw_word_s cn30xx; 4400215976Sjmallett struct cvmx_pip_raw_word_s cn31xx; 4401215976Sjmallett struct cvmx_pip_raw_word_s cn38xx; 4402215976Sjmallett struct cvmx_pip_raw_word_s cn38xxp2; 4403215976Sjmallett struct cvmx_pip_raw_word_s cn50xx; 4404215976Sjmallett struct cvmx_pip_raw_word_s cn52xx; 4405215976Sjmallett struct cvmx_pip_raw_word_s cn52xxp1; 4406215976Sjmallett struct cvmx_pip_raw_word_s cn56xx; 4407215976Sjmallett struct cvmx_pip_raw_word_s cn56xxp1; 4408215976Sjmallett struct cvmx_pip_raw_word_s cn58xx; 4409215976Sjmallett struct cvmx_pip_raw_word_s cn58xxp1; 4410232812Sjmallett struct cvmx_pip_raw_word_s cn61xx; 4411215976Sjmallett struct cvmx_pip_raw_word_s cn63xx; 4412215976Sjmallett struct cvmx_pip_raw_word_s cn63xxp1; 4413232812Sjmallett struct cvmx_pip_raw_word_s cn66xx; 4414232812Sjmallett struct cvmx_pip_raw_word_s cn68xx; 4415232812Sjmallett struct cvmx_pip_raw_word_s cn68xxp1; 4416232812Sjmallett struct cvmx_pip_raw_word_s cnf71xx; 4417215976Sjmallett}; 4418215976Sjmalletttypedef union cvmx_pip_raw_word cvmx_pip_raw_word_t; 4419215976Sjmallett 4420215976Sjmallett/** 4421215976Sjmallett * cvmx_pip_sft_rst 4422215976Sjmallett * 4423215976Sjmallett * PIP_SFT_RST = PIP Soft Reset 4424215976Sjmallett * 4425215976Sjmallett * When written to a '1', resets the pip block 4426215976Sjmallett * 4427215976Sjmallett * Notes: 4428215976Sjmallett * When RST is set to a '1' by SW, PIP will get a short reset pulse (3 cycles 4429215976Sjmallett * in duration). Although this will reset much of PIP's internal state, some 4430215976Sjmallett * CSRs will not reset. 4431215976Sjmallett * 4432215976Sjmallett * . PIP_BIST_STATUS 4433215976Sjmallett * . PIP_STAT0_PRT* 4434215976Sjmallett * . PIP_STAT1_PRT* 4435215976Sjmallett * . PIP_STAT2_PRT* 4436215976Sjmallett * . PIP_STAT3_PRT* 4437215976Sjmallett * . PIP_STAT4_PRT* 4438215976Sjmallett * . PIP_STAT5_PRT* 4439215976Sjmallett * . PIP_STAT6_PRT* 4440215976Sjmallett * . PIP_STAT7_PRT* 4441215976Sjmallett * . PIP_STAT8_PRT* 4442215976Sjmallett * . PIP_STAT9_PRT* 4443215976Sjmallett * . PIP_XSTAT0_PRT* 4444215976Sjmallett * . PIP_XSTAT1_PRT* 4445215976Sjmallett * . PIP_XSTAT2_PRT* 4446215976Sjmallett * . PIP_XSTAT3_PRT* 4447215976Sjmallett * . PIP_XSTAT4_PRT* 4448215976Sjmallett * . PIP_XSTAT5_PRT* 4449215976Sjmallett * . PIP_XSTAT6_PRT* 4450215976Sjmallett * . PIP_XSTAT7_PRT* 4451215976Sjmallett * . PIP_XSTAT8_PRT* 4452215976Sjmallett * . PIP_XSTAT9_PRT* 4453215976Sjmallett * . PIP_STAT_INB_PKTS* 4454215976Sjmallett * . PIP_STAT_INB_OCTS* 4455215976Sjmallett * . PIP_STAT_INB_ERRS* 4456215976Sjmallett * . PIP_TAG_INC* 4457215976Sjmallett */ 4458232812Sjmallettunion cvmx_pip_sft_rst { 4459215976Sjmallett uint64_t u64; 4460232812Sjmallett struct cvmx_pip_sft_rst_s { 4461232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4462215976Sjmallett uint64_t reserved_1_63 : 63; 4463215976Sjmallett uint64_t rst : 1; /**< Soft Reset */ 4464215976Sjmallett#else 4465215976Sjmallett uint64_t rst : 1; 4466215976Sjmallett uint64_t reserved_1_63 : 63; 4467215976Sjmallett#endif 4468215976Sjmallett } s; 4469215976Sjmallett struct cvmx_pip_sft_rst_s cn30xx; 4470215976Sjmallett struct cvmx_pip_sft_rst_s cn31xx; 4471215976Sjmallett struct cvmx_pip_sft_rst_s cn38xx; 4472215976Sjmallett struct cvmx_pip_sft_rst_s cn50xx; 4473215976Sjmallett struct cvmx_pip_sft_rst_s cn52xx; 4474215976Sjmallett struct cvmx_pip_sft_rst_s cn52xxp1; 4475215976Sjmallett struct cvmx_pip_sft_rst_s cn56xx; 4476215976Sjmallett struct cvmx_pip_sft_rst_s cn56xxp1; 4477215976Sjmallett struct cvmx_pip_sft_rst_s cn58xx; 4478215976Sjmallett struct cvmx_pip_sft_rst_s cn58xxp1; 4479232812Sjmallett struct cvmx_pip_sft_rst_s cn61xx; 4480215976Sjmallett struct cvmx_pip_sft_rst_s cn63xx; 4481215976Sjmallett struct cvmx_pip_sft_rst_s cn63xxp1; 4482232812Sjmallett struct cvmx_pip_sft_rst_s cn66xx; 4483232812Sjmallett struct cvmx_pip_sft_rst_s cn68xx; 4484232812Sjmallett struct cvmx_pip_sft_rst_s cn68xxp1; 4485232812Sjmallett struct cvmx_pip_sft_rst_s cnf71xx; 4486215976Sjmallett}; 4487215976Sjmalletttypedef union cvmx_pip_sft_rst cvmx_pip_sft_rst_t; 4488215976Sjmallett 4489215976Sjmallett/** 4490232812Sjmallett * cvmx_pip_stat0_# 4491232812Sjmallett * 4492232812Sjmallett * PIP Statistics Counters 4493232812Sjmallett * 4494232812Sjmallett * Note: special stat counter behavior 4495232812Sjmallett * 4496232812Sjmallett * 1) Read and write operations must arbitrate for the statistics resources 4497232812Sjmallett * along with the packet engines which are incrementing the counters. 4498232812Sjmallett * In order to not drop packet information, the packet HW is always a 4499232812Sjmallett * higher priority and the CSR requests will only be satisified when 4500232812Sjmallett * there are idle cycles. This can potentially cause long delays if the 4501232812Sjmallett * system becomes full. 4502232812Sjmallett * 4503232812Sjmallett * 2) stat counters can be cleared in two ways. If PIP_STAT_CTL[RDCLR] is 4504232812Sjmallett * set, then all read accesses will clear the register. In addition, 4505232812Sjmallett * any write to a stats register will also reset the register to zero. 4506232812Sjmallett * Please note that the clearing operations must obey rule \#1 above. 4507232812Sjmallett * 4508232812Sjmallett * 3) all counters are wrapping - software must ensure they are read periodically 4509232812Sjmallett * 4510232812Sjmallett * 4) The counters accumulate statistics for packets that are sent to PKI. If 4511232812Sjmallett * PTP_MODE is enabled, the 8B timestamp is prepended to the packet. This 4512232812Sjmallett * additional 8B of data is captured in the octet counts. 4513232812Sjmallett * 4514232812Sjmallett * 5) X represents either the packet's port-kind or backpressure ID as 4515232812Sjmallett * determined by PIP_STAT_CTL[MODE] 4516232812Sjmallett * PIP_STAT0_X = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS 4517232812Sjmallett */ 4518232812Sjmallettunion cvmx_pip_stat0_x { 4519232812Sjmallett uint64_t u64; 4520232812Sjmallett struct cvmx_pip_stat0_x_s { 4521232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4522232812Sjmallett uint64_t drp_pkts : 32; /**< Inbound packets marked to be dropped by the IPD 4523232812Sjmallett QOS widget per port */ 4524232812Sjmallett uint64_t drp_octs : 32; /**< Inbound octets marked to be dropped by the IPD 4525232812Sjmallett QOS widget per port */ 4526232812Sjmallett#else 4527232812Sjmallett uint64_t drp_octs : 32; 4528232812Sjmallett uint64_t drp_pkts : 32; 4529232812Sjmallett#endif 4530232812Sjmallett } s; 4531232812Sjmallett struct cvmx_pip_stat0_x_s cn68xx; 4532232812Sjmallett struct cvmx_pip_stat0_x_s cn68xxp1; 4533232812Sjmallett}; 4534232812Sjmalletttypedef union cvmx_pip_stat0_x cvmx_pip_stat0_x_t; 4535232812Sjmallett 4536232812Sjmallett/** 4537215976Sjmallett * cvmx_pip_stat0_prt# 4538215976Sjmallett * 4539215976Sjmallett * PIP Statistics Counters 4540215976Sjmallett * 4541215976Sjmallett * Note: special stat counter behavior 4542215976Sjmallett * 4543215976Sjmallett * 1) Read and write operations must arbitrate for the statistics resources 4544215976Sjmallett * along with the packet engines which are incrementing the counters. 4545215976Sjmallett * In order to not drop packet information, the packet HW is always a 4546215976Sjmallett * higher priority and the CSR requests will only be satisified when 4547215976Sjmallett * there are idle cycles. This can potentially cause long delays if the 4548215976Sjmallett * system becomes full. 4549215976Sjmallett * 4550215976Sjmallett * 2) stat counters can be cleared in two ways. If PIP_STAT_CTL[RDCLR] is 4551215976Sjmallett * set, then all read accesses will clear the register. In addition, 4552215976Sjmallett * any write to a stats register will also reset the register to zero. 4553215976Sjmallett * Please note that the clearing operations must obey rule \#1 above. 4554215976Sjmallett * 4555215976Sjmallett * 3) all counters are wrapping - software must ensure they are read periodically 4556215976Sjmallett * 4557215976Sjmallett * 4) The counters accumulate statistics for packets that are sent to PKI. If 4558215976Sjmallett * PTP_MODE is enabled, the 8B timestamp is prepended to the packet. This 4559215976Sjmallett * additional 8B of data is captured in the octet counts. 4560215976Sjmallett * PIP_STAT0_PRT = PIP_STAT_DRP_PKTS / PIP_STAT_DRP_OCTS 4561215976Sjmallett */ 4562232812Sjmallettunion cvmx_pip_stat0_prtx { 4563215976Sjmallett uint64_t u64; 4564232812Sjmallett struct cvmx_pip_stat0_prtx_s { 4565232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4566215976Sjmallett uint64_t drp_pkts : 32; /**< Inbound packets marked to be dropped by the IPD 4567215976Sjmallett QOS widget per port */ 4568215976Sjmallett uint64_t drp_octs : 32; /**< Inbound octets marked to be dropped by the IPD 4569215976Sjmallett QOS widget per port */ 4570215976Sjmallett#else 4571215976Sjmallett uint64_t drp_octs : 32; 4572215976Sjmallett uint64_t drp_pkts : 32; 4573215976Sjmallett#endif 4574215976Sjmallett } s; 4575215976Sjmallett struct cvmx_pip_stat0_prtx_s cn30xx; 4576215976Sjmallett struct cvmx_pip_stat0_prtx_s cn31xx; 4577215976Sjmallett struct cvmx_pip_stat0_prtx_s cn38xx; 4578215976Sjmallett struct cvmx_pip_stat0_prtx_s cn38xxp2; 4579215976Sjmallett struct cvmx_pip_stat0_prtx_s cn50xx; 4580215976Sjmallett struct cvmx_pip_stat0_prtx_s cn52xx; 4581215976Sjmallett struct cvmx_pip_stat0_prtx_s cn52xxp1; 4582215976Sjmallett struct cvmx_pip_stat0_prtx_s cn56xx; 4583215976Sjmallett struct cvmx_pip_stat0_prtx_s cn56xxp1; 4584215976Sjmallett struct cvmx_pip_stat0_prtx_s cn58xx; 4585215976Sjmallett struct cvmx_pip_stat0_prtx_s cn58xxp1; 4586232812Sjmallett struct cvmx_pip_stat0_prtx_s cn61xx; 4587215976Sjmallett struct cvmx_pip_stat0_prtx_s cn63xx; 4588215976Sjmallett struct cvmx_pip_stat0_prtx_s cn63xxp1; 4589232812Sjmallett struct cvmx_pip_stat0_prtx_s cn66xx; 4590232812Sjmallett struct cvmx_pip_stat0_prtx_s cnf71xx; 4591215976Sjmallett}; 4592215976Sjmalletttypedef union cvmx_pip_stat0_prtx cvmx_pip_stat0_prtx_t; 4593215976Sjmallett 4594215976Sjmallett/** 4595232812Sjmallett * cvmx_pip_stat10_# 4596232812Sjmallett * 4597232812Sjmallett * PIP_STAT10_X = PIP_STAT_L2_MCAST / PIP_STAT_L2_BCAST 4598232812Sjmallett * 4599232812Sjmallett */ 4600232812Sjmallettunion cvmx_pip_stat10_x { 4601232812Sjmallett uint64_t u64; 4602232812Sjmallett struct cvmx_pip_stat10_x_s { 4603232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4604232812Sjmallett uint64_t bcast : 32; /**< Number of packets with L2 Broadcast DMAC 4605232812Sjmallett that were dropped due to RED. 4606232812Sjmallett The HW will consider a packet to be an L2 4607232812Sjmallett broadcast packet when the 48-bit DMAC is all 1's. 4608232812Sjmallett Only applies when the parse mode for the packet 4609232812Sjmallett is SKIP-TO-L2. */ 4610232812Sjmallett uint64_t mcast : 32; /**< Number of packets with L2 Mulitcast DMAC 4611232812Sjmallett that were dropped due to RED. 4612232812Sjmallett The HW will consider a packet to be an L2 4613232812Sjmallett multicast packet when the least-significant bit 4614232812Sjmallett of the first byte of the DMAC is set and the 4615232812Sjmallett packet is not an L2 broadcast packet. 4616232812Sjmallett Only applies when the parse mode for the packet 4617232812Sjmallett is SKIP-TO-L2. */ 4618232812Sjmallett#else 4619232812Sjmallett uint64_t mcast : 32; 4620232812Sjmallett uint64_t bcast : 32; 4621232812Sjmallett#endif 4622232812Sjmallett } s; 4623232812Sjmallett struct cvmx_pip_stat10_x_s cn68xx; 4624232812Sjmallett struct cvmx_pip_stat10_x_s cn68xxp1; 4625232812Sjmallett}; 4626232812Sjmalletttypedef union cvmx_pip_stat10_x cvmx_pip_stat10_x_t; 4627232812Sjmallett 4628232812Sjmallett/** 4629232812Sjmallett * cvmx_pip_stat10_prt# 4630232812Sjmallett * 4631232812Sjmallett * PIP_STAT10_PRTX = PIP_STAT_L2_MCAST / PIP_STAT_L2_BCAST 4632232812Sjmallett * 4633232812Sjmallett */ 4634232812Sjmallettunion cvmx_pip_stat10_prtx { 4635232812Sjmallett uint64_t u64; 4636232812Sjmallett struct cvmx_pip_stat10_prtx_s { 4637232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4638232812Sjmallett uint64_t bcast : 32; /**< Number of packets with L2 Broadcast DMAC 4639232812Sjmallett that were dropped due to RED. 4640232812Sjmallett The HW will consider a packet to be an L2 4641232812Sjmallett broadcast packet when the 48-bit DMAC is all 1's. 4642232812Sjmallett Only applies when the parse mode for the packet 4643232812Sjmallett is SKIP-TO-L2. */ 4644232812Sjmallett uint64_t mcast : 32; /**< Number of packets with L2 Mulitcast DMAC 4645232812Sjmallett that were dropped due to RED. 4646232812Sjmallett The HW will consider a packet to be an L2 4647232812Sjmallett multicast packet when the least-significant bit 4648232812Sjmallett of the first byte of the DMAC is set and the 4649232812Sjmallett packet is not an L2 broadcast packet. 4650232812Sjmallett Only applies when the parse mode for the packet 4651232812Sjmallett is SKIP-TO-L2. */ 4652232812Sjmallett#else 4653232812Sjmallett uint64_t mcast : 32; 4654232812Sjmallett uint64_t bcast : 32; 4655232812Sjmallett#endif 4656232812Sjmallett } s; 4657232812Sjmallett struct cvmx_pip_stat10_prtx_s cn52xx; 4658232812Sjmallett struct cvmx_pip_stat10_prtx_s cn52xxp1; 4659232812Sjmallett struct cvmx_pip_stat10_prtx_s cn56xx; 4660232812Sjmallett struct cvmx_pip_stat10_prtx_s cn56xxp1; 4661232812Sjmallett struct cvmx_pip_stat10_prtx_s cn61xx; 4662232812Sjmallett struct cvmx_pip_stat10_prtx_s cn63xx; 4663232812Sjmallett struct cvmx_pip_stat10_prtx_s cn63xxp1; 4664232812Sjmallett struct cvmx_pip_stat10_prtx_s cn66xx; 4665232812Sjmallett struct cvmx_pip_stat10_prtx_s cnf71xx; 4666232812Sjmallett}; 4667232812Sjmalletttypedef union cvmx_pip_stat10_prtx cvmx_pip_stat10_prtx_t; 4668232812Sjmallett 4669232812Sjmallett/** 4670232812Sjmallett * cvmx_pip_stat11_# 4671232812Sjmallett * 4672232812Sjmallett * PIP_STAT11_X = PIP_STAT_L3_MCAST / PIP_STAT_L3_BCAST 4673232812Sjmallett * 4674232812Sjmallett */ 4675232812Sjmallettunion cvmx_pip_stat11_x { 4676232812Sjmallett uint64_t u64; 4677232812Sjmallett struct cvmx_pip_stat11_x_s { 4678232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4679232812Sjmallett uint64_t bcast : 32; /**< Number of packets with L3 Broadcast Dest Address 4680232812Sjmallett that were dropped due to RED. 4681232812Sjmallett The HW considers an IPv4 packet to be broadcast 4682232812Sjmallett when all bits are set in the MSB of the 4683232812Sjmallett destination address. IPv6 does not have the 4684232812Sjmallett concept of a broadcast packets. 4685232812Sjmallett Only applies when the parse mode for the packet 4686232812Sjmallett is SKIP-TO-L2 and the packet is IP or the parse 4687232812Sjmallett mode for the packet is SKIP-TO-IP. */ 4688232812Sjmallett uint64_t mcast : 32; /**< Number of packets with L3 Multicast Dest Address 4689232812Sjmallett that were dropped due to RED. 4690232812Sjmallett The HW considers an IPv4 packet to be multicast 4691232812Sjmallett when the most-significant nibble of the 32-bit 4692232812Sjmallett destination address is 0xE (i.e. it is a class D 4693232812Sjmallett address). The HW considers an IPv6 packet to be 4694232812Sjmallett multicast when the most-significant byte of the 4695232812Sjmallett 128-bit destination address is all 1's. 4696232812Sjmallett Only applies when the parse mode for the packet 4697232812Sjmallett is SKIP-TO-L2 and the packet is IP or the parse 4698232812Sjmallett mode for the packet is SKIP-TO-IP. */ 4699232812Sjmallett#else 4700232812Sjmallett uint64_t mcast : 32; 4701232812Sjmallett uint64_t bcast : 32; 4702232812Sjmallett#endif 4703232812Sjmallett } s; 4704232812Sjmallett struct cvmx_pip_stat11_x_s cn68xx; 4705232812Sjmallett struct cvmx_pip_stat11_x_s cn68xxp1; 4706232812Sjmallett}; 4707232812Sjmalletttypedef union cvmx_pip_stat11_x cvmx_pip_stat11_x_t; 4708232812Sjmallett 4709232812Sjmallett/** 4710232812Sjmallett * cvmx_pip_stat11_prt# 4711232812Sjmallett * 4712232812Sjmallett * PIP_STAT11_PRTX = PIP_STAT_L3_MCAST / PIP_STAT_L3_BCAST 4713232812Sjmallett * 4714232812Sjmallett */ 4715232812Sjmallettunion cvmx_pip_stat11_prtx { 4716232812Sjmallett uint64_t u64; 4717232812Sjmallett struct cvmx_pip_stat11_prtx_s { 4718232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4719232812Sjmallett uint64_t bcast : 32; /**< Number of packets with L3 Broadcast Dest Address 4720232812Sjmallett that were dropped due to RED. 4721232812Sjmallett The HW considers an IPv4 packet to be broadcast 4722232812Sjmallett when all bits are set in the MSB of the 4723232812Sjmallett destination address. IPv6 does not have the 4724232812Sjmallett concept of a broadcast packets. 4725232812Sjmallett Only applies when the parse mode for the packet 4726232812Sjmallett is SKIP-TO-L2 and the packet is IP or the parse 4727232812Sjmallett mode for the packet is SKIP-TO-IP. */ 4728232812Sjmallett uint64_t mcast : 32; /**< Number of packets with L3 Multicast Dest Address 4729232812Sjmallett that were dropped due to RED. 4730232812Sjmallett The HW considers an IPv4 packet to be multicast 4731232812Sjmallett when the most-significant nibble of the 32-bit 4732232812Sjmallett destination address is 0xE (i.e. it is a class D 4733232812Sjmallett address). The HW considers an IPv6 packet to be 4734232812Sjmallett multicast when the most-significant byte of the 4735232812Sjmallett 128-bit destination address is all 1's. 4736232812Sjmallett Only applies when the parse mode for the packet 4737232812Sjmallett is SKIP-TO-L2 and the packet is IP or the parse 4738232812Sjmallett mode for the packet is SKIP-TO-IP. */ 4739232812Sjmallett#else 4740232812Sjmallett uint64_t mcast : 32; 4741232812Sjmallett uint64_t bcast : 32; 4742232812Sjmallett#endif 4743232812Sjmallett } s; 4744232812Sjmallett struct cvmx_pip_stat11_prtx_s cn52xx; 4745232812Sjmallett struct cvmx_pip_stat11_prtx_s cn52xxp1; 4746232812Sjmallett struct cvmx_pip_stat11_prtx_s cn56xx; 4747232812Sjmallett struct cvmx_pip_stat11_prtx_s cn56xxp1; 4748232812Sjmallett struct cvmx_pip_stat11_prtx_s cn61xx; 4749232812Sjmallett struct cvmx_pip_stat11_prtx_s cn63xx; 4750232812Sjmallett struct cvmx_pip_stat11_prtx_s cn63xxp1; 4751232812Sjmallett struct cvmx_pip_stat11_prtx_s cn66xx; 4752232812Sjmallett struct cvmx_pip_stat11_prtx_s cnf71xx; 4753232812Sjmallett}; 4754232812Sjmalletttypedef union cvmx_pip_stat11_prtx cvmx_pip_stat11_prtx_t; 4755232812Sjmallett 4756232812Sjmallett/** 4757232812Sjmallett * cvmx_pip_stat1_# 4758232812Sjmallett * 4759232812Sjmallett * PIP_STAT1_X = PIP_STAT_OCTS 4760232812Sjmallett * 4761232812Sjmallett */ 4762232812Sjmallettunion cvmx_pip_stat1_x { 4763232812Sjmallett uint64_t u64; 4764232812Sjmallett struct cvmx_pip_stat1_x_s { 4765232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4766232812Sjmallett uint64_t reserved_48_63 : 16; 4767232812Sjmallett uint64_t octs : 48; /**< Number of octets received by PIP (good and bad) */ 4768232812Sjmallett#else 4769232812Sjmallett uint64_t octs : 48; 4770232812Sjmallett uint64_t reserved_48_63 : 16; 4771232812Sjmallett#endif 4772232812Sjmallett } s; 4773232812Sjmallett struct cvmx_pip_stat1_x_s cn68xx; 4774232812Sjmallett struct cvmx_pip_stat1_x_s cn68xxp1; 4775232812Sjmallett}; 4776232812Sjmalletttypedef union cvmx_pip_stat1_x cvmx_pip_stat1_x_t; 4777232812Sjmallett 4778232812Sjmallett/** 4779215976Sjmallett * cvmx_pip_stat1_prt# 4780215976Sjmallett * 4781215976Sjmallett * PIP_STAT1_PRTX = PIP_STAT_OCTS 4782215976Sjmallett * 4783215976Sjmallett */ 4784232812Sjmallettunion cvmx_pip_stat1_prtx { 4785215976Sjmallett uint64_t u64; 4786232812Sjmallett struct cvmx_pip_stat1_prtx_s { 4787232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4788215976Sjmallett uint64_t reserved_48_63 : 16; 4789215976Sjmallett uint64_t octs : 48; /**< Number of octets received by PIP (good and bad) */ 4790215976Sjmallett#else 4791215976Sjmallett uint64_t octs : 48; 4792215976Sjmallett uint64_t reserved_48_63 : 16; 4793215976Sjmallett#endif 4794215976Sjmallett } s; 4795215976Sjmallett struct cvmx_pip_stat1_prtx_s cn30xx; 4796215976Sjmallett struct cvmx_pip_stat1_prtx_s cn31xx; 4797215976Sjmallett struct cvmx_pip_stat1_prtx_s cn38xx; 4798215976Sjmallett struct cvmx_pip_stat1_prtx_s cn38xxp2; 4799215976Sjmallett struct cvmx_pip_stat1_prtx_s cn50xx; 4800215976Sjmallett struct cvmx_pip_stat1_prtx_s cn52xx; 4801215976Sjmallett struct cvmx_pip_stat1_prtx_s cn52xxp1; 4802215976Sjmallett struct cvmx_pip_stat1_prtx_s cn56xx; 4803215976Sjmallett struct cvmx_pip_stat1_prtx_s cn56xxp1; 4804215976Sjmallett struct cvmx_pip_stat1_prtx_s cn58xx; 4805215976Sjmallett struct cvmx_pip_stat1_prtx_s cn58xxp1; 4806232812Sjmallett struct cvmx_pip_stat1_prtx_s cn61xx; 4807215976Sjmallett struct cvmx_pip_stat1_prtx_s cn63xx; 4808215976Sjmallett struct cvmx_pip_stat1_prtx_s cn63xxp1; 4809232812Sjmallett struct cvmx_pip_stat1_prtx_s cn66xx; 4810232812Sjmallett struct cvmx_pip_stat1_prtx_s cnf71xx; 4811215976Sjmallett}; 4812215976Sjmalletttypedef union cvmx_pip_stat1_prtx cvmx_pip_stat1_prtx_t; 4813215976Sjmallett 4814215976Sjmallett/** 4815232812Sjmallett * cvmx_pip_stat2_# 4816232812Sjmallett * 4817232812Sjmallett * PIP_STAT2_X = PIP_STAT_PKTS / PIP_STAT_RAW 4818232812Sjmallett * 4819232812Sjmallett */ 4820232812Sjmallettunion cvmx_pip_stat2_x { 4821232812Sjmallett uint64_t u64; 4822232812Sjmallett struct cvmx_pip_stat2_x_s { 4823232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4824232812Sjmallett uint64_t pkts : 32; /**< Number of packets processed by PIP */ 4825232812Sjmallett uint64_t raw : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error 4826232812Sjmallett received by PIP per port */ 4827232812Sjmallett#else 4828232812Sjmallett uint64_t raw : 32; 4829232812Sjmallett uint64_t pkts : 32; 4830232812Sjmallett#endif 4831232812Sjmallett } s; 4832232812Sjmallett struct cvmx_pip_stat2_x_s cn68xx; 4833232812Sjmallett struct cvmx_pip_stat2_x_s cn68xxp1; 4834232812Sjmallett}; 4835232812Sjmalletttypedef union cvmx_pip_stat2_x cvmx_pip_stat2_x_t; 4836232812Sjmallett 4837232812Sjmallett/** 4838215976Sjmallett * cvmx_pip_stat2_prt# 4839215976Sjmallett * 4840215976Sjmallett * PIP_STAT2_PRTX = PIP_STAT_PKTS / PIP_STAT_RAW 4841215976Sjmallett * 4842215976Sjmallett */ 4843232812Sjmallettunion cvmx_pip_stat2_prtx { 4844215976Sjmallett uint64_t u64; 4845232812Sjmallett struct cvmx_pip_stat2_prtx_s { 4846232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4847215976Sjmallett uint64_t pkts : 32; /**< Number of packets processed by PIP */ 4848215976Sjmallett uint64_t raw : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error 4849215976Sjmallett received by PIP per port */ 4850215976Sjmallett#else 4851215976Sjmallett uint64_t raw : 32; 4852215976Sjmallett uint64_t pkts : 32; 4853215976Sjmallett#endif 4854215976Sjmallett } s; 4855215976Sjmallett struct cvmx_pip_stat2_prtx_s cn30xx; 4856215976Sjmallett struct cvmx_pip_stat2_prtx_s cn31xx; 4857215976Sjmallett struct cvmx_pip_stat2_prtx_s cn38xx; 4858215976Sjmallett struct cvmx_pip_stat2_prtx_s cn38xxp2; 4859215976Sjmallett struct cvmx_pip_stat2_prtx_s cn50xx; 4860215976Sjmallett struct cvmx_pip_stat2_prtx_s cn52xx; 4861215976Sjmallett struct cvmx_pip_stat2_prtx_s cn52xxp1; 4862215976Sjmallett struct cvmx_pip_stat2_prtx_s cn56xx; 4863215976Sjmallett struct cvmx_pip_stat2_prtx_s cn56xxp1; 4864215976Sjmallett struct cvmx_pip_stat2_prtx_s cn58xx; 4865215976Sjmallett struct cvmx_pip_stat2_prtx_s cn58xxp1; 4866232812Sjmallett struct cvmx_pip_stat2_prtx_s cn61xx; 4867215976Sjmallett struct cvmx_pip_stat2_prtx_s cn63xx; 4868215976Sjmallett struct cvmx_pip_stat2_prtx_s cn63xxp1; 4869232812Sjmallett struct cvmx_pip_stat2_prtx_s cn66xx; 4870232812Sjmallett struct cvmx_pip_stat2_prtx_s cnf71xx; 4871215976Sjmallett}; 4872215976Sjmalletttypedef union cvmx_pip_stat2_prtx cvmx_pip_stat2_prtx_t; 4873215976Sjmallett 4874215976Sjmallett/** 4875232812Sjmallett * cvmx_pip_stat3_# 4876232812Sjmallett * 4877232812Sjmallett * PIP_STAT3_X = PIP_STAT_BCST / PIP_STAT_MCST 4878232812Sjmallett * 4879232812Sjmallett */ 4880232812Sjmallettunion cvmx_pip_stat3_x { 4881232812Sjmallett uint64_t u64; 4882232812Sjmallett struct cvmx_pip_stat3_x_s { 4883232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4884232812Sjmallett uint64_t bcst : 32; /**< Number of indentified L2 broadcast packets 4885232812Sjmallett Does not include multicast packets 4886232812Sjmallett Only includes packets whose parse mode is 4887232812Sjmallett SKIP_TO_L2. */ 4888232812Sjmallett uint64_t mcst : 32; /**< Number of indentified L2 multicast packets 4889232812Sjmallett Does not include broadcast packets 4890232812Sjmallett Only includes packets whose parse mode is 4891232812Sjmallett SKIP_TO_L2. */ 4892232812Sjmallett#else 4893232812Sjmallett uint64_t mcst : 32; 4894232812Sjmallett uint64_t bcst : 32; 4895232812Sjmallett#endif 4896232812Sjmallett } s; 4897232812Sjmallett struct cvmx_pip_stat3_x_s cn68xx; 4898232812Sjmallett struct cvmx_pip_stat3_x_s cn68xxp1; 4899232812Sjmallett}; 4900232812Sjmalletttypedef union cvmx_pip_stat3_x cvmx_pip_stat3_x_t; 4901232812Sjmallett 4902232812Sjmallett/** 4903215976Sjmallett * cvmx_pip_stat3_prt# 4904215976Sjmallett * 4905215976Sjmallett * PIP_STAT3_PRTX = PIP_STAT_BCST / PIP_STAT_MCST 4906215976Sjmallett * 4907215976Sjmallett */ 4908232812Sjmallettunion cvmx_pip_stat3_prtx { 4909215976Sjmallett uint64_t u64; 4910232812Sjmallett struct cvmx_pip_stat3_prtx_s { 4911232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4912215976Sjmallett uint64_t bcst : 32; /**< Number of indentified L2 broadcast packets 4913215976Sjmallett Does not include multicast packets 4914215976Sjmallett Only includes packets whose parse mode is 4915215976Sjmallett SKIP_TO_L2. */ 4916215976Sjmallett uint64_t mcst : 32; /**< Number of indentified L2 multicast packets 4917215976Sjmallett Does not include broadcast packets 4918215976Sjmallett Only includes packets whose parse mode is 4919215976Sjmallett SKIP_TO_L2. */ 4920215976Sjmallett#else 4921215976Sjmallett uint64_t mcst : 32; 4922215976Sjmallett uint64_t bcst : 32; 4923215976Sjmallett#endif 4924215976Sjmallett } s; 4925215976Sjmallett struct cvmx_pip_stat3_prtx_s cn30xx; 4926215976Sjmallett struct cvmx_pip_stat3_prtx_s cn31xx; 4927215976Sjmallett struct cvmx_pip_stat3_prtx_s cn38xx; 4928215976Sjmallett struct cvmx_pip_stat3_prtx_s cn38xxp2; 4929215976Sjmallett struct cvmx_pip_stat3_prtx_s cn50xx; 4930215976Sjmallett struct cvmx_pip_stat3_prtx_s cn52xx; 4931215976Sjmallett struct cvmx_pip_stat3_prtx_s cn52xxp1; 4932215976Sjmallett struct cvmx_pip_stat3_prtx_s cn56xx; 4933215976Sjmallett struct cvmx_pip_stat3_prtx_s cn56xxp1; 4934215976Sjmallett struct cvmx_pip_stat3_prtx_s cn58xx; 4935215976Sjmallett struct cvmx_pip_stat3_prtx_s cn58xxp1; 4936232812Sjmallett struct cvmx_pip_stat3_prtx_s cn61xx; 4937215976Sjmallett struct cvmx_pip_stat3_prtx_s cn63xx; 4938215976Sjmallett struct cvmx_pip_stat3_prtx_s cn63xxp1; 4939232812Sjmallett struct cvmx_pip_stat3_prtx_s cn66xx; 4940232812Sjmallett struct cvmx_pip_stat3_prtx_s cnf71xx; 4941215976Sjmallett}; 4942215976Sjmalletttypedef union cvmx_pip_stat3_prtx cvmx_pip_stat3_prtx_t; 4943215976Sjmallett 4944215976Sjmallett/** 4945232812Sjmallett * cvmx_pip_stat4_# 4946232812Sjmallett * 4947232812Sjmallett * PIP_STAT4_X = PIP_STAT_HIST1 / PIP_STAT_HIST0 4948232812Sjmallett * 4949232812Sjmallett */ 4950232812Sjmallettunion cvmx_pip_stat4_x { 4951232812Sjmallett uint64_t u64; 4952232812Sjmallett struct cvmx_pip_stat4_x_s { 4953232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4954232812Sjmallett uint64_t h65to127 : 32; /**< Number of 65-127B packets */ 4955232812Sjmallett uint64_t h64 : 32; /**< Number of 1-64B packets */ 4956232812Sjmallett#else 4957232812Sjmallett uint64_t h64 : 32; 4958232812Sjmallett uint64_t h65to127 : 32; 4959232812Sjmallett#endif 4960232812Sjmallett } s; 4961232812Sjmallett struct cvmx_pip_stat4_x_s cn68xx; 4962232812Sjmallett struct cvmx_pip_stat4_x_s cn68xxp1; 4963232812Sjmallett}; 4964232812Sjmalletttypedef union cvmx_pip_stat4_x cvmx_pip_stat4_x_t; 4965232812Sjmallett 4966232812Sjmallett/** 4967215976Sjmallett * cvmx_pip_stat4_prt# 4968215976Sjmallett * 4969215976Sjmallett * PIP_STAT4_PRTX = PIP_STAT_HIST1 / PIP_STAT_HIST0 4970215976Sjmallett * 4971215976Sjmallett */ 4972232812Sjmallettunion cvmx_pip_stat4_prtx { 4973215976Sjmallett uint64_t u64; 4974232812Sjmallett struct cvmx_pip_stat4_prtx_s { 4975232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4976215976Sjmallett uint64_t h65to127 : 32; /**< Number of 65-127B packets */ 4977215976Sjmallett uint64_t h64 : 32; /**< Number of 1-64B packets */ 4978215976Sjmallett#else 4979215976Sjmallett uint64_t h64 : 32; 4980215976Sjmallett uint64_t h65to127 : 32; 4981215976Sjmallett#endif 4982215976Sjmallett } s; 4983215976Sjmallett struct cvmx_pip_stat4_prtx_s cn30xx; 4984215976Sjmallett struct cvmx_pip_stat4_prtx_s cn31xx; 4985215976Sjmallett struct cvmx_pip_stat4_prtx_s cn38xx; 4986215976Sjmallett struct cvmx_pip_stat4_prtx_s cn38xxp2; 4987215976Sjmallett struct cvmx_pip_stat4_prtx_s cn50xx; 4988215976Sjmallett struct cvmx_pip_stat4_prtx_s cn52xx; 4989215976Sjmallett struct cvmx_pip_stat4_prtx_s cn52xxp1; 4990215976Sjmallett struct cvmx_pip_stat4_prtx_s cn56xx; 4991215976Sjmallett struct cvmx_pip_stat4_prtx_s cn56xxp1; 4992215976Sjmallett struct cvmx_pip_stat4_prtx_s cn58xx; 4993215976Sjmallett struct cvmx_pip_stat4_prtx_s cn58xxp1; 4994232812Sjmallett struct cvmx_pip_stat4_prtx_s cn61xx; 4995215976Sjmallett struct cvmx_pip_stat4_prtx_s cn63xx; 4996215976Sjmallett struct cvmx_pip_stat4_prtx_s cn63xxp1; 4997232812Sjmallett struct cvmx_pip_stat4_prtx_s cn66xx; 4998232812Sjmallett struct cvmx_pip_stat4_prtx_s cnf71xx; 4999215976Sjmallett}; 5000215976Sjmalletttypedef union cvmx_pip_stat4_prtx cvmx_pip_stat4_prtx_t; 5001215976Sjmallett 5002215976Sjmallett/** 5003232812Sjmallett * cvmx_pip_stat5_# 5004232812Sjmallett * 5005232812Sjmallett * PIP_STAT5_X = PIP_STAT_HIST3 / PIP_STAT_HIST2 5006232812Sjmallett * 5007232812Sjmallett */ 5008232812Sjmallettunion cvmx_pip_stat5_x { 5009232812Sjmallett uint64_t u64; 5010232812Sjmallett struct cvmx_pip_stat5_x_s { 5011232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5012232812Sjmallett uint64_t h256to511 : 32; /**< Number of 256-511B packets */ 5013232812Sjmallett uint64_t h128to255 : 32; /**< Number of 128-255B packets */ 5014232812Sjmallett#else 5015232812Sjmallett uint64_t h128to255 : 32; 5016232812Sjmallett uint64_t h256to511 : 32; 5017232812Sjmallett#endif 5018232812Sjmallett } s; 5019232812Sjmallett struct cvmx_pip_stat5_x_s cn68xx; 5020232812Sjmallett struct cvmx_pip_stat5_x_s cn68xxp1; 5021232812Sjmallett}; 5022232812Sjmalletttypedef union cvmx_pip_stat5_x cvmx_pip_stat5_x_t; 5023232812Sjmallett 5024232812Sjmallett/** 5025215976Sjmallett * cvmx_pip_stat5_prt# 5026215976Sjmallett * 5027215976Sjmallett * PIP_STAT5_PRTX = PIP_STAT_HIST3 / PIP_STAT_HIST2 5028215976Sjmallett * 5029215976Sjmallett */ 5030232812Sjmallettunion cvmx_pip_stat5_prtx { 5031215976Sjmallett uint64_t u64; 5032232812Sjmallett struct cvmx_pip_stat5_prtx_s { 5033232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5034215976Sjmallett uint64_t h256to511 : 32; /**< Number of 256-511B packets */ 5035215976Sjmallett uint64_t h128to255 : 32; /**< Number of 128-255B packets */ 5036215976Sjmallett#else 5037215976Sjmallett uint64_t h128to255 : 32; 5038215976Sjmallett uint64_t h256to511 : 32; 5039215976Sjmallett#endif 5040215976Sjmallett } s; 5041215976Sjmallett struct cvmx_pip_stat5_prtx_s cn30xx; 5042215976Sjmallett struct cvmx_pip_stat5_prtx_s cn31xx; 5043215976Sjmallett struct cvmx_pip_stat5_prtx_s cn38xx; 5044215976Sjmallett struct cvmx_pip_stat5_prtx_s cn38xxp2; 5045215976Sjmallett struct cvmx_pip_stat5_prtx_s cn50xx; 5046215976Sjmallett struct cvmx_pip_stat5_prtx_s cn52xx; 5047215976Sjmallett struct cvmx_pip_stat5_prtx_s cn52xxp1; 5048215976Sjmallett struct cvmx_pip_stat5_prtx_s cn56xx; 5049215976Sjmallett struct cvmx_pip_stat5_prtx_s cn56xxp1; 5050215976Sjmallett struct cvmx_pip_stat5_prtx_s cn58xx; 5051215976Sjmallett struct cvmx_pip_stat5_prtx_s cn58xxp1; 5052232812Sjmallett struct cvmx_pip_stat5_prtx_s cn61xx; 5053215976Sjmallett struct cvmx_pip_stat5_prtx_s cn63xx; 5054215976Sjmallett struct cvmx_pip_stat5_prtx_s cn63xxp1; 5055232812Sjmallett struct cvmx_pip_stat5_prtx_s cn66xx; 5056232812Sjmallett struct cvmx_pip_stat5_prtx_s cnf71xx; 5057215976Sjmallett}; 5058215976Sjmalletttypedef union cvmx_pip_stat5_prtx cvmx_pip_stat5_prtx_t; 5059215976Sjmallett 5060215976Sjmallett/** 5061232812Sjmallett * cvmx_pip_stat6_# 5062232812Sjmallett * 5063232812Sjmallett * PIP_STAT6_X = PIP_STAT_HIST5 / PIP_STAT_HIST4 5064232812Sjmallett * 5065232812Sjmallett */ 5066232812Sjmallettunion cvmx_pip_stat6_x { 5067232812Sjmallett uint64_t u64; 5068232812Sjmallett struct cvmx_pip_stat6_x_s { 5069232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5070232812Sjmallett uint64_t h1024to1518 : 32; /**< Number of 1024-1518B packets */ 5071232812Sjmallett uint64_t h512to1023 : 32; /**< Number of 512-1023B packets */ 5072232812Sjmallett#else 5073232812Sjmallett uint64_t h512to1023 : 32; 5074232812Sjmallett uint64_t h1024to1518 : 32; 5075232812Sjmallett#endif 5076232812Sjmallett } s; 5077232812Sjmallett struct cvmx_pip_stat6_x_s cn68xx; 5078232812Sjmallett struct cvmx_pip_stat6_x_s cn68xxp1; 5079232812Sjmallett}; 5080232812Sjmalletttypedef union cvmx_pip_stat6_x cvmx_pip_stat6_x_t; 5081232812Sjmallett 5082232812Sjmallett/** 5083215976Sjmallett * cvmx_pip_stat6_prt# 5084215976Sjmallett * 5085215976Sjmallett * PIP_STAT6_PRTX = PIP_STAT_HIST5 / PIP_STAT_HIST4 5086215976Sjmallett * 5087215976Sjmallett */ 5088232812Sjmallettunion cvmx_pip_stat6_prtx { 5089215976Sjmallett uint64_t u64; 5090232812Sjmallett struct cvmx_pip_stat6_prtx_s { 5091232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5092215976Sjmallett uint64_t h1024to1518 : 32; /**< Number of 1024-1518B packets */ 5093215976Sjmallett uint64_t h512to1023 : 32; /**< Number of 512-1023B packets */ 5094215976Sjmallett#else 5095215976Sjmallett uint64_t h512to1023 : 32; 5096215976Sjmallett uint64_t h1024to1518 : 32; 5097215976Sjmallett#endif 5098215976Sjmallett } s; 5099215976Sjmallett struct cvmx_pip_stat6_prtx_s cn30xx; 5100215976Sjmallett struct cvmx_pip_stat6_prtx_s cn31xx; 5101215976Sjmallett struct cvmx_pip_stat6_prtx_s cn38xx; 5102215976Sjmallett struct cvmx_pip_stat6_prtx_s cn38xxp2; 5103215976Sjmallett struct cvmx_pip_stat6_prtx_s cn50xx; 5104215976Sjmallett struct cvmx_pip_stat6_prtx_s cn52xx; 5105215976Sjmallett struct cvmx_pip_stat6_prtx_s cn52xxp1; 5106215976Sjmallett struct cvmx_pip_stat6_prtx_s cn56xx; 5107215976Sjmallett struct cvmx_pip_stat6_prtx_s cn56xxp1; 5108215976Sjmallett struct cvmx_pip_stat6_prtx_s cn58xx; 5109215976Sjmallett struct cvmx_pip_stat6_prtx_s cn58xxp1; 5110232812Sjmallett struct cvmx_pip_stat6_prtx_s cn61xx; 5111215976Sjmallett struct cvmx_pip_stat6_prtx_s cn63xx; 5112215976Sjmallett struct cvmx_pip_stat6_prtx_s cn63xxp1; 5113232812Sjmallett struct cvmx_pip_stat6_prtx_s cn66xx; 5114232812Sjmallett struct cvmx_pip_stat6_prtx_s cnf71xx; 5115215976Sjmallett}; 5116215976Sjmalletttypedef union cvmx_pip_stat6_prtx cvmx_pip_stat6_prtx_t; 5117215976Sjmallett 5118215976Sjmallett/** 5119232812Sjmallett * cvmx_pip_stat7_# 5120232812Sjmallett * 5121232812Sjmallett * PIP_STAT7_X = PIP_STAT_FCS / PIP_STAT_HIST6 5122232812Sjmallett * 5123232812Sjmallett */ 5124232812Sjmallettunion cvmx_pip_stat7_x { 5125232812Sjmallett uint64_t u64; 5126232812Sjmallett struct cvmx_pip_stat7_x_s { 5127232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5128232812Sjmallett uint64_t fcs : 32; /**< Number of packets with FCS or Align opcode errors */ 5129232812Sjmallett uint64_t h1519 : 32; /**< Number of 1519-max packets */ 5130232812Sjmallett#else 5131232812Sjmallett uint64_t h1519 : 32; 5132232812Sjmallett uint64_t fcs : 32; 5133232812Sjmallett#endif 5134232812Sjmallett } s; 5135232812Sjmallett struct cvmx_pip_stat7_x_s cn68xx; 5136232812Sjmallett struct cvmx_pip_stat7_x_s cn68xxp1; 5137232812Sjmallett}; 5138232812Sjmalletttypedef union cvmx_pip_stat7_x cvmx_pip_stat7_x_t; 5139232812Sjmallett 5140232812Sjmallett/** 5141215976Sjmallett * cvmx_pip_stat7_prt# 5142215976Sjmallett * 5143215976Sjmallett * PIP_STAT7_PRTX = PIP_STAT_FCS / PIP_STAT_HIST6 5144215976Sjmallett * 5145215976Sjmallett * 5146215976Sjmallett * Notes: 5147232812Sjmallett * DPI does not check FCS, therefore FCS will never increment on DPI ports 32-35 5148232812Sjmallett * sRIO does not check FCS, therefore FCS will never increment on sRIO ports 40-47 5149215976Sjmallett */ 5150232812Sjmallettunion cvmx_pip_stat7_prtx { 5151215976Sjmallett uint64_t u64; 5152232812Sjmallett struct cvmx_pip_stat7_prtx_s { 5153232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5154215976Sjmallett uint64_t fcs : 32; /**< Number of packets with FCS or Align opcode errors */ 5155215976Sjmallett uint64_t h1519 : 32; /**< Number of 1519-max packets */ 5156215976Sjmallett#else 5157215976Sjmallett uint64_t h1519 : 32; 5158215976Sjmallett uint64_t fcs : 32; 5159215976Sjmallett#endif 5160215976Sjmallett } s; 5161215976Sjmallett struct cvmx_pip_stat7_prtx_s cn30xx; 5162215976Sjmallett struct cvmx_pip_stat7_prtx_s cn31xx; 5163215976Sjmallett struct cvmx_pip_stat7_prtx_s cn38xx; 5164215976Sjmallett struct cvmx_pip_stat7_prtx_s cn38xxp2; 5165215976Sjmallett struct cvmx_pip_stat7_prtx_s cn50xx; 5166215976Sjmallett struct cvmx_pip_stat7_prtx_s cn52xx; 5167215976Sjmallett struct cvmx_pip_stat7_prtx_s cn52xxp1; 5168215976Sjmallett struct cvmx_pip_stat7_prtx_s cn56xx; 5169215976Sjmallett struct cvmx_pip_stat7_prtx_s cn56xxp1; 5170215976Sjmallett struct cvmx_pip_stat7_prtx_s cn58xx; 5171215976Sjmallett struct cvmx_pip_stat7_prtx_s cn58xxp1; 5172232812Sjmallett struct cvmx_pip_stat7_prtx_s cn61xx; 5173215976Sjmallett struct cvmx_pip_stat7_prtx_s cn63xx; 5174215976Sjmallett struct cvmx_pip_stat7_prtx_s cn63xxp1; 5175232812Sjmallett struct cvmx_pip_stat7_prtx_s cn66xx; 5176232812Sjmallett struct cvmx_pip_stat7_prtx_s cnf71xx; 5177215976Sjmallett}; 5178215976Sjmalletttypedef union cvmx_pip_stat7_prtx cvmx_pip_stat7_prtx_t; 5179215976Sjmallett 5180215976Sjmallett/** 5181232812Sjmallett * cvmx_pip_stat8_# 5182232812Sjmallett * 5183232812Sjmallett * PIP_STAT8_X = PIP_STAT_FRAG / PIP_STAT_UNDER 5184232812Sjmallett * 5185232812Sjmallett */ 5186232812Sjmallettunion cvmx_pip_stat8_x { 5187232812Sjmallett uint64_t u64; 5188232812Sjmallett struct cvmx_pip_stat8_x_s { 5189232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5190232812Sjmallett uint64_t frag : 32; /**< Number of packets with length < min and FCS error */ 5191232812Sjmallett uint64_t undersz : 32; /**< Number of packets with length < min */ 5192232812Sjmallett#else 5193232812Sjmallett uint64_t undersz : 32; 5194232812Sjmallett uint64_t frag : 32; 5195232812Sjmallett#endif 5196232812Sjmallett } s; 5197232812Sjmallett struct cvmx_pip_stat8_x_s cn68xx; 5198232812Sjmallett struct cvmx_pip_stat8_x_s cn68xxp1; 5199232812Sjmallett}; 5200232812Sjmalletttypedef union cvmx_pip_stat8_x cvmx_pip_stat8_x_t; 5201232812Sjmallett 5202232812Sjmallett/** 5203215976Sjmallett * cvmx_pip_stat8_prt# 5204215976Sjmallett * 5205215976Sjmallett * PIP_STAT8_PRTX = PIP_STAT_FRAG / PIP_STAT_UNDER 5206215976Sjmallett * 5207215976Sjmallett * 5208215976Sjmallett * Notes: 5209232812Sjmallett * DPI does not check FCS, therefore FRAG will never increment on DPI ports 32-35 5210232812Sjmallett * sRIO does not check FCS, therefore FRAG will never increment on sRIO ports 40-47 5211215976Sjmallett */ 5212232812Sjmallettunion cvmx_pip_stat8_prtx { 5213215976Sjmallett uint64_t u64; 5214232812Sjmallett struct cvmx_pip_stat8_prtx_s { 5215232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5216215976Sjmallett uint64_t frag : 32; /**< Number of packets with length < min and FCS error */ 5217215976Sjmallett uint64_t undersz : 32; /**< Number of packets with length < min */ 5218215976Sjmallett#else 5219215976Sjmallett uint64_t undersz : 32; 5220215976Sjmallett uint64_t frag : 32; 5221215976Sjmallett#endif 5222215976Sjmallett } s; 5223215976Sjmallett struct cvmx_pip_stat8_prtx_s cn30xx; 5224215976Sjmallett struct cvmx_pip_stat8_prtx_s cn31xx; 5225215976Sjmallett struct cvmx_pip_stat8_prtx_s cn38xx; 5226215976Sjmallett struct cvmx_pip_stat8_prtx_s cn38xxp2; 5227215976Sjmallett struct cvmx_pip_stat8_prtx_s cn50xx; 5228215976Sjmallett struct cvmx_pip_stat8_prtx_s cn52xx; 5229215976Sjmallett struct cvmx_pip_stat8_prtx_s cn52xxp1; 5230215976Sjmallett struct cvmx_pip_stat8_prtx_s cn56xx; 5231215976Sjmallett struct cvmx_pip_stat8_prtx_s cn56xxp1; 5232215976Sjmallett struct cvmx_pip_stat8_prtx_s cn58xx; 5233215976Sjmallett struct cvmx_pip_stat8_prtx_s cn58xxp1; 5234232812Sjmallett struct cvmx_pip_stat8_prtx_s cn61xx; 5235215976Sjmallett struct cvmx_pip_stat8_prtx_s cn63xx; 5236215976Sjmallett struct cvmx_pip_stat8_prtx_s cn63xxp1; 5237232812Sjmallett struct cvmx_pip_stat8_prtx_s cn66xx; 5238232812Sjmallett struct cvmx_pip_stat8_prtx_s cnf71xx; 5239215976Sjmallett}; 5240215976Sjmalletttypedef union cvmx_pip_stat8_prtx cvmx_pip_stat8_prtx_t; 5241215976Sjmallett 5242215976Sjmallett/** 5243232812Sjmallett * cvmx_pip_stat9_# 5244232812Sjmallett * 5245232812Sjmallett * PIP_STAT9_X = PIP_STAT_JABBER / PIP_STAT_OVER 5246232812Sjmallett * 5247232812Sjmallett */ 5248232812Sjmallettunion cvmx_pip_stat9_x { 5249232812Sjmallett uint64_t u64; 5250232812Sjmallett struct cvmx_pip_stat9_x_s { 5251232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5252232812Sjmallett uint64_t jabber : 32; /**< Number of packets with length > max and FCS error */ 5253232812Sjmallett uint64_t oversz : 32; /**< Number of packets with length > max */ 5254232812Sjmallett#else 5255232812Sjmallett uint64_t oversz : 32; 5256232812Sjmallett uint64_t jabber : 32; 5257232812Sjmallett#endif 5258232812Sjmallett } s; 5259232812Sjmallett struct cvmx_pip_stat9_x_s cn68xx; 5260232812Sjmallett struct cvmx_pip_stat9_x_s cn68xxp1; 5261232812Sjmallett}; 5262232812Sjmalletttypedef union cvmx_pip_stat9_x cvmx_pip_stat9_x_t; 5263232812Sjmallett 5264232812Sjmallett/** 5265215976Sjmallett * cvmx_pip_stat9_prt# 5266215976Sjmallett * 5267215976Sjmallett * PIP_STAT9_PRTX = PIP_STAT_JABBER / PIP_STAT_OVER 5268215976Sjmallett * 5269215976Sjmallett * 5270215976Sjmallett * Notes: 5271232812Sjmallett * DPI does not check FCS, therefore JABBER will never increment on DPI ports 32-35 5272232812Sjmallett * sRIO does not check FCS, therefore JABBER will never increment on sRIO ports 40-47 due to FCS errors 5273232812Sjmallett * sRIO does use the JABBER opcode to communicate sRIO error, therefore JABBER can increment under the sRIO error conditions 5274215976Sjmallett */ 5275232812Sjmallettunion cvmx_pip_stat9_prtx { 5276215976Sjmallett uint64_t u64; 5277232812Sjmallett struct cvmx_pip_stat9_prtx_s { 5278232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5279215976Sjmallett uint64_t jabber : 32; /**< Number of packets with length > max and FCS error */ 5280215976Sjmallett uint64_t oversz : 32; /**< Number of packets with length > max */ 5281215976Sjmallett#else 5282215976Sjmallett uint64_t oversz : 32; 5283215976Sjmallett uint64_t jabber : 32; 5284215976Sjmallett#endif 5285215976Sjmallett } s; 5286215976Sjmallett struct cvmx_pip_stat9_prtx_s cn30xx; 5287215976Sjmallett struct cvmx_pip_stat9_prtx_s cn31xx; 5288215976Sjmallett struct cvmx_pip_stat9_prtx_s cn38xx; 5289215976Sjmallett struct cvmx_pip_stat9_prtx_s cn38xxp2; 5290215976Sjmallett struct cvmx_pip_stat9_prtx_s cn50xx; 5291215976Sjmallett struct cvmx_pip_stat9_prtx_s cn52xx; 5292215976Sjmallett struct cvmx_pip_stat9_prtx_s cn52xxp1; 5293215976Sjmallett struct cvmx_pip_stat9_prtx_s cn56xx; 5294215976Sjmallett struct cvmx_pip_stat9_prtx_s cn56xxp1; 5295215976Sjmallett struct cvmx_pip_stat9_prtx_s cn58xx; 5296215976Sjmallett struct cvmx_pip_stat9_prtx_s cn58xxp1; 5297232812Sjmallett struct cvmx_pip_stat9_prtx_s cn61xx; 5298215976Sjmallett struct cvmx_pip_stat9_prtx_s cn63xx; 5299215976Sjmallett struct cvmx_pip_stat9_prtx_s cn63xxp1; 5300232812Sjmallett struct cvmx_pip_stat9_prtx_s cn66xx; 5301232812Sjmallett struct cvmx_pip_stat9_prtx_s cnf71xx; 5302215976Sjmallett}; 5303215976Sjmalletttypedef union cvmx_pip_stat9_prtx cvmx_pip_stat9_prtx_t; 5304215976Sjmallett 5305215976Sjmallett/** 5306215976Sjmallett * cvmx_pip_stat_ctl 5307215976Sjmallett * 5308215976Sjmallett * PIP_STAT_CTL = PIP's Stat Control Register 5309215976Sjmallett * 5310215976Sjmallett * Controls how the PIP statistics counters are handled. 5311215976Sjmallett */ 5312232812Sjmallettunion cvmx_pip_stat_ctl { 5313215976Sjmallett uint64_t u64; 5314232812Sjmallett struct cvmx_pip_stat_ctl_s { 5315232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5316232812Sjmallett uint64_t reserved_9_63 : 55; 5317232812Sjmallett uint64_t mode : 1; /**< The PIP_STAT*_X registers can be indexed either by 5318232812Sjmallett port-kind or backpressure ID. 5319232812Sjmallett Does not apply to the PIP_STAT_INB* registers. 5320232812Sjmallett 0 = X represents the packet's port-kind 5321232812Sjmallett 1 = X represents the packet's backpressure ID */ 5322232812Sjmallett uint64_t reserved_1_7 : 7; 5323232812Sjmallett uint64_t rdclr : 1; /**< Stat registers are read and clear 5324232812Sjmallett 0 = stat registers hold value when read 5325232812Sjmallett 1 = stat registers are cleared when read */ 5326232812Sjmallett#else 5327232812Sjmallett uint64_t rdclr : 1; 5328232812Sjmallett uint64_t reserved_1_7 : 7; 5329232812Sjmallett uint64_t mode : 1; 5330232812Sjmallett uint64_t reserved_9_63 : 55; 5331232812Sjmallett#endif 5332232812Sjmallett } s; 5333232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx { 5334232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5335215976Sjmallett uint64_t reserved_1_63 : 63; 5336215976Sjmallett uint64_t rdclr : 1; /**< Stat registers are read and clear 5337215976Sjmallett 0 = stat registers hold value when read 5338215976Sjmallett 1 = stat registers are cleared when read */ 5339215976Sjmallett#else 5340215976Sjmallett uint64_t rdclr : 1; 5341215976Sjmallett uint64_t reserved_1_63 : 63; 5342215976Sjmallett#endif 5343232812Sjmallett } cn30xx; 5344232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn31xx; 5345232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn38xx; 5346232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn38xxp2; 5347232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn50xx; 5348232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn52xx; 5349232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn52xxp1; 5350232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn56xx; 5351232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn56xxp1; 5352232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn58xx; 5353232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn58xxp1; 5354232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn61xx; 5355232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn63xx; 5356232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn63xxp1; 5357232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cn66xx; 5358232812Sjmallett struct cvmx_pip_stat_ctl_s cn68xx; 5359232812Sjmallett struct cvmx_pip_stat_ctl_s cn68xxp1; 5360232812Sjmallett struct cvmx_pip_stat_ctl_cn30xx cnf71xx; 5361215976Sjmallett}; 5362215976Sjmalletttypedef union cvmx_pip_stat_ctl cvmx_pip_stat_ctl_t; 5363215976Sjmallett 5364215976Sjmallett/** 5365215976Sjmallett * cvmx_pip_stat_inb_errs# 5366215976Sjmallett * 5367215976Sjmallett * PIP_STAT_INB_ERRSX = Inbound error packets received by PIP per port 5368215976Sjmallett * 5369215976Sjmallett * Inbound stats collect all data sent to PIP from all packet interfaces. 5370215976Sjmallett * Its the raw counts of everything that comes into the block. The counts 5371215976Sjmallett * will reflect all error packets and packets dropped by the PKI RED engine. 5372215976Sjmallett * These counts are intended for system debug, but could convey useful 5373215976Sjmallett * information in production systems. 5374215976Sjmallett */ 5375232812Sjmallettunion cvmx_pip_stat_inb_errsx { 5376215976Sjmallett uint64_t u64; 5377232812Sjmallett struct cvmx_pip_stat_inb_errsx_s { 5378232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5379215976Sjmallett uint64_t reserved_16_63 : 48; 5380215976Sjmallett uint64_t errs : 16; /**< Number of packets with errors 5381215976Sjmallett received by PIP */ 5382215976Sjmallett#else 5383215976Sjmallett uint64_t errs : 16; 5384215976Sjmallett uint64_t reserved_16_63 : 48; 5385215976Sjmallett#endif 5386215976Sjmallett } s; 5387215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn30xx; 5388215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn31xx; 5389215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn38xx; 5390215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn38xxp2; 5391215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn50xx; 5392215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn52xx; 5393215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn52xxp1; 5394215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn56xx; 5395215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn56xxp1; 5396215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn58xx; 5397215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn58xxp1; 5398232812Sjmallett struct cvmx_pip_stat_inb_errsx_s cn61xx; 5399215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn63xx; 5400215976Sjmallett struct cvmx_pip_stat_inb_errsx_s cn63xxp1; 5401232812Sjmallett struct cvmx_pip_stat_inb_errsx_s cn66xx; 5402232812Sjmallett struct cvmx_pip_stat_inb_errsx_s cnf71xx; 5403215976Sjmallett}; 5404215976Sjmalletttypedef union cvmx_pip_stat_inb_errsx cvmx_pip_stat_inb_errsx_t; 5405215976Sjmallett 5406215976Sjmallett/** 5407232812Sjmallett * cvmx_pip_stat_inb_errs_pknd# 5408232812Sjmallett * 5409232812Sjmallett * PIP_STAT_INB_ERRS_PKNDX = Inbound error packets received by PIP per pkind 5410232812Sjmallett * 5411232812Sjmallett * Inbound stats collect all data sent to PIP from all packet interfaces. 5412232812Sjmallett * Its the raw counts of everything that comes into the block. The counts 5413232812Sjmallett * will reflect all error packets and packets dropped by the PKI RED engine. 5414232812Sjmallett * These counts are intended for system debug, but could convey useful 5415232812Sjmallett * information in production systems. 5416232812Sjmallett */ 5417232812Sjmallettunion cvmx_pip_stat_inb_errs_pkndx { 5418232812Sjmallett uint64_t u64; 5419232812Sjmallett struct cvmx_pip_stat_inb_errs_pkndx_s { 5420232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5421232812Sjmallett uint64_t reserved_16_63 : 48; 5422232812Sjmallett uint64_t errs : 16; /**< Number of packets with errors 5423232812Sjmallett received by PIP */ 5424232812Sjmallett#else 5425232812Sjmallett uint64_t errs : 16; 5426232812Sjmallett uint64_t reserved_16_63 : 48; 5427232812Sjmallett#endif 5428232812Sjmallett } s; 5429232812Sjmallett struct cvmx_pip_stat_inb_errs_pkndx_s cn68xx; 5430232812Sjmallett struct cvmx_pip_stat_inb_errs_pkndx_s cn68xxp1; 5431232812Sjmallett}; 5432232812Sjmalletttypedef union cvmx_pip_stat_inb_errs_pkndx cvmx_pip_stat_inb_errs_pkndx_t; 5433232812Sjmallett 5434232812Sjmallett/** 5435215976Sjmallett * cvmx_pip_stat_inb_octs# 5436215976Sjmallett * 5437215976Sjmallett * PIP_STAT_INB_OCTSX = Inbound octets received by PIP per port 5438215976Sjmallett * 5439215976Sjmallett * Inbound stats collect all data sent to PIP from all packet interfaces. 5440215976Sjmallett * Its the raw counts of everything that comes into the block. The counts 5441215976Sjmallett * will reflect all error packets and packets dropped by the PKI RED engine. 5442215976Sjmallett * These counts are intended for system debug, but could convey useful 5443215976Sjmallett * information in production systems. The OCTS will include the bytes from 5444215976Sjmallett * timestamp fields in PTP_MODE. 5445215976Sjmallett */ 5446232812Sjmallettunion cvmx_pip_stat_inb_octsx { 5447215976Sjmallett uint64_t u64; 5448232812Sjmallett struct cvmx_pip_stat_inb_octsx_s { 5449232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5450215976Sjmallett uint64_t reserved_48_63 : 16; 5451215976Sjmallett uint64_t octs : 48; /**< Total number of octets from all packets received 5452215976Sjmallett by PIP */ 5453215976Sjmallett#else 5454215976Sjmallett uint64_t octs : 48; 5455215976Sjmallett uint64_t reserved_48_63 : 16; 5456215976Sjmallett#endif 5457215976Sjmallett } s; 5458215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn30xx; 5459215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn31xx; 5460215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn38xx; 5461215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn38xxp2; 5462215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn50xx; 5463215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn52xx; 5464215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn52xxp1; 5465215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn56xx; 5466215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn56xxp1; 5467215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn58xx; 5468215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn58xxp1; 5469232812Sjmallett struct cvmx_pip_stat_inb_octsx_s cn61xx; 5470215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn63xx; 5471215976Sjmallett struct cvmx_pip_stat_inb_octsx_s cn63xxp1; 5472232812Sjmallett struct cvmx_pip_stat_inb_octsx_s cn66xx; 5473232812Sjmallett struct cvmx_pip_stat_inb_octsx_s cnf71xx; 5474215976Sjmallett}; 5475215976Sjmalletttypedef union cvmx_pip_stat_inb_octsx cvmx_pip_stat_inb_octsx_t; 5476215976Sjmallett 5477215976Sjmallett/** 5478232812Sjmallett * cvmx_pip_stat_inb_octs_pknd# 5479232812Sjmallett * 5480232812Sjmallett * PIP_STAT_INB_OCTS_PKNDX = Inbound octets received by PIP per pkind 5481232812Sjmallett * 5482232812Sjmallett * Inbound stats collect all data sent to PIP from all packet interfaces. 5483232812Sjmallett * Its the raw counts of everything that comes into the block. The counts 5484232812Sjmallett * will reflect all error packets and packets dropped by the PKI RED engine. 5485232812Sjmallett * These counts are intended for system debug, but could convey useful 5486232812Sjmallett * information in production systems. The OCTS will include the bytes from 5487232812Sjmallett * timestamp fields in PTP_MODE. 5488232812Sjmallett */ 5489232812Sjmallettunion cvmx_pip_stat_inb_octs_pkndx { 5490232812Sjmallett uint64_t u64; 5491232812Sjmallett struct cvmx_pip_stat_inb_octs_pkndx_s { 5492232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5493232812Sjmallett uint64_t reserved_48_63 : 16; 5494232812Sjmallett uint64_t octs : 48; /**< Total number of octets from all packets received 5495232812Sjmallett by PIP */ 5496232812Sjmallett#else 5497232812Sjmallett uint64_t octs : 48; 5498232812Sjmallett uint64_t reserved_48_63 : 16; 5499232812Sjmallett#endif 5500232812Sjmallett } s; 5501232812Sjmallett struct cvmx_pip_stat_inb_octs_pkndx_s cn68xx; 5502232812Sjmallett struct cvmx_pip_stat_inb_octs_pkndx_s cn68xxp1; 5503232812Sjmallett}; 5504232812Sjmalletttypedef union cvmx_pip_stat_inb_octs_pkndx cvmx_pip_stat_inb_octs_pkndx_t; 5505232812Sjmallett 5506232812Sjmallett/** 5507215976Sjmallett * cvmx_pip_stat_inb_pkts# 5508215976Sjmallett * 5509215976Sjmallett * PIP_STAT_INB_PKTSX = Inbound packets received by PIP per port 5510215976Sjmallett * 5511215976Sjmallett * Inbound stats collect all data sent to PIP from all packet interfaces. 5512215976Sjmallett * Its the raw counts of everything that comes into the block. The counts 5513215976Sjmallett * will reflect all error packets and packets dropped by the PKI RED engine. 5514215976Sjmallett * These counts are intended for system debug, but could convey useful 5515215976Sjmallett * information in production systems. 5516215976Sjmallett */ 5517232812Sjmallettunion cvmx_pip_stat_inb_pktsx { 5518215976Sjmallett uint64_t u64; 5519232812Sjmallett struct cvmx_pip_stat_inb_pktsx_s { 5520232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5521215976Sjmallett uint64_t reserved_32_63 : 32; 5522215976Sjmallett uint64_t pkts : 32; /**< Number of packets without errors 5523215976Sjmallett received by PIP */ 5524215976Sjmallett#else 5525215976Sjmallett uint64_t pkts : 32; 5526215976Sjmallett uint64_t reserved_32_63 : 32; 5527215976Sjmallett#endif 5528215976Sjmallett } s; 5529215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn30xx; 5530215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn31xx; 5531215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn38xx; 5532215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn38xxp2; 5533215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn50xx; 5534215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn52xx; 5535215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn52xxp1; 5536215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn56xx; 5537215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn56xxp1; 5538215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn58xx; 5539215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn58xxp1; 5540232812Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn61xx; 5541215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn63xx; 5542215976Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn63xxp1; 5543232812Sjmallett struct cvmx_pip_stat_inb_pktsx_s cn66xx; 5544232812Sjmallett struct cvmx_pip_stat_inb_pktsx_s cnf71xx; 5545215976Sjmallett}; 5546215976Sjmalletttypedef union cvmx_pip_stat_inb_pktsx cvmx_pip_stat_inb_pktsx_t; 5547215976Sjmallett 5548215976Sjmallett/** 5549232812Sjmallett * cvmx_pip_stat_inb_pkts_pknd# 5550232812Sjmallett * 5551232812Sjmallett * PIP_STAT_INB_PKTS_PKNDX = Inbound packets received by PIP per pkind 5552232812Sjmallett * 5553232812Sjmallett * Inbound stats collect all data sent to PIP from all packet interfaces. 5554232812Sjmallett * Its the raw counts of everything that comes into the block. The counts 5555232812Sjmallett * will reflect all error packets and packets dropped by the PKI RED engine. 5556232812Sjmallett * These counts are intended for system debug, but could convey useful 5557232812Sjmallett * information in production systems. 5558232812Sjmallett */ 5559232812Sjmallettunion cvmx_pip_stat_inb_pkts_pkndx { 5560232812Sjmallett uint64_t u64; 5561232812Sjmallett struct cvmx_pip_stat_inb_pkts_pkndx_s { 5562232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5563232812Sjmallett uint64_t reserved_32_63 : 32; 5564232812Sjmallett uint64_t pkts : 32; /**< Number of packets without errors 5565232812Sjmallett received by PIP */ 5566232812Sjmallett#else 5567232812Sjmallett uint64_t pkts : 32; 5568232812Sjmallett uint64_t reserved_32_63 : 32; 5569232812Sjmallett#endif 5570232812Sjmallett } s; 5571232812Sjmallett struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xx; 5572232812Sjmallett struct cvmx_pip_stat_inb_pkts_pkndx_s cn68xxp1; 5573232812Sjmallett}; 5574232812Sjmalletttypedef union cvmx_pip_stat_inb_pkts_pkndx cvmx_pip_stat_inb_pkts_pkndx_t; 5575232812Sjmallett 5576232812Sjmallett/** 5577232812Sjmallett * cvmx_pip_sub_pkind_fcs# 5578232812Sjmallett */ 5579232812Sjmallettunion cvmx_pip_sub_pkind_fcsx { 5580232812Sjmallett uint64_t u64; 5581232812Sjmallett struct cvmx_pip_sub_pkind_fcsx_s { 5582232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5583232812Sjmallett uint64_t port_bit : 64; /**< When set '1', the pkind corresponding to the bit 5584232812Sjmallett position set, will subtract the FCS for packets 5585232812Sjmallett on that pkind. */ 5586232812Sjmallett#else 5587232812Sjmallett uint64_t port_bit : 64; 5588232812Sjmallett#endif 5589232812Sjmallett } s; 5590232812Sjmallett struct cvmx_pip_sub_pkind_fcsx_s cn68xx; 5591232812Sjmallett struct cvmx_pip_sub_pkind_fcsx_s cn68xxp1; 5592232812Sjmallett}; 5593232812Sjmalletttypedef union cvmx_pip_sub_pkind_fcsx cvmx_pip_sub_pkind_fcsx_t; 5594232812Sjmallett 5595232812Sjmallett/** 5596215976Sjmallett * cvmx_pip_tag_inc# 5597215976Sjmallett * 5598215976Sjmallett * PIP_TAG_INC = Which bytes to include in the new tag hash algorithm 5599215976Sjmallett * 5600215976Sjmallett * # $PIP_TAG_INCX = 0x300+X X=(0..63) RegType=(RSL) RtlReg=(pip_tag_inc_csr_direct_TestbuilderTask) 5601215976Sjmallett */ 5602232812Sjmallettunion cvmx_pip_tag_incx { 5603215976Sjmallett uint64_t u64; 5604232812Sjmallett struct cvmx_pip_tag_incx_s { 5605232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5606215976Sjmallett uint64_t reserved_8_63 : 56; 5607215976Sjmallett uint64_t en : 8; /**< Which bytes to include in mask tag algorithm 5608215976Sjmallett Broken into 4, 16-entry masks to cover 128B 5609215976Sjmallett PIP_PRT_CFG[TAG_INC] selects 1 of 4 to use 5610215976Sjmallett registers 0-15 map to PIP_PRT_CFG[TAG_INC] == 0 5611215976Sjmallett registers 16-31 map to PIP_PRT_CFG[TAG_INC] == 1 5612215976Sjmallett registers 32-47 map to PIP_PRT_CFG[TAG_INC] == 2 5613215976Sjmallett registers 48-63 map to PIP_PRT_CFG[TAG_INC] == 3 5614215976Sjmallett [7] coresponds to the MSB of the 8B word 5615215976Sjmallett [0] coresponds to the LSB of the 8B word 5616215976Sjmallett If PTP_MODE, the 8B timestamp is prepended to the 5617215976Sjmallett packet. The EN byte masks should be adjusted to 5618215976Sjmallett compensate for the additional timestamp field. */ 5619215976Sjmallett#else 5620215976Sjmallett uint64_t en : 8; 5621215976Sjmallett uint64_t reserved_8_63 : 56; 5622215976Sjmallett#endif 5623215976Sjmallett } s; 5624215976Sjmallett struct cvmx_pip_tag_incx_s cn30xx; 5625215976Sjmallett struct cvmx_pip_tag_incx_s cn31xx; 5626215976Sjmallett struct cvmx_pip_tag_incx_s cn38xx; 5627215976Sjmallett struct cvmx_pip_tag_incx_s cn38xxp2; 5628215976Sjmallett struct cvmx_pip_tag_incx_s cn50xx; 5629215976Sjmallett struct cvmx_pip_tag_incx_s cn52xx; 5630215976Sjmallett struct cvmx_pip_tag_incx_s cn52xxp1; 5631215976Sjmallett struct cvmx_pip_tag_incx_s cn56xx; 5632215976Sjmallett struct cvmx_pip_tag_incx_s cn56xxp1; 5633215976Sjmallett struct cvmx_pip_tag_incx_s cn58xx; 5634215976Sjmallett struct cvmx_pip_tag_incx_s cn58xxp1; 5635232812Sjmallett struct cvmx_pip_tag_incx_s cn61xx; 5636215976Sjmallett struct cvmx_pip_tag_incx_s cn63xx; 5637215976Sjmallett struct cvmx_pip_tag_incx_s cn63xxp1; 5638232812Sjmallett struct cvmx_pip_tag_incx_s cn66xx; 5639232812Sjmallett struct cvmx_pip_tag_incx_s cn68xx; 5640232812Sjmallett struct cvmx_pip_tag_incx_s cn68xxp1; 5641232812Sjmallett struct cvmx_pip_tag_incx_s cnf71xx; 5642215976Sjmallett}; 5643215976Sjmalletttypedef union cvmx_pip_tag_incx cvmx_pip_tag_incx_t; 5644215976Sjmallett 5645215976Sjmallett/** 5646215976Sjmallett * cvmx_pip_tag_mask 5647215976Sjmallett * 5648215976Sjmallett * PIP_TAG_MASK = Mask bit in the tag generation 5649215976Sjmallett * 5650215976Sjmallett */ 5651232812Sjmallettunion cvmx_pip_tag_mask { 5652215976Sjmallett uint64_t u64; 5653232812Sjmallett struct cvmx_pip_tag_mask_s { 5654232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5655215976Sjmallett uint64_t reserved_16_63 : 48; 5656215976Sjmallett uint64_t mask : 16; /**< When set, MASK clears individual bits of lower 16 5657215976Sjmallett bits of the computed tag. Does not effect RAW 5658215976Sjmallett or INSTR HDR packets. */ 5659215976Sjmallett#else 5660215976Sjmallett uint64_t mask : 16; 5661215976Sjmallett uint64_t reserved_16_63 : 48; 5662215976Sjmallett#endif 5663215976Sjmallett } s; 5664215976Sjmallett struct cvmx_pip_tag_mask_s cn30xx; 5665215976Sjmallett struct cvmx_pip_tag_mask_s cn31xx; 5666215976Sjmallett struct cvmx_pip_tag_mask_s cn38xx; 5667215976Sjmallett struct cvmx_pip_tag_mask_s cn38xxp2; 5668215976Sjmallett struct cvmx_pip_tag_mask_s cn50xx; 5669215976Sjmallett struct cvmx_pip_tag_mask_s cn52xx; 5670215976Sjmallett struct cvmx_pip_tag_mask_s cn52xxp1; 5671215976Sjmallett struct cvmx_pip_tag_mask_s cn56xx; 5672215976Sjmallett struct cvmx_pip_tag_mask_s cn56xxp1; 5673215976Sjmallett struct cvmx_pip_tag_mask_s cn58xx; 5674215976Sjmallett struct cvmx_pip_tag_mask_s cn58xxp1; 5675232812Sjmallett struct cvmx_pip_tag_mask_s cn61xx; 5676215976Sjmallett struct cvmx_pip_tag_mask_s cn63xx; 5677215976Sjmallett struct cvmx_pip_tag_mask_s cn63xxp1; 5678232812Sjmallett struct cvmx_pip_tag_mask_s cn66xx; 5679232812Sjmallett struct cvmx_pip_tag_mask_s cn68xx; 5680232812Sjmallett struct cvmx_pip_tag_mask_s cn68xxp1; 5681232812Sjmallett struct cvmx_pip_tag_mask_s cnf71xx; 5682215976Sjmallett}; 5683215976Sjmalletttypedef union cvmx_pip_tag_mask cvmx_pip_tag_mask_t; 5684215976Sjmallett 5685215976Sjmallett/** 5686215976Sjmallett * cvmx_pip_tag_secret 5687215976Sjmallett * 5688215976Sjmallett * PIP_TAG_SECRET = Initial value in tag generation 5689215976Sjmallett * 5690215976Sjmallett * The source and destination IV's provide a mechanism for each Octeon to be unique. 5691215976Sjmallett */ 5692232812Sjmallettunion cvmx_pip_tag_secret { 5693215976Sjmallett uint64_t u64; 5694232812Sjmallett struct cvmx_pip_tag_secret_s { 5695232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5696215976Sjmallett uint64_t reserved_32_63 : 32; 5697215976Sjmallett uint64_t dst : 16; /**< Secret for the destination tuple tag CRC calc */ 5698215976Sjmallett uint64_t src : 16; /**< Secret for the source tuple tag CRC calc */ 5699215976Sjmallett#else 5700215976Sjmallett uint64_t src : 16; 5701215976Sjmallett uint64_t dst : 16; 5702215976Sjmallett uint64_t reserved_32_63 : 32; 5703215976Sjmallett#endif 5704215976Sjmallett } s; 5705215976Sjmallett struct cvmx_pip_tag_secret_s cn30xx; 5706215976Sjmallett struct cvmx_pip_tag_secret_s cn31xx; 5707215976Sjmallett struct cvmx_pip_tag_secret_s cn38xx; 5708215976Sjmallett struct cvmx_pip_tag_secret_s cn38xxp2; 5709215976Sjmallett struct cvmx_pip_tag_secret_s cn50xx; 5710215976Sjmallett struct cvmx_pip_tag_secret_s cn52xx; 5711215976Sjmallett struct cvmx_pip_tag_secret_s cn52xxp1; 5712215976Sjmallett struct cvmx_pip_tag_secret_s cn56xx; 5713215976Sjmallett struct cvmx_pip_tag_secret_s cn56xxp1; 5714215976Sjmallett struct cvmx_pip_tag_secret_s cn58xx; 5715215976Sjmallett struct cvmx_pip_tag_secret_s cn58xxp1; 5716232812Sjmallett struct cvmx_pip_tag_secret_s cn61xx; 5717215976Sjmallett struct cvmx_pip_tag_secret_s cn63xx; 5718215976Sjmallett struct cvmx_pip_tag_secret_s cn63xxp1; 5719232812Sjmallett struct cvmx_pip_tag_secret_s cn66xx; 5720232812Sjmallett struct cvmx_pip_tag_secret_s cn68xx; 5721232812Sjmallett struct cvmx_pip_tag_secret_s cn68xxp1; 5722232812Sjmallett struct cvmx_pip_tag_secret_s cnf71xx; 5723215976Sjmallett}; 5724215976Sjmalletttypedef union cvmx_pip_tag_secret cvmx_pip_tag_secret_t; 5725215976Sjmallett 5726215976Sjmallett/** 5727215976Sjmallett * cvmx_pip_todo_entry 5728215976Sjmallett * 5729215976Sjmallett * PIP_TODO_ENTRY = Head entry of the Todo list (debug only) 5730215976Sjmallett * 5731215976Sjmallett * Summary of the current packet that has completed and waiting to be processed 5732215976Sjmallett */ 5733232812Sjmallettunion cvmx_pip_todo_entry { 5734215976Sjmallett uint64_t u64; 5735232812Sjmallett struct cvmx_pip_todo_entry_s { 5736232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5737215976Sjmallett uint64_t val : 1; /**< Entry is valid */ 5738215976Sjmallett uint64_t reserved_62_62 : 1; 5739215976Sjmallett uint64_t entry : 62; /**< Todo list entry summary */ 5740215976Sjmallett#else 5741215976Sjmallett uint64_t entry : 62; 5742215976Sjmallett uint64_t reserved_62_62 : 1; 5743215976Sjmallett uint64_t val : 1; 5744215976Sjmallett#endif 5745215976Sjmallett } s; 5746215976Sjmallett struct cvmx_pip_todo_entry_s cn30xx; 5747215976Sjmallett struct cvmx_pip_todo_entry_s cn31xx; 5748215976Sjmallett struct cvmx_pip_todo_entry_s cn38xx; 5749215976Sjmallett struct cvmx_pip_todo_entry_s cn38xxp2; 5750215976Sjmallett struct cvmx_pip_todo_entry_s cn50xx; 5751215976Sjmallett struct cvmx_pip_todo_entry_s cn52xx; 5752215976Sjmallett struct cvmx_pip_todo_entry_s cn52xxp1; 5753215976Sjmallett struct cvmx_pip_todo_entry_s cn56xx; 5754215976Sjmallett struct cvmx_pip_todo_entry_s cn56xxp1; 5755215976Sjmallett struct cvmx_pip_todo_entry_s cn58xx; 5756215976Sjmallett struct cvmx_pip_todo_entry_s cn58xxp1; 5757232812Sjmallett struct cvmx_pip_todo_entry_s cn61xx; 5758215976Sjmallett struct cvmx_pip_todo_entry_s cn63xx; 5759215976Sjmallett struct cvmx_pip_todo_entry_s cn63xxp1; 5760232812Sjmallett struct cvmx_pip_todo_entry_s cn66xx; 5761232812Sjmallett struct cvmx_pip_todo_entry_s cn68xx; 5762232812Sjmallett struct cvmx_pip_todo_entry_s cn68xxp1; 5763232812Sjmallett struct cvmx_pip_todo_entry_s cnf71xx; 5764215976Sjmallett}; 5765215976Sjmalletttypedef union cvmx_pip_todo_entry cvmx_pip_todo_entry_t; 5766215976Sjmallett 5767215976Sjmallett/** 5768232812Sjmallett * cvmx_pip_vlan_etypes# 5769232812Sjmallett */ 5770232812Sjmallettunion cvmx_pip_vlan_etypesx { 5771232812Sjmallett uint64_t u64; 5772232812Sjmallett struct cvmx_pip_vlan_etypesx_s { 5773232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5774232812Sjmallett uint64_t type3 : 16; /**< VLAN Ethertype */ 5775232812Sjmallett uint64_t type2 : 16; /**< VLAN Ethertype */ 5776232812Sjmallett uint64_t type1 : 16; /**< VLAN Ethertype */ 5777232812Sjmallett uint64_t type0 : 16; /**< VLAN Ethertype 5778232812Sjmallett Specifies ethertypes that will be parsed as 5779232812Sjmallett containing VLAN information. Each TYPE is 5780232812Sjmallett orthagonal; if all eight are not required, set 5781232812Sjmallett multiple TYPEs to the same value (as in the 5782232812Sjmallett 0x8100 default value). */ 5783232812Sjmallett#else 5784232812Sjmallett uint64_t type0 : 16; 5785232812Sjmallett uint64_t type1 : 16; 5786232812Sjmallett uint64_t type2 : 16; 5787232812Sjmallett uint64_t type3 : 16; 5788232812Sjmallett#endif 5789232812Sjmallett } s; 5790232812Sjmallett struct cvmx_pip_vlan_etypesx_s cn61xx; 5791232812Sjmallett struct cvmx_pip_vlan_etypesx_s cn66xx; 5792232812Sjmallett struct cvmx_pip_vlan_etypesx_s cn68xx; 5793232812Sjmallett struct cvmx_pip_vlan_etypesx_s cnf71xx; 5794232812Sjmallett}; 5795232812Sjmalletttypedef union cvmx_pip_vlan_etypesx cvmx_pip_vlan_etypesx_t; 5796232812Sjmallett 5797232812Sjmallett/** 5798215976Sjmallett * cvmx_pip_xstat0_prt# 5799215976Sjmallett * 5800215976Sjmallett * PIP_XSTAT0_PRT = PIP_XSTAT_DRP_PKTS / PIP_XSTAT_DRP_OCTS 5801215976Sjmallett * 5802215976Sjmallett */ 5803232812Sjmallettunion cvmx_pip_xstat0_prtx { 5804215976Sjmallett uint64_t u64; 5805232812Sjmallett struct cvmx_pip_xstat0_prtx_s { 5806232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5807215976Sjmallett uint64_t drp_pkts : 32; /**< Inbound packets marked to be dropped by the IPD 5808215976Sjmallett QOS widget per port */ 5809215976Sjmallett uint64_t drp_octs : 32; /**< Inbound octets marked to be dropped by the IPD 5810215976Sjmallett QOS widget per port */ 5811215976Sjmallett#else 5812215976Sjmallett uint64_t drp_octs : 32; 5813215976Sjmallett uint64_t drp_pkts : 32; 5814215976Sjmallett#endif 5815215976Sjmallett } s; 5816215976Sjmallett struct cvmx_pip_xstat0_prtx_s cn63xx; 5817215976Sjmallett struct cvmx_pip_xstat0_prtx_s cn63xxp1; 5818232812Sjmallett struct cvmx_pip_xstat0_prtx_s cn66xx; 5819215976Sjmallett}; 5820215976Sjmalletttypedef union cvmx_pip_xstat0_prtx cvmx_pip_xstat0_prtx_t; 5821215976Sjmallett 5822215976Sjmallett/** 5823232812Sjmallett * cvmx_pip_xstat10_prt# 5824232812Sjmallett * 5825232812Sjmallett * PIP_XSTAT10_PRTX = PIP_XSTAT_L2_MCAST / PIP_XSTAT_L2_BCAST 5826232812Sjmallett * 5827232812Sjmallett */ 5828232812Sjmallettunion cvmx_pip_xstat10_prtx { 5829232812Sjmallett uint64_t u64; 5830232812Sjmallett struct cvmx_pip_xstat10_prtx_s { 5831232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5832232812Sjmallett uint64_t bcast : 32; /**< Number of packets with L2 Broadcast DMAC 5833232812Sjmallett that were dropped due to RED. 5834232812Sjmallett The HW will consider a packet to be an L2 5835232812Sjmallett broadcast packet when the 48-bit DMAC is all 1's. 5836232812Sjmallett Only applies when the parse mode for the packet 5837232812Sjmallett is SKIP-TO-L2. */ 5838232812Sjmallett uint64_t mcast : 32; /**< Number of packets with L2 Mulitcast DMAC 5839232812Sjmallett that were dropped due to RED. 5840232812Sjmallett The HW will consider a packet to be an L2 5841232812Sjmallett multicast packet when the least-significant bit 5842232812Sjmallett of the first byte of the DMAC is set and the 5843232812Sjmallett packet is not an L2 broadcast packet. 5844232812Sjmallett Only applies when the parse mode for the packet 5845232812Sjmallett is SKIP-TO-L2. */ 5846232812Sjmallett#else 5847232812Sjmallett uint64_t mcast : 32; 5848232812Sjmallett uint64_t bcast : 32; 5849232812Sjmallett#endif 5850232812Sjmallett } s; 5851232812Sjmallett struct cvmx_pip_xstat10_prtx_s cn63xx; 5852232812Sjmallett struct cvmx_pip_xstat10_prtx_s cn63xxp1; 5853232812Sjmallett struct cvmx_pip_xstat10_prtx_s cn66xx; 5854232812Sjmallett}; 5855232812Sjmalletttypedef union cvmx_pip_xstat10_prtx cvmx_pip_xstat10_prtx_t; 5856232812Sjmallett 5857232812Sjmallett/** 5858232812Sjmallett * cvmx_pip_xstat11_prt# 5859232812Sjmallett * 5860232812Sjmallett * PIP_XSTAT11_PRTX = PIP_XSTAT_L3_MCAST / PIP_XSTAT_L3_BCAST 5861232812Sjmallett * 5862232812Sjmallett */ 5863232812Sjmallettunion cvmx_pip_xstat11_prtx { 5864232812Sjmallett uint64_t u64; 5865232812Sjmallett struct cvmx_pip_xstat11_prtx_s { 5866232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5867232812Sjmallett uint64_t bcast : 32; /**< Number of packets with L3 Broadcast Dest Address 5868232812Sjmallett that were dropped due to RED. 5869232812Sjmallett The HW considers an IPv4 packet to be broadcast 5870232812Sjmallett when all bits are set in the MSB of the 5871232812Sjmallett destination address. IPv6 does not have the 5872232812Sjmallett concept of a broadcast packets. 5873232812Sjmallett Only applies when the parse mode for the packet 5874232812Sjmallett is SKIP-TO-L2 and the packet is IP or the parse 5875232812Sjmallett mode for the packet is SKIP-TO-IP. */ 5876232812Sjmallett uint64_t mcast : 32; /**< Number of packets with L3 Multicast Dest Address 5877232812Sjmallett that were dropped due to RED. 5878232812Sjmallett The HW considers an IPv4 packet to be multicast 5879232812Sjmallett when the most-significant nibble of the 32-bit 5880232812Sjmallett destination address is 0xE (i.e. it is a class D 5881232812Sjmallett address). The HW considers an IPv6 packet to be 5882232812Sjmallett multicast when the most-significant byte of the 5883232812Sjmallett 128-bit destination address is all 1's. 5884232812Sjmallett Only applies when the parse mode for the packet 5885232812Sjmallett is SKIP-TO-L2 and the packet is IP or the parse 5886232812Sjmallett mode for the packet is SKIP-TO-IP. */ 5887232812Sjmallett#else 5888232812Sjmallett uint64_t mcast : 32; 5889232812Sjmallett uint64_t bcast : 32; 5890232812Sjmallett#endif 5891232812Sjmallett } s; 5892232812Sjmallett struct cvmx_pip_xstat11_prtx_s cn63xx; 5893232812Sjmallett struct cvmx_pip_xstat11_prtx_s cn63xxp1; 5894232812Sjmallett struct cvmx_pip_xstat11_prtx_s cn66xx; 5895232812Sjmallett}; 5896232812Sjmalletttypedef union cvmx_pip_xstat11_prtx cvmx_pip_xstat11_prtx_t; 5897232812Sjmallett 5898232812Sjmallett/** 5899215976Sjmallett * cvmx_pip_xstat1_prt# 5900215976Sjmallett * 5901215976Sjmallett * PIP_XSTAT1_PRTX = PIP_XSTAT_OCTS 5902215976Sjmallett * 5903215976Sjmallett */ 5904232812Sjmallettunion cvmx_pip_xstat1_prtx { 5905215976Sjmallett uint64_t u64; 5906232812Sjmallett struct cvmx_pip_xstat1_prtx_s { 5907232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5908215976Sjmallett uint64_t reserved_48_63 : 16; 5909215976Sjmallett uint64_t octs : 48; /**< Number of octets received by PIP (good and bad) */ 5910215976Sjmallett#else 5911215976Sjmallett uint64_t octs : 48; 5912215976Sjmallett uint64_t reserved_48_63 : 16; 5913215976Sjmallett#endif 5914215976Sjmallett } s; 5915215976Sjmallett struct cvmx_pip_xstat1_prtx_s cn63xx; 5916215976Sjmallett struct cvmx_pip_xstat1_prtx_s cn63xxp1; 5917232812Sjmallett struct cvmx_pip_xstat1_prtx_s cn66xx; 5918215976Sjmallett}; 5919215976Sjmalletttypedef union cvmx_pip_xstat1_prtx cvmx_pip_xstat1_prtx_t; 5920215976Sjmallett 5921215976Sjmallett/** 5922215976Sjmallett * cvmx_pip_xstat2_prt# 5923215976Sjmallett * 5924215976Sjmallett * PIP_XSTAT2_PRTX = PIP_XSTAT_PKTS / PIP_XSTAT_RAW 5925215976Sjmallett * 5926215976Sjmallett */ 5927232812Sjmallettunion cvmx_pip_xstat2_prtx { 5928215976Sjmallett uint64_t u64; 5929232812Sjmallett struct cvmx_pip_xstat2_prtx_s { 5930232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5931215976Sjmallett uint64_t pkts : 32; /**< Number of packets processed by PIP */ 5932215976Sjmallett uint64_t raw : 32; /**< RAWFULL + RAWSCH Packets without an L1/L2 error 5933215976Sjmallett received by PIP per port */ 5934215976Sjmallett#else 5935215976Sjmallett uint64_t raw : 32; 5936215976Sjmallett uint64_t pkts : 32; 5937215976Sjmallett#endif 5938215976Sjmallett } s; 5939215976Sjmallett struct cvmx_pip_xstat2_prtx_s cn63xx; 5940215976Sjmallett struct cvmx_pip_xstat2_prtx_s cn63xxp1; 5941232812Sjmallett struct cvmx_pip_xstat2_prtx_s cn66xx; 5942215976Sjmallett}; 5943215976Sjmalletttypedef union cvmx_pip_xstat2_prtx cvmx_pip_xstat2_prtx_t; 5944215976Sjmallett 5945215976Sjmallett/** 5946215976Sjmallett * cvmx_pip_xstat3_prt# 5947215976Sjmallett * 5948215976Sjmallett * PIP_XSTAT3_PRTX = PIP_XSTAT_BCST / PIP_XSTAT_MCST 5949215976Sjmallett * 5950215976Sjmallett */ 5951232812Sjmallettunion cvmx_pip_xstat3_prtx { 5952215976Sjmallett uint64_t u64; 5953232812Sjmallett struct cvmx_pip_xstat3_prtx_s { 5954232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5955215976Sjmallett uint64_t bcst : 32; /**< Number of indentified L2 broadcast packets 5956215976Sjmallett Does not include multicast packets 5957215976Sjmallett Only includes packets whose parse mode is 5958215976Sjmallett SKIP_TO_L2. */ 5959215976Sjmallett uint64_t mcst : 32; /**< Number of indentified L2 multicast packets 5960215976Sjmallett Does not include broadcast packets 5961215976Sjmallett Only includes packets whose parse mode is 5962215976Sjmallett SKIP_TO_L2. */ 5963215976Sjmallett#else 5964215976Sjmallett uint64_t mcst : 32; 5965215976Sjmallett uint64_t bcst : 32; 5966215976Sjmallett#endif 5967215976Sjmallett } s; 5968215976Sjmallett struct cvmx_pip_xstat3_prtx_s cn63xx; 5969215976Sjmallett struct cvmx_pip_xstat3_prtx_s cn63xxp1; 5970232812Sjmallett struct cvmx_pip_xstat3_prtx_s cn66xx; 5971215976Sjmallett}; 5972215976Sjmalletttypedef union cvmx_pip_xstat3_prtx cvmx_pip_xstat3_prtx_t; 5973215976Sjmallett 5974215976Sjmallett/** 5975215976Sjmallett * cvmx_pip_xstat4_prt# 5976215976Sjmallett * 5977215976Sjmallett * PIP_XSTAT4_PRTX = PIP_XSTAT_HIST1 / PIP_XSTAT_HIST0 5978215976Sjmallett * 5979215976Sjmallett */ 5980232812Sjmallettunion cvmx_pip_xstat4_prtx { 5981215976Sjmallett uint64_t u64; 5982232812Sjmallett struct cvmx_pip_xstat4_prtx_s { 5983232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5984215976Sjmallett uint64_t h65to127 : 32; /**< Number of 65-127B packets */ 5985215976Sjmallett uint64_t h64 : 32; /**< Number of 1-64B packets */ 5986215976Sjmallett#else 5987215976Sjmallett uint64_t h64 : 32; 5988215976Sjmallett uint64_t h65to127 : 32; 5989215976Sjmallett#endif 5990215976Sjmallett } s; 5991215976Sjmallett struct cvmx_pip_xstat4_prtx_s cn63xx; 5992215976Sjmallett struct cvmx_pip_xstat4_prtx_s cn63xxp1; 5993232812Sjmallett struct cvmx_pip_xstat4_prtx_s cn66xx; 5994215976Sjmallett}; 5995215976Sjmalletttypedef union cvmx_pip_xstat4_prtx cvmx_pip_xstat4_prtx_t; 5996215976Sjmallett 5997215976Sjmallett/** 5998215976Sjmallett * cvmx_pip_xstat5_prt# 5999215976Sjmallett * 6000215976Sjmallett * PIP_XSTAT5_PRTX = PIP_XSTAT_HIST3 / PIP_XSTAT_HIST2 6001215976Sjmallett * 6002215976Sjmallett */ 6003232812Sjmallettunion cvmx_pip_xstat5_prtx { 6004215976Sjmallett uint64_t u64; 6005232812Sjmallett struct cvmx_pip_xstat5_prtx_s { 6006232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6007215976Sjmallett uint64_t h256to511 : 32; /**< Number of 256-511B packets */ 6008215976Sjmallett uint64_t h128to255 : 32; /**< Number of 128-255B packets */ 6009215976Sjmallett#else 6010215976Sjmallett uint64_t h128to255 : 32; 6011215976Sjmallett uint64_t h256to511 : 32; 6012215976Sjmallett#endif 6013215976Sjmallett } s; 6014215976Sjmallett struct cvmx_pip_xstat5_prtx_s cn63xx; 6015215976Sjmallett struct cvmx_pip_xstat5_prtx_s cn63xxp1; 6016232812Sjmallett struct cvmx_pip_xstat5_prtx_s cn66xx; 6017215976Sjmallett}; 6018215976Sjmalletttypedef union cvmx_pip_xstat5_prtx cvmx_pip_xstat5_prtx_t; 6019215976Sjmallett 6020215976Sjmallett/** 6021215976Sjmallett * cvmx_pip_xstat6_prt# 6022215976Sjmallett * 6023215976Sjmallett * PIP_XSTAT6_PRTX = PIP_XSTAT_HIST5 / PIP_XSTAT_HIST4 6024215976Sjmallett * 6025215976Sjmallett */ 6026232812Sjmallettunion cvmx_pip_xstat6_prtx { 6027215976Sjmallett uint64_t u64; 6028232812Sjmallett struct cvmx_pip_xstat6_prtx_s { 6029232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6030215976Sjmallett uint64_t h1024to1518 : 32; /**< Number of 1024-1518B packets */ 6031215976Sjmallett uint64_t h512to1023 : 32; /**< Number of 512-1023B packets */ 6032215976Sjmallett#else 6033215976Sjmallett uint64_t h512to1023 : 32; 6034215976Sjmallett uint64_t h1024to1518 : 32; 6035215976Sjmallett#endif 6036215976Sjmallett } s; 6037215976Sjmallett struct cvmx_pip_xstat6_prtx_s cn63xx; 6038215976Sjmallett struct cvmx_pip_xstat6_prtx_s cn63xxp1; 6039232812Sjmallett struct cvmx_pip_xstat6_prtx_s cn66xx; 6040215976Sjmallett}; 6041215976Sjmalletttypedef union cvmx_pip_xstat6_prtx cvmx_pip_xstat6_prtx_t; 6042215976Sjmallett 6043215976Sjmallett/** 6044215976Sjmallett * cvmx_pip_xstat7_prt# 6045215976Sjmallett * 6046215976Sjmallett * PIP_XSTAT7_PRTX = PIP_XSTAT_FCS / PIP_XSTAT_HIST6 6047215976Sjmallett * 6048215976Sjmallett * 6049215976Sjmallett * Notes: 6050232812Sjmallett * DPI does not check FCS, therefore FCS will never increment on DPI ports 32-35 6051232812Sjmallett * sRIO does not check FCS, therefore FCS will never increment on sRIO ports 40-47 6052215976Sjmallett */ 6053232812Sjmallettunion cvmx_pip_xstat7_prtx { 6054215976Sjmallett uint64_t u64; 6055232812Sjmallett struct cvmx_pip_xstat7_prtx_s { 6056232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6057215976Sjmallett uint64_t fcs : 32; /**< Number of packets with FCS or Align opcode errors */ 6058215976Sjmallett uint64_t h1519 : 32; /**< Number of 1519-max packets */ 6059215976Sjmallett#else 6060215976Sjmallett uint64_t h1519 : 32; 6061215976Sjmallett uint64_t fcs : 32; 6062215976Sjmallett#endif 6063215976Sjmallett } s; 6064215976Sjmallett struct cvmx_pip_xstat7_prtx_s cn63xx; 6065215976Sjmallett struct cvmx_pip_xstat7_prtx_s cn63xxp1; 6066232812Sjmallett struct cvmx_pip_xstat7_prtx_s cn66xx; 6067215976Sjmallett}; 6068215976Sjmalletttypedef union cvmx_pip_xstat7_prtx cvmx_pip_xstat7_prtx_t; 6069215976Sjmallett 6070215976Sjmallett/** 6071215976Sjmallett * cvmx_pip_xstat8_prt# 6072215976Sjmallett * 6073215976Sjmallett * PIP_XSTAT8_PRTX = PIP_XSTAT_FRAG / PIP_XSTAT_UNDER 6074215976Sjmallett * 6075215976Sjmallett * 6076215976Sjmallett * Notes: 6077232812Sjmallett * DPI does not check FCS, therefore FRAG will never increment on DPI ports 32-35 6078232812Sjmallett * sRIO does not check FCS, therefore FRAG will never increment on sRIO ports 40-47 6079215976Sjmallett */ 6080232812Sjmallettunion cvmx_pip_xstat8_prtx { 6081215976Sjmallett uint64_t u64; 6082232812Sjmallett struct cvmx_pip_xstat8_prtx_s { 6083232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6084215976Sjmallett uint64_t frag : 32; /**< Number of packets with length < min and FCS error */ 6085215976Sjmallett uint64_t undersz : 32; /**< Number of packets with length < min */ 6086215976Sjmallett#else 6087215976Sjmallett uint64_t undersz : 32; 6088215976Sjmallett uint64_t frag : 32; 6089215976Sjmallett#endif 6090215976Sjmallett } s; 6091215976Sjmallett struct cvmx_pip_xstat8_prtx_s cn63xx; 6092215976Sjmallett struct cvmx_pip_xstat8_prtx_s cn63xxp1; 6093232812Sjmallett struct cvmx_pip_xstat8_prtx_s cn66xx; 6094215976Sjmallett}; 6095215976Sjmalletttypedef union cvmx_pip_xstat8_prtx cvmx_pip_xstat8_prtx_t; 6096215976Sjmallett 6097215976Sjmallett/** 6098215976Sjmallett * cvmx_pip_xstat9_prt# 6099215976Sjmallett * 6100215976Sjmallett * PIP_XSTAT9_PRTX = PIP_XSTAT_JABBER / PIP_XSTAT_OVER 6101215976Sjmallett * 6102215976Sjmallett * 6103215976Sjmallett * Notes: 6104232812Sjmallett * DPI does not check FCS, therefore JABBER will never increment on DPI ports 32-35 6105232812Sjmallett * sRIO does not check FCS, therefore JABBER will never increment on sRIO ports 40-47 due to FCS errors 6106232812Sjmallett * sRIO does use the JABBER opcode to communicate sRIO error, therefore JABBER can increment under the sRIO error conditions 6107215976Sjmallett */ 6108232812Sjmallettunion cvmx_pip_xstat9_prtx { 6109215976Sjmallett uint64_t u64; 6110232812Sjmallett struct cvmx_pip_xstat9_prtx_s { 6111232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 6112215976Sjmallett uint64_t jabber : 32; /**< Number of packets with length > max and FCS error */ 6113215976Sjmallett uint64_t oversz : 32; /**< Number of packets with length > max */ 6114215976Sjmallett#else 6115215976Sjmallett uint64_t oversz : 32; 6116215976Sjmallett uint64_t jabber : 32; 6117215976Sjmallett#endif 6118215976Sjmallett } s; 6119215976Sjmallett struct cvmx_pip_xstat9_prtx_s cn63xx; 6120215976Sjmallett struct cvmx_pip_xstat9_prtx_s cn63xxp1; 6121232812Sjmallett struct cvmx_pip_xstat9_prtx_s cn66xx; 6122215976Sjmallett}; 6123215976Sjmalletttypedef union cvmx_pip_xstat9_prtx cvmx_pip_xstat9_prtx_t; 6124215976Sjmallett 6125215976Sjmallett#endif 6126