1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pexp-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) definitions for 45215976Sjmallett * OCTEON PEXP. 46215976Sjmallett * 47215976Sjmallett * <hr>$Revision$<hr> 48215976Sjmallett */ 49215976Sjmallett#ifndef __CVMX_PEXP_DEFS_H__ 50215976Sjmallett#define __CVMX_PEXP_DEFS_H__ 51215976Sjmallett 52215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 53215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset) 54215976Sjmallett{ 55215976Sjmallett if (!( 56215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 57215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 58215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); 59215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16; 60215976Sjmallett} 61215976Sjmallett#else 62215976Sjmallett#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16) 63215976Sjmallett#endif 64215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 65215976Sjmallett#define CVMX_PEXP_NPEI_BIST_STATUS CVMX_PEXP_NPEI_BIST_STATUS_FUNC() 66215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void) 67215976Sjmallett{ 68215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 69215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n"); 70215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008580ull); 71215976Sjmallett} 72215976Sjmallett#else 73215976Sjmallett#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull)) 74215976Sjmallett#endif 75215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 76215976Sjmallett#define CVMX_PEXP_NPEI_BIST_STATUS2 CVMX_PEXP_NPEI_BIST_STATUS2_FUNC() 77215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void) 78215976Sjmallett{ 79215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 80215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n"); 81215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008680ull); 82215976Sjmallett} 83215976Sjmallett#else 84215976Sjmallett#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull)) 85215976Sjmallett#endif 86215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 87215976Sjmallett#define CVMX_PEXP_NPEI_CTL_PORT0 CVMX_PEXP_NPEI_CTL_PORT0_FUNC() 88215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void) 89215976Sjmallett{ 90215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 91215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n"); 92215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008250ull); 93215976Sjmallett} 94215976Sjmallett#else 95215976Sjmallett#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull)) 96215976Sjmallett#endif 97215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 98215976Sjmallett#define CVMX_PEXP_NPEI_CTL_PORT1 CVMX_PEXP_NPEI_CTL_PORT1_FUNC() 99215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void) 100215976Sjmallett{ 101215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 102215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n"); 103215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008260ull); 104215976Sjmallett} 105215976Sjmallett#else 106215976Sjmallett#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull)) 107215976Sjmallett#endif 108215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 109215976Sjmallett#define CVMX_PEXP_NPEI_CTL_STATUS CVMX_PEXP_NPEI_CTL_STATUS_FUNC() 110215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void) 111215976Sjmallett{ 112215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 113215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n"); 114215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008570ull); 115215976Sjmallett} 116215976Sjmallett#else 117215976Sjmallett#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull)) 118215976Sjmallett#endif 119215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 120215976Sjmallett#define CVMX_PEXP_NPEI_CTL_STATUS2 CVMX_PEXP_NPEI_CTL_STATUS2_FUNC() 121215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void) 122215976Sjmallett{ 123215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 124215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n"); 125215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BC00ull); 126215976Sjmallett} 127215976Sjmallett#else 128215976Sjmallett#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull)) 129215976Sjmallett#endif 130215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131215976Sjmallett#define CVMX_PEXP_NPEI_DATA_OUT_CNT CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC() 132215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void) 133215976Sjmallett{ 134215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 135215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n"); 136215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000085F0ull); 137215976Sjmallett} 138215976Sjmallett#else 139215976Sjmallett#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull)) 140215976Sjmallett#endif 141215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 142215976Sjmallett#define CVMX_PEXP_NPEI_DBG_DATA CVMX_PEXP_NPEI_DBG_DATA_FUNC() 143215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DBG_DATA_FUNC(void) 144215976Sjmallett{ 145215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 146215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n"); 147215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008510ull); 148215976Sjmallett} 149215976Sjmallett#else 150215976Sjmallett#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull)) 151215976Sjmallett#endif 152215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 153215976Sjmallett#define CVMX_PEXP_NPEI_DBG_SELECT CVMX_PEXP_NPEI_DBG_SELECT_FUNC() 154215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void) 155215976Sjmallett{ 156215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 157215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n"); 158215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008500ull); 159215976Sjmallett} 160215976Sjmallett#else 161215976Sjmallett#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull)) 162215976Sjmallett#endif 163215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 164215976Sjmallett#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC() 165215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void) 166215976Sjmallett{ 167215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 168215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMA0_INT_LEVEL not supported on this chip\n"); 169215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000085C0ull); 170215976Sjmallett} 171215976Sjmallett#else 172215976Sjmallett#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull)) 173215976Sjmallett#endif 174215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175215976Sjmallett#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC() 176215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void) 177215976Sjmallett{ 178215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 179215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMA1_INT_LEVEL not supported on this chip\n"); 180215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000085D0ull); 181215976Sjmallett} 182215976Sjmallett#else 183215976Sjmallett#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull)) 184215976Sjmallett#endif 185215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset) 187215976Sjmallett{ 188215976Sjmallett if (!( 189215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 190215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 191215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset); 192215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16; 193215976Sjmallett} 194215976Sjmallett#else 195215976Sjmallett#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16) 196215976Sjmallett#endif 197215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 198215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset) 199215976Sjmallett{ 200215976Sjmallett if (!( 201215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 202215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 203215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset); 204215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16; 205215976Sjmallett} 206215976Sjmallett#else 207215976Sjmallett#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16) 208215976Sjmallett#endif 209215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset) 211215976Sjmallett{ 212215976Sjmallett if (!( 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 214215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 215215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset); 216215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16; 217215976Sjmallett} 218215976Sjmallett#else 219215976Sjmallett#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16) 220215976Sjmallett#endif 221215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 222215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset) 223215976Sjmallett{ 224215976Sjmallett if (!( 225215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) || 226215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4))))) 227215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset); 228215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16; 229215976Sjmallett} 230215976Sjmallett#else 231215976Sjmallett#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16) 232215976Sjmallett#endif 233215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 234215976Sjmallett#define CVMX_PEXP_NPEI_DMA_CNTS CVMX_PEXP_NPEI_DMA_CNTS_FUNC() 235215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void) 236215976Sjmallett{ 237215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 238215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMA_CNTS not supported on this chip\n"); 239215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000085E0ull); 240215976Sjmallett} 241215976Sjmallett#else 242215976Sjmallett#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull)) 243215976Sjmallett#endif 244215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 245215976Sjmallett#define CVMX_PEXP_NPEI_DMA_CONTROL CVMX_PEXP_NPEI_DMA_CONTROL_FUNC() 246215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void) 247215976Sjmallett{ 248215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 249215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMA_CONTROL not supported on this chip\n"); 250215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000083A0ull); 251215976Sjmallett} 252215976Sjmallett#else 253215976Sjmallett#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull)) 254215976Sjmallett#endif 255215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 256215976Sjmallett#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC() 257215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC(void) 258215976Sjmallett{ 259215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 260215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n"); 261215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000085B0ull); 262215976Sjmallett} 263215976Sjmallett#else 264215976Sjmallett#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull)) 265215976Sjmallett#endif 266215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 267215976Sjmallett#define CVMX_PEXP_NPEI_DMA_STATE1 CVMX_PEXP_NPEI_DMA_STATE1_FUNC() 268215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_FUNC(void) 269215976Sjmallett{ 270215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 271215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE1 not supported on this chip\n"); 272215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000086C0ull); 273215976Sjmallett} 274215976Sjmallett#else 275215976Sjmallett#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull)) 276215976Sjmallett#endif 277215976Sjmallett#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull)) 278215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 279215976Sjmallett#define CVMX_PEXP_NPEI_DMA_STATE2 CVMX_PEXP_NPEI_DMA_STATE2_FUNC() 280215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_FUNC(void) 281215976Sjmallett{ 282215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX))) 283215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE2 not supported on this chip\n"); 284215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000086D0ull); 285215976Sjmallett} 286215976Sjmallett#else 287215976Sjmallett#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull)) 288215976Sjmallett#endif 289215976Sjmallett#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull)) 290215976Sjmallett#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull)) 291215976Sjmallett#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull)) 292215976Sjmallett#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull)) 293215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 294215976Sjmallett#define CVMX_PEXP_NPEI_INT_A_ENB CVMX_PEXP_NPEI_INT_A_ENB_FUNC() 295215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void) 296215976Sjmallett{ 297215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 298215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB not supported on this chip\n"); 299215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008560ull); 300215976Sjmallett} 301215976Sjmallett#else 302215976Sjmallett#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull)) 303215976Sjmallett#endif 304215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 305215976Sjmallett#define CVMX_PEXP_NPEI_INT_A_ENB2 CVMX_PEXP_NPEI_INT_A_ENB2_FUNC() 306215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void) 307215976Sjmallett{ 308215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 309215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB2 not supported on this chip\n"); 310215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull); 311215976Sjmallett} 312215976Sjmallett#else 313215976Sjmallett#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)) 314215976Sjmallett#endif 315215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 316215976Sjmallett#define CVMX_PEXP_NPEI_INT_A_SUM CVMX_PEXP_NPEI_INT_A_SUM_FUNC() 317215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void) 318215976Sjmallett{ 319215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 320215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_INT_A_SUM not supported on this chip\n"); 321215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008550ull); 322215976Sjmallett} 323215976Sjmallett#else 324215976Sjmallett#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull)) 325215976Sjmallett#endif 326215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 327215976Sjmallett#define CVMX_PEXP_NPEI_INT_ENB CVMX_PEXP_NPEI_INT_ENB_FUNC() 328215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_INT_ENB_FUNC(void) 329215976Sjmallett{ 330215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 331215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_INT_ENB not supported on this chip\n"); 332215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008540ull); 333215976Sjmallett} 334215976Sjmallett#else 335215976Sjmallett#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull)) 336215976Sjmallett#endif 337215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 338215976Sjmallett#define CVMX_PEXP_NPEI_INT_ENB2 CVMX_PEXP_NPEI_INT_ENB2_FUNC() 339215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_INT_ENB2_FUNC(void) 340215976Sjmallett{ 341215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 342215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_INT_ENB2 not supported on this chip\n"); 343215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull); 344215976Sjmallett} 345215976Sjmallett#else 346215976Sjmallett#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)) 347215976Sjmallett#endif 348215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 349215976Sjmallett#define CVMX_PEXP_NPEI_INT_INFO CVMX_PEXP_NPEI_INT_INFO_FUNC() 350215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_INT_INFO_FUNC(void) 351215976Sjmallett{ 352215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 353215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_INT_INFO not supported on this chip\n"); 354215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008590ull); 355215976Sjmallett} 356215976Sjmallett#else 357215976Sjmallett#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull)) 358215976Sjmallett#endif 359215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 360215976Sjmallett#define CVMX_PEXP_NPEI_INT_SUM CVMX_PEXP_NPEI_INT_SUM_FUNC() 361215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_INT_SUM_FUNC(void) 362215976Sjmallett{ 363215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 364215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_INT_SUM not supported on this chip\n"); 365215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008530ull); 366215976Sjmallett} 367215976Sjmallett#else 368215976Sjmallett#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull)) 369215976Sjmallett#endif 370215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371215976Sjmallett#define CVMX_PEXP_NPEI_INT_SUM2 CVMX_PEXP_NPEI_INT_SUM2_FUNC() 372215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_INT_SUM2_FUNC(void) 373215976Sjmallett{ 374215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 375215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_INT_SUM2 not supported on this chip\n"); 376215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull); 377215976Sjmallett} 378215976Sjmallett#else 379215976Sjmallett#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)) 380215976Sjmallett#endif 381215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 382215976Sjmallett#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC() 383215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void) 384215976Sjmallett{ 385215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 386215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA0 not supported on this chip\n"); 387215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008600ull); 388215976Sjmallett} 389215976Sjmallett#else 390215976Sjmallett#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull)) 391215976Sjmallett#endif 392215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 393215976Sjmallett#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC() 394215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void) 395215976Sjmallett{ 396215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 397215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA1 not supported on this chip\n"); 398215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008610ull); 399215976Sjmallett} 400215976Sjmallett#else 401215976Sjmallett#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull)) 402215976Sjmallett#endif 403215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 404215976Sjmallett#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC() 405215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void) 406215976Sjmallett{ 407215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 408215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_CTL not supported on this chip\n"); 409215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000084F0ull); 410215976Sjmallett} 411215976Sjmallett#else 412215976Sjmallett#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull)) 413215976Sjmallett#endif 414215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 415215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset) 416215976Sjmallett{ 417215976Sjmallett if (!( 418215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) || 419215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27)))))) 420215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset); 421215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12; 422215976Sjmallett} 423215976Sjmallett#else 424215976Sjmallett#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12) 425215976Sjmallett#endif 426215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 427215976Sjmallett#define CVMX_PEXP_NPEI_MSI_ENB0 CVMX_PEXP_NPEI_MSI_ENB0_FUNC() 428215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void) 429215976Sjmallett{ 430215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 431215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB0 not supported on this chip\n"); 432215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BC50ull); 433215976Sjmallett} 434215976Sjmallett#else 435215976Sjmallett#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull)) 436215976Sjmallett#endif 437215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 438215976Sjmallett#define CVMX_PEXP_NPEI_MSI_ENB1 CVMX_PEXP_NPEI_MSI_ENB1_FUNC() 439215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void) 440215976Sjmallett{ 441215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 442215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB1 not supported on this chip\n"); 443215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BC60ull); 444215976Sjmallett} 445215976Sjmallett#else 446215976Sjmallett#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull)) 447215976Sjmallett#endif 448215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 449215976Sjmallett#define CVMX_PEXP_NPEI_MSI_ENB2 CVMX_PEXP_NPEI_MSI_ENB2_FUNC() 450215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void) 451215976Sjmallett{ 452215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 453215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB2 not supported on this chip\n"); 454215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BC70ull); 455215976Sjmallett} 456215976Sjmallett#else 457215976Sjmallett#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull)) 458215976Sjmallett#endif 459215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 460215976Sjmallett#define CVMX_PEXP_NPEI_MSI_ENB3 CVMX_PEXP_NPEI_MSI_ENB3_FUNC() 461215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void) 462215976Sjmallett{ 463215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 464215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB3 not supported on this chip\n"); 465215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BC80ull); 466215976Sjmallett} 467215976Sjmallett#else 468215976Sjmallett#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull)) 469215976Sjmallett#endif 470215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 471215976Sjmallett#define CVMX_PEXP_NPEI_MSI_RCV0 CVMX_PEXP_NPEI_MSI_RCV0_FUNC() 472215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void) 473215976Sjmallett{ 474215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 475215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV0 not supported on this chip\n"); 476215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BC10ull); 477215976Sjmallett} 478215976Sjmallett#else 479215976Sjmallett#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull)) 480215976Sjmallett#endif 481215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 482215976Sjmallett#define CVMX_PEXP_NPEI_MSI_RCV1 CVMX_PEXP_NPEI_MSI_RCV1_FUNC() 483215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void) 484215976Sjmallett{ 485215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 486215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV1 not supported on this chip\n"); 487215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BC20ull); 488215976Sjmallett} 489215976Sjmallett#else 490215976Sjmallett#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull)) 491215976Sjmallett#endif 492215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 493215976Sjmallett#define CVMX_PEXP_NPEI_MSI_RCV2 CVMX_PEXP_NPEI_MSI_RCV2_FUNC() 494215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void) 495215976Sjmallett{ 496215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 497215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV2 not supported on this chip\n"); 498215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BC30ull); 499215976Sjmallett} 500215976Sjmallett#else 501215976Sjmallett#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull)) 502215976Sjmallett#endif 503215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 504215976Sjmallett#define CVMX_PEXP_NPEI_MSI_RCV3 CVMX_PEXP_NPEI_MSI_RCV3_FUNC() 505215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void) 506215976Sjmallett{ 507215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 508215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV3 not supported on this chip\n"); 509215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BC40ull); 510215976Sjmallett} 511215976Sjmallett#else 512215976Sjmallett#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull)) 513215976Sjmallett#endif 514215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 515215976Sjmallett#define CVMX_PEXP_NPEI_MSI_RD_MAP CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC() 516215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void) 517215976Sjmallett{ 518215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 519215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_RD_MAP not supported on this chip\n"); 520215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull); 521215976Sjmallett} 522215976Sjmallett#else 523215976Sjmallett#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)) 524215976Sjmallett#endif 525215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 526215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC() 527215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void) 528215976Sjmallett{ 529215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 530215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB0 not supported on this chip\n"); 531215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull); 532215976Sjmallett} 533215976Sjmallett#else 534215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)) 535215976Sjmallett#endif 536215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 537215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC() 538215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void) 539215976Sjmallett{ 540215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 541215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB1 not supported on this chip\n"); 542215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BD00ull); 543215976Sjmallett} 544215976Sjmallett#else 545215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull)) 546215976Sjmallett#endif 547215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 548215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC() 549215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void) 550215976Sjmallett{ 551215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 552215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB2 not supported on this chip\n"); 553215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BD10ull); 554215976Sjmallett} 555215976Sjmallett#else 556215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull)) 557215976Sjmallett#endif 558215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 559215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC() 560215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void) 561215976Sjmallett{ 562215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 563215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB3 not supported on this chip\n"); 564215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BD20ull); 565215976Sjmallett} 566215976Sjmallett#else 567215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull)) 568215976Sjmallett#endif 569215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 570215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC() 571215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void) 572215976Sjmallett{ 573215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 574215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB0 not supported on this chip\n"); 575215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BD30ull); 576215976Sjmallett} 577215976Sjmallett#else 578215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull)) 579215976Sjmallett#endif 580215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 581215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC() 582215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void) 583215976Sjmallett{ 584215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 585215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB1 not supported on this chip\n"); 586215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BD40ull); 587215976Sjmallett} 588215976Sjmallett#else 589215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull)) 590215976Sjmallett#endif 591215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 592215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC() 593215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void) 594215976Sjmallett{ 595215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 596215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB2 not supported on this chip\n"); 597215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BD50ull); 598215976Sjmallett} 599215976Sjmallett#else 600215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull)) 601215976Sjmallett#endif 602215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 603215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC() 604215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void) 605215976Sjmallett{ 606215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 607215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB3 not supported on this chip\n"); 608215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BD60ull); 609215976Sjmallett} 610215976Sjmallett#else 611215976Sjmallett#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull)) 612215976Sjmallett#endif 613215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 614215976Sjmallett#define CVMX_PEXP_NPEI_MSI_WR_MAP CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC() 615215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void) 616215976Sjmallett{ 617215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 618215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_MSI_WR_MAP not supported on this chip\n"); 619215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BC90ull); 620215976Sjmallett} 621215976Sjmallett#else 622215976Sjmallett#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull)) 623215976Sjmallett#endif 624215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 625215976Sjmallett#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC() 626215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void) 627215976Sjmallett{ 628215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 629215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PCIE_CREDIT_CNT not supported on this chip\n"); 630215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BD70ull); 631215976Sjmallett} 632215976Sjmallett#else 633215976Sjmallett#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull)) 634215976Sjmallett#endif 635215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 636215976Sjmallett#define CVMX_PEXP_NPEI_PCIE_MSI_RCV CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC() 637215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void) 638215976Sjmallett{ 639215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 640215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV not supported on this chip\n"); 641215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull); 642215976Sjmallett} 643215976Sjmallett#else 644215976Sjmallett#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)) 645215976Sjmallett#endif 646215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 647215976Sjmallett#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC() 648215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void) 649215976Sjmallett{ 650215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 651215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n"); 652215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008650ull); 653215976Sjmallett} 654215976Sjmallett#else 655215976Sjmallett#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull)) 656215976Sjmallett#endif 657215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 658215976Sjmallett#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC() 659215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void) 660215976Sjmallett{ 661215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 662215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n"); 663215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008660ull); 664215976Sjmallett} 665215976Sjmallett#else 666215976Sjmallett#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull)) 667215976Sjmallett#endif 668215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 669215976Sjmallett#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC() 670215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void) 671215976Sjmallett{ 672215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 673215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n"); 674215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008670ull); 675215976Sjmallett} 676215976Sjmallett#else 677215976Sjmallett#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull)) 678215976Sjmallett#endif 679215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 680215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset) 681215976Sjmallett{ 682215976Sjmallett if (!( 683215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 684215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 685215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset); 686215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16; 687215976Sjmallett} 688215976Sjmallett#else 689215976Sjmallett#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16) 690215976Sjmallett#endif 691215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 692215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset) 693215976Sjmallett{ 694215976Sjmallett if (!( 695215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 696215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 697215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset); 698215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16; 699215976Sjmallett} 700215976Sjmallett#else 701215976Sjmallett#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16) 702215976Sjmallett#endif 703215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 704215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset) 705215976Sjmallett{ 706215976Sjmallett if (!( 707215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 708215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 709215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 710215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16; 711215976Sjmallett} 712215976Sjmallett#else 713215976Sjmallett#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16) 714215976Sjmallett#endif 715215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset) 717215976Sjmallett{ 718215976Sjmallett if (!( 719215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 720215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 721215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 722215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16; 723215976Sjmallett} 724215976Sjmallett#else 725215976Sjmallett#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16) 726215976Sjmallett#endif 727215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 728215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset) 729215976Sjmallett{ 730215976Sjmallett if (!( 731215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 732215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 733215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset); 734215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16; 735215976Sjmallett} 736215976Sjmallett#else 737215976Sjmallett#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16) 738215976Sjmallett#endif 739215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 740215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset) 741215976Sjmallett{ 742215976Sjmallett if (!( 743215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 744215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 745215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset); 746215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16; 747215976Sjmallett} 748215976Sjmallett#else 749215976Sjmallett#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16) 750215976Sjmallett#endif 751215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 752215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset) 753215976Sjmallett{ 754215976Sjmallett if (!( 755215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 756215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 757215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset); 758215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16; 759215976Sjmallett} 760215976Sjmallett#else 761215976Sjmallett#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16) 762215976Sjmallett#endif 763215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 764215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset) 765215976Sjmallett{ 766215976Sjmallett if (!( 767215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 768215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 769215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 770215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16; 771215976Sjmallett} 772215976Sjmallett#else 773215976Sjmallett#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16) 774215976Sjmallett#endif 775215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 776215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset) 777215976Sjmallett{ 778215976Sjmallett if (!( 779215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 780215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 781215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 782215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16; 783215976Sjmallett} 784215976Sjmallett#else 785215976Sjmallett#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16) 786215976Sjmallett#endif 787215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 788215976Sjmallett#define CVMX_PEXP_NPEI_PKT_CNT_INT CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC() 789215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void) 790215976Sjmallett{ 791215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 792215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT not supported on this chip\n"); 793215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009110ull); 794215976Sjmallett} 795215976Sjmallett#else 796215976Sjmallett#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull)) 797215976Sjmallett#endif 798215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 799215976Sjmallett#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC() 800215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void) 801215976Sjmallett{ 802215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 803215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT_ENB not supported on this chip\n"); 804215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009130ull); 805215976Sjmallett} 806215976Sjmallett#else 807215976Sjmallett#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull)) 808215976Sjmallett#endif 809215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 810215976Sjmallett#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC() 811215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void) 812215976Sjmallett{ 813215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 814215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ES not supported on this chip\n"); 815215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000090B0ull); 816215976Sjmallett} 817215976Sjmallett#else 818215976Sjmallett#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull)) 819215976Sjmallett#endif 820215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 821215976Sjmallett#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC() 822215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void) 823215976Sjmallett{ 824215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 825215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_NS not supported on this chip\n"); 826215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000090A0ull); 827215976Sjmallett} 828215976Sjmallett#else 829215976Sjmallett#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull)) 830215976Sjmallett#endif 831215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 832215976Sjmallett#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC() 833215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void) 834215976Sjmallett{ 835215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 836215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n"); 837215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009090ull); 838215976Sjmallett} 839215976Sjmallett#else 840215976Sjmallett#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull)) 841215976Sjmallett#endif 842215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 843215976Sjmallett#define CVMX_PEXP_NPEI_PKT_DPADDR CVMX_PEXP_NPEI_PKT_DPADDR_FUNC() 844215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void) 845215976Sjmallett{ 846215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 847215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_DPADDR not supported on this chip\n"); 848215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009080ull); 849215976Sjmallett} 850215976Sjmallett#else 851215976Sjmallett#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull)) 852215976Sjmallett#endif 853215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 854215976Sjmallett#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC() 855215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void) 856215976Sjmallett{ 857215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 858215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_INPUT_CONTROL not supported on this chip\n"); 859215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009150ull); 860215976Sjmallett} 861215976Sjmallett#else 862215976Sjmallett#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull)) 863215976Sjmallett#endif 864215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 865215976Sjmallett#define CVMX_PEXP_NPEI_PKT_INSTR_ENB CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC() 866215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void) 867215976Sjmallett{ 868215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 869215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_ENB not supported on this chip\n"); 870215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009000ull); 871215976Sjmallett} 872215976Sjmallett#else 873215976Sjmallett#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull)) 874215976Sjmallett#endif 875215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 876215976Sjmallett#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC() 877215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void) 878215976Sjmallett{ 879215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 880215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n"); 881215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009190ull); 882215976Sjmallett} 883215976Sjmallett#else 884215976Sjmallett#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull)) 885215976Sjmallett#endif 886215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 887215976Sjmallett#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC() 888215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void) 889215976Sjmallett{ 890215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 891215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_SIZE not supported on this chip\n"); 892215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009020ull); 893215976Sjmallett} 894215976Sjmallett#else 895215976Sjmallett#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull)) 896215976Sjmallett#endif 897215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 898215976Sjmallett#define CVMX_PEXP_NPEI_PKT_INT_LEVELS CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC() 899215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void) 900215976Sjmallett{ 901215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 902215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_INT_LEVELS not supported on this chip\n"); 903215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009100ull); 904215976Sjmallett} 905215976Sjmallett#else 906215976Sjmallett#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull)) 907215976Sjmallett#endif 908215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 909215976Sjmallett#define CVMX_PEXP_NPEI_PKT_IN_BP CVMX_PEXP_NPEI_PKT_IN_BP_FUNC() 910215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void) 911215976Sjmallett{ 912215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 913215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_BP not supported on this chip\n"); 914215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000086B0ull); 915215976Sjmallett} 916215976Sjmallett#else 917215976Sjmallett#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull)) 918215976Sjmallett#endif 919215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 920215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset) 921215976Sjmallett{ 922215976Sjmallett if (!( 923215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) || 924215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31))))) 925215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset); 926215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16; 927215976Sjmallett} 928215976Sjmallett#else 929215976Sjmallett#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16) 930215976Sjmallett#endif 931215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 932215976Sjmallett#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC() 933215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void) 934215976Sjmallett{ 935215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 936215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n"); 937215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000086A0ull); 938215976Sjmallett} 939215976Sjmallett#else 940215976Sjmallett#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull)) 941215976Sjmallett#endif 942215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 943215976Sjmallett#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC() 944215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void) 945215976Sjmallett{ 946215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 947215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n"); 948215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000091A0ull); 949215976Sjmallett} 950215976Sjmallett#else 951215976Sjmallett#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull)) 952215976Sjmallett#endif 953215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 954215976Sjmallett#define CVMX_PEXP_NPEI_PKT_IPTR CVMX_PEXP_NPEI_PKT_IPTR_FUNC() 955215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void) 956215976Sjmallett{ 957215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 958215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_IPTR not supported on this chip\n"); 959215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009070ull); 960215976Sjmallett} 961215976Sjmallett#else 962215976Sjmallett#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull)) 963215976Sjmallett#endif 964215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 965215976Sjmallett#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC() 966215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void) 967215976Sjmallett{ 968215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 969215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n"); 970215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009160ull); 971215976Sjmallett} 972215976Sjmallett#else 973215976Sjmallett#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull)) 974215976Sjmallett#endif 975215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 976215976Sjmallett#define CVMX_PEXP_NPEI_PKT_OUT_BMODE CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC() 977215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void) 978215976Sjmallett{ 979215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 980215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_BMODE not supported on this chip\n"); 981215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000090D0ull); 982215976Sjmallett} 983215976Sjmallett#else 984215976Sjmallett#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull)) 985215976Sjmallett#endif 986215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 987215976Sjmallett#define CVMX_PEXP_NPEI_PKT_OUT_ENB CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC() 988215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void) 989215976Sjmallett{ 990215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 991215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_ENB not supported on this chip\n"); 992215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009010ull); 993215976Sjmallett} 994215976Sjmallett#else 995215976Sjmallett#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull)) 996215976Sjmallett#endif 997215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 998215976Sjmallett#define CVMX_PEXP_NPEI_PKT_PCIE_PORT CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC() 999215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void) 1000215976Sjmallett{ 1001215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1002215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_PCIE_PORT not supported on this chip\n"); 1003215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000090E0ull); 1004215976Sjmallett} 1005215976Sjmallett#else 1006215976Sjmallett#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull)) 1007215976Sjmallett#endif 1008215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1009215976Sjmallett#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC() 1010215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void) 1011215976Sjmallett{ 1012215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1013215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_PORT_IN_RST not supported on this chip\n"); 1014215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008690ull); 1015215976Sjmallett} 1016215976Sjmallett#else 1017215976Sjmallett#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull)) 1018215976Sjmallett#endif 1019215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1020215976Sjmallett#define CVMX_PEXP_NPEI_PKT_SLIST_ES CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC() 1021215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void) 1022215976Sjmallett{ 1023215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1024215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ES not supported on this chip\n"); 1025215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009050ull); 1026215976Sjmallett} 1027215976Sjmallett#else 1028215976Sjmallett#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull)) 1029215976Sjmallett#endif 1030215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1031215976Sjmallett#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC() 1032215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void) 1033215976Sjmallett{ 1034215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1035215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n"); 1036215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009180ull); 1037215976Sjmallett} 1038215976Sjmallett#else 1039215976Sjmallett#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull)) 1040215976Sjmallett#endif 1041215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1042215976Sjmallett#define CVMX_PEXP_NPEI_PKT_SLIST_NS CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC() 1043215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void) 1044215976Sjmallett{ 1045215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1046215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_NS not supported on this chip\n"); 1047215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009040ull); 1048215976Sjmallett} 1049215976Sjmallett#else 1050215976Sjmallett#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull)) 1051215976Sjmallett#endif 1052215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1053215976Sjmallett#define CVMX_PEXP_NPEI_PKT_SLIST_ROR CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC() 1054215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void) 1055215976Sjmallett{ 1056215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1057215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ROR not supported on this chip\n"); 1058215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009030ull); 1059215976Sjmallett} 1060215976Sjmallett#else 1061215976Sjmallett#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull)) 1062215976Sjmallett#endif 1063215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1064215976Sjmallett#define CVMX_PEXP_NPEI_PKT_TIME_INT CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC() 1065215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void) 1066215976Sjmallett{ 1067215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1068215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT not supported on this chip\n"); 1069215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009120ull); 1070215976Sjmallett} 1071215976Sjmallett#else 1072215976Sjmallett#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull)) 1073215976Sjmallett#endif 1074215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1075215976Sjmallett#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC() 1076215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void) 1077215976Sjmallett{ 1078215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1079215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT_ENB not supported on this chip\n"); 1080215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000009140ull); 1081215976Sjmallett} 1082215976Sjmallett#else 1083215976Sjmallett#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull)) 1084215976Sjmallett#endif 1085215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1086215976Sjmallett#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC() 1087215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void) 1088215976Sjmallett{ 1089215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1090215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_RSL_INT_BLOCKS not supported on this chip\n"); 1091215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008520ull); 1092215976Sjmallett} 1093215976Sjmallett#else 1094215976Sjmallett#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull)) 1095215976Sjmallett#endif 1096215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1097215976Sjmallett#define CVMX_PEXP_NPEI_SCRATCH_1 CVMX_PEXP_NPEI_SCRATCH_1_FUNC() 1098215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void) 1099215976Sjmallett{ 1100215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1101215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_SCRATCH_1 not supported on this chip\n"); 1102215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008270ull); 1103215976Sjmallett} 1104215976Sjmallett#else 1105215976Sjmallett#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull)) 1106215976Sjmallett#endif 1107215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1108215976Sjmallett#define CVMX_PEXP_NPEI_STATE1 CVMX_PEXP_NPEI_STATE1_FUNC() 1109215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_STATE1_FUNC(void) 1110215976Sjmallett{ 1111215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1112215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_STATE1 not supported on this chip\n"); 1113215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008620ull); 1114215976Sjmallett} 1115215976Sjmallett#else 1116215976Sjmallett#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull)) 1117215976Sjmallett#endif 1118215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1119215976Sjmallett#define CVMX_PEXP_NPEI_STATE2 CVMX_PEXP_NPEI_STATE2_FUNC() 1120215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_STATE2_FUNC(void) 1121215976Sjmallett{ 1122215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1123215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_STATE2 not supported on this chip\n"); 1124215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008630ull); 1125215976Sjmallett} 1126215976Sjmallett#else 1127215976Sjmallett#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull)) 1128215976Sjmallett#endif 1129215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1130215976Sjmallett#define CVMX_PEXP_NPEI_STATE3 CVMX_PEXP_NPEI_STATE3_FUNC() 1131215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_STATE3_FUNC(void) 1132215976Sjmallett{ 1133215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1134215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_STATE3 not supported on this chip\n"); 1135215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008640ull); 1136215976Sjmallett} 1137215976Sjmallett#else 1138215976Sjmallett#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull)) 1139215976Sjmallett#endif 1140215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1141215976Sjmallett#define CVMX_PEXP_NPEI_WINDOW_CTL CVMX_PEXP_NPEI_WINDOW_CTL_FUNC() 1142215976Sjmallettstatic inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void) 1143215976Sjmallett{ 1144215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 1145215976Sjmallett cvmx_warn("CVMX_PEXP_NPEI_WINDOW_CTL not supported on this chip\n"); 1146215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000008380ull); 1147215976Sjmallett} 1148215976Sjmallett#else 1149215976Sjmallett#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull)) 1150215976Sjmallett#endif 1151215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1152215976Sjmallett#define CVMX_PEXP_SLI_BIST_STATUS CVMX_PEXP_SLI_BIST_STATUS_FUNC() 1153215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_BIST_STATUS_FUNC(void) 1154215976Sjmallett{ 1155232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1156215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_BIST_STATUS not supported on this chip\n"); 1157215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010580ull); 1158215976Sjmallett} 1159215976Sjmallett#else 1160215976Sjmallett#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull)) 1161215976Sjmallett#endif 1162215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1163215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset) 1164215976Sjmallett{ 1165215976Sjmallett if (!( 1166232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1168232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 1169232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1170232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1171215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset); 1172232812Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16; 1173215976Sjmallett} 1174215976Sjmallett#else 1175232812Sjmallett#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16) 1176215976Sjmallett#endif 1177215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1178215976Sjmallett#define CVMX_PEXP_SLI_CTL_STATUS CVMX_PEXP_SLI_CTL_STATUS_FUNC() 1179215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_CTL_STATUS_FUNC(void) 1180215976Sjmallett{ 1181232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1182215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_CTL_STATUS not supported on this chip\n"); 1183215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010570ull); 1184215976Sjmallett} 1185215976Sjmallett#else 1186215976Sjmallett#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull)) 1187215976Sjmallett#endif 1188215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1189215976Sjmallett#define CVMX_PEXP_SLI_DATA_OUT_CNT CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC() 1190215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC(void) 1191215976Sjmallett{ 1192232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1193215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_DATA_OUT_CNT not supported on this chip\n"); 1194215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000105F0ull); 1195215976Sjmallett} 1196215976Sjmallett#else 1197215976Sjmallett#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull)) 1198215976Sjmallett#endif 1199215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1200215976Sjmallett#define CVMX_PEXP_SLI_DBG_DATA CVMX_PEXP_SLI_DBG_DATA_FUNC() 1201215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_DBG_DATA_FUNC(void) 1202215976Sjmallett{ 1203232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1204215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_DBG_DATA not supported on this chip\n"); 1205215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010310ull); 1206215976Sjmallett} 1207215976Sjmallett#else 1208215976Sjmallett#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull)) 1209215976Sjmallett#endif 1210215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1211215976Sjmallett#define CVMX_PEXP_SLI_DBG_SELECT CVMX_PEXP_SLI_DBG_SELECT_FUNC() 1212215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_DBG_SELECT_FUNC(void) 1213215976Sjmallett{ 1214232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1215215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_DBG_SELECT not supported on this chip\n"); 1216215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010300ull); 1217215976Sjmallett} 1218215976Sjmallett#else 1219215976Sjmallett#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull)) 1220215976Sjmallett#endif 1221215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1222215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset) 1223215976Sjmallett{ 1224215976Sjmallett if (!( 1225232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1226232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1227232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1228232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1229232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1230215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset); 1231215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16; 1232215976Sjmallett} 1233215976Sjmallett#else 1234215976Sjmallett#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16) 1235215976Sjmallett#endif 1236215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1237215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset) 1238215976Sjmallett{ 1239215976Sjmallett if (!( 1240232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1241232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1242232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1243232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1244232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1245215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset); 1246215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16; 1247215976Sjmallett} 1248215976Sjmallett#else 1249215976Sjmallett#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16) 1250215976Sjmallett#endif 1251215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1252215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset) 1253215976Sjmallett{ 1254215976Sjmallett if (!( 1255232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1256232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1257232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1258232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1259232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1260215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset); 1261215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16; 1262215976Sjmallett} 1263215976Sjmallett#else 1264215976Sjmallett#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16) 1265215976Sjmallett#endif 1266215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1267215976Sjmallett#define CVMX_PEXP_SLI_INT_ENB_CIU CVMX_PEXP_SLI_INT_ENB_CIU_FUNC() 1268215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_INT_ENB_CIU_FUNC(void) 1269215976Sjmallett{ 1270232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1271215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_INT_ENB_CIU not supported on this chip\n"); 1272215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013CD0ull); 1273215976Sjmallett} 1274215976Sjmallett#else 1275215976Sjmallett#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull)) 1276215976Sjmallett#endif 1277215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1278215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_INT_ENB_PORTX(unsigned long offset) 1279215976Sjmallett{ 1280215976Sjmallett if (!( 1281232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 1282232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 1283232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 1284232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 1285232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 1286215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset); 1287215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16; 1288215976Sjmallett} 1289215976Sjmallett#else 1290215976Sjmallett#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16) 1291215976Sjmallett#endif 1292215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1293215976Sjmallett#define CVMX_PEXP_SLI_INT_SUM CVMX_PEXP_SLI_INT_SUM_FUNC() 1294215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_INT_SUM_FUNC(void) 1295215976Sjmallett{ 1296232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1297215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_INT_SUM not supported on this chip\n"); 1298215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010330ull); 1299215976Sjmallett} 1300215976Sjmallett#else 1301215976Sjmallett#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull)) 1302215976Sjmallett#endif 1303215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1304215976Sjmallett#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC() 1305215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC(void) 1306215976Sjmallett{ 1307232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1308215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA0 not supported on this chip\n"); 1309215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010600ull); 1310215976Sjmallett} 1311215976Sjmallett#else 1312215976Sjmallett#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull)) 1313215976Sjmallett#endif 1314215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1315215976Sjmallett#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC() 1316215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC(void) 1317215976Sjmallett{ 1318232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1319215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA1 not supported on this chip\n"); 1320215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010610ull); 1321215976Sjmallett} 1322215976Sjmallett#else 1323215976Sjmallett#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull)) 1324215976Sjmallett#endif 1325215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1326232812Sjmallett#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 CVMX_PEXP_SLI_LAST_WIN_RDATA2_FUNC() 1327232812Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA2_FUNC(void) 1328232812Sjmallett{ 1329232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1330232812Sjmallett cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA2 not supported on this chip\n"); 1331232812Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000106C0ull); 1332232812Sjmallett} 1333232812Sjmallett#else 1334232812Sjmallett#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull)) 1335232812Sjmallett#endif 1336232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1337232812Sjmallett#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 CVMX_PEXP_SLI_LAST_WIN_RDATA3_FUNC() 1338232812Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA3_FUNC(void) 1339232812Sjmallett{ 1340232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1341232812Sjmallett cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA3 not supported on this chip\n"); 1342232812Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000106D0ull); 1343232812Sjmallett} 1344232812Sjmallett#else 1345232812Sjmallett#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull)) 1346232812Sjmallett#endif 1347232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1348215976Sjmallett#define CVMX_PEXP_SLI_MAC_CREDIT_CNT CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC() 1349215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC(void) 1350215976Sjmallett{ 1351232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1352215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT not supported on this chip\n"); 1353215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013D70ull); 1354215976Sjmallett} 1355215976Sjmallett#else 1356215976Sjmallett#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull)) 1357215976Sjmallett#endif 1358215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1359232812Sjmallett#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC() 1360232812Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC(void) 1361232812Sjmallett{ 1362232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1363232812Sjmallett cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT2 not supported on this chip\n"); 1364232812Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013E10ull); 1365232812Sjmallett} 1366232812Sjmallett#else 1367232812Sjmallett#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull)) 1368232812Sjmallett#endif 1369232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1370215976Sjmallett#define CVMX_PEXP_SLI_MEM_ACCESS_CTL CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC() 1371215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC(void) 1372215976Sjmallett{ 1373232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1374215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_CTL not supported on this chip\n"); 1375215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000102F0ull); 1376215976Sjmallett} 1377215976Sjmallett#else 1378215976Sjmallett#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull)) 1379215976Sjmallett#endif 1380215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1381215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset) 1382215976Sjmallett{ 1383215976Sjmallett if (!( 1384232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 12) && (offset <= 27)))) || 1385232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))) || 1386232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 12) && (offset <= 27)))) || 1387232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 12) && (offset <= 27)))) || 1388232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 12) && (offset <= 27)))))) 1389215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset); 1390215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12; 1391215976Sjmallett} 1392215976Sjmallett#else 1393215976Sjmallett#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12) 1394215976Sjmallett#endif 1395215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1396215976Sjmallett#define CVMX_PEXP_SLI_MSI_ENB0 CVMX_PEXP_SLI_MSI_ENB0_FUNC() 1397215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_ENB0_FUNC(void) 1398215976Sjmallett{ 1399232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1400215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_ENB0 not supported on this chip\n"); 1401215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013C50ull); 1402215976Sjmallett} 1403215976Sjmallett#else 1404215976Sjmallett#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull)) 1405215976Sjmallett#endif 1406215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1407215976Sjmallett#define CVMX_PEXP_SLI_MSI_ENB1 CVMX_PEXP_SLI_MSI_ENB1_FUNC() 1408215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_ENB1_FUNC(void) 1409215976Sjmallett{ 1410232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1411215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_ENB1 not supported on this chip\n"); 1412215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013C60ull); 1413215976Sjmallett} 1414215976Sjmallett#else 1415215976Sjmallett#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull)) 1416215976Sjmallett#endif 1417215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1418215976Sjmallett#define CVMX_PEXP_SLI_MSI_ENB2 CVMX_PEXP_SLI_MSI_ENB2_FUNC() 1419215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_ENB2_FUNC(void) 1420215976Sjmallett{ 1421232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1422215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_ENB2 not supported on this chip\n"); 1423215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013C70ull); 1424215976Sjmallett} 1425215976Sjmallett#else 1426215976Sjmallett#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull)) 1427215976Sjmallett#endif 1428215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1429215976Sjmallett#define CVMX_PEXP_SLI_MSI_ENB3 CVMX_PEXP_SLI_MSI_ENB3_FUNC() 1430215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_ENB3_FUNC(void) 1431215976Sjmallett{ 1432232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1433215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_ENB3 not supported on this chip\n"); 1434215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013C80ull); 1435215976Sjmallett} 1436215976Sjmallett#else 1437215976Sjmallett#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull)) 1438215976Sjmallett#endif 1439215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1440215976Sjmallett#define CVMX_PEXP_SLI_MSI_RCV0 CVMX_PEXP_SLI_MSI_RCV0_FUNC() 1441215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_RCV0_FUNC(void) 1442215976Sjmallett{ 1443232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1444215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_RCV0 not supported on this chip\n"); 1445215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013C10ull); 1446215976Sjmallett} 1447215976Sjmallett#else 1448215976Sjmallett#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull)) 1449215976Sjmallett#endif 1450215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1451215976Sjmallett#define CVMX_PEXP_SLI_MSI_RCV1 CVMX_PEXP_SLI_MSI_RCV1_FUNC() 1452215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_RCV1_FUNC(void) 1453215976Sjmallett{ 1454232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1455215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_RCV1 not supported on this chip\n"); 1456215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013C20ull); 1457215976Sjmallett} 1458215976Sjmallett#else 1459215976Sjmallett#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull)) 1460215976Sjmallett#endif 1461215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1462215976Sjmallett#define CVMX_PEXP_SLI_MSI_RCV2 CVMX_PEXP_SLI_MSI_RCV2_FUNC() 1463215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_RCV2_FUNC(void) 1464215976Sjmallett{ 1465232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1466215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_RCV2 not supported on this chip\n"); 1467215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013C30ull); 1468215976Sjmallett} 1469215976Sjmallett#else 1470215976Sjmallett#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull)) 1471215976Sjmallett#endif 1472215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1473215976Sjmallett#define CVMX_PEXP_SLI_MSI_RCV3 CVMX_PEXP_SLI_MSI_RCV3_FUNC() 1474215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_RCV3_FUNC(void) 1475215976Sjmallett{ 1476232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1477215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_RCV3 not supported on this chip\n"); 1478215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013C40ull); 1479215976Sjmallett} 1480215976Sjmallett#else 1481215976Sjmallett#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull)) 1482215976Sjmallett#endif 1483215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1484215976Sjmallett#define CVMX_PEXP_SLI_MSI_RD_MAP CVMX_PEXP_SLI_MSI_RD_MAP_FUNC() 1485215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_RD_MAP_FUNC(void) 1486215976Sjmallett{ 1487232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1488215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_RD_MAP not supported on this chip\n"); 1489215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013CA0ull); 1490215976Sjmallett} 1491215976Sjmallett#else 1492215976Sjmallett#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull)) 1493215976Sjmallett#endif 1494215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1495215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1C_ENB0 CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC() 1496215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC(void) 1497215976Sjmallett{ 1498232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1499215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB0 not supported on this chip\n"); 1500215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013CF0ull); 1501215976Sjmallett} 1502215976Sjmallett#else 1503215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull)) 1504215976Sjmallett#endif 1505215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1506215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1C_ENB1 CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC() 1507215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC(void) 1508215976Sjmallett{ 1509232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1510215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB1 not supported on this chip\n"); 1511215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013D00ull); 1512215976Sjmallett} 1513215976Sjmallett#else 1514215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull)) 1515215976Sjmallett#endif 1516215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1517215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1C_ENB2 CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC() 1518215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC(void) 1519215976Sjmallett{ 1520232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1521215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB2 not supported on this chip\n"); 1522215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013D10ull); 1523215976Sjmallett} 1524215976Sjmallett#else 1525215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull)) 1526215976Sjmallett#endif 1527215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1528215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1C_ENB3 CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC() 1529215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC(void) 1530215976Sjmallett{ 1531232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1532215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB3 not supported on this chip\n"); 1533215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013D20ull); 1534215976Sjmallett} 1535215976Sjmallett#else 1536215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull)) 1537215976Sjmallett#endif 1538215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1539215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1S_ENB0 CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC() 1540215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC(void) 1541215976Sjmallett{ 1542232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1543215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB0 not supported on this chip\n"); 1544215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013D30ull); 1545215976Sjmallett} 1546215976Sjmallett#else 1547215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull)) 1548215976Sjmallett#endif 1549215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1550215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1S_ENB1 CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC() 1551215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC(void) 1552215976Sjmallett{ 1553232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1554215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB1 not supported on this chip\n"); 1555215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013D40ull); 1556215976Sjmallett} 1557215976Sjmallett#else 1558215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull)) 1559215976Sjmallett#endif 1560215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1561215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1S_ENB2 CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC() 1562215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC(void) 1563215976Sjmallett{ 1564232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1565215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB2 not supported on this chip\n"); 1566215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013D50ull); 1567215976Sjmallett} 1568215976Sjmallett#else 1569215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull)) 1570215976Sjmallett#endif 1571215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1572215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1S_ENB3 CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC() 1573215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC(void) 1574215976Sjmallett{ 1575232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1576215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB3 not supported on this chip\n"); 1577215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013D60ull); 1578215976Sjmallett} 1579215976Sjmallett#else 1580215976Sjmallett#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull)) 1581215976Sjmallett#endif 1582215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1583215976Sjmallett#define CVMX_PEXP_SLI_MSI_WR_MAP CVMX_PEXP_SLI_MSI_WR_MAP_FUNC() 1584215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_MSI_WR_MAP_FUNC(void) 1585215976Sjmallett{ 1586232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1587215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_MSI_WR_MAP not supported on this chip\n"); 1588215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013C90ull); 1589215976Sjmallett} 1590215976Sjmallett#else 1591215976Sjmallett#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull)) 1592215976Sjmallett#endif 1593215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1594215976Sjmallett#define CVMX_PEXP_SLI_PCIE_MSI_RCV CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC() 1595215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC(void) 1596215976Sjmallett{ 1597232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1598215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV not supported on this chip\n"); 1599215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013CB0ull); 1600215976Sjmallett} 1601215976Sjmallett#else 1602215976Sjmallett#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull)) 1603215976Sjmallett#endif 1604215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1605215976Sjmallett#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC() 1606215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC(void) 1607215976Sjmallett{ 1608232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1609215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n"); 1610215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010650ull); 1611215976Sjmallett} 1612215976Sjmallett#else 1613215976Sjmallett#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull)) 1614215976Sjmallett#endif 1615215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1616215976Sjmallett#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC() 1617215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC(void) 1618215976Sjmallett{ 1619232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1620215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n"); 1621215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010660ull); 1622215976Sjmallett} 1623215976Sjmallett#else 1624215976Sjmallett#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull)) 1625215976Sjmallett#endif 1626215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1627215976Sjmallett#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC() 1628215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC(void) 1629215976Sjmallett{ 1630232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1631215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n"); 1632215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010670ull); 1633215976Sjmallett} 1634215976Sjmallett#else 1635215976Sjmallett#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull)) 1636215976Sjmallett#endif 1637215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1638215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset) 1639215976Sjmallett{ 1640215976Sjmallett if (!( 1641232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1642232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1643232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1644232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 1645232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1646215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset); 1647215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16; 1648215976Sjmallett} 1649215976Sjmallett#else 1650215976Sjmallett#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16) 1651215976Sjmallett#endif 1652215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1653215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset) 1654215976Sjmallett{ 1655215976Sjmallett if (!( 1656232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1657232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1658232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1659232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 1660232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1661215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset); 1662215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16; 1663215976Sjmallett} 1664215976Sjmallett#else 1665215976Sjmallett#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16) 1666215976Sjmallett#endif 1667215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1668215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset) 1669215976Sjmallett{ 1670215976Sjmallett if (!( 1671232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1672232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1673232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1674232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 1675232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1676215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 1677215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16; 1678215976Sjmallett} 1679215976Sjmallett#else 1680215976Sjmallett#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16) 1681215976Sjmallett#endif 1682215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1683215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset) 1684215976Sjmallett{ 1685215976Sjmallett if (!( 1686232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1687232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1688232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1689232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 1690232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1691215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 1692215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16; 1693215976Sjmallett} 1694215976Sjmallett#else 1695215976Sjmallett#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16) 1696215976Sjmallett#endif 1697215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1698215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_HEADER(unsigned long offset) 1699215976Sjmallett{ 1700215976Sjmallett if (!( 1701232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1702232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1703232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1704232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 1705232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1706215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset); 1707215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16; 1708215976Sjmallett} 1709215976Sjmallett#else 1710215976Sjmallett#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16) 1711215976Sjmallett#endif 1712215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1713215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKTX_IN_BP(unsigned long offset) 1714215976Sjmallett{ 1715215976Sjmallett if (!( 1716232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1717232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1718232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1719232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1720215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset); 1721215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16; 1722215976Sjmallett} 1723215976Sjmallett#else 1724215976Sjmallett#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16) 1725215976Sjmallett#endif 1726215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1727215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset) 1728215976Sjmallett{ 1729215976Sjmallett if (!( 1730232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1731232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1732232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1733232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 1734232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1735215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset); 1736215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16; 1737215976Sjmallett} 1738215976Sjmallett#else 1739215976Sjmallett#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16) 1740215976Sjmallett#endif 1741215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1742215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset) 1743215976Sjmallett{ 1744215976Sjmallett if (!( 1745232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1746232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1747232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1748232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 1749232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1750215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset); 1751215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16; 1752215976Sjmallett} 1753215976Sjmallett#else 1754215976Sjmallett#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16) 1755215976Sjmallett#endif 1756215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1757215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset) 1758215976Sjmallett{ 1759215976Sjmallett if (!( 1760232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1761232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1762232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1763232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 1764232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1765215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset); 1766215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16; 1767215976Sjmallett} 1768215976Sjmallett#else 1769215976Sjmallett#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16) 1770215976Sjmallett#endif 1771215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1772215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset) 1773215976Sjmallett{ 1774215976Sjmallett if (!( 1775232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1776232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1777232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1778232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 1779232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1780215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset); 1781215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16; 1782215976Sjmallett} 1783215976Sjmallett#else 1784215976Sjmallett#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16) 1785215976Sjmallett#endif 1786215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1787215976Sjmallett#define CVMX_PEXP_SLI_PKT_CNT_INT CVMX_PEXP_SLI_PKT_CNT_INT_FUNC() 1788215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_FUNC(void) 1789215976Sjmallett{ 1790232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1791215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT not supported on this chip\n"); 1792215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011130ull); 1793215976Sjmallett} 1794215976Sjmallett#else 1795215976Sjmallett#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull)) 1796215976Sjmallett#endif 1797215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1798215976Sjmallett#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC() 1799215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC(void) 1800215976Sjmallett{ 1801232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1802215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT_ENB not supported on this chip\n"); 1803215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011150ull); 1804215976Sjmallett} 1805215976Sjmallett#else 1806215976Sjmallett#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull)) 1807215976Sjmallett#endif 1808215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1809215976Sjmallett#define CVMX_PEXP_SLI_PKT_CTL CVMX_PEXP_SLI_PKT_CTL_FUNC() 1810215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_CTL_FUNC(void) 1811215976Sjmallett{ 1812232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1813215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_CTL not supported on this chip\n"); 1814215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011220ull); 1815215976Sjmallett} 1816215976Sjmallett#else 1817215976Sjmallett#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull)) 1818215976Sjmallett#endif 1819215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1820215976Sjmallett#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC() 1821215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC(void) 1822215976Sjmallett{ 1823232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1824215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ES not supported on this chip\n"); 1825215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000110B0ull); 1826215976Sjmallett} 1827215976Sjmallett#else 1828215976Sjmallett#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull)) 1829215976Sjmallett#endif 1830215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1831215976Sjmallett#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC() 1832215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC(void) 1833215976Sjmallett{ 1834232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1835215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_NS not supported on this chip\n"); 1836215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000110A0ull); 1837215976Sjmallett} 1838215976Sjmallett#else 1839215976Sjmallett#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull)) 1840215976Sjmallett#endif 1841215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1842215976Sjmallett#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC() 1843215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC(void) 1844215976Sjmallett{ 1845232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1846215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ROR not supported on this chip\n"); 1847215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011090ull); 1848215976Sjmallett} 1849215976Sjmallett#else 1850215976Sjmallett#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull)) 1851215976Sjmallett#endif 1852215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1853215976Sjmallett#define CVMX_PEXP_SLI_PKT_DPADDR CVMX_PEXP_SLI_PKT_DPADDR_FUNC() 1854215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_DPADDR_FUNC(void) 1855215976Sjmallett{ 1856232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1857215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_DPADDR not supported on this chip\n"); 1858215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011080ull); 1859215976Sjmallett} 1860215976Sjmallett#else 1861215976Sjmallett#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull)) 1862215976Sjmallett#endif 1863215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1864215976Sjmallett#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC() 1865215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC(void) 1866215976Sjmallett{ 1867232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1868215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_INPUT_CONTROL not supported on this chip\n"); 1869215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011170ull); 1870215976Sjmallett} 1871215976Sjmallett#else 1872215976Sjmallett#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull)) 1873215976Sjmallett#endif 1874215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1875215976Sjmallett#define CVMX_PEXP_SLI_PKT_INSTR_ENB CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC() 1876215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC(void) 1877215976Sjmallett{ 1878232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1879215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_ENB not supported on this chip\n"); 1880215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011000ull); 1881215976Sjmallett} 1882215976Sjmallett#else 1883215976Sjmallett#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull)) 1884215976Sjmallett#endif 1885215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1886215976Sjmallett#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC() 1887215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC(void) 1888215976Sjmallett{ 1889232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1890215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n"); 1891215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000111A0ull); 1892215976Sjmallett} 1893215976Sjmallett#else 1894215976Sjmallett#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull)) 1895215976Sjmallett#endif 1896215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1897215976Sjmallett#define CVMX_PEXP_SLI_PKT_INSTR_SIZE CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC() 1898215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC(void) 1899215976Sjmallett{ 1900232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1901215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_SIZE not supported on this chip\n"); 1902215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011020ull); 1903215976Sjmallett} 1904215976Sjmallett#else 1905215976Sjmallett#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull)) 1906215976Sjmallett#endif 1907215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1908215976Sjmallett#define CVMX_PEXP_SLI_PKT_INT_LEVELS CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC() 1909215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC(void) 1910215976Sjmallett{ 1911232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1912215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_INT_LEVELS not supported on this chip\n"); 1913215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011120ull); 1914215976Sjmallett} 1915215976Sjmallett#else 1916215976Sjmallett#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull)) 1917215976Sjmallett#endif 1918215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1919215976Sjmallett#define CVMX_PEXP_SLI_PKT_IN_BP CVMX_PEXP_SLI_PKT_IN_BP_FUNC() 1920215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_IN_BP_FUNC(void) 1921215976Sjmallett{ 1922232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1923215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_IN_BP not supported on this chip\n"); 1924215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011210ull); 1925215976Sjmallett} 1926215976Sjmallett#else 1927215976Sjmallett#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull)) 1928215976Sjmallett#endif 1929215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1930215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset) 1931215976Sjmallett{ 1932215976Sjmallett if (!( 1933232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) || 1934232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) || 1935232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) || 1936232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) || 1937232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31))))) 1938215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset); 1939215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16; 1940215976Sjmallett} 1941215976Sjmallett#else 1942215976Sjmallett#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16) 1943215976Sjmallett#endif 1944215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1945215976Sjmallett#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC() 1946215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC(void) 1947215976Sjmallett{ 1948232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1949215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n"); 1950215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011200ull); 1951215976Sjmallett} 1952215976Sjmallett#else 1953215976Sjmallett#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull)) 1954215976Sjmallett#endif 1955215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1956215976Sjmallett#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC() 1957215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC(void) 1958215976Sjmallett{ 1959232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1960215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_IN_PCIE_PORT not supported on this chip\n"); 1961215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000111B0ull); 1962215976Sjmallett} 1963215976Sjmallett#else 1964215976Sjmallett#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull)) 1965215976Sjmallett#endif 1966215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1967215976Sjmallett#define CVMX_PEXP_SLI_PKT_IPTR CVMX_PEXP_SLI_PKT_IPTR_FUNC() 1968215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_IPTR_FUNC(void) 1969215976Sjmallett{ 1970232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1971215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_IPTR not supported on this chip\n"); 1972215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011070ull); 1973215976Sjmallett} 1974215976Sjmallett#else 1975215976Sjmallett#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull)) 1976215976Sjmallett#endif 1977215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1978215976Sjmallett#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC() 1979215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC(void) 1980215976Sjmallett{ 1981232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1982215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_OUTPUT_WMARK not supported on this chip\n"); 1983215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011180ull); 1984215976Sjmallett} 1985215976Sjmallett#else 1986215976Sjmallett#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull)) 1987215976Sjmallett#endif 1988215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1989215976Sjmallett#define CVMX_PEXP_SLI_PKT_OUT_BMODE CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC() 1990215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC(void) 1991215976Sjmallett{ 1992232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 1993215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BMODE not supported on this chip\n"); 1994215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000110D0ull); 1995215976Sjmallett} 1996215976Sjmallett#else 1997215976Sjmallett#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull)) 1998215976Sjmallett#endif 1999215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2000232812Sjmallett#define CVMX_PEXP_SLI_PKT_OUT_BP_EN CVMX_PEXP_SLI_PKT_OUT_BP_EN_FUNC() 2001232812Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BP_EN_FUNC(void) 2002232812Sjmallett{ 2003232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 2004232812Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BP_EN not supported on this chip\n"); 2005232812Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011240ull); 2006232812Sjmallett} 2007232812Sjmallett#else 2008232812Sjmallett#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull)) 2009232812Sjmallett#endif 2010232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2011215976Sjmallett#define CVMX_PEXP_SLI_PKT_OUT_ENB CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC() 2012215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC(void) 2013215976Sjmallett{ 2014232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2015215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_ENB not supported on this chip\n"); 2016215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011010ull); 2017215976Sjmallett} 2018215976Sjmallett#else 2019215976Sjmallett#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull)) 2020215976Sjmallett#endif 2021215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2022215976Sjmallett#define CVMX_PEXP_SLI_PKT_PCIE_PORT CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC() 2023215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC(void) 2024215976Sjmallett{ 2025232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2026215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_PCIE_PORT not supported on this chip\n"); 2027215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000110E0ull); 2028215976Sjmallett} 2029215976Sjmallett#else 2030215976Sjmallett#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull)) 2031215976Sjmallett#endif 2032215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2033215976Sjmallett#define CVMX_PEXP_SLI_PKT_PORT_IN_RST CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC() 2034215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC(void) 2035215976Sjmallett{ 2036232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2037215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_PORT_IN_RST not supported on this chip\n"); 2038215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000111F0ull); 2039215976Sjmallett} 2040215976Sjmallett#else 2041215976Sjmallett#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull)) 2042215976Sjmallett#endif 2043215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2044215976Sjmallett#define CVMX_PEXP_SLI_PKT_SLIST_ES CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC() 2045215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC(void) 2046215976Sjmallett{ 2047232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2048215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ES not supported on this chip\n"); 2049215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011050ull); 2050215976Sjmallett} 2051215976Sjmallett#else 2052215976Sjmallett#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull)) 2053215976Sjmallett#endif 2054215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2055215976Sjmallett#define CVMX_PEXP_SLI_PKT_SLIST_NS CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC() 2056215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC(void) 2057215976Sjmallett{ 2058232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2059215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_NS not supported on this chip\n"); 2060215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011040ull); 2061215976Sjmallett} 2062215976Sjmallett#else 2063215976Sjmallett#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull)) 2064215976Sjmallett#endif 2065215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2066215976Sjmallett#define CVMX_PEXP_SLI_PKT_SLIST_ROR CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC() 2067215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC(void) 2068215976Sjmallett{ 2069232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2070215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ROR not supported on this chip\n"); 2071215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011030ull); 2072215976Sjmallett} 2073215976Sjmallett#else 2074215976Sjmallett#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull)) 2075215976Sjmallett#endif 2076215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2077215976Sjmallett#define CVMX_PEXP_SLI_PKT_TIME_INT CVMX_PEXP_SLI_PKT_TIME_INT_FUNC() 2078215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_FUNC(void) 2079215976Sjmallett{ 2080232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2081215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT not supported on this chip\n"); 2082215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011140ull); 2083215976Sjmallett} 2084215976Sjmallett#else 2085215976Sjmallett#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull)) 2086215976Sjmallett#endif 2087215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2088215976Sjmallett#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC() 2089215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC(void) 2090215976Sjmallett{ 2091232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2092215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT_ENB not supported on this chip\n"); 2093215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011160ull); 2094215976Sjmallett} 2095215976Sjmallett#else 2096215976Sjmallett#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull)) 2097215976Sjmallett#endif 2098215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2099232812Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_PORTX_PKIND(unsigned long offset) 2100232812Sjmallett{ 2101232812Sjmallett if (!( 2102232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))))) 2103232812Sjmallett cvmx_warn("CVMX_PEXP_SLI_PORTX_PKIND(%lu) is invalid on this chip\n", offset); 2104232812Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16; 2105232812Sjmallett} 2106232812Sjmallett#else 2107232812Sjmallett#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16) 2108232812Sjmallett#endif 2109232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2110215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset) 2111215976Sjmallett{ 2112215976Sjmallett if (!( 2113232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 2114232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 2115232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 2116232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 2117232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 2118215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset); 2119232812Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16; 2120215976Sjmallett} 2121215976Sjmallett#else 2122232812Sjmallett#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16) 2123215976Sjmallett#endif 2124215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2125215976Sjmallett#define CVMX_PEXP_SLI_SCRATCH_1 CVMX_PEXP_SLI_SCRATCH_1_FUNC() 2126215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_SCRATCH_1_FUNC(void) 2127215976Sjmallett{ 2128232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2129215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_SCRATCH_1 not supported on this chip\n"); 2130215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000103C0ull); 2131215976Sjmallett} 2132215976Sjmallett#else 2133215976Sjmallett#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull)) 2134215976Sjmallett#endif 2135215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2136215976Sjmallett#define CVMX_PEXP_SLI_SCRATCH_2 CVMX_PEXP_SLI_SCRATCH_2_FUNC() 2137215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_SCRATCH_2_FUNC(void) 2138215976Sjmallett{ 2139232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2140215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_SCRATCH_2 not supported on this chip\n"); 2141215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000103D0ull); 2142215976Sjmallett} 2143215976Sjmallett#else 2144215976Sjmallett#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull)) 2145215976Sjmallett#endif 2146215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2147215976Sjmallett#define CVMX_PEXP_SLI_STATE1 CVMX_PEXP_SLI_STATE1_FUNC() 2148215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_STATE1_FUNC(void) 2149215976Sjmallett{ 2150232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2151215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_STATE1 not supported on this chip\n"); 2152215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010620ull); 2153215976Sjmallett} 2154215976Sjmallett#else 2155215976Sjmallett#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull)) 2156215976Sjmallett#endif 2157215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2158215976Sjmallett#define CVMX_PEXP_SLI_STATE2 CVMX_PEXP_SLI_STATE2_FUNC() 2159215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_STATE2_FUNC(void) 2160215976Sjmallett{ 2161232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2162215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_STATE2 not supported on this chip\n"); 2163215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010630ull); 2164215976Sjmallett} 2165215976Sjmallett#else 2166215976Sjmallett#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull)) 2167215976Sjmallett#endif 2168215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2169215976Sjmallett#define CVMX_PEXP_SLI_STATE3 CVMX_PEXP_SLI_STATE3_FUNC() 2170215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_STATE3_FUNC(void) 2171215976Sjmallett{ 2172232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2173215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_STATE3 not supported on this chip\n"); 2174215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000010640ull); 2175215976Sjmallett} 2176215976Sjmallett#else 2177215976Sjmallett#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull)) 2178215976Sjmallett#endif 2179215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2180232812Sjmallett#define CVMX_PEXP_SLI_TX_PIPE CVMX_PEXP_SLI_TX_PIPE_FUNC() 2181232812Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_TX_PIPE_FUNC(void) 2182232812Sjmallett{ 2183232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 2184232812Sjmallett cvmx_warn("CVMX_PEXP_SLI_TX_PIPE not supported on this chip\n"); 2185232812Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000011230ull); 2186232812Sjmallett} 2187232812Sjmallett#else 2188232812Sjmallett#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull)) 2189232812Sjmallett#endif 2190232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2191215976Sjmallett#define CVMX_PEXP_SLI_WINDOW_CTL CVMX_PEXP_SLI_WINDOW_CTL_FUNC() 2192215976Sjmallettstatic inline uint64_t CVMX_PEXP_SLI_WINDOW_CTL_FUNC(void) 2193215976Sjmallett{ 2194232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 2195215976Sjmallett cvmx_warn("CVMX_PEXP_SLI_WINDOW_CTL not supported on this chip\n"); 2196215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000102E0ull); 2197215976Sjmallett} 2198215976Sjmallett#else 2199215976Sjmallett#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull)) 2200215976Sjmallett#endif 2201215976Sjmallett 2202215976Sjmallett#endif 2203