1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pemx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pemx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_PEMX_DEFS_H__ 53232812Sjmallett#define __CVMX_PEMX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 15)) && ((block_id <= 1)))) || 60232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) || 61232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id <= 1)))) || 62232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 15)) && ((block_id <= 1)))) || 63232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 15)) && ((block_id <= 1)))))) 64215976Sjmallett cvmx_warn("CVMX_PEMX_BAR1_INDEXX(%lu,%lu) is invalid on this chip\n", offset, block_id); 65215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8; 66215976Sjmallett} 67215976Sjmallett#else 68215976Sjmallett#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8) 69215976Sjmallett#endif 70215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71232812Sjmallettstatic inline uint64_t CVMX_PEMX_BAR2_MASK(unsigned long block_id) 72232812Sjmallett{ 73232812Sjmallett if (!( 74232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 75232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 76232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 77232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 78232812Sjmallett cvmx_warn("CVMX_PEMX_BAR2_MASK(%lu) is invalid on this chip\n", block_id); 79232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull; 80232812Sjmallett} 81232812Sjmallett#else 82232812Sjmallett#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull) 83232812Sjmallett#endif 84232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 85215976Sjmallettstatic inline uint64_t CVMX_PEMX_BAR_CTL(unsigned long block_id) 86215976Sjmallett{ 87215976Sjmallett if (!( 88232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 89232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 90232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 91232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 92232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 93215976Sjmallett cvmx_warn("CVMX_PEMX_BAR_CTL(%lu) is invalid on this chip\n", block_id); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull; 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallettstatic inline uint64_t CVMX_PEMX_BIST_STATUS(unsigned long block_id) 101215976Sjmallett{ 102215976Sjmallett if (!( 103232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 104232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 105232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 106232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 107232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 108215976Sjmallett cvmx_warn("CVMX_PEMX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 109215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull; 110215976Sjmallett} 111215976Sjmallett#else 112215976Sjmallett#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull) 113215976Sjmallett#endif 114215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 115215976Sjmallettstatic inline uint64_t CVMX_PEMX_BIST_STATUS2(unsigned long block_id) 116215976Sjmallett{ 117215976Sjmallett if (!( 118232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 119232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 120232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 121232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 122232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 123215976Sjmallett cvmx_warn("CVMX_PEMX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id); 124215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull; 125215976Sjmallett} 126215976Sjmallett#else 127215976Sjmallett#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull) 128215976Sjmallett#endif 129215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 130215976Sjmallettstatic inline uint64_t CVMX_PEMX_CFG_RD(unsigned long block_id) 131215976Sjmallett{ 132215976Sjmallett if (!( 133232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 134232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 135232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 136232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 137232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 138215976Sjmallett cvmx_warn("CVMX_PEMX_CFG_RD(%lu) is invalid on this chip\n", block_id); 139215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull; 140215976Sjmallett} 141215976Sjmallett#else 142215976Sjmallett#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull) 143215976Sjmallett#endif 144215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 145215976Sjmallettstatic inline uint64_t CVMX_PEMX_CFG_WR(unsigned long block_id) 146215976Sjmallett{ 147215976Sjmallett if (!( 148232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 149232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 150232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 151232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 152232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 153215976Sjmallett cvmx_warn("CVMX_PEMX_CFG_WR(%lu) is invalid on this chip\n", block_id); 154215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull; 155215976Sjmallett} 156215976Sjmallett#else 157215976Sjmallett#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull) 158215976Sjmallett#endif 159215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160215976Sjmallettstatic inline uint64_t CVMX_PEMX_CPL_LUT_VALID(unsigned long block_id) 161215976Sjmallett{ 162215976Sjmallett if (!( 163232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 164232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 165232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 166232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 168215976Sjmallett cvmx_warn("CVMX_PEMX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id); 169215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull; 170215976Sjmallett} 171215976Sjmallett#else 172215976Sjmallett#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull) 173215976Sjmallett#endif 174215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175215976Sjmallettstatic inline uint64_t CVMX_PEMX_CTL_STATUS(unsigned long block_id) 176215976Sjmallett{ 177215976Sjmallett if (!( 178232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 179232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 180232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 181232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 182232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 183215976Sjmallett cvmx_warn("CVMX_PEMX_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 184215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull; 185215976Sjmallett} 186215976Sjmallett#else 187215976Sjmallett#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull) 188215976Sjmallett#endif 189215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 190215976Sjmallettstatic inline uint64_t CVMX_PEMX_DBG_INFO(unsigned long block_id) 191215976Sjmallett{ 192215976Sjmallett if (!( 193232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 194232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 195232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 196232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 197232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 198215976Sjmallett cvmx_warn("CVMX_PEMX_DBG_INFO(%lu) is invalid on this chip\n", block_id); 199215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull; 200215976Sjmallett} 201215976Sjmallett#else 202215976Sjmallett#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull) 203215976Sjmallett#endif 204215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 205215976Sjmallettstatic inline uint64_t CVMX_PEMX_DBG_INFO_EN(unsigned long block_id) 206215976Sjmallett{ 207215976Sjmallett if (!( 208232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 209232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 210232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 211232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 212232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 213215976Sjmallett cvmx_warn("CVMX_PEMX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id); 214215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull; 215215976Sjmallett} 216215976Sjmallett#else 217215976Sjmallett#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull) 218215976Sjmallett#endif 219215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 220215976Sjmallettstatic inline uint64_t CVMX_PEMX_DIAG_STATUS(unsigned long block_id) 221215976Sjmallett{ 222215976Sjmallett if (!( 223232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 224232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 225232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 226232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 227232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 228215976Sjmallett cvmx_warn("CVMX_PEMX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id); 229215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull; 230215976Sjmallett} 231215976Sjmallett#else 232215976Sjmallett#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull) 233215976Sjmallett#endif 234215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 235232812Sjmallettstatic inline uint64_t CVMX_PEMX_INB_READ_CREDITS(unsigned long block_id) 236232812Sjmallett{ 237232812Sjmallett if (!( 238232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 239232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 240232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 241232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 242232812Sjmallett cvmx_warn("CVMX_PEMX_INB_READ_CREDITS(%lu) is invalid on this chip\n", block_id); 243232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull; 244232812Sjmallett} 245232812Sjmallett#else 246232812Sjmallett#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull) 247232812Sjmallett#endif 248232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 249215976Sjmallettstatic inline uint64_t CVMX_PEMX_INT_ENB(unsigned long block_id) 250215976Sjmallett{ 251215976Sjmallett if (!( 252232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 253232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 254232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 255232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 256232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 257215976Sjmallett cvmx_warn("CVMX_PEMX_INT_ENB(%lu) is invalid on this chip\n", block_id); 258215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull; 259215976Sjmallett} 260215976Sjmallett#else 261215976Sjmallett#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull) 262215976Sjmallett#endif 263215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 264215976Sjmallettstatic inline uint64_t CVMX_PEMX_INT_ENB_INT(unsigned long block_id) 265215976Sjmallett{ 266215976Sjmallett if (!( 267232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 268232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 269232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 270232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 271232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 272215976Sjmallett cvmx_warn("CVMX_PEMX_INT_ENB_INT(%lu) is invalid on this chip\n", block_id); 273215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull; 274215976Sjmallett} 275215976Sjmallett#else 276215976Sjmallett#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull) 277215976Sjmallett#endif 278215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 279215976Sjmallettstatic inline uint64_t CVMX_PEMX_INT_SUM(unsigned long block_id) 280215976Sjmallett{ 281215976Sjmallett if (!( 282232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 283232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 284232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 285232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 286232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 287215976Sjmallett cvmx_warn("CVMX_PEMX_INT_SUM(%lu) is invalid on this chip\n", block_id); 288215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull; 289215976Sjmallett} 290215976Sjmallett#else 291215976Sjmallett#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull) 292215976Sjmallett#endif 293215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 294215976Sjmallettstatic inline uint64_t CVMX_PEMX_P2N_BAR0_START(unsigned long block_id) 295215976Sjmallett{ 296215976Sjmallett if (!( 297232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 298232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 299232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 300232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 301232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 302215976Sjmallett cvmx_warn("CVMX_PEMX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id); 303215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull; 304215976Sjmallett} 305215976Sjmallett#else 306215976Sjmallett#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull) 307215976Sjmallett#endif 308215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309215976Sjmallettstatic inline uint64_t CVMX_PEMX_P2N_BAR1_START(unsigned long block_id) 310215976Sjmallett{ 311215976Sjmallett if (!( 312232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 313232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 314232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 315232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 316232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 317215976Sjmallett cvmx_warn("CVMX_PEMX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id); 318215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull; 319215976Sjmallett} 320215976Sjmallett#else 321215976Sjmallett#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull) 322215976Sjmallett#endif 323215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 324215976Sjmallettstatic inline uint64_t CVMX_PEMX_P2N_BAR2_START(unsigned long block_id) 325215976Sjmallett{ 326215976Sjmallett if (!( 327232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 328232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 329232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 330232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 331232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 332215976Sjmallett cvmx_warn("CVMX_PEMX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id); 333215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull; 334215976Sjmallett} 335215976Sjmallett#else 336215976Sjmallett#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull) 337215976Sjmallett#endif 338215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 339215976Sjmallettstatic inline uint64_t CVMX_PEMX_P2P_BARX_END(unsigned long offset, unsigned long block_id) 340215976Sjmallett{ 341215976Sjmallett if (!( 342232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) || 343232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id <= 1)))) || 344232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 1)))))) 345215976Sjmallett cvmx_warn("CVMX_PEMX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id); 346215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16; 347215976Sjmallett} 348215976Sjmallett#else 349215976Sjmallett#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16) 350215976Sjmallett#endif 351215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 352215976Sjmallettstatic inline uint64_t CVMX_PEMX_P2P_BARX_START(unsigned long offset, unsigned long block_id) 353215976Sjmallett{ 354215976Sjmallett if (!( 355232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) || 356232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id <= 1)))) || 357232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 1)))))) 358215976Sjmallett cvmx_warn("CVMX_PEMX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id); 359215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16; 360215976Sjmallett} 361215976Sjmallett#else 362215976Sjmallett#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16) 363215976Sjmallett#endif 364215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 365215976Sjmallettstatic inline uint64_t CVMX_PEMX_TLP_CREDITS(unsigned long block_id) 366215976Sjmallett{ 367215976Sjmallett if (!( 368232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 369232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 370232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 371232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 372232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 373215976Sjmallett cvmx_warn("CVMX_PEMX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id); 374215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull; 375215976Sjmallett} 376215976Sjmallett#else 377215976Sjmallett#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull) 378215976Sjmallett#endif 379215976Sjmallett 380215976Sjmallett/** 381215976Sjmallett * cvmx_pem#_bar1_index# 382215976Sjmallett * 383215976Sjmallett * PEM_BAR1_INDEXX = PEM BAR1 IndexX Register 384215976Sjmallett * 385215976Sjmallett * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22]. 386215976Sjmallett */ 387232812Sjmallettunion cvmx_pemx_bar1_indexx { 388215976Sjmallett uint64_t u64; 389232812Sjmallett struct cvmx_pemx_bar1_indexx_s { 390232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 391215976Sjmallett uint64_t reserved_20_63 : 44; 392215976Sjmallett uint64_t addr_idx : 16; /**< Address bits [37:22] sent to L2C */ 393215976Sjmallett uint64_t ca : 1; /**< Set '1' when access is not to be cached in L2. */ 394215976Sjmallett uint64_t end_swp : 2; /**< Endian Swap Mode */ 395215976Sjmallett uint64_t addr_v : 1; /**< Set '1' when the selected address range is valid. */ 396215976Sjmallett#else 397215976Sjmallett uint64_t addr_v : 1; 398215976Sjmallett uint64_t end_swp : 2; 399215976Sjmallett uint64_t ca : 1; 400215976Sjmallett uint64_t addr_idx : 16; 401215976Sjmallett uint64_t reserved_20_63 : 44; 402215976Sjmallett#endif 403215976Sjmallett } s; 404232812Sjmallett struct cvmx_pemx_bar1_indexx_s cn61xx; 405215976Sjmallett struct cvmx_pemx_bar1_indexx_s cn63xx; 406215976Sjmallett struct cvmx_pemx_bar1_indexx_s cn63xxp1; 407232812Sjmallett struct cvmx_pemx_bar1_indexx_s cn66xx; 408232812Sjmallett struct cvmx_pemx_bar1_indexx_s cn68xx; 409232812Sjmallett struct cvmx_pemx_bar1_indexx_s cn68xxp1; 410232812Sjmallett struct cvmx_pemx_bar1_indexx_s cnf71xx; 411215976Sjmallett}; 412215976Sjmalletttypedef union cvmx_pemx_bar1_indexx cvmx_pemx_bar1_indexx_t; 413215976Sjmallett 414215976Sjmallett/** 415232812Sjmallett * cvmx_pem#_bar2_mask 416232812Sjmallett * 417232812Sjmallett * PEM_BAR2_MASK = PEM BAR2 MASK 418232812Sjmallett * 419232812Sjmallett * The mask pattern that is ANDED with the address from PCIe core for BAR2 hits. 420232812Sjmallett */ 421232812Sjmallettunion cvmx_pemx_bar2_mask { 422232812Sjmallett uint64_t u64; 423232812Sjmallett struct cvmx_pemx_bar2_mask_s { 424232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 425232812Sjmallett uint64_t reserved_38_63 : 26; 426232812Sjmallett uint64_t mask : 35; /**< The value to be ANDED with the address sent to 427232812Sjmallett the Octeon memory. */ 428232812Sjmallett uint64_t reserved_0_2 : 3; 429232812Sjmallett#else 430232812Sjmallett uint64_t reserved_0_2 : 3; 431232812Sjmallett uint64_t mask : 35; 432232812Sjmallett uint64_t reserved_38_63 : 26; 433232812Sjmallett#endif 434232812Sjmallett } s; 435232812Sjmallett struct cvmx_pemx_bar2_mask_s cn61xx; 436232812Sjmallett struct cvmx_pemx_bar2_mask_s cn66xx; 437232812Sjmallett struct cvmx_pemx_bar2_mask_s cn68xx; 438232812Sjmallett struct cvmx_pemx_bar2_mask_s cn68xxp1; 439232812Sjmallett struct cvmx_pemx_bar2_mask_s cnf71xx; 440232812Sjmallett}; 441232812Sjmalletttypedef union cvmx_pemx_bar2_mask cvmx_pemx_bar2_mask_t; 442232812Sjmallett 443232812Sjmallett/** 444215976Sjmallett * cvmx_pem#_bar_ctl 445215976Sjmallett * 446232812Sjmallett * PEM_BAR_CTL = PEM BAR Control 447215976Sjmallett * 448215976Sjmallett * Contains control for BAR accesses. 449215976Sjmallett */ 450232812Sjmallettunion cvmx_pemx_bar_ctl { 451215976Sjmallett uint64_t u64; 452232812Sjmallett struct cvmx_pemx_bar_ctl_s { 453232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 454215976Sjmallett uint64_t reserved_7_63 : 57; 455215976Sjmallett uint64_t bar1_siz : 3; /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB, 456215976Sjmallett 3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB, 457215976Sjmallett 0 and 7 are reserved. */ 458215976Sjmallett uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 459215976Sjmallett clear '0' BAR2 access will cause UR responses. */ 460215976Sjmallett uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[39:38] to 461215976Sjmallett determine the endian swap mode. */ 462215976Sjmallett uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[40] to 463215976Sjmallett determine the L2 cache attribute. 464215976Sjmallett Not cached in L2 if XOR result is 1 */ 465215976Sjmallett#else 466215976Sjmallett uint64_t bar2_cax : 1; 467215976Sjmallett uint64_t bar2_esx : 2; 468215976Sjmallett uint64_t bar2_enb : 1; 469215976Sjmallett uint64_t bar1_siz : 3; 470215976Sjmallett uint64_t reserved_7_63 : 57; 471215976Sjmallett#endif 472215976Sjmallett } s; 473232812Sjmallett struct cvmx_pemx_bar_ctl_s cn61xx; 474215976Sjmallett struct cvmx_pemx_bar_ctl_s cn63xx; 475215976Sjmallett struct cvmx_pemx_bar_ctl_s cn63xxp1; 476232812Sjmallett struct cvmx_pemx_bar_ctl_s cn66xx; 477232812Sjmallett struct cvmx_pemx_bar_ctl_s cn68xx; 478232812Sjmallett struct cvmx_pemx_bar_ctl_s cn68xxp1; 479232812Sjmallett struct cvmx_pemx_bar_ctl_s cnf71xx; 480215976Sjmallett}; 481215976Sjmalletttypedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t; 482215976Sjmallett 483215976Sjmallett/** 484215976Sjmallett * cvmx_pem#_bist_status 485215976Sjmallett * 486215976Sjmallett * PEM_BIST_STATUS = PEM Bist Status 487215976Sjmallett * 488215976Sjmallett * Contains the diffrent interrupt summary bits of the PEM. 489215976Sjmallett */ 490232812Sjmallettunion cvmx_pemx_bist_status { 491215976Sjmallett uint64_t u64; 492232812Sjmallett struct cvmx_pemx_bist_status_s { 493232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 494215976Sjmallett uint64_t reserved_8_63 : 56; 495215976Sjmallett uint64_t retry : 1; /**< Retry Buffer. */ 496215976Sjmallett uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */ 497215976Sjmallett uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */ 498215976Sjmallett uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */ 499215976Sjmallett uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */ 500215976Sjmallett uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */ 501215976Sjmallett uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */ 502215976Sjmallett uint64_t sot : 1; /**< SOT Buffer. */ 503215976Sjmallett#else 504215976Sjmallett uint64_t sot : 1; 505215976Sjmallett uint64_t rqhdr0 : 1; 506215976Sjmallett uint64_t rqhdr1 : 1; 507215976Sjmallett uint64_t rqdata3 : 1; 508215976Sjmallett uint64_t rqdata2 : 1; 509215976Sjmallett uint64_t rqdata1 : 1; 510215976Sjmallett uint64_t rqdata0 : 1; 511215976Sjmallett uint64_t retry : 1; 512215976Sjmallett uint64_t reserved_8_63 : 56; 513215976Sjmallett#endif 514215976Sjmallett } s; 515232812Sjmallett struct cvmx_pemx_bist_status_s cn61xx; 516215976Sjmallett struct cvmx_pemx_bist_status_s cn63xx; 517215976Sjmallett struct cvmx_pemx_bist_status_s cn63xxp1; 518232812Sjmallett struct cvmx_pemx_bist_status_s cn66xx; 519232812Sjmallett struct cvmx_pemx_bist_status_s cn68xx; 520232812Sjmallett struct cvmx_pemx_bist_status_s cn68xxp1; 521232812Sjmallett struct cvmx_pemx_bist_status_s cnf71xx; 522215976Sjmallett}; 523215976Sjmalletttypedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t; 524215976Sjmallett 525215976Sjmallett/** 526215976Sjmallett * cvmx_pem#_bist_status2 527215976Sjmallett * 528215976Sjmallett * PEM(0..1)_BIST_STATUS2 = PEM BIST Status Register 529215976Sjmallett * 530215976Sjmallett * Results from BIST runs of PEM's memories. 531215976Sjmallett */ 532232812Sjmallettunion cvmx_pemx_bist_status2 { 533215976Sjmallett uint64_t u64; 534232812Sjmallett struct cvmx_pemx_bist_status2_s { 535232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 536215976Sjmallett uint64_t reserved_10_63 : 54; 537215976Sjmallett uint64_t e2p_cpl : 1; /**< BIST Status for the e2p_cpl_fifo */ 538215976Sjmallett uint64_t e2p_n : 1; /**< BIST Status for the e2p_n_fifo */ 539215976Sjmallett uint64_t e2p_p : 1; /**< BIST Status for the e2p_p_fifo */ 540215976Sjmallett uint64_t peai_p2e : 1; /**< BIST Status for the peai__pesc_fifo */ 541215976Sjmallett uint64_t pef_tpf1 : 1; /**< BIST Status for the pef_tlp_p_fifo1 */ 542215976Sjmallett uint64_t pef_tpf0 : 1; /**< BIST Status for the pef_tlp_p_fifo0 */ 543215976Sjmallett uint64_t pef_tnf : 1; /**< BIST Status for the pef_tlp_n_fifo */ 544215976Sjmallett uint64_t pef_tcf1 : 1; /**< BIST Status for the pef_tlp_cpl_fifo1 */ 545215976Sjmallett uint64_t pef_tc0 : 1; /**< BIST Status for the pef_tlp_cpl_fifo0 */ 546215976Sjmallett uint64_t ppf : 1; /**< BIST Status for the ppf_fifo */ 547215976Sjmallett#else 548215976Sjmallett uint64_t ppf : 1; 549215976Sjmallett uint64_t pef_tc0 : 1; 550215976Sjmallett uint64_t pef_tcf1 : 1; 551215976Sjmallett uint64_t pef_tnf : 1; 552215976Sjmallett uint64_t pef_tpf0 : 1; 553215976Sjmallett uint64_t pef_tpf1 : 1; 554215976Sjmallett uint64_t peai_p2e : 1; 555215976Sjmallett uint64_t e2p_p : 1; 556215976Sjmallett uint64_t e2p_n : 1; 557215976Sjmallett uint64_t e2p_cpl : 1; 558215976Sjmallett uint64_t reserved_10_63 : 54; 559215976Sjmallett#endif 560215976Sjmallett } s; 561232812Sjmallett struct cvmx_pemx_bist_status2_s cn61xx; 562215976Sjmallett struct cvmx_pemx_bist_status2_s cn63xx; 563215976Sjmallett struct cvmx_pemx_bist_status2_s cn63xxp1; 564232812Sjmallett struct cvmx_pemx_bist_status2_s cn66xx; 565232812Sjmallett struct cvmx_pemx_bist_status2_s cn68xx; 566232812Sjmallett struct cvmx_pemx_bist_status2_s cn68xxp1; 567232812Sjmallett struct cvmx_pemx_bist_status2_s cnf71xx; 568215976Sjmallett}; 569215976Sjmalletttypedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t; 570215976Sjmallett 571215976Sjmallett/** 572215976Sjmallett * cvmx_pem#_cfg_rd 573215976Sjmallett * 574215976Sjmallett * PEM_CFG_RD = PEM Configuration Read 575215976Sjmallett * 576215976Sjmallett * Allows read access to the configuration in the PCIe Core. 577215976Sjmallett */ 578232812Sjmallettunion cvmx_pemx_cfg_rd { 579215976Sjmallett uint64_t u64; 580232812Sjmallett struct cvmx_pemx_cfg_rd_s { 581232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 582215976Sjmallett uint64_t data : 32; /**< Data. */ 583215976Sjmallett uint64_t addr : 32; /**< Address to read. A write to this register 584215976Sjmallett starts a read operation. */ 585215976Sjmallett#else 586215976Sjmallett uint64_t addr : 32; 587215976Sjmallett uint64_t data : 32; 588215976Sjmallett#endif 589215976Sjmallett } s; 590232812Sjmallett struct cvmx_pemx_cfg_rd_s cn61xx; 591215976Sjmallett struct cvmx_pemx_cfg_rd_s cn63xx; 592215976Sjmallett struct cvmx_pemx_cfg_rd_s cn63xxp1; 593232812Sjmallett struct cvmx_pemx_cfg_rd_s cn66xx; 594232812Sjmallett struct cvmx_pemx_cfg_rd_s cn68xx; 595232812Sjmallett struct cvmx_pemx_cfg_rd_s cn68xxp1; 596232812Sjmallett struct cvmx_pemx_cfg_rd_s cnf71xx; 597215976Sjmallett}; 598215976Sjmalletttypedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t; 599215976Sjmallett 600215976Sjmallett/** 601215976Sjmallett * cvmx_pem#_cfg_wr 602215976Sjmallett * 603215976Sjmallett * PEM_CFG_WR = PEM Configuration Write 604215976Sjmallett * 605215976Sjmallett * Allows write access to the configuration in the PCIe Core. 606215976Sjmallett */ 607232812Sjmallettunion cvmx_pemx_cfg_wr { 608215976Sjmallett uint64_t u64; 609232812Sjmallett struct cvmx_pemx_cfg_wr_s { 610232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 611215976Sjmallett uint64_t data : 32; /**< Data to write. A write to this register starts 612215976Sjmallett a write operation. */ 613215976Sjmallett uint64_t addr : 32; /**< Address to write. A write to this register starts 614215976Sjmallett a write operation. */ 615215976Sjmallett#else 616215976Sjmallett uint64_t addr : 32; 617215976Sjmallett uint64_t data : 32; 618215976Sjmallett#endif 619215976Sjmallett } s; 620232812Sjmallett struct cvmx_pemx_cfg_wr_s cn61xx; 621215976Sjmallett struct cvmx_pemx_cfg_wr_s cn63xx; 622215976Sjmallett struct cvmx_pemx_cfg_wr_s cn63xxp1; 623232812Sjmallett struct cvmx_pemx_cfg_wr_s cn66xx; 624232812Sjmallett struct cvmx_pemx_cfg_wr_s cn68xx; 625232812Sjmallett struct cvmx_pemx_cfg_wr_s cn68xxp1; 626232812Sjmallett struct cvmx_pemx_cfg_wr_s cnf71xx; 627215976Sjmallett}; 628215976Sjmalletttypedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t; 629215976Sjmallett 630215976Sjmallett/** 631215976Sjmallett * cvmx_pem#_cpl_lut_valid 632215976Sjmallett * 633215976Sjmallett * PEM_CPL_LUT_VALID = PEM Cmpletion Lookup Table Valid 634215976Sjmallett * 635215976Sjmallett * Bit set for outstanding tag read. 636215976Sjmallett */ 637232812Sjmallettunion cvmx_pemx_cpl_lut_valid { 638215976Sjmallett uint64_t u64; 639232812Sjmallett struct cvmx_pemx_cpl_lut_valid_s { 640232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 641215976Sjmallett uint64_t reserved_32_63 : 32; 642215976Sjmallett uint64_t tag : 32; /**< Bit vector set cooresponds to an outstanding tag 643215976Sjmallett expecting a completion. */ 644215976Sjmallett#else 645215976Sjmallett uint64_t tag : 32; 646215976Sjmallett uint64_t reserved_32_63 : 32; 647215976Sjmallett#endif 648215976Sjmallett } s; 649232812Sjmallett struct cvmx_pemx_cpl_lut_valid_s cn61xx; 650215976Sjmallett struct cvmx_pemx_cpl_lut_valid_s cn63xx; 651215976Sjmallett struct cvmx_pemx_cpl_lut_valid_s cn63xxp1; 652232812Sjmallett struct cvmx_pemx_cpl_lut_valid_s cn66xx; 653232812Sjmallett struct cvmx_pemx_cpl_lut_valid_s cn68xx; 654232812Sjmallett struct cvmx_pemx_cpl_lut_valid_s cn68xxp1; 655232812Sjmallett struct cvmx_pemx_cpl_lut_valid_s cnf71xx; 656215976Sjmallett}; 657215976Sjmalletttypedef union cvmx_pemx_cpl_lut_valid cvmx_pemx_cpl_lut_valid_t; 658215976Sjmallett 659215976Sjmallett/** 660215976Sjmallett * cvmx_pem#_ctl_status 661215976Sjmallett * 662232812Sjmallett * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1 663232812Sjmallett * For normal operation(sgmii or 1000Base-X), this bit must be 0. 664232812Sjmallett * See pcsx.csr for xaui logic analyzer mode. 665232812Sjmallett * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt 666215976Sjmallett * 667232812Sjmallett * 668232812Sjmallett * PEM_CTL_STATUS = PEM Control Status 669232812Sjmallett * 670232812Sjmallett * General control and status of the PEM. 671215976Sjmallett */ 672232812Sjmallettunion cvmx_pemx_ctl_status { 673215976Sjmallett uint64_t u64; 674232812Sjmallett struct cvmx_pemx_ctl_status_s { 675232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 676215976Sjmallett uint64_t reserved_48_63 : 16; 677215976Sjmallett uint64_t auto_sd : 1; /**< Link Hardware Autonomous Speed Disable. */ 678215976Sjmallett uint64_t dnum : 5; /**< Primary bus device number. */ 679215976Sjmallett uint64_t pbus : 8; /**< Primary bus number. */ 680215976Sjmallett uint64_t reserved_32_33 : 2; 681215976Sjmallett uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a 682215976Sjmallett CPL to a CFG RD that does not carry a Retry Status. 683215976Sjmallett Until such time that the timeout occurs and Retry 684215976Sjmallett Status is received for a CFG RD, the Read CFG Read 685215976Sjmallett will be resent. A value of 0 disables retries and 686215976Sjmallett treats a CPL Retry as a CPL UR. 687215976Sjmallett When enabled only one CFG RD may be issued until 688215976Sjmallett either successful completion or CPL UR. */ 689215976Sjmallett uint64_t reserved_12_15 : 4; 690215976Sjmallett uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is 691215976Sjmallett to the PCIe core pm_xmt_turnoff port. RC mode. */ 692215976Sjmallett uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is 693215976Sjmallett to the PCIe core pm_xmt_pme port. EP mode. */ 694215976Sjmallett uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is 695215976Sjmallett to the PCIe core outband_pwrup_cmd port. EP mode. */ 696215976Sjmallett uint64_t reserved_7_8 : 2; 697215976Sjmallett uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */ 698215976Sjmallett uint64_t dly_one : 1; /**< When set the output client state machines will 699215976Sjmallett wait one cycle before starting a new TLP out. */ 700215976Sjmallett uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the 701215976Sjmallett link is disabled. This bit only is active when in 702215976Sjmallett RC mode. */ 703215976Sjmallett uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will 704215976Sjmallett not wait for P-TLPs that normaly would be sent 705215976Sjmallett first. */ 706215976Sjmallett uint64_t fast_lm : 1; /**< When '1' forces fast link mode. */ 707215976Sjmallett uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */ 708215976Sjmallett uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */ 709215976Sjmallett#else 710215976Sjmallett uint64_t inv_lcrc : 1; 711215976Sjmallett uint64_t inv_ecrc : 1; 712215976Sjmallett uint64_t fast_lm : 1; 713215976Sjmallett uint64_t ro_ctlp : 1; 714215976Sjmallett uint64_t lnk_enb : 1; 715215976Sjmallett uint64_t dly_one : 1; 716215976Sjmallett uint64_t nf_ecrc : 1; 717215976Sjmallett uint64_t reserved_7_8 : 2; 718215976Sjmallett uint64_t ob_p_cmd : 1; 719215976Sjmallett uint64_t pm_xpme : 1; 720215976Sjmallett uint64_t pm_xtoff : 1; 721215976Sjmallett uint64_t reserved_12_15 : 4; 722215976Sjmallett uint64_t cfg_rtry : 16; 723215976Sjmallett uint64_t reserved_32_33 : 2; 724215976Sjmallett uint64_t pbus : 8; 725215976Sjmallett uint64_t dnum : 5; 726215976Sjmallett uint64_t auto_sd : 1; 727215976Sjmallett uint64_t reserved_48_63 : 16; 728215976Sjmallett#endif 729215976Sjmallett } s; 730232812Sjmallett struct cvmx_pemx_ctl_status_s cn61xx; 731215976Sjmallett struct cvmx_pemx_ctl_status_s cn63xx; 732215976Sjmallett struct cvmx_pemx_ctl_status_s cn63xxp1; 733232812Sjmallett struct cvmx_pemx_ctl_status_s cn66xx; 734232812Sjmallett struct cvmx_pemx_ctl_status_s cn68xx; 735232812Sjmallett struct cvmx_pemx_ctl_status_s cn68xxp1; 736232812Sjmallett struct cvmx_pemx_ctl_status_s cnf71xx; 737215976Sjmallett}; 738215976Sjmalletttypedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t; 739215976Sjmallett 740215976Sjmallett/** 741215976Sjmallett * cvmx_pem#_dbg_info 742215976Sjmallett * 743215976Sjmallett * PEM(0..1)_DBG_INFO = PEM Debug Information 744215976Sjmallett * 745215976Sjmallett * General debug info. 746215976Sjmallett */ 747232812Sjmallettunion cvmx_pemx_dbg_info { 748215976Sjmallett uint64_t u64; 749232812Sjmallett struct cvmx_pemx_dbg_info_s { 750232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 751215976Sjmallett uint64_t reserved_31_63 : 33; 752215976Sjmallett uint64_t ecrc_e : 1; /**< Received a ECRC error. 753215976Sjmallett radm_ecrc_err */ 754215976Sjmallett uint64_t rawwpp : 1; /**< Received a write with poisoned payload 755215976Sjmallett radm_rcvd_wreq_poisoned */ 756215976Sjmallett uint64_t racpp : 1; /**< Received a completion with poisoned payload 757215976Sjmallett radm_rcvd_cpl_poisoned */ 758215976Sjmallett uint64_t ramtlp : 1; /**< Received a malformed TLP 759215976Sjmallett radm_mlf_tlp_err */ 760215976Sjmallett uint64_t rarwdns : 1; /**< Recieved a request which device does not support 761215976Sjmallett radm_rcvd_ur_req */ 762215976Sjmallett uint64_t caar : 1; /**< Completer aborted a request 763215976Sjmallett radm_rcvd_ca_req 764215976Sjmallett This bit will never be set because Octeon does 765215976Sjmallett not generate Completer Aborts. */ 766215976Sjmallett uint64_t racca : 1; /**< Received a completion with CA status 767215976Sjmallett radm_rcvd_cpl_ca */ 768215976Sjmallett uint64_t racur : 1; /**< Received a completion with UR status 769215976Sjmallett radm_rcvd_cpl_ur */ 770215976Sjmallett uint64_t rauc : 1; /**< Received an unexpected completion 771215976Sjmallett radm_unexp_cpl_err */ 772215976Sjmallett uint64_t rqo : 1; /**< Receive queue overflow. Normally happens only when 773215976Sjmallett flow control advertisements are ignored 774215976Sjmallett radm_qoverflow */ 775215976Sjmallett uint64_t fcuv : 1; /**< Flow Control Update Violation (opt. checks) 776215976Sjmallett int_xadm_fc_prot_err */ 777215976Sjmallett uint64_t rpe : 1; /**< When the PHY reports 8B/10B decode error 778215976Sjmallett (RxStatus = 3b100) or disparity error 779215976Sjmallett (RxStatus = 3b111), the signal rmlh_rcvd_err will 780215976Sjmallett be asserted. 781215976Sjmallett rmlh_rcvd_err */ 782215976Sjmallett uint64_t fcpvwt : 1; /**< Flow Control Protocol Violation (Watchdog Timer) 783215976Sjmallett rtlh_fc_prot_err */ 784215976Sjmallett uint64_t dpeoosd : 1; /**< DLLP protocol error (out of sequence DLLP) 785215976Sjmallett rdlh_prot_err */ 786215976Sjmallett uint64_t rtwdle : 1; /**< Received TLP with DataLink Layer Error 787215976Sjmallett rdlh_bad_tlp_err */ 788215976Sjmallett uint64_t rdwdle : 1; /**< Received DLLP with DataLink Layer Error 789215976Sjmallett rdlh_bad_dllp_err */ 790215976Sjmallett uint64_t mre : 1; /**< Max Retries Exceeded 791215976Sjmallett xdlh_replay_num_rlover_err */ 792215976Sjmallett uint64_t rte : 1; /**< Replay Timer Expired 793215976Sjmallett xdlh_replay_timeout_err 794215976Sjmallett This bit is set when the REPLAY_TIMER expires in 795215976Sjmallett the PCIE core. The probability of this bit being 796215976Sjmallett set will increase with the traffic load. */ 797215976Sjmallett uint64_t acto : 1; /**< A Completion Timeout Occured 798215976Sjmallett pedc_radm_cpl_timeout */ 799215976Sjmallett uint64_t rvdm : 1; /**< Received Vendor-Defined Message 800215976Sjmallett pedc_radm_vendor_msg */ 801215976Sjmallett uint64_t rumep : 1; /**< Received Unlock Message (EP Mode Only) 802215976Sjmallett pedc_radm_msg_unlock */ 803215976Sjmallett uint64_t rptamrc : 1; /**< Received PME Turnoff Acknowledge Message 804215976Sjmallett (RC Mode only) 805215976Sjmallett pedc_radm_pm_to_ack */ 806215976Sjmallett uint64_t rpmerc : 1; /**< Received PME Message (RC Mode only) 807215976Sjmallett pedc_radm_pm_pme */ 808215976Sjmallett uint64_t rfemrc : 1; /**< Received Fatal Error Message (RC Mode only) 809215976Sjmallett pedc_radm_fatal_err 810215976Sjmallett Bit set when a message with ERR_FATAL is set. */ 811215976Sjmallett uint64_t rnfemrc : 1; /**< Received Non-Fatal Error Message (RC Mode only) 812215976Sjmallett pedc_radm_nonfatal_err */ 813215976Sjmallett uint64_t rcemrc : 1; /**< Received Correctable Error Message (RC Mode only) 814215976Sjmallett pedc_radm_correctable_err */ 815215976Sjmallett uint64_t rpoison : 1; /**< Received Poisoned TLP 816215976Sjmallett pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */ 817215976Sjmallett uint64_t recrce : 1; /**< Received ECRC Error 818215976Sjmallett pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */ 819215976Sjmallett uint64_t rtlplle : 1; /**< Received TLP has link layer error 820215976Sjmallett pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */ 821215976Sjmallett uint64_t rtlpmal : 1; /**< Received TLP is malformed or a message. 822215976Sjmallett pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot 823215976Sjmallett If the core receives a MSG (or Vendor Message) 824215976Sjmallett this bit will be set. */ 825215976Sjmallett uint64_t spoison : 1; /**< Poisoned TLP sent 826215976Sjmallett peai__client0_tlp_ep & peai__client0_tlp_hv */ 827215976Sjmallett#else 828215976Sjmallett uint64_t spoison : 1; 829215976Sjmallett uint64_t rtlpmal : 1; 830215976Sjmallett uint64_t rtlplle : 1; 831215976Sjmallett uint64_t recrce : 1; 832215976Sjmallett uint64_t rpoison : 1; 833215976Sjmallett uint64_t rcemrc : 1; 834215976Sjmallett uint64_t rnfemrc : 1; 835215976Sjmallett uint64_t rfemrc : 1; 836215976Sjmallett uint64_t rpmerc : 1; 837215976Sjmallett uint64_t rptamrc : 1; 838215976Sjmallett uint64_t rumep : 1; 839215976Sjmallett uint64_t rvdm : 1; 840215976Sjmallett uint64_t acto : 1; 841215976Sjmallett uint64_t rte : 1; 842215976Sjmallett uint64_t mre : 1; 843215976Sjmallett uint64_t rdwdle : 1; 844215976Sjmallett uint64_t rtwdle : 1; 845215976Sjmallett uint64_t dpeoosd : 1; 846215976Sjmallett uint64_t fcpvwt : 1; 847215976Sjmallett uint64_t rpe : 1; 848215976Sjmallett uint64_t fcuv : 1; 849215976Sjmallett uint64_t rqo : 1; 850215976Sjmallett uint64_t rauc : 1; 851215976Sjmallett uint64_t racur : 1; 852215976Sjmallett uint64_t racca : 1; 853215976Sjmallett uint64_t caar : 1; 854215976Sjmallett uint64_t rarwdns : 1; 855215976Sjmallett uint64_t ramtlp : 1; 856215976Sjmallett uint64_t racpp : 1; 857215976Sjmallett uint64_t rawwpp : 1; 858215976Sjmallett uint64_t ecrc_e : 1; 859215976Sjmallett uint64_t reserved_31_63 : 33; 860215976Sjmallett#endif 861215976Sjmallett } s; 862232812Sjmallett struct cvmx_pemx_dbg_info_s cn61xx; 863215976Sjmallett struct cvmx_pemx_dbg_info_s cn63xx; 864215976Sjmallett struct cvmx_pemx_dbg_info_s cn63xxp1; 865232812Sjmallett struct cvmx_pemx_dbg_info_s cn66xx; 866232812Sjmallett struct cvmx_pemx_dbg_info_s cn68xx; 867232812Sjmallett struct cvmx_pemx_dbg_info_s cn68xxp1; 868232812Sjmallett struct cvmx_pemx_dbg_info_s cnf71xx; 869215976Sjmallett}; 870215976Sjmalletttypedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t; 871215976Sjmallett 872215976Sjmallett/** 873215976Sjmallett * cvmx_pem#_dbg_info_en 874215976Sjmallett * 875215976Sjmallett * PEM(0..1)_DBG_INFO_EN = PEM Debug Information Enable 876215976Sjmallett * 877215976Sjmallett * Allows PEM_DBG_INFO to generate interrupts when cooresponding enable bit is set. 878215976Sjmallett */ 879232812Sjmallettunion cvmx_pemx_dbg_info_en { 880215976Sjmallett uint64_t u64; 881232812Sjmallett struct cvmx_pemx_dbg_info_en_s { 882232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 883215976Sjmallett uint64_t reserved_31_63 : 33; 884215976Sjmallett uint64_t ecrc_e : 1; /**< Allows PEM_DBG_INFO[30] to generate an interrupt. */ 885215976Sjmallett uint64_t rawwpp : 1; /**< Allows PEM_DBG_INFO[29] to generate an interrupt. */ 886215976Sjmallett uint64_t racpp : 1; /**< Allows PEM_DBG_INFO[28] to generate an interrupt. */ 887215976Sjmallett uint64_t ramtlp : 1; /**< Allows PEM_DBG_INFO[27] to generate an interrupt. */ 888215976Sjmallett uint64_t rarwdns : 1; /**< Allows PEM_DBG_INFO[26] to generate an interrupt. */ 889215976Sjmallett uint64_t caar : 1; /**< Allows PEM_DBG_INFO[25] to generate an interrupt. */ 890215976Sjmallett uint64_t racca : 1; /**< Allows PEM_DBG_INFO[24] to generate an interrupt. */ 891215976Sjmallett uint64_t racur : 1; /**< Allows PEM_DBG_INFO[23] to generate an interrupt. */ 892215976Sjmallett uint64_t rauc : 1; /**< Allows PEM_DBG_INFO[22] to generate an interrupt. */ 893215976Sjmallett uint64_t rqo : 1; /**< Allows PEM_DBG_INFO[21] to generate an interrupt. */ 894215976Sjmallett uint64_t fcuv : 1; /**< Allows PEM_DBG_INFO[20] to generate an interrupt. */ 895215976Sjmallett uint64_t rpe : 1; /**< Allows PEM_DBG_INFO[19] to generate an interrupt. */ 896215976Sjmallett uint64_t fcpvwt : 1; /**< Allows PEM_DBG_INFO[18] to generate an interrupt. */ 897215976Sjmallett uint64_t dpeoosd : 1; /**< Allows PEM_DBG_INFO[17] to generate an interrupt. */ 898215976Sjmallett uint64_t rtwdle : 1; /**< Allows PEM_DBG_INFO[16] to generate an interrupt. */ 899215976Sjmallett uint64_t rdwdle : 1; /**< Allows PEM_DBG_INFO[15] to generate an interrupt. */ 900215976Sjmallett uint64_t mre : 1; /**< Allows PEM_DBG_INFO[14] to generate an interrupt. */ 901215976Sjmallett uint64_t rte : 1; /**< Allows PEM_DBG_INFO[13] to generate an interrupt. */ 902215976Sjmallett uint64_t acto : 1; /**< Allows PEM_DBG_INFO[12] to generate an interrupt. */ 903215976Sjmallett uint64_t rvdm : 1; /**< Allows PEM_DBG_INFO[11] to generate an interrupt. */ 904215976Sjmallett uint64_t rumep : 1; /**< Allows PEM_DBG_INFO[10] to generate an interrupt. */ 905215976Sjmallett uint64_t rptamrc : 1; /**< Allows PEM_DBG_INFO[9] to generate an interrupt. */ 906215976Sjmallett uint64_t rpmerc : 1; /**< Allows PEM_DBG_INFO[8] to generate an interrupt. */ 907215976Sjmallett uint64_t rfemrc : 1; /**< Allows PEM_DBG_INFO[7] to generate an interrupt. */ 908215976Sjmallett uint64_t rnfemrc : 1; /**< Allows PEM_DBG_INFO[6] to generate an interrupt. */ 909215976Sjmallett uint64_t rcemrc : 1; /**< Allows PEM_DBG_INFO[5] to generate an interrupt. */ 910215976Sjmallett uint64_t rpoison : 1; /**< Allows PEM_DBG_INFO[4] to generate an interrupt. */ 911215976Sjmallett uint64_t recrce : 1; /**< Allows PEM_DBG_INFO[3] to generate an interrupt. */ 912215976Sjmallett uint64_t rtlplle : 1; /**< Allows PEM_DBG_INFO[2] to generate an interrupt. */ 913215976Sjmallett uint64_t rtlpmal : 1; /**< Allows PEM_DBG_INFO[1] to generate an interrupt. */ 914215976Sjmallett uint64_t spoison : 1; /**< Allows PEM_DBG_INFO[0] to generate an interrupt. */ 915215976Sjmallett#else 916215976Sjmallett uint64_t spoison : 1; 917215976Sjmallett uint64_t rtlpmal : 1; 918215976Sjmallett uint64_t rtlplle : 1; 919215976Sjmallett uint64_t recrce : 1; 920215976Sjmallett uint64_t rpoison : 1; 921215976Sjmallett uint64_t rcemrc : 1; 922215976Sjmallett uint64_t rnfemrc : 1; 923215976Sjmallett uint64_t rfemrc : 1; 924215976Sjmallett uint64_t rpmerc : 1; 925215976Sjmallett uint64_t rptamrc : 1; 926215976Sjmallett uint64_t rumep : 1; 927215976Sjmallett uint64_t rvdm : 1; 928215976Sjmallett uint64_t acto : 1; 929215976Sjmallett uint64_t rte : 1; 930215976Sjmallett uint64_t mre : 1; 931215976Sjmallett uint64_t rdwdle : 1; 932215976Sjmallett uint64_t rtwdle : 1; 933215976Sjmallett uint64_t dpeoosd : 1; 934215976Sjmallett uint64_t fcpvwt : 1; 935215976Sjmallett uint64_t rpe : 1; 936215976Sjmallett uint64_t fcuv : 1; 937215976Sjmallett uint64_t rqo : 1; 938215976Sjmallett uint64_t rauc : 1; 939215976Sjmallett uint64_t racur : 1; 940215976Sjmallett uint64_t racca : 1; 941215976Sjmallett uint64_t caar : 1; 942215976Sjmallett uint64_t rarwdns : 1; 943215976Sjmallett uint64_t ramtlp : 1; 944215976Sjmallett uint64_t racpp : 1; 945215976Sjmallett uint64_t rawwpp : 1; 946215976Sjmallett uint64_t ecrc_e : 1; 947215976Sjmallett uint64_t reserved_31_63 : 33; 948215976Sjmallett#endif 949215976Sjmallett } s; 950232812Sjmallett struct cvmx_pemx_dbg_info_en_s cn61xx; 951215976Sjmallett struct cvmx_pemx_dbg_info_en_s cn63xx; 952215976Sjmallett struct cvmx_pemx_dbg_info_en_s cn63xxp1; 953232812Sjmallett struct cvmx_pemx_dbg_info_en_s cn66xx; 954232812Sjmallett struct cvmx_pemx_dbg_info_en_s cn68xx; 955232812Sjmallett struct cvmx_pemx_dbg_info_en_s cn68xxp1; 956232812Sjmallett struct cvmx_pemx_dbg_info_en_s cnf71xx; 957215976Sjmallett}; 958215976Sjmalletttypedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t; 959215976Sjmallett 960215976Sjmallett/** 961215976Sjmallett * cvmx_pem#_diag_status 962215976Sjmallett * 963215976Sjmallett * PEM_DIAG_STATUS = PEM Diagnostic Status 964215976Sjmallett * 965215976Sjmallett * Selection control for the cores diagnostic bus. 966215976Sjmallett */ 967232812Sjmallettunion cvmx_pemx_diag_status { 968215976Sjmallett uint64_t u64; 969232812Sjmallett struct cvmx_pemx_diag_status_s { 970232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 971215976Sjmallett uint64_t reserved_4_63 : 60; 972215976Sjmallett uint64_t pm_dst : 1; /**< Current power management DSTATE. */ 973215976Sjmallett uint64_t pm_stat : 1; /**< Power Management Status. */ 974215976Sjmallett uint64_t pm_en : 1; /**< Power Management Event Enable. */ 975215976Sjmallett uint64_t aux_en : 1; /**< Auxilary Power Enable. */ 976215976Sjmallett#else 977215976Sjmallett uint64_t aux_en : 1; 978215976Sjmallett uint64_t pm_en : 1; 979215976Sjmallett uint64_t pm_stat : 1; 980215976Sjmallett uint64_t pm_dst : 1; 981215976Sjmallett uint64_t reserved_4_63 : 60; 982215976Sjmallett#endif 983215976Sjmallett } s; 984232812Sjmallett struct cvmx_pemx_diag_status_s cn61xx; 985215976Sjmallett struct cvmx_pemx_diag_status_s cn63xx; 986215976Sjmallett struct cvmx_pemx_diag_status_s cn63xxp1; 987232812Sjmallett struct cvmx_pemx_diag_status_s cn66xx; 988232812Sjmallett struct cvmx_pemx_diag_status_s cn68xx; 989232812Sjmallett struct cvmx_pemx_diag_status_s cn68xxp1; 990232812Sjmallett struct cvmx_pemx_diag_status_s cnf71xx; 991215976Sjmallett}; 992215976Sjmalletttypedef union cvmx_pemx_diag_status cvmx_pemx_diag_status_t; 993215976Sjmallett 994215976Sjmallett/** 995232812Sjmallett * cvmx_pem#_inb_read_credits 996232812Sjmallett * 997232812Sjmallett * PEM_INB_READ_CREDITS 998232812Sjmallett * 999232812Sjmallett * The number of in flight reads from PCIe core to SLI 1000232812Sjmallett */ 1001232812Sjmallettunion cvmx_pemx_inb_read_credits { 1002232812Sjmallett uint64_t u64; 1003232812Sjmallett struct cvmx_pemx_inb_read_credits_s { 1004232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1005232812Sjmallett uint64_t reserved_6_63 : 58; 1006232812Sjmallett uint64_t num : 6; /**< The number of reads that may be in flight from 1007232812Sjmallett the PCIe core to the SLI. Min number is 2 max 1008232812Sjmallett number is 32. */ 1009232812Sjmallett#else 1010232812Sjmallett uint64_t num : 6; 1011232812Sjmallett uint64_t reserved_6_63 : 58; 1012232812Sjmallett#endif 1013232812Sjmallett } s; 1014232812Sjmallett struct cvmx_pemx_inb_read_credits_s cn61xx; 1015232812Sjmallett struct cvmx_pemx_inb_read_credits_s cn66xx; 1016232812Sjmallett struct cvmx_pemx_inb_read_credits_s cn68xx; 1017232812Sjmallett struct cvmx_pemx_inb_read_credits_s cnf71xx; 1018232812Sjmallett}; 1019232812Sjmalletttypedef union cvmx_pemx_inb_read_credits cvmx_pemx_inb_read_credits_t; 1020232812Sjmallett 1021232812Sjmallett/** 1022215976Sjmallett * cvmx_pem#_int_enb 1023215976Sjmallett * 1024215976Sjmallett * PEM(0..1)_INT_ENB = PEM Interrupt Enable 1025215976Sjmallett * 1026215976Sjmallett * Enables interrupt conditions for the PEM to generate an RSL interrupt. 1027215976Sjmallett */ 1028232812Sjmallettunion cvmx_pemx_int_enb { 1029215976Sjmallett uint64_t u64; 1030232812Sjmallett struct cvmx_pemx_int_enb_s { 1031232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1032215976Sjmallett uint64_t reserved_14_63 : 50; 1033215976Sjmallett uint64_t crs_dr : 1; /**< Enables PEM_INT_SUM[13] to generate an 1034215976Sjmallett interrupt to the MIO. */ 1035215976Sjmallett uint64_t crs_er : 1; /**< Enables PEM_INT_SUM[12] to generate an 1036215976Sjmallett interrupt to the MIO. */ 1037215976Sjmallett uint64_t rdlk : 1; /**< Enables PEM_INT_SUM[11] to generate an 1038215976Sjmallett interrupt to the MIO. */ 1039215976Sjmallett uint64_t exc : 1; /**< Enables PEM_INT_SUM[10] to generate an 1040215976Sjmallett interrupt to the MIO. */ 1041215976Sjmallett uint64_t un_bx : 1; /**< Enables PEM_INT_SUM[9] to generate an 1042215976Sjmallett interrupt to the MIO. */ 1043215976Sjmallett uint64_t un_b2 : 1; /**< Enables PEM_INT_SUM[8] to generate an 1044215976Sjmallett interrupt to the MIO. */ 1045215976Sjmallett uint64_t un_b1 : 1; /**< Enables PEM_INT_SUM[7] to generate an 1046215976Sjmallett interrupt to the MIO. */ 1047215976Sjmallett uint64_t up_bx : 1; /**< Enables PEM_INT_SUM[6] to generate an 1048215976Sjmallett interrupt to the MIO. */ 1049215976Sjmallett uint64_t up_b2 : 1; /**< Enables PEM_INT_SUM[5] to generate an 1050215976Sjmallett interrupt to the MIO. */ 1051215976Sjmallett uint64_t up_b1 : 1; /**< Enables PEM_INT_SUM[4] to generate an 1052215976Sjmallett interrupt to the MIO. */ 1053215976Sjmallett uint64_t pmem : 1; /**< Enables PEM_INT_SUM[3] to generate an 1054215976Sjmallett interrupt to the MIO. */ 1055215976Sjmallett uint64_t pmei : 1; /**< Enables PEM_INT_SUM[2] to generate an 1056215976Sjmallett interrupt to the MIO. */ 1057215976Sjmallett uint64_t se : 1; /**< Enables PEM_INT_SUM[1] to generate an 1058215976Sjmallett interrupt to the MIO. */ 1059215976Sjmallett uint64_t aeri : 1; /**< Enables PEM_INT_SUM[0] to generate an 1060215976Sjmallett interrupt to the MIO. */ 1061215976Sjmallett#else 1062215976Sjmallett uint64_t aeri : 1; 1063215976Sjmallett uint64_t se : 1; 1064215976Sjmallett uint64_t pmei : 1; 1065215976Sjmallett uint64_t pmem : 1; 1066215976Sjmallett uint64_t up_b1 : 1; 1067215976Sjmallett uint64_t up_b2 : 1; 1068215976Sjmallett uint64_t up_bx : 1; 1069215976Sjmallett uint64_t un_b1 : 1; 1070215976Sjmallett uint64_t un_b2 : 1; 1071215976Sjmallett uint64_t un_bx : 1; 1072215976Sjmallett uint64_t exc : 1; 1073215976Sjmallett uint64_t rdlk : 1; 1074215976Sjmallett uint64_t crs_er : 1; 1075215976Sjmallett uint64_t crs_dr : 1; 1076215976Sjmallett uint64_t reserved_14_63 : 50; 1077215976Sjmallett#endif 1078215976Sjmallett } s; 1079232812Sjmallett struct cvmx_pemx_int_enb_s cn61xx; 1080215976Sjmallett struct cvmx_pemx_int_enb_s cn63xx; 1081215976Sjmallett struct cvmx_pemx_int_enb_s cn63xxp1; 1082232812Sjmallett struct cvmx_pemx_int_enb_s cn66xx; 1083232812Sjmallett struct cvmx_pemx_int_enb_s cn68xx; 1084232812Sjmallett struct cvmx_pemx_int_enb_s cn68xxp1; 1085232812Sjmallett struct cvmx_pemx_int_enb_s cnf71xx; 1086215976Sjmallett}; 1087215976Sjmalletttypedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t; 1088215976Sjmallett 1089215976Sjmallett/** 1090215976Sjmallett * cvmx_pem#_int_enb_int 1091215976Sjmallett * 1092215976Sjmallett * PEM(0..1)_INT_ENB_INT = PEM Interrupt Enable 1093215976Sjmallett * 1094215976Sjmallett * Enables interrupt conditions for the PEM to generate an RSL interrupt. 1095215976Sjmallett */ 1096232812Sjmallettunion cvmx_pemx_int_enb_int { 1097215976Sjmallett uint64_t u64; 1098232812Sjmallett struct cvmx_pemx_int_enb_int_s { 1099232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1100215976Sjmallett uint64_t reserved_14_63 : 50; 1101215976Sjmallett uint64_t crs_dr : 1; /**< Enables PEM_INT_SUM[13] to generate an 1102215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1103215976Sjmallett uint64_t crs_er : 1; /**< Enables PEM_INT_SUM[12] to generate an 1104215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1105215976Sjmallett uint64_t rdlk : 1; /**< Enables PEM_INT_SUM[11] to generate an 1106215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1107215976Sjmallett uint64_t exc : 1; /**< Enables PEM_INT_SUM[10] to generate an 1108215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1109215976Sjmallett uint64_t un_bx : 1; /**< Enables PEM_INT_SUM[9] to generate an 1110215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1111215976Sjmallett uint64_t un_b2 : 1; /**< Enables PEM_INT_SUM[8] to generate an 1112215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1113215976Sjmallett uint64_t un_b1 : 1; /**< Enables PEM_INT_SUM[7] to generate an 1114215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1115215976Sjmallett uint64_t up_bx : 1; /**< Enables PEM_INT_SUM[6] to generate an 1116215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1117215976Sjmallett uint64_t up_b2 : 1; /**< Enables PEM_INT_SUM[5] to generate an 1118215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1119215976Sjmallett uint64_t up_b1 : 1; /**< Enables PEM_INT_SUM[4] to generate an 1120215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1121215976Sjmallett uint64_t pmem : 1; /**< Enables PEM_INT_SUM[3] to generate an 1122215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1123215976Sjmallett uint64_t pmei : 1; /**< Enables PEM_INT_SUM[2] to generate an 1124215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1125215976Sjmallett uint64_t se : 1; /**< Enables PEM_INT_SUM[1] to generate an 1126215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1127215976Sjmallett uint64_t aeri : 1; /**< Enables PEM_INT_SUM[0] to generate an 1128215976Sjmallett interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */ 1129215976Sjmallett#else 1130215976Sjmallett uint64_t aeri : 1; 1131215976Sjmallett uint64_t se : 1; 1132215976Sjmallett uint64_t pmei : 1; 1133215976Sjmallett uint64_t pmem : 1; 1134215976Sjmallett uint64_t up_b1 : 1; 1135215976Sjmallett uint64_t up_b2 : 1; 1136215976Sjmallett uint64_t up_bx : 1; 1137215976Sjmallett uint64_t un_b1 : 1; 1138215976Sjmallett uint64_t un_b2 : 1; 1139215976Sjmallett uint64_t un_bx : 1; 1140215976Sjmallett uint64_t exc : 1; 1141215976Sjmallett uint64_t rdlk : 1; 1142215976Sjmallett uint64_t crs_er : 1; 1143215976Sjmallett uint64_t crs_dr : 1; 1144215976Sjmallett uint64_t reserved_14_63 : 50; 1145215976Sjmallett#endif 1146215976Sjmallett } s; 1147232812Sjmallett struct cvmx_pemx_int_enb_int_s cn61xx; 1148215976Sjmallett struct cvmx_pemx_int_enb_int_s cn63xx; 1149215976Sjmallett struct cvmx_pemx_int_enb_int_s cn63xxp1; 1150232812Sjmallett struct cvmx_pemx_int_enb_int_s cn66xx; 1151232812Sjmallett struct cvmx_pemx_int_enb_int_s cn68xx; 1152232812Sjmallett struct cvmx_pemx_int_enb_int_s cn68xxp1; 1153232812Sjmallett struct cvmx_pemx_int_enb_int_s cnf71xx; 1154215976Sjmallett}; 1155215976Sjmalletttypedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t; 1156215976Sjmallett 1157215976Sjmallett/** 1158215976Sjmallett * cvmx_pem#_int_sum 1159215976Sjmallett * 1160215976Sjmallett * Below are in pesc_csr 1161215976Sjmallett * 1162215976Sjmallett * PEM(0..1)_INT_SUM = PEM Interrupt Summary 1163215976Sjmallett * 1164215976Sjmallett * Interrupt conditions for the PEM. 1165215976Sjmallett */ 1166232812Sjmallettunion cvmx_pemx_int_sum { 1167215976Sjmallett uint64_t u64; 1168232812Sjmallett struct cvmx_pemx_int_sum_s { 1169232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1170215976Sjmallett uint64_t reserved_14_63 : 50; 1171215976Sjmallett uint64_t crs_dr : 1; /**< Had a CRS Timeout when Retries were disabled. */ 1172215976Sjmallett uint64_t crs_er : 1; /**< Had a CRS Timeout when Retries were enabled. */ 1173215976Sjmallett uint64_t rdlk : 1; /**< Received Read Lock TLP. */ 1174215976Sjmallett uint64_t exc : 1; /**< Set when the PEM_DBG_INFO register has a bit 1175215976Sjmallett set and its cooresponding PEM_DBG_INFO_EN bit 1176215976Sjmallett is set. */ 1177215976Sjmallett uint64_t un_bx : 1; /**< Received N-TLP for an unknown Bar. */ 1178215976Sjmallett uint64_t un_b2 : 1; /**< Received N-TLP for Bar2 when bar2 is disabled. */ 1179215976Sjmallett uint64_t un_b1 : 1; /**< Received N-TLP for Bar1 when bar1 index valid 1180215976Sjmallett is not set. */ 1181215976Sjmallett uint64_t up_bx : 1; /**< Received P-TLP for an unknown Bar. */ 1182215976Sjmallett uint64_t up_b2 : 1; /**< Received P-TLP for Bar2 when bar2 is disabeld. */ 1183215976Sjmallett uint64_t up_b1 : 1; /**< Received P-TLP for Bar1 when bar1 index valid 1184215976Sjmallett is not set. */ 1185215976Sjmallett uint64_t pmem : 1; /**< Recived PME MSG. 1186215976Sjmallett (radm_pm_pme) */ 1187215976Sjmallett uint64_t pmei : 1; /**< PME Interrupt. 1188215976Sjmallett (cfg_pme_int) */ 1189215976Sjmallett uint64_t se : 1; /**< System Error, RC Mode Only. 1190215976Sjmallett (cfg_sys_err_rc) */ 1191215976Sjmallett uint64_t aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only. 1192215976Sjmallett (cfg_aer_rc_err_int). */ 1193215976Sjmallett#else 1194215976Sjmallett uint64_t aeri : 1; 1195215976Sjmallett uint64_t se : 1; 1196215976Sjmallett uint64_t pmei : 1; 1197215976Sjmallett uint64_t pmem : 1; 1198215976Sjmallett uint64_t up_b1 : 1; 1199215976Sjmallett uint64_t up_b2 : 1; 1200215976Sjmallett uint64_t up_bx : 1; 1201215976Sjmallett uint64_t un_b1 : 1; 1202215976Sjmallett uint64_t un_b2 : 1; 1203215976Sjmallett uint64_t un_bx : 1; 1204215976Sjmallett uint64_t exc : 1; 1205215976Sjmallett uint64_t rdlk : 1; 1206215976Sjmallett uint64_t crs_er : 1; 1207215976Sjmallett uint64_t crs_dr : 1; 1208215976Sjmallett uint64_t reserved_14_63 : 50; 1209215976Sjmallett#endif 1210215976Sjmallett } s; 1211232812Sjmallett struct cvmx_pemx_int_sum_s cn61xx; 1212215976Sjmallett struct cvmx_pemx_int_sum_s cn63xx; 1213215976Sjmallett struct cvmx_pemx_int_sum_s cn63xxp1; 1214232812Sjmallett struct cvmx_pemx_int_sum_s cn66xx; 1215232812Sjmallett struct cvmx_pemx_int_sum_s cn68xx; 1216232812Sjmallett struct cvmx_pemx_int_sum_s cn68xxp1; 1217232812Sjmallett struct cvmx_pemx_int_sum_s cnf71xx; 1218215976Sjmallett}; 1219215976Sjmalletttypedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t; 1220215976Sjmallett 1221215976Sjmallett/** 1222215976Sjmallett * cvmx_pem#_p2n_bar0_start 1223215976Sjmallett * 1224215976Sjmallett * PEM_P2N_BAR0_START = PEM PCIe to Npei BAR0 Start 1225215976Sjmallett * 1226215976Sjmallett * The starting address for addresses to forwarded to the SLI in RC Mode. 1227215976Sjmallett */ 1228232812Sjmallettunion cvmx_pemx_p2n_bar0_start { 1229215976Sjmallett uint64_t u64; 1230232812Sjmallett struct cvmx_pemx_p2n_bar0_start_s { 1231232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1232215976Sjmallett uint64_t addr : 50; /**< The starting address of the 16KB address space that 1233215976Sjmallett is the BAR0 address space. */ 1234215976Sjmallett uint64_t reserved_0_13 : 14; 1235215976Sjmallett#else 1236215976Sjmallett uint64_t reserved_0_13 : 14; 1237215976Sjmallett uint64_t addr : 50; 1238215976Sjmallett#endif 1239215976Sjmallett } s; 1240232812Sjmallett struct cvmx_pemx_p2n_bar0_start_s cn61xx; 1241215976Sjmallett struct cvmx_pemx_p2n_bar0_start_s cn63xx; 1242215976Sjmallett struct cvmx_pemx_p2n_bar0_start_s cn63xxp1; 1243232812Sjmallett struct cvmx_pemx_p2n_bar0_start_s cn66xx; 1244232812Sjmallett struct cvmx_pemx_p2n_bar0_start_s cn68xx; 1245232812Sjmallett struct cvmx_pemx_p2n_bar0_start_s cn68xxp1; 1246232812Sjmallett struct cvmx_pemx_p2n_bar0_start_s cnf71xx; 1247215976Sjmallett}; 1248215976Sjmalletttypedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t; 1249215976Sjmallett 1250215976Sjmallett/** 1251215976Sjmallett * cvmx_pem#_p2n_bar1_start 1252215976Sjmallett * 1253215976Sjmallett * PEM_P2N_BAR1_START = PEM PCIe to Npei BAR1 Start 1254215976Sjmallett * 1255215976Sjmallett * The starting address for addresses to forwarded to the SLI in RC Mode. 1256215976Sjmallett */ 1257232812Sjmallettunion cvmx_pemx_p2n_bar1_start { 1258215976Sjmallett uint64_t u64; 1259232812Sjmallett struct cvmx_pemx_p2n_bar1_start_s { 1260232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1261215976Sjmallett uint64_t addr : 38; /**< The starting address of the 64KB address space 1262215976Sjmallett that is the BAR1 address space. */ 1263215976Sjmallett uint64_t reserved_0_25 : 26; 1264215976Sjmallett#else 1265215976Sjmallett uint64_t reserved_0_25 : 26; 1266215976Sjmallett uint64_t addr : 38; 1267215976Sjmallett#endif 1268215976Sjmallett } s; 1269232812Sjmallett struct cvmx_pemx_p2n_bar1_start_s cn61xx; 1270215976Sjmallett struct cvmx_pemx_p2n_bar1_start_s cn63xx; 1271215976Sjmallett struct cvmx_pemx_p2n_bar1_start_s cn63xxp1; 1272232812Sjmallett struct cvmx_pemx_p2n_bar1_start_s cn66xx; 1273232812Sjmallett struct cvmx_pemx_p2n_bar1_start_s cn68xx; 1274232812Sjmallett struct cvmx_pemx_p2n_bar1_start_s cn68xxp1; 1275232812Sjmallett struct cvmx_pemx_p2n_bar1_start_s cnf71xx; 1276215976Sjmallett}; 1277215976Sjmalletttypedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t; 1278215976Sjmallett 1279215976Sjmallett/** 1280215976Sjmallett * cvmx_pem#_p2n_bar2_start 1281215976Sjmallett * 1282215976Sjmallett * PEM_P2N_BAR2_START = PEM PCIe to Npei BAR2 Start 1283215976Sjmallett * 1284215976Sjmallett * The starting address for addresses to forwarded to the SLI in RC Mode. 1285215976Sjmallett */ 1286232812Sjmallettunion cvmx_pemx_p2n_bar2_start { 1287215976Sjmallett uint64_t u64; 1288232812Sjmallett struct cvmx_pemx_p2n_bar2_start_s { 1289232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1290215976Sjmallett uint64_t addr : 23; /**< The starting address of the 2^41 address space 1291215976Sjmallett that is the BAR2 address space. */ 1292215976Sjmallett uint64_t reserved_0_40 : 41; 1293215976Sjmallett#else 1294215976Sjmallett uint64_t reserved_0_40 : 41; 1295215976Sjmallett uint64_t addr : 23; 1296215976Sjmallett#endif 1297215976Sjmallett } s; 1298232812Sjmallett struct cvmx_pemx_p2n_bar2_start_s cn61xx; 1299215976Sjmallett struct cvmx_pemx_p2n_bar2_start_s cn63xx; 1300215976Sjmallett struct cvmx_pemx_p2n_bar2_start_s cn63xxp1; 1301232812Sjmallett struct cvmx_pemx_p2n_bar2_start_s cn66xx; 1302232812Sjmallett struct cvmx_pemx_p2n_bar2_start_s cn68xx; 1303232812Sjmallett struct cvmx_pemx_p2n_bar2_start_s cn68xxp1; 1304232812Sjmallett struct cvmx_pemx_p2n_bar2_start_s cnf71xx; 1305215976Sjmallett}; 1306215976Sjmalletttypedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t; 1307215976Sjmallett 1308215976Sjmallett/** 1309215976Sjmallett * cvmx_pem#_p2p_bar#_end 1310215976Sjmallett * 1311215976Sjmallett * PEM_P2P_BAR#_END = PEM Peer-To-Peer BAR0 End 1312215976Sjmallett * 1313215976Sjmallett * The ending address for addresses to forwarded to the PCIe peer port. 1314215976Sjmallett */ 1315232812Sjmallettunion cvmx_pemx_p2p_barx_end { 1316215976Sjmallett uint64_t u64; 1317232812Sjmallett struct cvmx_pemx_p2p_barx_end_s { 1318232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1319215976Sjmallett uint64_t addr : 52; /**< The ending address of the address window created 1320215976Sjmallett this field and the PEM_P2P_BAR0_START[63:12] 1321215976Sjmallett field. The full 64-bits of address are created by: 1322215976Sjmallett [ADDR[63:12], 12'b0]. */ 1323215976Sjmallett uint64_t reserved_0_11 : 12; 1324215976Sjmallett#else 1325215976Sjmallett uint64_t reserved_0_11 : 12; 1326215976Sjmallett uint64_t addr : 52; 1327215976Sjmallett#endif 1328215976Sjmallett } s; 1329215976Sjmallett struct cvmx_pemx_p2p_barx_end_s cn63xx; 1330215976Sjmallett struct cvmx_pemx_p2p_barx_end_s cn63xxp1; 1331232812Sjmallett struct cvmx_pemx_p2p_barx_end_s cn66xx; 1332232812Sjmallett struct cvmx_pemx_p2p_barx_end_s cn68xx; 1333232812Sjmallett struct cvmx_pemx_p2p_barx_end_s cn68xxp1; 1334215976Sjmallett}; 1335215976Sjmalletttypedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t; 1336215976Sjmallett 1337215976Sjmallett/** 1338215976Sjmallett * cvmx_pem#_p2p_bar#_start 1339215976Sjmallett * 1340215976Sjmallett * PEM_P2P_BAR#_START = PEM Peer-To-Peer BAR0 Start 1341215976Sjmallett * 1342215976Sjmallett * The starting address and enable for addresses to forwarded to the PCIe peer port. 1343215976Sjmallett */ 1344232812Sjmallettunion cvmx_pemx_p2p_barx_start { 1345215976Sjmallett uint64_t u64; 1346232812Sjmallett struct cvmx_pemx_p2p_barx_start_s { 1347232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1348215976Sjmallett uint64_t addr : 52; /**< The starting address of the address window created 1349215976Sjmallett by this field and the PEM_P2P_BAR0_END[63:12] 1350215976Sjmallett field. The full 64-bits of address are created by: 1351215976Sjmallett [ADDR[63:12], 12'b0]. */ 1352215976Sjmallett uint64_t reserved_0_11 : 12; 1353215976Sjmallett#else 1354215976Sjmallett uint64_t reserved_0_11 : 12; 1355215976Sjmallett uint64_t addr : 52; 1356215976Sjmallett#endif 1357215976Sjmallett } s; 1358215976Sjmallett struct cvmx_pemx_p2p_barx_start_s cn63xx; 1359215976Sjmallett struct cvmx_pemx_p2p_barx_start_s cn63xxp1; 1360232812Sjmallett struct cvmx_pemx_p2p_barx_start_s cn66xx; 1361232812Sjmallett struct cvmx_pemx_p2p_barx_start_s cn68xx; 1362232812Sjmallett struct cvmx_pemx_p2p_barx_start_s cn68xxp1; 1363215976Sjmallett}; 1364215976Sjmalletttypedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t; 1365215976Sjmallett 1366215976Sjmallett/** 1367215976Sjmallett * cvmx_pem#_tlp_credits 1368215976Sjmallett * 1369215976Sjmallett * PEM_TLP_CREDITS = PEM TLP Credits 1370215976Sjmallett * 1371215976Sjmallett * Specifies the number of credits the PEM for use in moving TLPs. When this register is written the credit values are 1372215976Sjmallett * reset to the register value. A write to this register should take place BEFORE traffic flow starts. 1373215976Sjmallett */ 1374232812Sjmallettunion cvmx_pemx_tlp_credits { 1375215976Sjmallett uint64_t u64; 1376232812Sjmallett struct cvmx_pemx_tlp_credits_s { 1377232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1378215976Sjmallett uint64_t reserved_56_63 : 8; 1379215976Sjmallett uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer. 1380232812Sjmallett The value in this register should not be changed. 1381232812Sjmallett Values other than 0x80 can lead to unpredictable 1382232812Sjmallett behavior */ 1383215976Sjmallett uint64_t pem_cpl : 8; /**< TLP credits for Completion TLPs in the Peer. 1384215976Sjmallett Legal values are 0x24 to 0x80. */ 1385215976Sjmallett uint64_t pem_np : 8; /**< TLP credits for Non-Posted TLPs in the Peer. 1386215976Sjmallett Legal values are 0x4 to 0x10. */ 1387215976Sjmallett uint64_t pem_p : 8; /**< TLP credits for Posted TLPs in the Peer. 1388215976Sjmallett Legal values are 0x24 to 0x80. */ 1389215976Sjmallett uint64_t sli_cpl : 8; /**< TLP credits for Completion TLPs in the SLI. 1390215976Sjmallett Legal values are 0x24 to 0x80. */ 1391215976Sjmallett uint64_t sli_np : 8; /**< TLP credits for Non-Posted TLPs in the SLI. 1392215976Sjmallett Legal values are 0x4 to 0x10. */ 1393215976Sjmallett uint64_t sli_p : 8; /**< TLP credits for Posted TLPs in the SLI. 1394215976Sjmallett Legal values are 0x24 to 0x80. */ 1395215976Sjmallett#else 1396215976Sjmallett uint64_t sli_p : 8; 1397215976Sjmallett uint64_t sli_np : 8; 1398215976Sjmallett uint64_t sli_cpl : 8; 1399215976Sjmallett uint64_t pem_p : 8; 1400215976Sjmallett uint64_t pem_np : 8; 1401215976Sjmallett uint64_t pem_cpl : 8; 1402215976Sjmallett uint64_t peai_ppf : 8; 1403215976Sjmallett uint64_t reserved_56_63 : 8; 1404215976Sjmallett#endif 1405215976Sjmallett } s; 1406232812Sjmallett struct cvmx_pemx_tlp_credits_cn61xx { 1407232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1408232812Sjmallett uint64_t reserved_56_63 : 8; 1409232812Sjmallett uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer. 1410232812Sjmallett The value in this register should not be changed. 1411232812Sjmallett Values other than 0x80 can lead to unpredictable 1412232812Sjmallett behavior */ 1413232812Sjmallett uint64_t reserved_24_47 : 24; 1414232812Sjmallett uint64_t sli_cpl : 8; /**< TLP credits for Completion TLPs in the SLI. 1415232812Sjmallett Legal values are 0x24 to 0x80. */ 1416232812Sjmallett uint64_t sli_np : 8; /**< TLP credits for Non-Posted TLPs in the SLI. 1417232812Sjmallett Legal values are 0x4 to 0x10. */ 1418232812Sjmallett uint64_t sli_p : 8; /**< TLP credits for Posted TLPs in the SLI. 1419232812Sjmallett Legal values are 0x24 to 0x80. */ 1420232812Sjmallett#else 1421232812Sjmallett uint64_t sli_p : 8; 1422232812Sjmallett uint64_t sli_np : 8; 1423232812Sjmallett uint64_t sli_cpl : 8; 1424232812Sjmallett uint64_t reserved_24_47 : 24; 1425232812Sjmallett uint64_t peai_ppf : 8; 1426232812Sjmallett uint64_t reserved_56_63 : 8; 1427232812Sjmallett#endif 1428232812Sjmallett } cn61xx; 1429215976Sjmallett struct cvmx_pemx_tlp_credits_s cn63xx; 1430215976Sjmallett struct cvmx_pemx_tlp_credits_s cn63xxp1; 1431232812Sjmallett struct cvmx_pemx_tlp_credits_s cn66xx; 1432232812Sjmallett struct cvmx_pemx_tlp_credits_s cn68xx; 1433232812Sjmallett struct cvmx_pemx_tlp_credits_s cn68xxp1; 1434232812Sjmallett struct cvmx_pemx_tlp_credits_cn61xx cnf71xx; 1435215976Sjmallett}; 1436215976Sjmalletttypedef union cvmx_pemx_tlp_credits cvmx_pemx_tlp_credits_t; 1437215976Sjmallett 1438215976Sjmallett#endif 1439