1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pcsx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pcsx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_PCSX_DEFS_H__ 53232812Sjmallett#define __CVMX_PCSX_DEFS_H__ 54215976Sjmallett 55215976Sjmallettstatic inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id) 56215976Sjmallett{ 57232812Sjmallett switch(cvmx_get_octeon_family()) { 58232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 59232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 60232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 61232812Sjmallett break; 62232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 63232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 64232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 65232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 66232812Sjmallett break; 67232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 68232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 69232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 70232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 71232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 72232812Sjmallett break; 73232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 74232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 75232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 76232812Sjmallett break; 77232812Sjmallett } 78232812Sjmallett cvmx_warn("CVMX_PCSX_ANX_ADV_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 79232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 80215976Sjmallett} 81215976Sjmallettstatic inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id) 82215976Sjmallett{ 83232812Sjmallett switch(cvmx_get_octeon_family()) { 84232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 85232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 86232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 87232812Sjmallett break; 88232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 89232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 90232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 91232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 92232812Sjmallett break; 93232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 94232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 95232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 96232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 97232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 98232812Sjmallett break; 99232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 100232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 101232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 102232812Sjmallett break; 103232812Sjmallett } 104232812Sjmallett cvmx_warn("CVMX_PCSX_ANX_EXT_ST_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 105232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 106215976Sjmallett} 107215976Sjmallettstatic inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id) 108215976Sjmallett{ 109232812Sjmallett switch(cvmx_get_octeon_family()) { 110232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 111232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 112232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 113232812Sjmallett break; 114232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 115232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 116232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 117232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 118232812Sjmallett break; 119232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 120232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 121232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 122232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 123232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 124232812Sjmallett break; 125232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 126232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 127232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 128232812Sjmallett break; 129232812Sjmallett } 130232812Sjmallett cvmx_warn("CVMX_PCSX_ANX_LP_ABIL_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 131232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 132215976Sjmallett} 133215976Sjmallettstatic inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id) 134215976Sjmallett{ 135232812Sjmallett switch(cvmx_get_octeon_family()) { 136232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 137232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 138232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 139232812Sjmallett break; 140232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 141232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 142232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 143232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 144232812Sjmallett break; 145232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 146232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 147232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 148232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 149232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 150232812Sjmallett break; 151232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 152232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 153232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 154232812Sjmallett break; 155232812Sjmallett } 156232812Sjmallett cvmx_warn("CVMX_PCSX_ANX_RESULTS_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 157232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 158215976Sjmallett} 159215976Sjmallettstatic inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id) 160215976Sjmallett{ 161232812Sjmallett switch(cvmx_get_octeon_family()) { 162232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 163232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 164232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 165232812Sjmallett break; 166232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 167232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 168232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 169232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 170232812Sjmallett break; 171232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 172232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 173232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 174232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 175232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 176232812Sjmallett break; 177232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 178232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 179232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 180232812Sjmallett break; 181232812Sjmallett } 182232812Sjmallett cvmx_warn("CVMX_PCSX_INTX_EN_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 183232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 184215976Sjmallett} 185215976Sjmallettstatic inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id) 186215976Sjmallett{ 187232812Sjmallett switch(cvmx_get_octeon_family()) { 188232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 189232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 190232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 191232812Sjmallett break; 192232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 193232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 194232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 195232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 196232812Sjmallett break; 197232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 198232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 199232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 200232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 201232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 202232812Sjmallett break; 203232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 204232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 205232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 206232812Sjmallett break; 207232812Sjmallett } 208232812Sjmallett cvmx_warn("CVMX_PCSX_INTX_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 209232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 210215976Sjmallett} 211215976Sjmallettstatic inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id) 212215976Sjmallett{ 213232812Sjmallett switch(cvmx_get_octeon_family()) { 214232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 215232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 216232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 217232812Sjmallett break; 218232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 219232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 220232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 221232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 222232812Sjmallett break; 223232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 224232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 225232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 226232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 227232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 228232812Sjmallett break; 229232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 230232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 231232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 232232812Sjmallett break; 233232812Sjmallett } 234232812Sjmallett cvmx_warn("CVMX_PCSX_LINKX_TIMER_COUNT_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 235232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 236215976Sjmallett} 237215976Sjmallettstatic inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id) 238215976Sjmallett{ 239232812Sjmallett switch(cvmx_get_octeon_family()) { 240232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 241232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 242232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 243232812Sjmallett break; 244232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 245232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 246232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 247232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 248232812Sjmallett break; 249232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 250232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 251232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 252232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 253232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 254232812Sjmallett break; 255232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 256232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 257232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 258232812Sjmallett break; 259232812Sjmallett } 260232812Sjmallett cvmx_warn("CVMX_PCSX_LOG_ANLX_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 261232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 262215976Sjmallett} 263215976Sjmallettstatic inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id) 264215976Sjmallett{ 265232812Sjmallett switch(cvmx_get_octeon_family()) { 266232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 267232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 268232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 269232812Sjmallett break; 270232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 271232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 272232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 273232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 274232812Sjmallett break; 275232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 276232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 277232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 278232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 279232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 280232812Sjmallett break; 281232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 282232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 283232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 284232812Sjmallett break; 285232812Sjmallett } 286232812Sjmallett cvmx_warn("CVMX_PCSX_MISCX_CTL_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 287232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 288215976Sjmallett} 289215976Sjmallettstatic inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id) 290215976Sjmallett{ 291232812Sjmallett switch(cvmx_get_octeon_family()) { 292232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 293232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 294232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 295232812Sjmallett break; 296232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 297232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 298232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 299232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 300232812Sjmallett break; 301232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 302232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 303232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 304232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 305232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 306232812Sjmallett break; 307232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 308232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 309232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 310232812Sjmallett break; 311232812Sjmallett } 312232812Sjmallett cvmx_warn("CVMX_PCSX_MRX_CONTROL_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 313232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 314215976Sjmallett} 315215976Sjmallettstatic inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id) 316215976Sjmallett{ 317232812Sjmallett switch(cvmx_get_octeon_family()) { 318232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 319232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 320232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 321232812Sjmallett break; 322232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 323232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 324232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 325232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 326232812Sjmallett break; 327232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 328232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 329232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 330232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 331232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 332232812Sjmallett break; 333232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 334232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 335232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 336232812Sjmallett break; 337232812Sjmallett } 338232812Sjmallett cvmx_warn("CVMX_PCSX_MRX_STATUS_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 339232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 340215976Sjmallett} 341215976Sjmallettstatic inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id) 342215976Sjmallett{ 343232812Sjmallett switch(cvmx_get_octeon_family()) { 344232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 345232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 346232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 347232812Sjmallett break; 348232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 349232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 350232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 351232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 352232812Sjmallett break; 353232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 354232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 355232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 356232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 357232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 358232812Sjmallett break; 359232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 360232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 361232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 362232812Sjmallett break; 363232812Sjmallett } 364232812Sjmallett cvmx_warn("CVMX_PCSX_RXX_STATES_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 365232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 366215976Sjmallett} 367215976Sjmallettstatic inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id) 368215976Sjmallett{ 369232812Sjmallett switch(cvmx_get_octeon_family()) { 370232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 371232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 372232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 373232812Sjmallett break; 374232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 375232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 376232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 377232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 378232812Sjmallett break; 379232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 380232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 381232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 382232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 383232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 384232812Sjmallett break; 385232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 386232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 387232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 388232812Sjmallett break; 389232812Sjmallett } 390232812Sjmallett cvmx_warn("CVMX_PCSX_RXX_SYNC_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 391232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 392215976Sjmallett} 393215976Sjmallettstatic inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id) 394215976Sjmallett{ 395232812Sjmallett switch(cvmx_get_octeon_family()) { 396232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 397232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 398232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 399232812Sjmallett break; 400232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 401232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 402232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 403232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 404232812Sjmallett break; 405232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 406232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 407232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 408232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 409232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 410232812Sjmallett break; 411232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 412232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 413232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 414232812Sjmallett break; 415232812Sjmallett } 416232812Sjmallett cvmx_warn("CVMX_PCSX_SGMX_AN_ADV_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 417232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 418215976Sjmallett} 419215976Sjmallettstatic inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id) 420215976Sjmallett{ 421232812Sjmallett switch(cvmx_get_octeon_family()) { 422232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 423232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 424232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 425232812Sjmallett break; 426232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 427232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 428232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 429232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 430232812Sjmallett break; 431232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 432232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 433232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 434232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 435232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 436232812Sjmallett break; 437232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 438232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 439232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 440232812Sjmallett break; 441232812Sjmallett } 442232812Sjmallett cvmx_warn("CVMX_PCSX_SGMX_LP_ADV_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 443232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 444215976Sjmallett} 445215976Sjmallettstatic inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id) 446215976Sjmallett{ 447232812Sjmallett switch(cvmx_get_octeon_family()) { 448232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 449232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 450232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 451232812Sjmallett break; 452232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 453232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 454232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 455232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 456232812Sjmallett break; 457232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 458232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 459232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 460232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 461232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 462232812Sjmallett break; 463232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 464232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 465232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 466232812Sjmallett break; 467232812Sjmallett } 468232812Sjmallett cvmx_warn("CVMX_PCSX_TXX_STATES_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 469232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 470215976Sjmallett} 471215976Sjmallettstatic inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id) 472215976Sjmallett{ 473232812Sjmallett switch(cvmx_get_octeon_family()) { 474232812Sjmallett case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 475232812Sjmallett if (((offset <= 1)) && ((block_id == 0))) 476232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 477232812Sjmallett break; 478232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 479232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 480232812Sjmallett if (((offset <= 3)) && ((block_id == 0))) 481232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024; 482232812Sjmallett break; 483232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 484232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 485232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 486232812Sjmallett if (((offset <= 3)) && ((block_id <= 1))) 487232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024; 488232812Sjmallett break; 489232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 490232812Sjmallett if (((offset <= 3)) && ((block_id <= 4))) 491232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024; 492232812Sjmallett break; 493232812Sjmallett } 494232812Sjmallett cvmx_warn("CVMX_PCSX_TX_RXX_POLARITY_REG (%lu, %lu) not supported on this chip\n", offset, block_id); 495232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024; 496215976Sjmallett} 497215976Sjmallett 498215976Sjmallett/** 499215976Sjmallett * cvmx_pcs#_an#_adv_reg 500215976Sjmallett * 501215976Sjmallett * Bits [15:9] in the Status Register indicate ability to operate as per those signalling specification, 502215976Sjmallett * when misc ctl reg MAC_PHY bit is set to MAC mode. Bits [15:9] will all, always read 1'b0, indicating 503215976Sjmallett * that the chip cannot operate in the corresponding modes. 504215976Sjmallett * 505215976Sjmallett * Bit [4] RM_FLT is a don't care when the selected mode is SGMII. 506215976Sjmallett * 507215976Sjmallett * 508215976Sjmallett * 509215976Sjmallett * PCS_AN_ADV_REG = AN Advertisement Register4 510215976Sjmallett */ 511232812Sjmallettunion cvmx_pcsx_anx_adv_reg { 512215976Sjmallett uint64_t u64; 513232812Sjmallett struct cvmx_pcsx_anx_adv_reg_s { 514232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 515215976Sjmallett uint64_t reserved_16_63 : 48; 516215976Sjmallett uint64_t np : 1; /**< Always 0, no next page capability supported */ 517215976Sjmallett uint64_t reserved_14_14 : 1; 518215976Sjmallett uint64_t rem_flt : 2; /**< [<13>,<12>] 519215976Sjmallett 0 0 Link OK XMIT=DATA 520215976Sjmallett 0 1 Link failure (loss of sync, XMIT!= DATA) 521215976Sjmallett 1 0 local device Offline 522215976Sjmallett 1 1 AN Error failure to complete AN 523215976Sjmallett AN Error is set if resolution function 524215976Sjmallett precludes operation with link partner */ 525215976Sjmallett uint64_t reserved_9_11 : 3; 526215976Sjmallett uint64_t pause : 2; /**< [<8>, <7>] Pause frame flow capability across link 527215976Sjmallett Exchanged during Auto Negotiation 528215976Sjmallett 0 0 No Pause 529215976Sjmallett 0 1 Symmetric pause 530215976Sjmallett 1 0 Asymmetric Pause 531215976Sjmallett 1 1 Both symm and asymm pause to local device */ 532215976Sjmallett uint64_t hfd : 1; /**< 1 means local device Half Duplex capable */ 533215976Sjmallett uint64_t fd : 1; /**< 1 means local device Full Duplex capable */ 534215976Sjmallett uint64_t reserved_0_4 : 5; 535215976Sjmallett#else 536215976Sjmallett uint64_t reserved_0_4 : 5; 537215976Sjmallett uint64_t fd : 1; 538215976Sjmallett uint64_t hfd : 1; 539215976Sjmallett uint64_t pause : 2; 540215976Sjmallett uint64_t reserved_9_11 : 3; 541215976Sjmallett uint64_t rem_flt : 2; 542215976Sjmallett uint64_t reserved_14_14 : 1; 543215976Sjmallett uint64_t np : 1; 544215976Sjmallett uint64_t reserved_16_63 : 48; 545215976Sjmallett#endif 546215976Sjmallett } s; 547215976Sjmallett struct cvmx_pcsx_anx_adv_reg_s cn52xx; 548215976Sjmallett struct cvmx_pcsx_anx_adv_reg_s cn52xxp1; 549215976Sjmallett struct cvmx_pcsx_anx_adv_reg_s cn56xx; 550215976Sjmallett struct cvmx_pcsx_anx_adv_reg_s cn56xxp1; 551232812Sjmallett struct cvmx_pcsx_anx_adv_reg_s cn61xx; 552215976Sjmallett struct cvmx_pcsx_anx_adv_reg_s cn63xx; 553215976Sjmallett struct cvmx_pcsx_anx_adv_reg_s cn63xxp1; 554232812Sjmallett struct cvmx_pcsx_anx_adv_reg_s cn66xx; 555232812Sjmallett struct cvmx_pcsx_anx_adv_reg_s cn68xx; 556232812Sjmallett struct cvmx_pcsx_anx_adv_reg_s cn68xxp1; 557232812Sjmallett struct cvmx_pcsx_anx_adv_reg_s cnf71xx; 558215976Sjmallett}; 559215976Sjmalletttypedef union cvmx_pcsx_anx_adv_reg cvmx_pcsx_anx_adv_reg_t; 560215976Sjmallett 561215976Sjmallett/** 562215976Sjmallett * cvmx_pcs#_an#_ext_st_reg 563215976Sjmallett * 564215976Sjmallett * NOTE: 565215976Sjmallett * an_results_reg is don't care when AN_OVRD is set to 1. If AN_OVRD=0 and AN_CPT=1 566215976Sjmallett * the an_results_reg is valid. 567215976Sjmallett * 568215976Sjmallett * 569215976Sjmallett * PCS_AN_EXT_ST_REG = AN Extended Status Register15 570215976Sjmallett * as per IEEE802.3 Clause 22 571215976Sjmallett */ 572232812Sjmallettunion cvmx_pcsx_anx_ext_st_reg { 573215976Sjmallett uint64_t u64; 574232812Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s { 575232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 576215976Sjmallett uint64_t reserved_16_63 : 48; 577215976Sjmallett uint64_t thou_xfd : 1; /**< 1 means PHY is 1000BASE-X Full Dup capable */ 578215976Sjmallett uint64_t thou_xhd : 1; /**< 1 means PHY is 1000BASE-X Half Dup capable */ 579215976Sjmallett uint64_t thou_tfd : 1; /**< 1 means PHY is 1000BASE-T Full Dup capable */ 580215976Sjmallett uint64_t thou_thd : 1; /**< 1 means PHY is 1000BASE-T Half Dup capable */ 581215976Sjmallett uint64_t reserved_0_11 : 12; 582215976Sjmallett#else 583215976Sjmallett uint64_t reserved_0_11 : 12; 584215976Sjmallett uint64_t thou_thd : 1; 585215976Sjmallett uint64_t thou_tfd : 1; 586215976Sjmallett uint64_t thou_xhd : 1; 587215976Sjmallett uint64_t thou_xfd : 1; 588215976Sjmallett uint64_t reserved_16_63 : 48; 589215976Sjmallett#endif 590215976Sjmallett } s; 591215976Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cn52xx; 592215976Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1; 593215976Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cn56xx; 594215976Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1; 595232812Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cn61xx; 596215976Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cn63xx; 597215976Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1; 598232812Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cn66xx; 599232812Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cn68xx; 600232812Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1; 601232812Sjmallett struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx; 602215976Sjmallett}; 603215976Sjmalletttypedef union cvmx_pcsx_anx_ext_st_reg cvmx_pcsx_anx_ext_st_reg_t; 604215976Sjmallett 605215976Sjmallett/** 606215976Sjmallett * cvmx_pcs#_an#_lp_abil_reg 607215976Sjmallett * 608215976Sjmallett * PCS_AN_LP_ABIL_REG = AN link Partner Ability Register5 609215976Sjmallett * as per IEEE802.3 Clause 37 610215976Sjmallett */ 611232812Sjmallettunion cvmx_pcsx_anx_lp_abil_reg { 612215976Sjmallett uint64_t u64; 613232812Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s { 614232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 615215976Sjmallett uint64_t reserved_16_63 : 48; 616215976Sjmallett uint64_t np : 1; /**< 1=lp next page capable, 0=lp not next page capable */ 617215976Sjmallett uint64_t ack : 1; /**< 1=Acknowledgement received */ 618215976Sjmallett uint64_t rem_flt : 2; /**< [<13>,<12>] Link Partner's link status 619215976Sjmallett 0 0 Link OK 620215976Sjmallett 0 1 Offline 621215976Sjmallett 1 0 Link failure 622215976Sjmallett 1 1 AN Error */ 623215976Sjmallett uint64_t reserved_9_11 : 3; 624215976Sjmallett uint64_t pause : 2; /**< [<8>, <7>] Link Partner Pause setting 625215976Sjmallett 0 0 No Pause 626215976Sjmallett 0 1 Symmetric pause 627215976Sjmallett 1 0 Asymmetric Pause 628215976Sjmallett 1 1 Both symm and asymm pause to local device */ 629215976Sjmallett uint64_t hfd : 1; /**< 1 means link partner Half Duplex capable */ 630215976Sjmallett uint64_t fd : 1; /**< 1 means link partner Full Duplex capable */ 631215976Sjmallett uint64_t reserved_0_4 : 5; 632215976Sjmallett#else 633215976Sjmallett uint64_t reserved_0_4 : 5; 634215976Sjmallett uint64_t fd : 1; 635215976Sjmallett uint64_t hfd : 1; 636215976Sjmallett uint64_t pause : 2; 637215976Sjmallett uint64_t reserved_9_11 : 3; 638215976Sjmallett uint64_t rem_flt : 2; 639215976Sjmallett uint64_t ack : 1; 640215976Sjmallett uint64_t np : 1; 641215976Sjmallett uint64_t reserved_16_63 : 48; 642215976Sjmallett#endif 643215976Sjmallett } s; 644215976Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx; 645215976Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1; 646215976Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx; 647215976Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1; 648232812Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx; 649215976Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx; 650215976Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1; 651232812Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx; 652232812Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx; 653232812Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1; 654232812Sjmallett struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx; 655215976Sjmallett}; 656215976Sjmalletttypedef union cvmx_pcsx_anx_lp_abil_reg cvmx_pcsx_anx_lp_abil_reg_t; 657215976Sjmallett 658215976Sjmallett/** 659215976Sjmallett * cvmx_pcs#_an#_results_reg 660215976Sjmallett * 661215976Sjmallett * PCS_AN_RESULTS_REG = AN Results Register 662215976Sjmallett * 663215976Sjmallett */ 664232812Sjmallettunion cvmx_pcsx_anx_results_reg { 665215976Sjmallett uint64_t u64; 666232812Sjmallett struct cvmx_pcsx_anx_results_reg_s { 667232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 668215976Sjmallett uint64_t reserved_7_63 : 57; 669215976Sjmallett uint64_t pause : 2; /**< [<6>, <5>] PAUSE Selection (Don't care for SGMII) 670215976Sjmallett 0 0 Disable Pause, TX and RX 671215976Sjmallett 0 1 Enable pause frames RX only 672215976Sjmallett 1 0 Enable Pause frames TX only 673215976Sjmallett 1 1 Enable pause frames TX and RX */ 674215976Sjmallett uint64_t spd : 2; /**< [<4>, <3>] Link Speed Selection 675215976Sjmallett 0 0 10Mb/s 676215976Sjmallett 0 1 100Mb/s 677215976Sjmallett 1 0 1000Mb/s 678215976Sjmallett 1 1 NS */ 679215976Sjmallett uint64_t an_cpt : 1; /**< 1=AN Completed, 0=AN not completed or failed */ 680215976Sjmallett uint64_t dup : 1; /**< 1=Full Duplex, 0=Half Duplex */ 681215976Sjmallett uint64_t link_ok : 1; /**< 1=Link up(OK), 0=Link down */ 682215976Sjmallett#else 683215976Sjmallett uint64_t link_ok : 1; 684215976Sjmallett uint64_t dup : 1; 685215976Sjmallett uint64_t an_cpt : 1; 686215976Sjmallett uint64_t spd : 2; 687215976Sjmallett uint64_t pause : 2; 688215976Sjmallett uint64_t reserved_7_63 : 57; 689215976Sjmallett#endif 690215976Sjmallett } s; 691215976Sjmallett struct cvmx_pcsx_anx_results_reg_s cn52xx; 692215976Sjmallett struct cvmx_pcsx_anx_results_reg_s cn52xxp1; 693215976Sjmallett struct cvmx_pcsx_anx_results_reg_s cn56xx; 694215976Sjmallett struct cvmx_pcsx_anx_results_reg_s cn56xxp1; 695232812Sjmallett struct cvmx_pcsx_anx_results_reg_s cn61xx; 696215976Sjmallett struct cvmx_pcsx_anx_results_reg_s cn63xx; 697215976Sjmallett struct cvmx_pcsx_anx_results_reg_s cn63xxp1; 698232812Sjmallett struct cvmx_pcsx_anx_results_reg_s cn66xx; 699232812Sjmallett struct cvmx_pcsx_anx_results_reg_s cn68xx; 700232812Sjmallett struct cvmx_pcsx_anx_results_reg_s cn68xxp1; 701232812Sjmallett struct cvmx_pcsx_anx_results_reg_s cnf71xx; 702215976Sjmallett}; 703215976Sjmalletttypedef union cvmx_pcsx_anx_results_reg cvmx_pcsx_anx_results_reg_t; 704215976Sjmallett 705215976Sjmallett/** 706215976Sjmallett * cvmx_pcs#_int#_en_reg 707215976Sjmallett * 708215976Sjmallett * NOTE: RXERR and TXERR conditions to be discussed with Dan before finalising 709215976Sjmallett * DBG_SYNC interrupt fires when code group synchronization state machine makes a transition from 710215976Sjmallett * SYNC_ACQUIRED_1 state to SYNC_ACQUIRED_2 state(See IEEE 802.3-2005 figure 37-9). It is an indication that a bad code group 711215976Sjmallett * was received after code group synchronizaton was achieved. This interrupt should be disabled during normal link operation. 712215976Sjmallett * Use it as a debug help feature only. 713215976Sjmallett * 714215976Sjmallett * 715215976Sjmallett * PCS Interrupt Enable Register 716215976Sjmallett */ 717232812Sjmallettunion cvmx_pcsx_intx_en_reg { 718215976Sjmallett uint64_t u64; 719232812Sjmallett struct cvmx_pcsx_intx_en_reg_s { 720232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 721215976Sjmallett uint64_t reserved_13_63 : 51; 722215976Sjmallett uint64_t dbg_sync_en : 1; /**< Code Group sync failure debug help */ 723215976Sjmallett uint64_t dup : 1; /**< Enable duplex mode changed interrupt */ 724215976Sjmallett uint64_t sync_bad_en : 1; /**< Enable rx sync st machine in bad state interrupt */ 725215976Sjmallett uint64_t an_bad_en : 1; /**< Enable AN state machine bad state interrupt */ 726215976Sjmallett uint64_t rxlock_en : 1; /**< Enable rx code group sync/bit lock failure interrupt */ 727215976Sjmallett uint64_t rxbad_en : 1; /**< Enable rx state machine in bad state interrupt */ 728215976Sjmallett uint64_t rxerr_en : 1; /**< Enable RX error condition interrupt */ 729215976Sjmallett uint64_t txbad_en : 1; /**< Enable tx state machine in bad state interrupt */ 730215976Sjmallett uint64_t txfifo_en : 1; /**< Enable tx fifo overflow condition interrupt */ 731215976Sjmallett uint64_t txfifu_en : 1; /**< Enable tx fifo underflow condition intrrupt */ 732215976Sjmallett uint64_t an_err_en : 1; /**< Enable AN Error condition interrupt */ 733215976Sjmallett uint64_t xmit_en : 1; /**< Enable XMIT variable state change interrupt */ 734215976Sjmallett uint64_t lnkspd_en : 1; /**< Enable Link Speed has changed interrupt */ 735215976Sjmallett#else 736215976Sjmallett uint64_t lnkspd_en : 1; 737215976Sjmallett uint64_t xmit_en : 1; 738215976Sjmallett uint64_t an_err_en : 1; 739215976Sjmallett uint64_t txfifu_en : 1; 740215976Sjmallett uint64_t txfifo_en : 1; 741215976Sjmallett uint64_t txbad_en : 1; 742215976Sjmallett uint64_t rxerr_en : 1; 743215976Sjmallett uint64_t rxbad_en : 1; 744215976Sjmallett uint64_t rxlock_en : 1; 745215976Sjmallett uint64_t an_bad_en : 1; 746215976Sjmallett uint64_t sync_bad_en : 1; 747215976Sjmallett uint64_t dup : 1; 748215976Sjmallett uint64_t dbg_sync_en : 1; 749215976Sjmallett uint64_t reserved_13_63 : 51; 750215976Sjmallett#endif 751215976Sjmallett } s; 752232812Sjmallett struct cvmx_pcsx_intx_en_reg_cn52xx { 753232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 754215976Sjmallett uint64_t reserved_12_63 : 52; 755215976Sjmallett uint64_t dup : 1; /**< Enable duplex mode changed interrupt */ 756215976Sjmallett uint64_t sync_bad_en : 1; /**< Enable rx sync st machine in bad state interrupt */ 757215976Sjmallett uint64_t an_bad_en : 1; /**< Enable AN state machine bad state interrupt */ 758215976Sjmallett uint64_t rxlock_en : 1; /**< Enable rx code group sync/bit lock failure interrupt */ 759215976Sjmallett uint64_t rxbad_en : 1; /**< Enable rx state machine in bad state interrupt */ 760215976Sjmallett uint64_t rxerr_en : 1; /**< Enable RX error condition interrupt */ 761215976Sjmallett uint64_t txbad_en : 1; /**< Enable tx state machine in bad state interrupt */ 762215976Sjmallett uint64_t txfifo_en : 1; /**< Enable tx fifo overflow condition interrupt */ 763215976Sjmallett uint64_t txfifu_en : 1; /**< Enable tx fifo underflow condition intrrupt */ 764215976Sjmallett uint64_t an_err_en : 1; /**< Enable AN Error condition interrupt */ 765215976Sjmallett uint64_t xmit_en : 1; /**< Enable XMIT variable state change interrupt */ 766215976Sjmallett uint64_t lnkspd_en : 1; /**< Enable Link Speed has changed interrupt */ 767215976Sjmallett#else 768215976Sjmallett uint64_t lnkspd_en : 1; 769215976Sjmallett uint64_t xmit_en : 1; 770215976Sjmallett uint64_t an_err_en : 1; 771215976Sjmallett uint64_t txfifu_en : 1; 772215976Sjmallett uint64_t txfifo_en : 1; 773215976Sjmallett uint64_t txbad_en : 1; 774215976Sjmallett uint64_t rxerr_en : 1; 775215976Sjmallett uint64_t rxbad_en : 1; 776215976Sjmallett uint64_t rxlock_en : 1; 777215976Sjmallett uint64_t an_bad_en : 1; 778215976Sjmallett uint64_t sync_bad_en : 1; 779215976Sjmallett uint64_t dup : 1; 780215976Sjmallett uint64_t reserved_12_63 : 52; 781215976Sjmallett#endif 782215976Sjmallett } cn52xx; 783215976Sjmallett struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1; 784215976Sjmallett struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx; 785215976Sjmallett struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1; 786232812Sjmallett struct cvmx_pcsx_intx_en_reg_s cn61xx; 787215976Sjmallett struct cvmx_pcsx_intx_en_reg_s cn63xx; 788215976Sjmallett struct cvmx_pcsx_intx_en_reg_s cn63xxp1; 789232812Sjmallett struct cvmx_pcsx_intx_en_reg_s cn66xx; 790232812Sjmallett struct cvmx_pcsx_intx_en_reg_s cn68xx; 791232812Sjmallett struct cvmx_pcsx_intx_en_reg_s cn68xxp1; 792232812Sjmallett struct cvmx_pcsx_intx_en_reg_s cnf71xx; 793215976Sjmallett}; 794215976Sjmalletttypedef union cvmx_pcsx_intx_en_reg cvmx_pcsx_intx_en_reg_t; 795215976Sjmallett 796215976Sjmallett/** 797215976Sjmallett * cvmx_pcs#_int#_reg 798215976Sjmallett * 799215976Sjmallett * SGMII bit [12] is really a misnomer, it is a decode of pi_qlm_cfg pins to indicate SGMII or 1000Base-X modes. 800215976Sjmallett * 801215976Sjmallett * Note: MODE bit 802215976Sjmallett * When MODE=1, 1000Base-X mode is selected. Auto negotiation will follow IEEE 802.3 clause 37. 803215976Sjmallett * When MODE=0, SGMII mode is selected and the following note will apply. 804215976Sjmallett * Repeat note from SGM_AN_ADV register 805215976Sjmallett * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg 806215976Sjmallett * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1. 807215976Sjmallett * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results. 808215976Sjmallett * 809215976Sjmallett * PCS Interrupt Register 810215976Sjmallett */ 811232812Sjmallettunion cvmx_pcsx_intx_reg { 812215976Sjmallett uint64_t u64; 813232812Sjmallett struct cvmx_pcsx_intx_reg_s { 814232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 815215976Sjmallett uint64_t reserved_13_63 : 51; 816215976Sjmallett uint64_t dbg_sync : 1; /**< Code Group sync failure debug help */ 817215976Sjmallett uint64_t dup : 1; /**< Set whenever Duplex mode changes on the link */ 818215976Sjmallett uint64_t sync_bad : 1; /**< Set by HW whenever rx sync st machine reaches a bad 819215976Sjmallett state. Should never be set during normal operation */ 820215976Sjmallett uint64_t an_bad : 1; /**< Set by HW whenever AN st machine reaches a bad 821215976Sjmallett state. Should never be set during normal operation */ 822215976Sjmallett uint64_t rxlock : 1; /**< Set by HW whenever code group Sync or bit lock 823215976Sjmallett failure occurs 824215976Sjmallett Cannot fire in loopback1 mode */ 825215976Sjmallett uint64_t rxbad : 1; /**< Set by HW whenever rx st machine reaches a bad 826215976Sjmallett state. Should never be set during normal operation */ 827215976Sjmallett uint64_t rxerr : 1; /**< Set whenever RX receives a code group error in 828215976Sjmallett 10 bit to 8 bit decode logic 829215976Sjmallett Cannot fire in loopback1 mode */ 830215976Sjmallett uint64_t txbad : 1; /**< Set by HW whenever tx st machine reaches a bad 831215976Sjmallett state. Should never be set during normal operation */ 832215976Sjmallett uint64_t txfifo : 1; /**< Set whenever HW detects a TX fifo overflow 833215976Sjmallett condition */ 834215976Sjmallett uint64_t txfifu : 1; /**< Set whenever HW detects a TX fifo underflowflow 835215976Sjmallett condition */ 836215976Sjmallett uint64_t an_err : 1; /**< AN Error, AN resolution function failed */ 837215976Sjmallett uint64_t xmit : 1; /**< Set whenever HW detects a change in the XMIT 838215976Sjmallett variable. XMIT variable states are IDLE, CONFIG and 839215976Sjmallett DATA */ 840215976Sjmallett uint64_t lnkspd : 1; /**< Set by HW whenever Link Speed has changed */ 841215976Sjmallett#else 842215976Sjmallett uint64_t lnkspd : 1; 843215976Sjmallett uint64_t xmit : 1; 844215976Sjmallett uint64_t an_err : 1; 845215976Sjmallett uint64_t txfifu : 1; 846215976Sjmallett uint64_t txfifo : 1; 847215976Sjmallett uint64_t txbad : 1; 848215976Sjmallett uint64_t rxerr : 1; 849215976Sjmallett uint64_t rxbad : 1; 850215976Sjmallett uint64_t rxlock : 1; 851215976Sjmallett uint64_t an_bad : 1; 852215976Sjmallett uint64_t sync_bad : 1; 853215976Sjmallett uint64_t dup : 1; 854215976Sjmallett uint64_t dbg_sync : 1; 855215976Sjmallett uint64_t reserved_13_63 : 51; 856215976Sjmallett#endif 857215976Sjmallett } s; 858232812Sjmallett struct cvmx_pcsx_intx_reg_cn52xx { 859232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 860215976Sjmallett uint64_t reserved_12_63 : 52; 861215976Sjmallett uint64_t dup : 1; /**< Set whenever Duplex mode changes on the link */ 862215976Sjmallett uint64_t sync_bad : 1; /**< Set by HW whenever rx sync st machine reaches a bad 863215976Sjmallett state. Should never be set during normal operation */ 864215976Sjmallett uint64_t an_bad : 1; /**< Set by HW whenever AN st machine reaches a bad 865215976Sjmallett state. Should never be set during normal operation */ 866215976Sjmallett uint64_t rxlock : 1; /**< Set by HW whenever code group Sync or bit lock 867215976Sjmallett failure occurs 868215976Sjmallett Cannot fire in loopback1 mode */ 869215976Sjmallett uint64_t rxbad : 1; /**< Set by HW whenever rx st machine reaches a bad 870215976Sjmallett state. Should never be set during normal operation */ 871215976Sjmallett uint64_t rxerr : 1; /**< Set whenever RX receives a code group error in 872215976Sjmallett 10 bit to 8 bit decode logic 873215976Sjmallett Cannot fire in loopback1 mode */ 874215976Sjmallett uint64_t txbad : 1; /**< Set by HW whenever tx st machine reaches a bad 875215976Sjmallett state. Should never be set during normal operation */ 876215976Sjmallett uint64_t txfifo : 1; /**< Set whenever HW detects a TX fifo overflow 877215976Sjmallett condition */ 878215976Sjmallett uint64_t txfifu : 1; /**< Set whenever HW detects a TX fifo underflowflow 879215976Sjmallett condition */ 880215976Sjmallett uint64_t an_err : 1; /**< AN Error, AN resolution function failed */ 881215976Sjmallett uint64_t xmit : 1; /**< Set whenever HW detects a change in the XMIT 882215976Sjmallett variable. XMIT variable states are IDLE, CONFIG and 883215976Sjmallett DATA */ 884215976Sjmallett uint64_t lnkspd : 1; /**< Set by HW whenever Link Speed has changed */ 885215976Sjmallett#else 886215976Sjmallett uint64_t lnkspd : 1; 887215976Sjmallett uint64_t xmit : 1; 888215976Sjmallett uint64_t an_err : 1; 889215976Sjmallett uint64_t txfifu : 1; 890215976Sjmallett uint64_t txfifo : 1; 891215976Sjmallett uint64_t txbad : 1; 892215976Sjmallett uint64_t rxerr : 1; 893215976Sjmallett uint64_t rxbad : 1; 894215976Sjmallett uint64_t rxlock : 1; 895215976Sjmallett uint64_t an_bad : 1; 896215976Sjmallett uint64_t sync_bad : 1; 897215976Sjmallett uint64_t dup : 1; 898215976Sjmallett uint64_t reserved_12_63 : 52; 899215976Sjmallett#endif 900215976Sjmallett } cn52xx; 901215976Sjmallett struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1; 902215976Sjmallett struct cvmx_pcsx_intx_reg_cn52xx cn56xx; 903215976Sjmallett struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1; 904232812Sjmallett struct cvmx_pcsx_intx_reg_s cn61xx; 905215976Sjmallett struct cvmx_pcsx_intx_reg_s cn63xx; 906215976Sjmallett struct cvmx_pcsx_intx_reg_s cn63xxp1; 907232812Sjmallett struct cvmx_pcsx_intx_reg_s cn66xx; 908232812Sjmallett struct cvmx_pcsx_intx_reg_s cn68xx; 909232812Sjmallett struct cvmx_pcsx_intx_reg_s cn68xxp1; 910232812Sjmallett struct cvmx_pcsx_intx_reg_s cnf71xx; 911215976Sjmallett}; 912215976Sjmalletttypedef union cvmx_pcsx_intx_reg cvmx_pcsx_intx_reg_t; 913215976Sjmallett 914215976Sjmallett/** 915215976Sjmallett * cvmx_pcs#_link#_timer_count_reg 916215976Sjmallett * 917215976Sjmallett * PCS_LINK_TIMER_COUNT_REG = 1.6ms nominal link timer register 918215976Sjmallett * 919215976Sjmallett */ 920232812Sjmallettunion cvmx_pcsx_linkx_timer_count_reg { 921215976Sjmallett uint64_t u64; 922232812Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s { 923232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 924215976Sjmallett uint64_t reserved_16_63 : 48; 925215976Sjmallett uint64_t count : 16; /**< (core clock period times 1024) times "COUNT" should 926215976Sjmallett be 1.6ms(SGMII)/10ms(otherwise) which is the link 927215976Sjmallett timer used in auto negotiation. 928215976Sjmallett Reset assums a 700MHz eclk for 1.6ms link timer */ 929215976Sjmallett#else 930215976Sjmallett uint64_t count : 16; 931215976Sjmallett uint64_t reserved_16_63 : 48; 932215976Sjmallett#endif 933215976Sjmallett } s; 934215976Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx; 935215976Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1; 936215976Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx; 937215976Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1; 938232812Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx; 939215976Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx; 940215976Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1; 941232812Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx; 942232812Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx; 943232812Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1; 944232812Sjmallett struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx; 945215976Sjmallett}; 946215976Sjmalletttypedef union cvmx_pcsx_linkx_timer_count_reg cvmx_pcsx_linkx_timer_count_reg_t; 947215976Sjmallett 948215976Sjmallett/** 949215976Sjmallett * cvmx_pcs#_log_anl#_reg 950215976Sjmallett * 951215976Sjmallett * PCS Logic Analyzer Register 952215976Sjmallett * 953215976Sjmallett */ 954232812Sjmallettunion cvmx_pcsx_log_anlx_reg { 955215976Sjmallett uint64_t u64; 956232812Sjmallett struct cvmx_pcsx_log_anlx_reg_s { 957232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 958215976Sjmallett uint64_t reserved_4_63 : 60; 959215976Sjmallett uint64_t lafifovfl : 1; /**< 1=logic analyser fif overflowed during packetization 960215976Sjmallett Write 1 to clear this bit */ 961215976Sjmallett uint64_t la_en : 1; /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */ 962215976Sjmallett uint64_t pkt_sz : 2; /**< [<1>, <0>] Logic Analyzer Packet Size 963215976Sjmallett 0 0 Packet size 1k bytes 964215976Sjmallett 0 1 Packet size 4k bytes 965215976Sjmallett 1 0 Packet size 8k bytes 966215976Sjmallett 1 1 Packet size 16k bytes */ 967215976Sjmallett#else 968215976Sjmallett uint64_t pkt_sz : 2; 969215976Sjmallett uint64_t la_en : 1; 970215976Sjmallett uint64_t lafifovfl : 1; 971215976Sjmallett uint64_t reserved_4_63 : 60; 972215976Sjmallett#endif 973215976Sjmallett } s; 974215976Sjmallett struct cvmx_pcsx_log_anlx_reg_s cn52xx; 975215976Sjmallett struct cvmx_pcsx_log_anlx_reg_s cn52xxp1; 976215976Sjmallett struct cvmx_pcsx_log_anlx_reg_s cn56xx; 977215976Sjmallett struct cvmx_pcsx_log_anlx_reg_s cn56xxp1; 978232812Sjmallett struct cvmx_pcsx_log_anlx_reg_s cn61xx; 979215976Sjmallett struct cvmx_pcsx_log_anlx_reg_s cn63xx; 980215976Sjmallett struct cvmx_pcsx_log_anlx_reg_s cn63xxp1; 981232812Sjmallett struct cvmx_pcsx_log_anlx_reg_s cn66xx; 982232812Sjmallett struct cvmx_pcsx_log_anlx_reg_s cn68xx; 983232812Sjmallett struct cvmx_pcsx_log_anlx_reg_s cn68xxp1; 984232812Sjmallett struct cvmx_pcsx_log_anlx_reg_s cnf71xx; 985215976Sjmallett}; 986215976Sjmalletttypedef union cvmx_pcsx_log_anlx_reg cvmx_pcsx_log_anlx_reg_t; 987215976Sjmallett 988215976Sjmallett/** 989215976Sjmallett * cvmx_pcs#_misc#_ctl_reg 990215976Sjmallett * 991215976Sjmallett * SGMII Misc Control Register 992215976Sjmallett * 993215976Sjmallett */ 994232812Sjmallettunion cvmx_pcsx_miscx_ctl_reg { 995215976Sjmallett uint64_t u64; 996232812Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s { 997232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 998215976Sjmallett uint64_t reserved_13_63 : 51; 999215976Sjmallett uint64_t sgmii : 1; /**< 1=SGMII or 1000Base-X mode selected, 1000215976Sjmallett 0=XAUI or PCIE mode selected 1001215976Sjmallett This bit represents pi_qlm1/3_cfg[1:0] pin status */ 1002215976Sjmallett uint64_t gmxeno : 1; /**< GMX Enable override. When set to 1, forces GMX to 1003215976Sjmallett appear disabled. The enable/disable status of GMX 1004215976Sjmallett is checked only at SOP of every packet. */ 1005215976Sjmallett uint64_t loopbck2 : 1; /**< Sets external loopback mode to return rx data back 1006215976Sjmallett out via tx data path. 0=no loopback, 1=loopback */ 1007215976Sjmallett uint64_t mac_phy : 1; /**< 0=MAC, 1=PHY decides the tx_config_reg value to be 1008215976Sjmallett sent during auto negotiation. 1009215976Sjmallett See SGMII spec ENG-46158 from CISCO */ 1010215976Sjmallett uint64_t mode : 1; /**< 0=SGMII or 1= 1000 Base X */ 1011215976Sjmallett uint64_t an_ovrd : 1; /**< 0=disable, 1= enable over ride AN results 1012215976Sjmallett Auto negotiation is allowed to happen but the 1013215976Sjmallett results are ignored when set. Duplex and Link speed 1014215976Sjmallett values are set from the pcs_mr_ctrl reg */ 1015215976Sjmallett uint64_t samp_pt : 7; /**< Byte# in elongated frames for 10/100Mb/s operation 1016215976Sjmallett for data sampling on RX side in PCS. 1017215976Sjmallett Recommended values are 0x5 for 100Mb/s operation 1018215976Sjmallett and 0x32 for 10Mb/s operation. 1019215976Sjmallett For 10Mb/s operaton this field should be set to a 1020215976Sjmallett value less than 99 and greater than 0. If set out 1021215976Sjmallett of this range a value of 50 will be used for actual 1022215976Sjmallett sampling internally without affecting the CSR field 1023215976Sjmallett For 100Mb/s operation this field should be set to a 1024215976Sjmallett value less than 9 and greater than 0. If set out of 1025215976Sjmallett this range a value of 5 will be used for actual 1026215976Sjmallett sampling internally without affecting the CSR field */ 1027215976Sjmallett#else 1028215976Sjmallett uint64_t samp_pt : 7; 1029215976Sjmallett uint64_t an_ovrd : 1; 1030215976Sjmallett uint64_t mode : 1; 1031215976Sjmallett uint64_t mac_phy : 1; 1032215976Sjmallett uint64_t loopbck2 : 1; 1033215976Sjmallett uint64_t gmxeno : 1; 1034215976Sjmallett uint64_t sgmii : 1; 1035215976Sjmallett uint64_t reserved_13_63 : 51; 1036215976Sjmallett#endif 1037215976Sjmallett } s; 1038215976Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cn52xx; 1039215976Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1; 1040215976Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cn56xx; 1041215976Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1; 1042232812Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cn61xx; 1043215976Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cn63xx; 1044215976Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1; 1045232812Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cn66xx; 1046232812Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cn68xx; 1047232812Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1; 1048232812Sjmallett struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx; 1049215976Sjmallett}; 1050215976Sjmalletttypedef union cvmx_pcsx_miscx_ctl_reg cvmx_pcsx_miscx_ctl_reg_t; 1051215976Sjmallett 1052215976Sjmallett/** 1053215976Sjmallett * cvmx_pcs#_mr#_control_reg 1054215976Sjmallett * 1055215976Sjmallett * PCS_MR_CONTROL_REG = Control Register0 1056215976Sjmallett * 1057215976Sjmallett */ 1058232812Sjmallettunion cvmx_pcsx_mrx_control_reg { 1059215976Sjmallett uint64_t u64; 1060232812Sjmallett struct cvmx_pcsx_mrx_control_reg_s { 1061232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1062215976Sjmallett uint64_t reserved_16_63 : 48; 1063215976Sjmallett uint64_t reset : 1; /**< 1=SW Reset, the bit will return to 0 after pcs has 1064215976Sjmallett been reset. Takes 32 eclk cycles to reset pcs */ 1065215976Sjmallett uint64_t loopbck1 : 1; /**< 0=normal operation, 1=loopback. The loopback mode 1066215976Sjmallett will return(loopback) tx data from GMII tx back to 1067215976Sjmallett GMII rx interface. The loopback happens in the pcs 1068215976Sjmallett module. Auto Negotiation will be disabled even if 1069215976Sjmallett the AN_EN bit is set, during loopback */ 1070215976Sjmallett uint64_t spdlsb : 1; /**< See bit 6 description */ 1071215976Sjmallett uint64_t an_en : 1; /**< 1=AN Enable, 0=AN Disable */ 1072215976Sjmallett uint64_t pwr_dn : 1; /**< 1=Power Down(HW reset), 0=Normal operation */ 1073215976Sjmallett uint64_t reserved_10_10 : 1; 1074215976Sjmallett uint64_t rst_an : 1; /**< If bit 12 is set and bit 3 of status reg is 1 1075215976Sjmallett Auto Negotiation begins. Else,SW writes are ignored 1076215976Sjmallett and this bit remians at 0. This bit clears itself 1077215976Sjmallett to 0, when AN starts. */ 1078215976Sjmallett uint64_t dup : 1; /**< 1=full duplex, 0=half duplex; effective only if AN 1079215976Sjmallett disabled. If status register bits [15:9] and and 1080215976Sjmallett extended status reg bits [15:12] allow only one 1081215976Sjmallett duplex mode|, this bit will correspond to that 1082215976Sjmallett value and any attempt to write will be ignored. */ 1083215976Sjmallett uint64_t coltst : 1; /**< 1=enable COL signal test, 0=disable test 1084215976Sjmallett During COL test, the COL signal will reflect the 1085215976Sjmallett GMII TX_EN signal with less than 16BT delay */ 1086215976Sjmallett uint64_t spdmsb : 1; /**< [<6>, <13>]Link Speed effective only if AN disabled 1087215976Sjmallett 0 0 10Mb/s 1088215976Sjmallett 0 1 100Mb/s 1089215976Sjmallett 1 0 1000Mb/s 1090215976Sjmallett 1 1 NS */ 1091215976Sjmallett uint64_t uni : 1; /**< Unidirectional (Std 802.3-2005, Clause 66.2) 1092215976Sjmallett This bit will override the AN_EN bit and disable 1093215976Sjmallett auto-negotiation variable mr_an_enable, when set 1094215976Sjmallett Used in both 1000Base-X and SGMII modes */ 1095215976Sjmallett uint64_t reserved_0_4 : 5; 1096215976Sjmallett#else 1097215976Sjmallett uint64_t reserved_0_4 : 5; 1098215976Sjmallett uint64_t uni : 1; 1099215976Sjmallett uint64_t spdmsb : 1; 1100215976Sjmallett uint64_t coltst : 1; 1101215976Sjmallett uint64_t dup : 1; 1102215976Sjmallett uint64_t rst_an : 1; 1103215976Sjmallett uint64_t reserved_10_10 : 1; 1104215976Sjmallett uint64_t pwr_dn : 1; 1105215976Sjmallett uint64_t an_en : 1; 1106215976Sjmallett uint64_t spdlsb : 1; 1107215976Sjmallett uint64_t loopbck1 : 1; 1108215976Sjmallett uint64_t reset : 1; 1109215976Sjmallett uint64_t reserved_16_63 : 48; 1110215976Sjmallett#endif 1111215976Sjmallett } s; 1112215976Sjmallett struct cvmx_pcsx_mrx_control_reg_s cn52xx; 1113215976Sjmallett struct cvmx_pcsx_mrx_control_reg_s cn52xxp1; 1114215976Sjmallett struct cvmx_pcsx_mrx_control_reg_s cn56xx; 1115215976Sjmallett struct cvmx_pcsx_mrx_control_reg_s cn56xxp1; 1116232812Sjmallett struct cvmx_pcsx_mrx_control_reg_s cn61xx; 1117215976Sjmallett struct cvmx_pcsx_mrx_control_reg_s cn63xx; 1118215976Sjmallett struct cvmx_pcsx_mrx_control_reg_s cn63xxp1; 1119232812Sjmallett struct cvmx_pcsx_mrx_control_reg_s cn66xx; 1120232812Sjmallett struct cvmx_pcsx_mrx_control_reg_s cn68xx; 1121232812Sjmallett struct cvmx_pcsx_mrx_control_reg_s cn68xxp1; 1122232812Sjmallett struct cvmx_pcsx_mrx_control_reg_s cnf71xx; 1123215976Sjmallett}; 1124215976Sjmalletttypedef union cvmx_pcsx_mrx_control_reg cvmx_pcsx_mrx_control_reg_t; 1125215976Sjmallett 1126215976Sjmallett/** 1127215976Sjmallett * cvmx_pcs#_mr#_status_reg 1128215976Sjmallett * 1129215976Sjmallett * NOTE: 1130215976Sjmallett * Whenever AN_EN bit[12] is set, Auto negotiation is allowed to happen. The results 1131215976Sjmallett * of the auto negotiation process set the fields in the AN_RESULTS reg. When AN_EN is not set, 1132215976Sjmallett * AN_RESULTS reg is don't care. The effective SPD, DUP etc.. get their values 1133215976Sjmallett * from the pcs_mr_ctrl reg. 1134215976Sjmallett * 1135215976Sjmallett * PCS_MR_STATUS_REG = Status Register1 1136215976Sjmallett */ 1137232812Sjmallettunion cvmx_pcsx_mrx_status_reg { 1138215976Sjmallett uint64_t u64; 1139232812Sjmallett struct cvmx_pcsx_mrx_status_reg_s { 1140232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1141215976Sjmallett uint64_t reserved_16_63 : 48; 1142215976Sjmallett uint64_t hun_t4 : 1; /**< 1 means 100Base-T4 capable */ 1143215976Sjmallett uint64_t hun_xfd : 1; /**< 1 means 100Base-X Full Duplex */ 1144215976Sjmallett uint64_t hun_xhd : 1; /**< 1 means 100Base-X Half Duplex */ 1145215976Sjmallett uint64_t ten_fd : 1; /**< 1 means 10Mb/s Full Duplex */ 1146215976Sjmallett uint64_t ten_hd : 1; /**< 1 means 10Mb/s Half Duplex */ 1147215976Sjmallett uint64_t hun_t2fd : 1; /**< 1 means 100Base-T2 Full Duplex */ 1148215976Sjmallett uint64_t hun_t2hd : 1; /**< 1 means 100Base-T2 Half Duplex */ 1149215976Sjmallett uint64_t ext_st : 1; /**< 1 means extended status info in reg15 */ 1150215976Sjmallett uint64_t reserved_7_7 : 1; 1151215976Sjmallett uint64_t prb_sup : 1; /**< 1 means able to work without preamble bytes at the 1152215976Sjmallett beginning of frames. 0 means not able to accept 1153215976Sjmallett frames without preamble bytes preceding them. */ 1154215976Sjmallett uint64_t an_cpt : 1; /**< 1 means Auto Negotiation is complete and the 1155215976Sjmallett contents of the an_results_reg are valid. */ 1156215976Sjmallett uint64_t rm_flt : 1; /**< Set to 1 when remote flt condition occurs. This bit 1157215976Sjmallett implements a latching Hi behavior. It is cleared by 1158215976Sjmallett SW read of this reg or when reset bit [15] in 1159215976Sjmallett Control Reg is asserted. 1160215976Sjmallett See an adv reg[13:12] for flt conditions */ 1161215976Sjmallett uint64_t an_abil : 1; /**< 1 means Auto Negotiation capable */ 1162215976Sjmallett uint64_t lnk_st : 1; /**< 1=link up, 0=link down. Set during AN process 1163215976Sjmallett Set whenever XMIT=DATA. Latching Lo behavior when 1164215976Sjmallett link goes down. Link down value of the bit stays 1165215976Sjmallett low until SW reads the reg. */ 1166215976Sjmallett uint64_t reserved_1_1 : 1; 1167215976Sjmallett uint64_t extnd : 1; /**< Always 0, no extended capability regs present */ 1168215976Sjmallett#else 1169215976Sjmallett uint64_t extnd : 1; 1170215976Sjmallett uint64_t reserved_1_1 : 1; 1171215976Sjmallett uint64_t lnk_st : 1; 1172215976Sjmallett uint64_t an_abil : 1; 1173215976Sjmallett uint64_t rm_flt : 1; 1174215976Sjmallett uint64_t an_cpt : 1; 1175215976Sjmallett uint64_t prb_sup : 1; 1176215976Sjmallett uint64_t reserved_7_7 : 1; 1177215976Sjmallett uint64_t ext_st : 1; 1178215976Sjmallett uint64_t hun_t2hd : 1; 1179215976Sjmallett uint64_t hun_t2fd : 1; 1180215976Sjmallett uint64_t ten_hd : 1; 1181215976Sjmallett uint64_t ten_fd : 1; 1182215976Sjmallett uint64_t hun_xhd : 1; 1183215976Sjmallett uint64_t hun_xfd : 1; 1184215976Sjmallett uint64_t hun_t4 : 1; 1185215976Sjmallett uint64_t reserved_16_63 : 48; 1186215976Sjmallett#endif 1187215976Sjmallett } s; 1188215976Sjmallett struct cvmx_pcsx_mrx_status_reg_s cn52xx; 1189215976Sjmallett struct cvmx_pcsx_mrx_status_reg_s cn52xxp1; 1190215976Sjmallett struct cvmx_pcsx_mrx_status_reg_s cn56xx; 1191215976Sjmallett struct cvmx_pcsx_mrx_status_reg_s cn56xxp1; 1192232812Sjmallett struct cvmx_pcsx_mrx_status_reg_s cn61xx; 1193215976Sjmallett struct cvmx_pcsx_mrx_status_reg_s cn63xx; 1194215976Sjmallett struct cvmx_pcsx_mrx_status_reg_s cn63xxp1; 1195232812Sjmallett struct cvmx_pcsx_mrx_status_reg_s cn66xx; 1196232812Sjmallett struct cvmx_pcsx_mrx_status_reg_s cn68xx; 1197232812Sjmallett struct cvmx_pcsx_mrx_status_reg_s cn68xxp1; 1198232812Sjmallett struct cvmx_pcsx_mrx_status_reg_s cnf71xx; 1199215976Sjmallett}; 1200215976Sjmalletttypedef union cvmx_pcsx_mrx_status_reg cvmx_pcsx_mrx_status_reg_t; 1201215976Sjmallett 1202215976Sjmallett/** 1203215976Sjmallett * cvmx_pcs#_rx#_states_reg 1204215976Sjmallett * 1205215976Sjmallett * PCS_RX_STATES_REG = RX State Machines states register 1206215976Sjmallett * 1207215976Sjmallett */ 1208232812Sjmallettunion cvmx_pcsx_rxx_states_reg { 1209215976Sjmallett uint64_t u64; 1210232812Sjmallett struct cvmx_pcsx_rxx_states_reg_s { 1211232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1212215976Sjmallett uint64_t reserved_16_63 : 48; 1213215976Sjmallett uint64_t rx_bad : 1; /**< Receive state machine in an illegal state */ 1214215976Sjmallett uint64_t rx_st : 5; /**< Receive state machine state */ 1215215976Sjmallett uint64_t sync_bad : 1; /**< Receive synchronization SM in an illegal state */ 1216215976Sjmallett uint64_t sync : 4; /**< Receive synchronization SM state */ 1217215976Sjmallett uint64_t an_bad : 1; /**< Auto Negotiation state machine in an illegal state */ 1218215976Sjmallett uint64_t an_st : 4; /**< Auto Negotiation state machine state */ 1219215976Sjmallett#else 1220215976Sjmallett uint64_t an_st : 4; 1221215976Sjmallett uint64_t an_bad : 1; 1222215976Sjmallett uint64_t sync : 4; 1223215976Sjmallett uint64_t sync_bad : 1; 1224215976Sjmallett uint64_t rx_st : 5; 1225215976Sjmallett uint64_t rx_bad : 1; 1226215976Sjmallett uint64_t reserved_16_63 : 48; 1227215976Sjmallett#endif 1228215976Sjmallett } s; 1229215976Sjmallett struct cvmx_pcsx_rxx_states_reg_s cn52xx; 1230215976Sjmallett struct cvmx_pcsx_rxx_states_reg_s cn52xxp1; 1231215976Sjmallett struct cvmx_pcsx_rxx_states_reg_s cn56xx; 1232215976Sjmallett struct cvmx_pcsx_rxx_states_reg_s cn56xxp1; 1233232812Sjmallett struct cvmx_pcsx_rxx_states_reg_s cn61xx; 1234215976Sjmallett struct cvmx_pcsx_rxx_states_reg_s cn63xx; 1235215976Sjmallett struct cvmx_pcsx_rxx_states_reg_s cn63xxp1; 1236232812Sjmallett struct cvmx_pcsx_rxx_states_reg_s cn66xx; 1237232812Sjmallett struct cvmx_pcsx_rxx_states_reg_s cn68xx; 1238232812Sjmallett struct cvmx_pcsx_rxx_states_reg_s cn68xxp1; 1239232812Sjmallett struct cvmx_pcsx_rxx_states_reg_s cnf71xx; 1240215976Sjmallett}; 1241215976Sjmalletttypedef union cvmx_pcsx_rxx_states_reg cvmx_pcsx_rxx_states_reg_t; 1242215976Sjmallett 1243215976Sjmallett/** 1244215976Sjmallett * cvmx_pcs#_rx#_sync_reg 1245215976Sjmallett * 1246215976Sjmallett * Note: 1247215976Sjmallett * r_tx_rx_polarity_reg bit [2] will show correct polarity needed on the link receive path after code grp synchronization is achieved. 1248215976Sjmallett * 1249215976Sjmallett * 1250215976Sjmallett * PCS_RX_SYNC_REG = Code Group synchronization reg 1251215976Sjmallett */ 1252232812Sjmallettunion cvmx_pcsx_rxx_sync_reg { 1253215976Sjmallett uint64_t u64; 1254232812Sjmallett struct cvmx_pcsx_rxx_sync_reg_s { 1255232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1256215976Sjmallett uint64_t reserved_2_63 : 62; 1257215976Sjmallett uint64_t sync : 1; /**< 1 means code group synchronization achieved */ 1258215976Sjmallett uint64_t bit_lock : 1; /**< 1 means bit lock achieved */ 1259215976Sjmallett#else 1260215976Sjmallett uint64_t bit_lock : 1; 1261215976Sjmallett uint64_t sync : 1; 1262215976Sjmallett uint64_t reserved_2_63 : 62; 1263215976Sjmallett#endif 1264215976Sjmallett } s; 1265215976Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cn52xx; 1266215976Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1; 1267215976Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cn56xx; 1268215976Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1; 1269232812Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cn61xx; 1270215976Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cn63xx; 1271215976Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1; 1272232812Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cn66xx; 1273232812Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cn68xx; 1274232812Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1; 1275232812Sjmallett struct cvmx_pcsx_rxx_sync_reg_s cnf71xx; 1276215976Sjmallett}; 1277215976Sjmalletttypedef union cvmx_pcsx_rxx_sync_reg cvmx_pcsx_rxx_sync_reg_t; 1278215976Sjmallett 1279215976Sjmallett/** 1280215976Sjmallett * cvmx_pcs#_sgm#_an_adv_reg 1281215976Sjmallett * 1282215976Sjmallett * SGMII AN Advertisement Register (sent out as tx_config_reg) 1283215976Sjmallett * 1284215976Sjmallett */ 1285232812Sjmallettunion cvmx_pcsx_sgmx_an_adv_reg { 1286215976Sjmallett uint64_t u64; 1287232812Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s { 1288232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1289215976Sjmallett uint64_t reserved_16_63 : 48; 1290215976Sjmallett uint64_t link : 1; /**< Link status 1 Link Up, 0 Link Down */ 1291215976Sjmallett uint64_t ack : 1; /**< Auto negotiation ack */ 1292215976Sjmallett uint64_t reserved_13_13 : 1; 1293215976Sjmallett uint64_t dup : 1; /**< Duplex mode 1=full duplex, 0=half duplex */ 1294215976Sjmallett uint64_t speed : 2; /**< Link Speed 1295215976Sjmallett 0 0 10Mb/s 1296215976Sjmallett 0 1 100Mb/s 1297215976Sjmallett 1 0 1000Mb/s 1298215976Sjmallett 1 1 NS */ 1299215976Sjmallett uint64_t reserved_1_9 : 9; 1300215976Sjmallett uint64_t one : 1; /**< Always set to match tx_config_reg<0> */ 1301215976Sjmallett#else 1302215976Sjmallett uint64_t one : 1; 1303215976Sjmallett uint64_t reserved_1_9 : 9; 1304215976Sjmallett uint64_t speed : 2; 1305215976Sjmallett uint64_t dup : 1; 1306215976Sjmallett uint64_t reserved_13_13 : 1; 1307215976Sjmallett uint64_t ack : 1; 1308215976Sjmallett uint64_t link : 1; 1309215976Sjmallett uint64_t reserved_16_63 : 48; 1310215976Sjmallett#endif 1311215976Sjmallett } s; 1312215976Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx; 1313215976Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1; 1314215976Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx; 1315215976Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1; 1316232812Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx; 1317215976Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx; 1318215976Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1; 1319232812Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx; 1320232812Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx; 1321232812Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1; 1322232812Sjmallett struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx; 1323215976Sjmallett}; 1324215976Sjmalletttypedef union cvmx_pcsx_sgmx_an_adv_reg cvmx_pcsx_sgmx_an_adv_reg_t; 1325215976Sjmallett 1326215976Sjmallett/** 1327215976Sjmallett * cvmx_pcs#_sgm#_lp_adv_reg 1328215976Sjmallett * 1329215976Sjmallett * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg 1330215976Sjmallett * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1. 1331215976Sjmallett * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results. 1332215976Sjmallett * 1333215976Sjmallett * SGMII LP Advertisement Register (received as rx_config_reg) 1334215976Sjmallett */ 1335232812Sjmallettunion cvmx_pcsx_sgmx_lp_adv_reg { 1336215976Sjmallett uint64_t u64; 1337232812Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s { 1338232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1339215976Sjmallett uint64_t reserved_16_63 : 48; 1340215976Sjmallett uint64_t link : 1; /**< Link status 1 Link Up, 0 Link Down */ 1341215976Sjmallett uint64_t reserved_13_14 : 2; 1342215976Sjmallett uint64_t dup : 1; /**< Duplex mode 1=full duplex, 0=half duplex */ 1343215976Sjmallett uint64_t speed : 2; /**< Link Speed 1344215976Sjmallett 0 0 10Mb/s 1345215976Sjmallett 0 1 100Mb/s 1346215976Sjmallett 1 0 1000Mb/s 1347215976Sjmallett 1 1 NS */ 1348215976Sjmallett uint64_t reserved_1_9 : 9; 1349215976Sjmallett uint64_t one : 1; /**< Always set to match tx_config_reg<0> */ 1350215976Sjmallett#else 1351215976Sjmallett uint64_t one : 1; 1352215976Sjmallett uint64_t reserved_1_9 : 9; 1353215976Sjmallett uint64_t speed : 2; 1354215976Sjmallett uint64_t dup : 1; 1355215976Sjmallett uint64_t reserved_13_14 : 2; 1356215976Sjmallett uint64_t link : 1; 1357215976Sjmallett uint64_t reserved_16_63 : 48; 1358215976Sjmallett#endif 1359215976Sjmallett } s; 1360215976Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx; 1361215976Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1; 1362215976Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx; 1363215976Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1; 1364232812Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx; 1365215976Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx; 1366215976Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1; 1367232812Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx; 1368232812Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx; 1369232812Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1; 1370232812Sjmallett struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx; 1371215976Sjmallett}; 1372215976Sjmalletttypedef union cvmx_pcsx_sgmx_lp_adv_reg cvmx_pcsx_sgmx_lp_adv_reg_t; 1373215976Sjmallett 1374215976Sjmallett/** 1375215976Sjmallett * cvmx_pcs#_tx#_states_reg 1376215976Sjmallett * 1377215976Sjmallett * PCS_TX_STATES_REG = TX State Machines states register 1378215976Sjmallett * 1379215976Sjmallett */ 1380232812Sjmallettunion cvmx_pcsx_txx_states_reg { 1381215976Sjmallett uint64_t u64; 1382232812Sjmallett struct cvmx_pcsx_txx_states_reg_s { 1383232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1384215976Sjmallett uint64_t reserved_7_63 : 57; 1385215976Sjmallett uint64_t xmit : 2; /**< 0=undefined, 1=config, 2=idle, 3=data */ 1386215976Sjmallett uint64_t tx_bad : 1; /**< Xmit state machine in a bad state */ 1387215976Sjmallett uint64_t ord_st : 4; /**< Xmit ordered set state machine state */ 1388215976Sjmallett#else 1389215976Sjmallett uint64_t ord_st : 4; 1390215976Sjmallett uint64_t tx_bad : 1; 1391215976Sjmallett uint64_t xmit : 2; 1392215976Sjmallett uint64_t reserved_7_63 : 57; 1393215976Sjmallett#endif 1394215976Sjmallett } s; 1395215976Sjmallett struct cvmx_pcsx_txx_states_reg_s cn52xx; 1396215976Sjmallett struct cvmx_pcsx_txx_states_reg_s cn52xxp1; 1397215976Sjmallett struct cvmx_pcsx_txx_states_reg_s cn56xx; 1398215976Sjmallett struct cvmx_pcsx_txx_states_reg_s cn56xxp1; 1399232812Sjmallett struct cvmx_pcsx_txx_states_reg_s cn61xx; 1400215976Sjmallett struct cvmx_pcsx_txx_states_reg_s cn63xx; 1401215976Sjmallett struct cvmx_pcsx_txx_states_reg_s cn63xxp1; 1402232812Sjmallett struct cvmx_pcsx_txx_states_reg_s cn66xx; 1403232812Sjmallett struct cvmx_pcsx_txx_states_reg_s cn68xx; 1404232812Sjmallett struct cvmx_pcsx_txx_states_reg_s cn68xxp1; 1405232812Sjmallett struct cvmx_pcsx_txx_states_reg_s cnf71xx; 1406215976Sjmallett}; 1407215976Sjmalletttypedef union cvmx_pcsx_txx_states_reg cvmx_pcsx_txx_states_reg_t; 1408215976Sjmallett 1409215976Sjmallett/** 1410215976Sjmallett * cvmx_pcs#_tx_rx#_polarity_reg 1411215976Sjmallett * 1412215976Sjmallett * PCS_POLARITY_REG = TX_RX polarity reg 1413215976Sjmallett * 1414215976Sjmallett */ 1415232812Sjmallettunion cvmx_pcsx_tx_rxx_polarity_reg { 1416215976Sjmallett uint64_t u64; 1417232812Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s { 1418232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1419215976Sjmallett uint64_t reserved_4_63 : 60; 1420215976Sjmallett uint64_t rxovrd : 1; /**< When 0, <2> determines polarity 1421215976Sjmallett when 1, <1> determines polarity */ 1422215976Sjmallett uint64_t autorxpl : 1; /**< Auto RX polarity detected. 1=inverted, 0=normal 1423215976Sjmallett This bit always represents the correct rx polarity 1424215976Sjmallett setting needed for successful rx path operartion, 1425215976Sjmallett once a successful code group sync is obtained */ 1426215976Sjmallett uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 1427215976Sjmallett uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 1428215976Sjmallett#else 1429215976Sjmallett uint64_t txplrt : 1; 1430215976Sjmallett uint64_t rxplrt : 1; 1431215976Sjmallett uint64_t autorxpl : 1; 1432215976Sjmallett uint64_t rxovrd : 1; 1433215976Sjmallett uint64_t reserved_4_63 : 60; 1434215976Sjmallett#endif 1435215976Sjmallett } s; 1436215976Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx; 1437215976Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1; 1438215976Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx; 1439215976Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1; 1440232812Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx; 1441215976Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx; 1442215976Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1; 1443232812Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx; 1444232812Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx; 1445232812Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1; 1446232812Sjmallett struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx; 1447215976Sjmallett}; 1448215976Sjmalletttypedef union cvmx_pcsx_tx_rxx_polarity_reg cvmx_pcsx_tx_rxx_polarity_reg_t; 1449215976Sjmallett 1450215976Sjmallett#endif 1451