cvmx-pcmx-defs.h revision 215976
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pcmx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pcmx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PCMX_TYPEDEFS_H__ 53#define __CVMX_PCMX_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PCMX_DMA_CFG(unsigned long offset) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 62 cvmx_warn("CVMX_PCMX_DMA_CFG(%lu) is invalid on this chip\n", offset); 63 return CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384; 64} 65#else 66#define CVMX_PCMX_DMA_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010018ull) + ((offset) & 3) * 16384) 67#endif 68#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 69static inline uint64_t CVMX_PCMX_INT_ENA(unsigned long offset) 70{ 71 if (!( 72 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 73 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 74 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 75 cvmx_warn("CVMX_PCMX_INT_ENA(%lu) is invalid on this chip\n", offset); 76 return CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384; 77} 78#else 79#define CVMX_PCMX_INT_ENA(offset) (CVMX_ADD_IO_SEG(0x0001070000010020ull) + ((offset) & 3) * 16384) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82static inline uint64_t CVMX_PCMX_INT_SUM(unsigned long offset) 83{ 84 if (!( 85 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 86 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 87 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 88 cvmx_warn("CVMX_PCMX_INT_SUM(%lu) is invalid on this chip\n", offset); 89 return CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384; 90} 91#else 92#define CVMX_PCMX_INT_SUM(offset) (CVMX_ADD_IO_SEG(0x0001070000010028ull) + ((offset) & 3) * 16384) 93#endif 94#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 95static inline uint64_t CVMX_PCMX_RXADDR(unsigned long offset) 96{ 97 if (!( 98 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 99 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 100 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 101 cvmx_warn("CVMX_PCMX_RXADDR(%lu) is invalid on this chip\n", offset); 102 return CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384; 103} 104#else 105#define CVMX_PCMX_RXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010068ull) + ((offset) & 3) * 16384) 106#endif 107#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 108static inline uint64_t CVMX_PCMX_RXCNT(unsigned long offset) 109{ 110 if (!( 111 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 112 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 113 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 114 cvmx_warn("CVMX_PCMX_RXCNT(%lu) is invalid on this chip\n", offset); 115 return CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384; 116} 117#else 118#define CVMX_PCMX_RXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010060ull) + ((offset) & 3) * 16384) 119#endif 120#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121static inline uint64_t CVMX_PCMX_RXMSK0(unsigned long offset) 122{ 123 if (!( 124 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 125 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 126 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 127 cvmx_warn("CVMX_PCMX_RXMSK0(%lu) is invalid on this chip\n", offset); 128 return CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384; 129} 130#else 131#define CVMX_PCMX_RXMSK0(offset) (CVMX_ADD_IO_SEG(0x00010700000100C0ull) + ((offset) & 3) * 16384) 132#endif 133#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 134static inline uint64_t CVMX_PCMX_RXMSK1(unsigned long offset) 135{ 136 if (!( 137 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 138 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 139 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 140 cvmx_warn("CVMX_PCMX_RXMSK1(%lu) is invalid on this chip\n", offset); 141 return CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384; 142} 143#else 144#define CVMX_PCMX_RXMSK1(offset) (CVMX_ADD_IO_SEG(0x00010700000100C8ull) + ((offset) & 3) * 16384) 145#endif 146#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 147static inline uint64_t CVMX_PCMX_RXMSK2(unsigned long offset) 148{ 149 if (!( 150 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 151 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 152 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 153 cvmx_warn("CVMX_PCMX_RXMSK2(%lu) is invalid on this chip\n", offset); 154 return CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384; 155} 156#else 157#define CVMX_PCMX_RXMSK2(offset) (CVMX_ADD_IO_SEG(0x00010700000100D0ull) + ((offset) & 3) * 16384) 158#endif 159#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160static inline uint64_t CVMX_PCMX_RXMSK3(unsigned long offset) 161{ 162 if (!( 163 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 164 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 165 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 166 cvmx_warn("CVMX_PCMX_RXMSK3(%lu) is invalid on this chip\n", offset); 167 return CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384; 168} 169#else 170#define CVMX_PCMX_RXMSK3(offset) (CVMX_ADD_IO_SEG(0x00010700000100D8ull) + ((offset) & 3) * 16384) 171#endif 172#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 173static inline uint64_t CVMX_PCMX_RXMSK4(unsigned long offset) 174{ 175 if (!( 176 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 177 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 178 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 179 cvmx_warn("CVMX_PCMX_RXMSK4(%lu) is invalid on this chip\n", offset); 180 return CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384; 181} 182#else 183#define CVMX_PCMX_RXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100E0ull) + ((offset) & 3) * 16384) 184#endif 185#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 186static inline uint64_t CVMX_PCMX_RXMSK5(unsigned long offset) 187{ 188 if (!( 189 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 190 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 191 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 192 cvmx_warn("CVMX_PCMX_RXMSK5(%lu) is invalid on this chip\n", offset); 193 return CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384; 194} 195#else 196#define CVMX_PCMX_RXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100E8ull) + ((offset) & 3) * 16384) 197#endif 198#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199static inline uint64_t CVMX_PCMX_RXMSK6(unsigned long offset) 200{ 201 if (!( 202 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 203 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 204 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 205 cvmx_warn("CVMX_PCMX_RXMSK6(%lu) is invalid on this chip\n", offset); 206 return CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384; 207} 208#else 209#define CVMX_PCMX_RXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100F0ull) + ((offset) & 3) * 16384) 210#endif 211#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212static inline uint64_t CVMX_PCMX_RXMSK7(unsigned long offset) 213{ 214 if (!( 215 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 216 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 217 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 218 cvmx_warn("CVMX_PCMX_RXMSK7(%lu) is invalid on this chip\n", offset); 219 return CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384; 220} 221#else 222#define CVMX_PCMX_RXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100F8ull) + ((offset) & 3) * 16384) 223#endif 224#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225static inline uint64_t CVMX_PCMX_RXSTART(unsigned long offset) 226{ 227 if (!( 228 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 229 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 230 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 231 cvmx_warn("CVMX_PCMX_RXSTART(%lu) is invalid on this chip\n", offset); 232 return CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384; 233} 234#else 235#define CVMX_PCMX_RXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010058ull) + ((offset) & 3) * 16384) 236#endif 237#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 238static inline uint64_t CVMX_PCMX_TDM_CFG(unsigned long offset) 239{ 240 if (!( 241 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 242 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 243 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 244 cvmx_warn("CVMX_PCMX_TDM_CFG(%lu) is invalid on this chip\n", offset); 245 return CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384; 246} 247#else 248#define CVMX_PCMX_TDM_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010010ull) + ((offset) & 3) * 16384) 249#endif 250#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251static inline uint64_t CVMX_PCMX_TDM_DBG(unsigned long offset) 252{ 253 if (!( 254 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 255 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 256 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 257 cvmx_warn("CVMX_PCMX_TDM_DBG(%lu) is invalid on this chip\n", offset); 258 return CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384; 259} 260#else 261#define CVMX_PCMX_TDM_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010030ull) + ((offset) & 3) * 16384) 262#endif 263#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 264static inline uint64_t CVMX_PCMX_TXADDR(unsigned long offset) 265{ 266 if (!( 267 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 268 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 269 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 270 cvmx_warn("CVMX_PCMX_TXADDR(%lu) is invalid on this chip\n", offset); 271 return CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384; 272} 273#else 274#define CVMX_PCMX_TXADDR(offset) (CVMX_ADD_IO_SEG(0x0001070000010050ull) + ((offset) & 3) * 16384) 275#endif 276#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277static inline uint64_t CVMX_PCMX_TXCNT(unsigned long offset) 278{ 279 if (!( 280 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 281 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 282 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 283 cvmx_warn("CVMX_PCMX_TXCNT(%lu) is invalid on this chip\n", offset); 284 return CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384; 285} 286#else 287#define CVMX_PCMX_TXCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000010048ull) + ((offset) & 3) * 16384) 288#endif 289#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 290static inline uint64_t CVMX_PCMX_TXMSK0(unsigned long offset) 291{ 292 if (!( 293 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 294 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 295 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 296 cvmx_warn("CVMX_PCMX_TXMSK0(%lu) is invalid on this chip\n", offset); 297 return CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384; 298} 299#else 300#define CVMX_PCMX_TXMSK0(offset) (CVMX_ADD_IO_SEG(0x0001070000010080ull) + ((offset) & 3) * 16384) 301#endif 302#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 303static inline uint64_t CVMX_PCMX_TXMSK1(unsigned long offset) 304{ 305 if (!( 306 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 307 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 308 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 309 cvmx_warn("CVMX_PCMX_TXMSK1(%lu) is invalid on this chip\n", offset); 310 return CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384; 311} 312#else 313#define CVMX_PCMX_TXMSK1(offset) (CVMX_ADD_IO_SEG(0x0001070000010088ull) + ((offset) & 3) * 16384) 314#endif 315#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 316static inline uint64_t CVMX_PCMX_TXMSK2(unsigned long offset) 317{ 318 if (!( 319 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 320 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 321 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 322 cvmx_warn("CVMX_PCMX_TXMSK2(%lu) is invalid on this chip\n", offset); 323 return CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384; 324} 325#else 326#define CVMX_PCMX_TXMSK2(offset) (CVMX_ADD_IO_SEG(0x0001070000010090ull) + ((offset) & 3) * 16384) 327#endif 328#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 329static inline uint64_t CVMX_PCMX_TXMSK3(unsigned long offset) 330{ 331 if (!( 332 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 333 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 334 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 335 cvmx_warn("CVMX_PCMX_TXMSK3(%lu) is invalid on this chip\n", offset); 336 return CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384; 337} 338#else 339#define CVMX_PCMX_TXMSK3(offset) (CVMX_ADD_IO_SEG(0x0001070000010098ull) + ((offset) & 3) * 16384) 340#endif 341#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342static inline uint64_t CVMX_PCMX_TXMSK4(unsigned long offset) 343{ 344 if (!( 345 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 346 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 347 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 348 cvmx_warn("CVMX_PCMX_TXMSK4(%lu) is invalid on this chip\n", offset); 349 return CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384; 350} 351#else 352#define CVMX_PCMX_TXMSK4(offset) (CVMX_ADD_IO_SEG(0x00010700000100A0ull) + ((offset) & 3) * 16384) 353#endif 354#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 355static inline uint64_t CVMX_PCMX_TXMSK5(unsigned long offset) 356{ 357 if (!( 358 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 359 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 360 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 361 cvmx_warn("CVMX_PCMX_TXMSK5(%lu) is invalid on this chip\n", offset); 362 return CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384; 363} 364#else 365#define CVMX_PCMX_TXMSK5(offset) (CVMX_ADD_IO_SEG(0x00010700000100A8ull) + ((offset) & 3) * 16384) 366#endif 367#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 368static inline uint64_t CVMX_PCMX_TXMSK6(unsigned long offset) 369{ 370 if (!( 371 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 372 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 373 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 374 cvmx_warn("CVMX_PCMX_TXMSK6(%lu) is invalid on this chip\n", offset); 375 return CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384; 376} 377#else 378#define CVMX_PCMX_TXMSK6(offset) (CVMX_ADD_IO_SEG(0x00010700000100B0ull) + ((offset) & 3) * 16384) 379#endif 380#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 381static inline uint64_t CVMX_PCMX_TXMSK7(unsigned long offset) 382{ 383 if (!( 384 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 385 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 386 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 387 cvmx_warn("CVMX_PCMX_TXMSK7(%lu) is invalid on this chip\n", offset); 388 return CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384; 389} 390#else 391#define CVMX_PCMX_TXMSK7(offset) (CVMX_ADD_IO_SEG(0x00010700000100B8ull) + ((offset) & 3) * 16384) 392#endif 393#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 394static inline uint64_t CVMX_PCMX_TXSTART(unsigned long offset) 395{ 396 if (!( 397 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 398 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 399 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))))) 400 cvmx_warn("CVMX_PCMX_TXSTART(%lu) is invalid on this chip\n", offset); 401 return CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384; 402} 403#else 404#define CVMX_PCMX_TXSTART(offset) (CVMX_ADD_IO_SEG(0x0001070000010040ull) + ((offset) & 3) * 16384) 405#endif 406 407/** 408 * cvmx_pcm#_dma_cfg 409 */ 410union cvmx_pcmx_dma_cfg 411{ 412 uint64_t u64; 413 struct cvmx_pcmx_dma_cfg_s 414 { 415#if __BYTE_ORDER == __BIG_ENDIAN 416 uint64_t rdpend : 1; /**< If 0, no L2C read responses pending 417 1, L2C read responses are outstanding 418 NOTE: When restarting after stopping a running TDM 419 engine, software must wait for RDPEND to read 0 420 before writing PCMn_TDM_CFG[ENABLE] to a 1 */ 421 uint64_t reserved_54_62 : 9; 422 uint64_t rxslots : 10; /**< Number of 8-bit slots to receive per frame 423 (number of slots in a receive superframe) */ 424 uint64_t reserved_42_43 : 2; 425 uint64_t txslots : 10; /**< Number of 8-bit slots to transmit per frame 426 (number of slots in a transmit superframe) */ 427 uint64_t reserved_30_31 : 2; 428 uint64_t rxst : 10; /**< Number of frame writes for interrupt */ 429 uint64_t reserved_19_19 : 1; 430 uint64_t useldt : 1; /**< If 0, use LDI command to read from L2C 431 1, use LDT command to read from L2C */ 432 uint64_t txrd : 10; /**< Number of frame reads for interrupt */ 433 uint64_t fetchsiz : 4; /**< FETCHSIZ+1 timeslots are read when threshold is 434 reached. */ 435 uint64_t thresh : 4; /**< If number of bytes remaining in the DMA fifo is <= 436 THRESH, initiate a fetch of timeslot data from the 437 transmit memory region. 438 NOTE: there are only 16B of buffer for each engine 439 so the seetings for FETCHSIZ and THRESH must be 440 such that the buffer will not be overrun: 441 442 THRESH + min(FETCHSIZ + 1,TXSLOTS) MUST BE <= 16 */ 443#else 444 uint64_t thresh : 4; 445 uint64_t fetchsiz : 4; 446 uint64_t txrd : 10; 447 uint64_t useldt : 1; 448 uint64_t reserved_19_19 : 1; 449 uint64_t rxst : 10; 450 uint64_t reserved_30_31 : 2; 451 uint64_t txslots : 10; 452 uint64_t reserved_42_43 : 2; 453 uint64_t rxslots : 10; 454 uint64_t reserved_54_62 : 9; 455 uint64_t rdpend : 1; 456#endif 457 } s; 458 struct cvmx_pcmx_dma_cfg_s cn30xx; 459 struct cvmx_pcmx_dma_cfg_s cn31xx; 460 struct cvmx_pcmx_dma_cfg_s cn50xx; 461}; 462typedef union cvmx_pcmx_dma_cfg cvmx_pcmx_dma_cfg_t; 463 464/** 465 * cvmx_pcm#_int_ena 466 */ 467union cvmx_pcmx_int_ena 468{ 469 uint64_t u64; 470 struct cvmx_pcmx_int_ena_s 471 { 472#if __BYTE_ORDER == __BIG_ENDIAN 473 uint64_t reserved_8_63 : 56; 474 uint64_t rxovf : 1; /**< Enable interrupt if RX byte overflows */ 475 uint64_t txempty : 1; /**< Enable interrupt on TX byte empty */ 476 uint64_t txrd : 1; /**< Enable DMA engine frame read interrupts */ 477 uint64_t txwrap : 1; /**< Enable TX region wrap interrupts */ 478 uint64_t rxst : 1; /**< Enable DMA engine frame store interrupts */ 479 uint64_t rxwrap : 1; /**< Enable RX region wrap interrupts */ 480 uint64_t fsyncextra : 1; /**< Enable FSYNC extra interrupts 481 NOTE: FSYNCEXTRA errors are defined as an FSYNC 482 found in the "wrong" spot of a frame given the 483 programming of PCMn_CLK_CFG[NUMSLOTS] and 484 PCMn_CLK_CFG[EXTRABIT]. */ 485 uint64_t fsyncmissed : 1; /**< Enable FSYNC missed interrupts 486 NOTE: FSYNCMISSED errors are defined as an FSYNC 487 missing from the correct spot in a frame given 488 the programming of PCMn_CLK_CFG[NUMSLOTS] and 489 PCMn_CLK_CFG[EXTRABIT]. */ 490#else 491 uint64_t fsyncmissed : 1; 492 uint64_t fsyncextra : 1; 493 uint64_t rxwrap : 1; 494 uint64_t rxst : 1; 495 uint64_t txwrap : 1; 496 uint64_t txrd : 1; 497 uint64_t txempty : 1; 498 uint64_t rxovf : 1; 499 uint64_t reserved_8_63 : 56; 500#endif 501 } s; 502 struct cvmx_pcmx_int_ena_s cn30xx; 503 struct cvmx_pcmx_int_ena_s cn31xx; 504 struct cvmx_pcmx_int_ena_s cn50xx; 505}; 506typedef union cvmx_pcmx_int_ena cvmx_pcmx_int_ena_t; 507 508/** 509 * cvmx_pcm#_int_sum 510 */ 511union cvmx_pcmx_int_sum 512{ 513 uint64_t u64; 514 struct cvmx_pcmx_int_sum_s 515 { 516#if __BYTE_ORDER == __BIG_ENDIAN 517 uint64_t reserved_8_63 : 56; 518 uint64_t rxovf : 1; /**< RX byte overflowed */ 519 uint64_t txempty : 1; /**< TX byte was empty when sampled */ 520 uint64_t txrd : 1; /**< DMA engine frame read interrupt occurred */ 521 uint64_t txwrap : 1; /**< TX region wrap interrupt occurred */ 522 uint64_t rxst : 1; /**< DMA engine frame store interrupt occurred */ 523 uint64_t rxwrap : 1; /**< RX region wrap interrupt occurred */ 524 uint64_t fsyncextra : 1; /**< FSYNC extra interrupt occurred */ 525 uint64_t fsyncmissed : 1; /**< FSYNC missed interrupt occurred */ 526#else 527 uint64_t fsyncmissed : 1; 528 uint64_t fsyncextra : 1; 529 uint64_t rxwrap : 1; 530 uint64_t rxst : 1; 531 uint64_t txwrap : 1; 532 uint64_t txrd : 1; 533 uint64_t txempty : 1; 534 uint64_t rxovf : 1; 535 uint64_t reserved_8_63 : 56; 536#endif 537 } s; 538 struct cvmx_pcmx_int_sum_s cn30xx; 539 struct cvmx_pcmx_int_sum_s cn31xx; 540 struct cvmx_pcmx_int_sum_s cn50xx; 541}; 542typedef union cvmx_pcmx_int_sum cvmx_pcmx_int_sum_t; 543 544/** 545 * cvmx_pcm#_rxaddr 546 */ 547union cvmx_pcmx_rxaddr 548{ 549 uint64_t u64; 550 struct cvmx_pcmx_rxaddr_s 551 { 552#if __BYTE_ORDER == __BIG_ENDIAN 553 uint64_t reserved_36_63 : 28; 554 uint64_t addr : 36; /**< Address of the next write to the receive memory 555 region */ 556#else 557 uint64_t addr : 36; 558 uint64_t reserved_36_63 : 28; 559#endif 560 } s; 561 struct cvmx_pcmx_rxaddr_s cn30xx; 562 struct cvmx_pcmx_rxaddr_s cn31xx; 563 struct cvmx_pcmx_rxaddr_s cn50xx; 564}; 565typedef union cvmx_pcmx_rxaddr cvmx_pcmx_rxaddr_t; 566 567/** 568 * cvmx_pcm#_rxcnt 569 */ 570union cvmx_pcmx_rxcnt 571{ 572 uint64_t u64; 573 struct cvmx_pcmx_rxcnt_s 574 { 575#if __BYTE_ORDER == __BIG_ENDIAN 576 uint64_t reserved_16_63 : 48; 577 uint64_t cnt : 16; /**< Number of superframes in receive memory region */ 578#else 579 uint64_t cnt : 16; 580 uint64_t reserved_16_63 : 48; 581#endif 582 } s; 583 struct cvmx_pcmx_rxcnt_s cn30xx; 584 struct cvmx_pcmx_rxcnt_s cn31xx; 585 struct cvmx_pcmx_rxcnt_s cn50xx; 586}; 587typedef union cvmx_pcmx_rxcnt cvmx_pcmx_rxcnt_t; 588 589/** 590 * cvmx_pcm#_rxmsk0 591 */ 592union cvmx_pcmx_rxmsk0 593{ 594 uint64_t u64; 595 struct cvmx_pcmx_rxmsk0_s 596 { 597#if __BYTE_ORDER == __BIG_ENDIAN 598 uint64_t mask : 64; /**< Receive mask bits for slots 63 to 0 599 (1 means transmit, 0 means don't transmit) */ 600#else 601 uint64_t mask : 64; 602#endif 603 } s; 604 struct cvmx_pcmx_rxmsk0_s cn30xx; 605 struct cvmx_pcmx_rxmsk0_s cn31xx; 606 struct cvmx_pcmx_rxmsk0_s cn50xx; 607}; 608typedef union cvmx_pcmx_rxmsk0 cvmx_pcmx_rxmsk0_t; 609 610/** 611 * cvmx_pcm#_rxmsk1 612 */ 613union cvmx_pcmx_rxmsk1 614{ 615 uint64_t u64; 616 struct cvmx_pcmx_rxmsk1_s 617 { 618#if __BYTE_ORDER == __BIG_ENDIAN 619 uint64_t mask : 64; /**< Receive mask bits for slots 127 to 64 620 (1 means transmit, 0 means don't transmit) */ 621#else 622 uint64_t mask : 64; 623#endif 624 } s; 625 struct cvmx_pcmx_rxmsk1_s cn30xx; 626 struct cvmx_pcmx_rxmsk1_s cn31xx; 627 struct cvmx_pcmx_rxmsk1_s cn50xx; 628}; 629typedef union cvmx_pcmx_rxmsk1 cvmx_pcmx_rxmsk1_t; 630 631/** 632 * cvmx_pcm#_rxmsk2 633 */ 634union cvmx_pcmx_rxmsk2 635{ 636 uint64_t u64; 637 struct cvmx_pcmx_rxmsk2_s 638 { 639#if __BYTE_ORDER == __BIG_ENDIAN 640 uint64_t mask : 64; /**< Receive mask bits for slots 191 to 128 641 (1 means transmit, 0 means don't transmit) */ 642#else 643 uint64_t mask : 64; 644#endif 645 } s; 646 struct cvmx_pcmx_rxmsk2_s cn30xx; 647 struct cvmx_pcmx_rxmsk2_s cn31xx; 648 struct cvmx_pcmx_rxmsk2_s cn50xx; 649}; 650typedef union cvmx_pcmx_rxmsk2 cvmx_pcmx_rxmsk2_t; 651 652/** 653 * cvmx_pcm#_rxmsk3 654 */ 655union cvmx_pcmx_rxmsk3 656{ 657 uint64_t u64; 658 struct cvmx_pcmx_rxmsk3_s 659 { 660#if __BYTE_ORDER == __BIG_ENDIAN 661 uint64_t mask : 64; /**< Receive mask bits for slots 255 to 192 662 (1 means transmit, 0 means don't transmit) */ 663#else 664 uint64_t mask : 64; 665#endif 666 } s; 667 struct cvmx_pcmx_rxmsk3_s cn30xx; 668 struct cvmx_pcmx_rxmsk3_s cn31xx; 669 struct cvmx_pcmx_rxmsk3_s cn50xx; 670}; 671typedef union cvmx_pcmx_rxmsk3 cvmx_pcmx_rxmsk3_t; 672 673/** 674 * cvmx_pcm#_rxmsk4 675 */ 676union cvmx_pcmx_rxmsk4 677{ 678 uint64_t u64; 679 struct cvmx_pcmx_rxmsk4_s 680 { 681#if __BYTE_ORDER == __BIG_ENDIAN 682 uint64_t mask : 64; /**< Receive mask bits for slots 319 to 256 683 (1 means transmit, 0 means don't transmit) */ 684#else 685 uint64_t mask : 64; 686#endif 687 } s; 688 struct cvmx_pcmx_rxmsk4_s cn30xx; 689 struct cvmx_pcmx_rxmsk4_s cn31xx; 690 struct cvmx_pcmx_rxmsk4_s cn50xx; 691}; 692typedef union cvmx_pcmx_rxmsk4 cvmx_pcmx_rxmsk4_t; 693 694/** 695 * cvmx_pcm#_rxmsk5 696 */ 697union cvmx_pcmx_rxmsk5 698{ 699 uint64_t u64; 700 struct cvmx_pcmx_rxmsk5_s 701 { 702#if __BYTE_ORDER == __BIG_ENDIAN 703 uint64_t mask : 64; /**< Receive mask bits for slots 383 to 320 704 (1 means transmit, 0 means don't transmit) */ 705#else 706 uint64_t mask : 64; 707#endif 708 } s; 709 struct cvmx_pcmx_rxmsk5_s cn30xx; 710 struct cvmx_pcmx_rxmsk5_s cn31xx; 711 struct cvmx_pcmx_rxmsk5_s cn50xx; 712}; 713typedef union cvmx_pcmx_rxmsk5 cvmx_pcmx_rxmsk5_t; 714 715/** 716 * cvmx_pcm#_rxmsk6 717 */ 718union cvmx_pcmx_rxmsk6 719{ 720 uint64_t u64; 721 struct cvmx_pcmx_rxmsk6_s 722 { 723#if __BYTE_ORDER == __BIG_ENDIAN 724 uint64_t mask : 64; /**< Receive mask bits for slots 447 to 384 725 (1 means transmit, 0 means don't transmit) */ 726#else 727 uint64_t mask : 64; 728#endif 729 } s; 730 struct cvmx_pcmx_rxmsk6_s cn30xx; 731 struct cvmx_pcmx_rxmsk6_s cn31xx; 732 struct cvmx_pcmx_rxmsk6_s cn50xx; 733}; 734typedef union cvmx_pcmx_rxmsk6 cvmx_pcmx_rxmsk6_t; 735 736/** 737 * cvmx_pcm#_rxmsk7 738 */ 739union cvmx_pcmx_rxmsk7 740{ 741 uint64_t u64; 742 struct cvmx_pcmx_rxmsk7_s 743 { 744#if __BYTE_ORDER == __BIG_ENDIAN 745 uint64_t mask : 64; /**< Receive mask bits for slots 511 to 448 746 (1 means transmit, 0 means don't transmit) */ 747#else 748 uint64_t mask : 64; 749#endif 750 } s; 751 struct cvmx_pcmx_rxmsk7_s cn30xx; 752 struct cvmx_pcmx_rxmsk7_s cn31xx; 753 struct cvmx_pcmx_rxmsk7_s cn50xx; 754}; 755typedef union cvmx_pcmx_rxmsk7 cvmx_pcmx_rxmsk7_t; 756 757/** 758 * cvmx_pcm#_rxstart 759 */ 760union cvmx_pcmx_rxstart 761{ 762 uint64_t u64; 763 struct cvmx_pcmx_rxstart_s 764 { 765#if __BYTE_ORDER == __BIG_ENDIAN 766 uint64_t reserved_36_63 : 28; 767 uint64_t addr : 33; /**< Starting address for the receive memory region */ 768 uint64_t reserved_0_2 : 3; 769#else 770 uint64_t reserved_0_2 : 3; 771 uint64_t addr : 33; 772 uint64_t reserved_36_63 : 28; 773#endif 774 } s; 775 struct cvmx_pcmx_rxstart_s cn30xx; 776 struct cvmx_pcmx_rxstart_s cn31xx; 777 struct cvmx_pcmx_rxstart_s cn50xx; 778}; 779typedef union cvmx_pcmx_rxstart cvmx_pcmx_rxstart_t; 780 781/** 782 * cvmx_pcm#_tdm_cfg 783 */ 784union cvmx_pcmx_tdm_cfg 785{ 786 uint64_t u64; 787 struct cvmx_pcmx_tdm_cfg_s 788 { 789#if __BYTE_ORDER == __BIG_ENDIAN 790 uint64_t drvtim : 16; /**< Number of ECLKs from start of bit time to stop 791 driving last bit of timeslot (if not driving next 792 timeslot) */ 793 uint64_t samppt : 16; /**< Number of ECLKs from start of bit time to sample 794 data bit. */ 795 uint64_t reserved_3_31 : 29; 796 uint64_t lsbfirst : 1; /**< If 0, shift/receive MSB first 797 1, shift/receive LSB first */ 798 uint64_t useclk1 : 1; /**< If 0, this PCM is based on BCLK/FSYNC0 799 1, this PCM is based on BCLK/FSYNC1 */ 800 uint64_t enable : 1; /**< If 1, PCM is enabled, otherwise pins are GPIOs 801 NOTE: when TDM is disabled by detection of an 802 FSYNC error all transmission and reception is 803 halted. In addition, PCMn_TX/RXADDR are updated 804 to point to the position at which the error was 805 detected. */ 806#else 807 uint64_t enable : 1; 808 uint64_t useclk1 : 1; 809 uint64_t lsbfirst : 1; 810 uint64_t reserved_3_31 : 29; 811 uint64_t samppt : 16; 812 uint64_t drvtim : 16; 813#endif 814 } s; 815 struct cvmx_pcmx_tdm_cfg_s cn30xx; 816 struct cvmx_pcmx_tdm_cfg_s cn31xx; 817 struct cvmx_pcmx_tdm_cfg_s cn50xx; 818}; 819typedef union cvmx_pcmx_tdm_cfg cvmx_pcmx_tdm_cfg_t; 820 821/** 822 * cvmx_pcm#_tdm_dbg 823 */ 824union cvmx_pcmx_tdm_dbg 825{ 826 uint64_t u64; 827 struct cvmx_pcmx_tdm_dbg_s 828 { 829#if __BYTE_ORDER == __BIG_ENDIAN 830 uint64_t debuginfo : 64; /**< Miscellaneous debug information */ 831#else 832 uint64_t debuginfo : 64; 833#endif 834 } s; 835 struct cvmx_pcmx_tdm_dbg_s cn30xx; 836 struct cvmx_pcmx_tdm_dbg_s cn31xx; 837 struct cvmx_pcmx_tdm_dbg_s cn50xx; 838}; 839typedef union cvmx_pcmx_tdm_dbg cvmx_pcmx_tdm_dbg_t; 840 841/** 842 * cvmx_pcm#_txaddr 843 */ 844union cvmx_pcmx_txaddr 845{ 846 uint64_t u64; 847 struct cvmx_pcmx_txaddr_s 848 { 849#if __BYTE_ORDER == __BIG_ENDIAN 850 uint64_t reserved_36_63 : 28; 851 uint64_t addr : 33; /**< Address of the next read from the transmit memory 852 region */ 853 uint64_t fram : 3; /**< Frame offset 854 NOTE: this is used to extract the correct byte from 855 each 64b word read from the transmit memory region */ 856#else 857 uint64_t fram : 3; 858 uint64_t addr : 33; 859 uint64_t reserved_36_63 : 28; 860#endif 861 } s; 862 struct cvmx_pcmx_txaddr_s cn30xx; 863 struct cvmx_pcmx_txaddr_s cn31xx; 864 struct cvmx_pcmx_txaddr_s cn50xx; 865}; 866typedef union cvmx_pcmx_txaddr cvmx_pcmx_txaddr_t; 867 868/** 869 * cvmx_pcm#_txcnt 870 */ 871union cvmx_pcmx_txcnt 872{ 873 uint64_t u64; 874 struct cvmx_pcmx_txcnt_s 875 { 876#if __BYTE_ORDER == __BIG_ENDIAN 877 uint64_t reserved_16_63 : 48; 878 uint64_t cnt : 16; /**< Number of superframes in transmit memory region */ 879#else 880 uint64_t cnt : 16; 881 uint64_t reserved_16_63 : 48; 882#endif 883 } s; 884 struct cvmx_pcmx_txcnt_s cn30xx; 885 struct cvmx_pcmx_txcnt_s cn31xx; 886 struct cvmx_pcmx_txcnt_s cn50xx; 887}; 888typedef union cvmx_pcmx_txcnt cvmx_pcmx_txcnt_t; 889 890/** 891 * cvmx_pcm#_txmsk0 892 */ 893union cvmx_pcmx_txmsk0 894{ 895 uint64_t u64; 896 struct cvmx_pcmx_txmsk0_s 897 { 898#if __BYTE_ORDER == __BIG_ENDIAN 899 uint64_t mask : 64; /**< Transmit mask bits for slots 63 to 0 900 (1 means transmit, 0 means don't transmit) */ 901#else 902 uint64_t mask : 64; 903#endif 904 } s; 905 struct cvmx_pcmx_txmsk0_s cn30xx; 906 struct cvmx_pcmx_txmsk0_s cn31xx; 907 struct cvmx_pcmx_txmsk0_s cn50xx; 908}; 909typedef union cvmx_pcmx_txmsk0 cvmx_pcmx_txmsk0_t; 910 911/** 912 * cvmx_pcm#_txmsk1 913 */ 914union cvmx_pcmx_txmsk1 915{ 916 uint64_t u64; 917 struct cvmx_pcmx_txmsk1_s 918 { 919#if __BYTE_ORDER == __BIG_ENDIAN 920 uint64_t mask : 64; /**< Transmit mask bits for slots 127 to 64 921 (1 means transmit, 0 means don't transmit) */ 922#else 923 uint64_t mask : 64; 924#endif 925 } s; 926 struct cvmx_pcmx_txmsk1_s cn30xx; 927 struct cvmx_pcmx_txmsk1_s cn31xx; 928 struct cvmx_pcmx_txmsk1_s cn50xx; 929}; 930typedef union cvmx_pcmx_txmsk1 cvmx_pcmx_txmsk1_t; 931 932/** 933 * cvmx_pcm#_txmsk2 934 */ 935union cvmx_pcmx_txmsk2 936{ 937 uint64_t u64; 938 struct cvmx_pcmx_txmsk2_s 939 { 940#if __BYTE_ORDER == __BIG_ENDIAN 941 uint64_t mask : 64; /**< Transmit mask bits for slots 191 to 128 942 (1 means transmit, 0 means don't transmit) */ 943#else 944 uint64_t mask : 64; 945#endif 946 } s; 947 struct cvmx_pcmx_txmsk2_s cn30xx; 948 struct cvmx_pcmx_txmsk2_s cn31xx; 949 struct cvmx_pcmx_txmsk2_s cn50xx; 950}; 951typedef union cvmx_pcmx_txmsk2 cvmx_pcmx_txmsk2_t; 952 953/** 954 * cvmx_pcm#_txmsk3 955 */ 956union cvmx_pcmx_txmsk3 957{ 958 uint64_t u64; 959 struct cvmx_pcmx_txmsk3_s 960 { 961#if __BYTE_ORDER == __BIG_ENDIAN 962 uint64_t mask : 64; /**< Transmit mask bits for slots 255 to 192 963 (1 means transmit, 0 means don't transmit) */ 964#else 965 uint64_t mask : 64; 966#endif 967 } s; 968 struct cvmx_pcmx_txmsk3_s cn30xx; 969 struct cvmx_pcmx_txmsk3_s cn31xx; 970 struct cvmx_pcmx_txmsk3_s cn50xx; 971}; 972typedef union cvmx_pcmx_txmsk3 cvmx_pcmx_txmsk3_t; 973 974/** 975 * cvmx_pcm#_txmsk4 976 */ 977union cvmx_pcmx_txmsk4 978{ 979 uint64_t u64; 980 struct cvmx_pcmx_txmsk4_s 981 { 982#if __BYTE_ORDER == __BIG_ENDIAN 983 uint64_t mask : 64; /**< Transmit mask bits for slots 319 to 256 984 (1 means transmit, 0 means don't transmit) */ 985#else 986 uint64_t mask : 64; 987#endif 988 } s; 989 struct cvmx_pcmx_txmsk4_s cn30xx; 990 struct cvmx_pcmx_txmsk4_s cn31xx; 991 struct cvmx_pcmx_txmsk4_s cn50xx; 992}; 993typedef union cvmx_pcmx_txmsk4 cvmx_pcmx_txmsk4_t; 994 995/** 996 * cvmx_pcm#_txmsk5 997 */ 998union cvmx_pcmx_txmsk5 999{ 1000 uint64_t u64; 1001 struct cvmx_pcmx_txmsk5_s 1002 { 1003#if __BYTE_ORDER == __BIG_ENDIAN 1004 uint64_t mask : 64; /**< Transmit mask bits for slots 383 to 320 1005 (1 means transmit, 0 means don't transmit) */ 1006#else 1007 uint64_t mask : 64; 1008#endif 1009 } s; 1010 struct cvmx_pcmx_txmsk5_s cn30xx; 1011 struct cvmx_pcmx_txmsk5_s cn31xx; 1012 struct cvmx_pcmx_txmsk5_s cn50xx; 1013}; 1014typedef union cvmx_pcmx_txmsk5 cvmx_pcmx_txmsk5_t; 1015 1016/** 1017 * cvmx_pcm#_txmsk6 1018 */ 1019union cvmx_pcmx_txmsk6 1020{ 1021 uint64_t u64; 1022 struct cvmx_pcmx_txmsk6_s 1023 { 1024#if __BYTE_ORDER == __BIG_ENDIAN 1025 uint64_t mask : 64; /**< Transmit mask bits for slots 447 to 384 1026 (1 means transmit, 0 means don't transmit) */ 1027#else 1028 uint64_t mask : 64; 1029#endif 1030 } s; 1031 struct cvmx_pcmx_txmsk6_s cn30xx; 1032 struct cvmx_pcmx_txmsk6_s cn31xx; 1033 struct cvmx_pcmx_txmsk6_s cn50xx; 1034}; 1035typedef union cvmx_pcmx_txmsk6 cvmx_pcmx_txmsk6_t; 1036 1037/** 1038 * cvmx_pcm#_txmsk7 1039 */ 1040union cvmx_pcmx_txmsk7 1041{ 1042 uint64_t u64; 1043 struct cvmx_pcmx_txmsk7_s 1044 { 1045#if __BYTE_ORDER == __BIG_ENDIAN 1046 uint64_t mask : 64; /**< Transmit mask bits for slots 511 to 448 1047 (1 means transmit, 0 means don't transmit) */ 1048#else 1049 uint64_t mask : 64; 1050#endif 1051 } s; 1052 struct cvmx_pcmx_txmsk7_s cn30xx; 1053 struct cvmx_pcmx_txmsk7_s cn31xx; 1054 struct cvmx_pcmx_txmsk7_s cn50xx; 1055}; 1056typedef union cvmx_pcmx_txmsk7 cvmx_pcmx_txmsk7_t; 1057 1058/** 1059 * cvmx_pcm#_txstart 1060 */ 1061union cvmx_pcmx_txstart 1062{ 1063 uint64_t u64; 1064 struct cvmx_pcmx_txstart_s 1065 { 1066#if __BYTE_ORDER == __BIG_ENDIAN 1067 uint64_t reserved_36_63 : 28; 1068 uint64_t addr : 33; /**< Starting address for the transmit memory region */ 1069 uint64_t reserved_0_2 : 3; 1070#else 1071 uint64_t reserved_0_2 : 3; 1072 uint64_t addr : 33; 1073 uint64_t reserved_36_63 : 28; 1074#endif 1075 } s; 1076 struct cvmx_pcmx_txstart_s cn30xx; 1077 struct cvmx_pcmx_txstart_s cn31xx; 1078 struct cvmx_pcmx_txstart_s cn50xx; 1079}; 1080typedef union cvmx_pcmx_txstart cvmx_pcmx_txstart_t; 1081 1082#endif 1083