1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pcm-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pcm. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_PCM_DEFS_H__ 53232812Sjmallett#define __CVMX_PCM_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 61232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 62232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 63232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 64215976Sjmallett cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n", offset); 65215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384; 66215976Sjmallett} 67215976Sjmallett#else 68215976Sjmallett#define CVMX_PCM_CLKX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384) 69215976Sjmallett#endif 70215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71215976Sjmallettstatic inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset) 72215976Sjmallett{ 73215976Sjmallett if (!( 74215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 75215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 76232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 77232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 78232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 79215976Sjmallett cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n", offset); 80215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384; 81215976Sjmallett} 82215976Sjmallett#else 83215976Sjmallett#define CVMX_PCM_CLKX_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384) 84215976Sjmallett#endif 85215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86215976Sjmallettstatic inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset) 87215976Sjmallett{ 88215976Sjmallett if (!( 89215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 90215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 91232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 92232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 93232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 94215976Sjmallett cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n", offset); 95215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384; 96215976Sjmallett} 97215976Sjmallett#else 98215976Sjmallett#define CVMX_PCM_CLKX_GEN(offset) (CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384) 99215976Sjmallett#endif 100215976Sjmallett 101215976Sjmallett/** 102215976Sjmallett * cvmx_pcm_clk#_cfg 103215976Sjmallett */ 104232812Sjmallettunion cvmx_pcm_clkx_cfg { 105215976Sjmallett uint64_t u64; 106232812Sjmallett struct cvmx_pcm_clkx_cfg_s { 107232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 108232812Sjmallett uint64_t fsyncgood : 1; /**< FSYNC status | NS 109215976Sjmallett If 1, the last frame had a correctly positioned 110215976Sjmallett fsync pulse 111215976Sjmallett If 0, none/extra fsync pulse seen on most recent 112215976Sjmallett frame 113215976Sjmallett NOTE: this is intended for startup. the FSYNCEXTRA 114215976Sjmallett and FSYNCMISSING interrupts are intended for 115215976Sjmallett detecting loss of sync during normal operation. */ 116215976Sjmallett uint64_t reserved_48_62 : 15; 117232812Sjmallett uint64_t fsyncsamp : 16; /**< Number of ECLKs from internal BCLK edge to | NS 118215976Sjmallett sample FSYNC 119215976Sjmallett NOTE: used to sync to the start of a frame and to 120215976Sjmallett check for FSYNC errors. */ 121215976Sjmallett uint64_t reserved_26_31 : 6; 122232812Sjmallett uint64_t fsynclen : 5; /**< Number of 1/2 BCLKs FSYNC is asserted for | NS 123215976Sjmallett NOTE: only used when GEN==1 */ 124232812Sjmallett uint64_t fsyncloc : 5; /**< FSYNC location, in 1/2 BCLKS before timeslot 0, | NS 125215976Sjmallett bit 0. 126215976Sjmallett NOTE: also used to detect framing errors and 127215976Sjmallett therefore must have a correct value even if GEN==0 */ 128232812Sjmallett uint64_t numslots : 10; /**< Number of 8-bit slots in a frame | NS 129215976Sjmallett NOTE: this, along with EXTRABIT and Fbclk 130215976Sjmallett determines FSYNC frequency when GEN == 1 131215976Sjmallett NOTE: also used to detect framing errors and 132215976Sjmallett therefore must have a correct value even if GEN==0 */ 133232812Sjmallett uint64_t extrabit : 1; /**< If 0, no frame bit | NS 134215976Sjmallett If 1, add one extra bit time for frame bit 135215976Sjmallett NOTE: if GEN == 1, then FSYNC will be delayed one 136215976Sjmallett extra bit time. 137215976Sjmallett NOTE: also used to detect framing errors and 138215976Sjmallett therefore must have a correct value even if GEN==0 139215976Sjmallett NOTE: the extra bit comes from the LSB/MSB of the 140215976Sjmallett first byte of the frame in the transmit memory 141215976Sjmallett region. LSB vs MSB is determined from the setting 142215976Sjmallett of PCMn_TDM_CFG[LSBFIRST]. */ 143232812Sjmallett uint64_t bitlen : 2; /**< Number of BCLKs in a bit time. | NS 144215976Sjmallett 0 : 1 BCLK 145215976Sjmallett 1 : 2 BCLKs 146215976Sjmallett 2 : 4 BCLKs 147215976Sjmallett 3 : operation undefined */ 148232812Sjmallett uint64_t bclkpol : 1; /**< If 0, BCLK rise edge is start of bit time | NS 149215976Sjmallett If 1, BCLK fall edge is start of bit time 150215976Sjmallett NOTE: also used to detect framing errors and 151215976Sjmallett therefore must have a correct value even if GEN==0 */ 152232812Sjmallett uint64_t fsyncpol : 1; /**< If 0, FSYNC idles low, asserts high | NS 153215976Sjmallett If 1, FSYNC idles high, asserts low 154215976Sjmallett NOTE: also used to detect framing errors and 155215976Sjmallett therefore must have a correct value even if GEN==0 */ 156232812Sjmallett uint64_t ena : 1; /**< If 0, Clock receiving logic is doing nothing | NS 157215976Sjmallett 1, Clock receiving logic is looking for sync */ 158215976Sjmallett#else 159215976Sjmallett uint64_t ena : 1; 160215976Sjmallett uint64_t fsyncpol : 1; 161215976Sjmallett uint64_t bclkpol : 1; 162215976Sjmallett uint64_t bitlen : 2; 163215976Sjmallett uint64_t extrabit : 1; 164215976Sjmallett uint64_t numslots : 10; 165215976Sjmallett uint64_t fsyncloc : 5; 166215976Sjmallett uint64_t fsynclen : 5; 167215976Sjmallett uint64_t reserved_26_31 : 6; 168215976Sjmallett uint64_t fsyncsamp : 16; 169215976Sjmallett uint64_t reserved_48_62 : 15; 170215976Sjmallett uint64_t fsyncgood : 1; 171215976Sjmallett#endif 172215976Sjmallett } s; 173215976Sjmallett struct cvmx_pcm_clkx_cfg_s cn30xx; 174215976Sjmallett struct cvmx_pcm_clkx_cfg_s cn31xx; 175215976Sjmallett struct cvmx_pcm_clkx_cfg_s cn50xx; 176232812Sjmallett struct cvmx_pcm_clkx_cfg_s cn61xx; 177232812Sjmallett struct cvmx_pcm_clkx_cfg_s cnf71xx; 178215976Sjmallett}; 179215976Sjmalletttypedef union cvmx_pcm_clkx_cfg cvmx_pcm_clkx_cfg_t; 180215976Sjmallett 181215976Sjmallett/** 182215976Sjmallett * cvmx_pcm_clk#_dbg 183215976Sjmallett */ 184232812Sjmallettunion cvmx_pcm_clkx_dbg { 185215976Sjmallett uint64_t u64; 186232812Sjmallett struct cvmx_pcm_clkx_dbg_s { 187232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 188232812Sjmallett uint64_t debuginfo : 64; /**< Miscellaneous debug information | NS */ 189215976Sjmallett#else 190215976Sjmallett uint64_t debuginfo : 64; 191215976Sjmallett#endif 192215976Sjmallett } s; 193215976Sjmallett struct cvmx_pcm_clkx_dbg_s cn30xx; 194215976Sjmallett struct cvmx_pcm_clkx_dbg_s cn31xx; 195215976Sjmallett struct cvmx_pcm_clkx_dbg_s cn50xx; 196232812Sjmallett struct cvmx_pcm_clkx_dbg_s cn61xx; 197232812Sjmallett struct cvmx_pcm_clkx_dbg_s cnf71xx; 198215976Sjmallett}; 199215976Sjmalletttypedef union cvmx_pcm_clkx_dbg cvmx_pcm_clkx_dbg_t; 200215976Sjmallett 201215976Sjmallett/** 202215976Sjmallett * cvmx_pcm_clk#_gen 203215976Sjmallett */ 204232812Sjmallettunion cvmx_pcm_clkx_gen { 205215976Sjmallett uint64_t u64; 206232812Sjmallett struct cvmx_pcm_clkx_gen_s { 207232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 208232812Sjmallett uint64_t deltasamp : 16; /**< Signed number of ECLKs to move sampled BCLK edge | NS 209215976Sjmallett NOTE: the complete number of ECLKs to move is: 210215976Sjmallett NUMSAMP + 2 + 1 + DELTASAMP 211215976Sjmallett NUMSAMP to compensate for sampling delay 212215976Sjmallett + 2 to compensate for dual-rank synchronizer 213215976Sjmallett + 1 for uncertainity 214215976Sjmallett + DELTASAMP to CMA/debugging */ 215232812Sjmallett uint64_t numsamp : 16; /**< Number of ECLK samples to detect BCLK change when | NS 216215976Sjmallett receiving clock. */ 217232812Sjmallett uint64_t n : 32; /**< Determines BCLK frequency when generating clock | NS 218215976Sjmallett NOTE: Fbclk = Feclk * N / 2^32 219215976Sjmallett N = (Fbclk / Feclk) * 2^32 220215976Sjmallett NOTE: writing N == 0 stops the clock generator, and 221215976Sjmallett causes bclk and fsync to be RECEIVED */ 222215976Sjmallett#else 223215976Sjmallett uint64_t n : 32; 224215976Sjmallett uint64_t numsamp : 16; 225215976Sjmallett uint64_t deltasamp : 16; 226215976Sjmallett#endif 227215976Sjmallett } s; 228215976Sjmallett struct cvmx_pcm_clkx_gen_s cn30xx; 229215976Sjmallett struct cvmx_pcm_clkx_gen_s cn31xx; 230215976Sjmallett struct cvmx_pcm_clkx_gen_s cn50xx; 231232812Sjmallett struct cvmx_pcm_clkx_gen_s cn61xx; 232232812Sjmallett struct cvmx_pcm_clkx_gen_s cnf71xx; 233215976Sjmallett}; 234215976Sjmalletttypedef union cvmx_pcm_clkx_gen cvmx_pcm_clkx_gen_t; 235215976Sjmallett 236215976Sjmallett#endif 237