1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-pci-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon pci. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_PCI_DEFS_H__ 53#define __CVMX_PCI_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_PCI_BAR1_INDEXX(unsigned long offset) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) || 60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) || 61 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) || 62 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) || 63 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31))))) 64 cvmx_warn("CVMX_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); 65 return 0x0000000000000100ull + ((offset) & 31) * 4; 66} 67#else 68#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4) 69#endif 70#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71#define CVMX_PCI_BIST_REG CVMX_PCI_BIST_REG_FUNC() 72static inline uint64_t CVMX_PCI_BIST_REG_FUNC(void) 73{ 74 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX))) 75 cvmx_warn("CVMX_PCI_BIST_REG not supported on this chip\n"); 76 return 0x00000000000001C0ull; 77} 78#else 79#define CVMX_PCI_BIST_REG (0x00000000000001C0ull) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82#define CVMX_PCI_CFG00 CVMX_PCI_CFG00_FUNC() 83static inline uint64_t CVMX_PCI_CFG00_FUNC(void) 84{ 85 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 86 cvmx_warn("CVMX_PCI_CFG00 not supported on this chip\n"); 87 return 0x0000000000000000ull; 88} 89#else 90#define CVMX_PCI_CFG00 (0x0000000000000000ull) 91#endif 92#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 93#define CVMX_PCI_CFG01 CVMX_PCI_CFG01_FUNC() 94static inline uint64_t CVMX_PCI_CFG01_FUNC(void) 95{ 96 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 97 cvmx_warn("CVMX_PCI_CFG01 not supported on this chip\n"); 98 return 0x0000000000000004ull; 99} 100#else 101#define CVMX_PCI_CFG01 (0x0000000000000004ull) 102#endif 103#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 104#define CVMX_PCI_CFG02 CVMX_PCI_CFG02_FUNC() 105static inline uint64_t CVMX_PCI_CFG02_FUNC(void) 106{ 107 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 108 cvmx_warn("CVMX_PCI_CFG02 not supported on this chip\n"); 109 return 0x0000000000000008ull; 110} 111#else 112#define CVMX_PCI_CFG02 (0x0000000000000008ull) 113#endif 114#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 115#define CVMX_PCI_CFG03 CVMX_PCI_CFG03_FUNC() 116static inline uint64_t CVMX_PCI_CFG03_FUNC(void) 117{ 118 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 119 cvmx_warn("CVMX_PCI_CFG03 not supported on this chip\n"); 120 return 0x000000000000000Cull; 121} 122#else 123#define CVMX_PCI_CFG03 (0x000000000000000Cull) 124#endif 125#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 126#define CVMX_PCI_CFG04 CVMX_PCI_CFG04_FUNC() 127static inline uint64_t CVMX_PCI_CFG04_FUNC(void) 128{ 129 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 130 cvmx_warn("CVMX_PCI_CFG04 not supported on this chip\n"); 131 return 0x0000000000000010ull; 132} 133#else 134#define CVMX_PCI_CFG04 (0x0000000000000010ull) 135#endif 136#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 137#define CVMX_PCI_CFG05 CVMX_PCI_CFG05_FUNC() 138static inline uint64_t CVMX_PCI_CFG05_FUNC(void) 139{ 140 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 141 cvmx_warn("CVMX_PCI_CFG05 not supported on this chip\n"); 142 return 0x0000000000000014ull; 143} 144#else 145#define CVMX_PCI_CFG05 (0x0000000000000014ull) 146#endif 147#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 148#define CVMX_PCI_CFG06 CVMX_PCI_CFG06_FUNC() 149static inline uint64_t CVMX_PCI_CFG06_FUNC(void) 150{ 151 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 152 cvmx_warn("CVMX_PCI_CFG06 not supported on this chip\n"); 153 return 0x0000000000000018ull; 154} 155#else 156#define CVMX_PCI_CFG06 (0x0000000000000018ull) 157#endif 158#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 159#define CVMX_PCI_CFG07 CVMX_PCI_CFG07_FUNC() 160static inline uint64_t CVMX_PCI_CFG07_FUNC(void) 161{ 162 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 163 cvmx_warn("CVMX_PCI_CFG07 not supported on this chip\n"); 164 return 0x000000000000001Cull; 165} 166#else 167#define CVMX_PCI_CFG07 (0x000000000000001Cull) 168#endif 169#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 170#define CVMX_PCI_CFG08 CVMX_PCI_CFG08_FUNC() 171static inline uint64_t CVMX_PCI_CFG08_FUNC(void) 172{ 173 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 174 cvmx_warn("CVMX_PCI_CFG08 not supported on this chip\n"); 175 return 0x0000000000000020ull; 176} 177#else 178#define CVMX_PCI_CFG08 (0x0000000000000020ull) 179#endif 180#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 181#define CVMX_PCI_CFG09 CVMX_PCI_CFG09_FUNC() 182static inline uint64_t CVMX_PCI_CFG09_FUNC(void) 183{ 184 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 185 cvmx_warn("CVMX_PCI_CFG09 not supported on this chip\n"); 186 return 0x0000000000000024ull; 187} 188#else 189#define CVMX_PCI_CFG09 (0x0000000000000024ull) 190#endif 191#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 192#define CVMX_PCI_CFG10 CVMX_PCI_CFG10_FUNC() 193static inline uint64_t CVMX_PCI_CFG10_FUNC(void) 194{ 195 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 196 cvmx_warn("CVMX_PCI_CFG10 not supported on this chip\n"); 197 return 0x0000000000000028ull; 198} 199#else 200#define CVMX_PCI_CFG10 (0x0000000000000028ull) 201#endif 202#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 203#define CVMX_PCI_CFG11 CVMX_PCI_CFG11_FUNC() 204static inline uint64_t CVMX_PCI_CFG11_FUNC(void) 205{ 206 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 207 cvmx_warn("CVMX_PCI_CFG11 not supported on this chip\n"); 208 return 0x000000000000002Cull; 209} 210#else 211#define CVMX_PCI_CFG11 (0x000000000000002Cull) 212#endif 213#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 214#define CVMX_PCI_CFG12 CVMX_PCI_CFG12_FUNC() 215static inline uint64_t CVMX_PCI_CFG12_FUNC(void) 216{ 217 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 218 cvmx_warn("CVMX_PCI_CFG12 not supported on this chip\n"); 219 return 0x0000000000000030ull; 220} 221#else 222#define CVMX_PCI_CFG12 (0x0000000000000030ull) 223#endif 224#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 225#define CVMX_PCI_CFG13 CVMX_PCI_CFG13_FUNC() 226static inline uint64_t CVMX_PCI_CFG13_FUNC(void) 227{ 228 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 229 cvmx_warn("CVMX_PCI_CFG13 not supported on this chip\n"); 230 return 0x0000000000000034ull; 231} 232#else 233#define CVMX_PCI_CFG13 (0x0000000000000034ull) 234#endif 235#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236#define CVMX_PCI_CFG15 CVMX_PCI_CFG15_FUNC() 237static inline uint64_t CVMX_PCI_CFG15_FUNC(void) 238{ 239 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 240 cvmx_warn("CVMX_PCI_CFG15 not supported on this chip\n"); 241 return 0x000000000000003Cull; 242} 243#else 244#define CVMX_PCI_CFG15 (0x000000000000003Cull) 245#endif 246#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 247#define CVMX_PCI_CFG16 CVMX_PCI_CFG16_FUNC() 248static inline uint64_t CVMX_PCI_CFG16_FUNC(void) 249{ 250 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 251 cvmx_warn("CVMX_PCI_CFG16 not supported on this chip\n"); 252 return 0x0000000000000040ull; 253} 254#else 255#define CVMX_PCI_CFG16 (0x0000000000000040ull) 256#endif 257#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 258#define CVMX_PCI_CFG17 CVMX_PCI_CFG17_FUNC() 259static inline uint64_t CVMX_PCI_CFG17_FUNC(void) 260{ 261 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 262 cvmx_warn("CVMX_PCI_CFG17 not supported on this chip\n"); 263 return 0x0000000000000044ull; 264} 265#else 266#define CVMX_PCI_CFG17 (0x0000000000000044ull) 267#endif 268#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 269#define CVMX_PCI_CFG18 CVMX_PCI_CFG18_FUNC() 270static inline uint64_t CVMX_PCI_CFG18_FUNC(void) 271{ 272 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 273 cvmx_warn("CVMX_PCI_CFG18 not supported on this chip\n"); 274 return 0x0000000000000048ull; 275} 276#else 277#define CVMX_PCI_CFG18 (0x0000000000000048ull) 278#endif 279#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 280#define CVMX_PCI_CFG19 CVMX_PCI_CFG19_FUNC() 281static inline uint64_t CVMX_PCI_CFG19_FUNC(void) 282{ 283 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 284 cvmx_warn("CVMX_PCI_CFG19 not supported on this chip\n"); 285 return 0x000000000000004Cull; 286} 287#else 288#define CVMX_PCI_CFG19 (0x000000000000004Cull) 289#endif 290#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 291#define CVMX_PCI_CFG20 CVMX_PCI_CFG20_FUNC() 292static inline uint64_t CVMX_PCI_CFG20_FUNC(void) 293{ 294 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 295 cvmx_warn("CVMX_PCI_CFG20 not supported on this chip\n"); 296 return 0x0000000000000050ull; 297} 298#else 299#define CVMX_PCI_CFG20 (0x0000000000000050ull) 300#endif 301#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 302#define CVMX_PCI_CFG21 CVMX_PCI_CFG21_FUNC() 303static inline uint64_t CVMX_PCI_CFG21_FUNC(void) 304{ 305 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 306 cvmx_warn("CVMX_PCI_CFG21 not supported on this chip\n"); 307 return 0x0000000000000054ull; 308} 309#else 310#define CVMX_PCI_CFG21 (0x0000000000000054ull) 311#endif 312#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 313#define CVMX_PCI_CFG22 CVMX_PCI_CFG22_FUNC() 314static inline uint64_t CVMX_PCI_CFG22_FUNC(void) 315{ 316 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 317 cvmx_warn("CVMX_PCI_CFG22 not supported on this chip\n"); 318 return 0x0000000000000058ull; 319} 320#else 321#define CVMX_PCI_CFG22 (0x0000000000000058ull) 322#endif 323#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 324#define CVMX_PCI_CFG56 CVMX_PCI_CFG56_FUNC() 325static inline uint64_t CVMX_PCI_CFG56_FUNC(void) 326{ 327 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 328 cvmx_warn("CVMX_PCI_CFG56 not supported on this chip\n"); 329 return 0x00000000000000E0ull; 330} 331#else 332#define CVMX_PCI_CFG56 (0x00000000000000E0ull) 333#endif 334#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 335#define CVMX_PCI_CFG57 CVMX_PCI_CFG57_FUNC() 336static inline uint64_t CVMX_PCI_CFG57_FUNC(void) 337{ 338 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 339 cvmx_warn("CVMX_PCI_CFG57 not supported on this chip\n"); 340 return 0x00000000000000E4ull; 341} 342#else 343#define CVMX_PCI_CFG57 (0x00000000000000E4ull) 344#endif 345#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 346#define CVMX_PCI_CFG58 CVMX_PCI_CFG58_FUNC() 347static inline uint64_t CVMX_PCI_CFG58_FUNC(void) 348{ 349 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 350 cvmx_warn("CVMX_PCI_CFG58 not supported on this chip\n"); 351 return 0x00000000000000E8ull; 352} 353#else 354#define CVMX_PCI_CFG58 (0x00000000000000E8ull) 355#endif 356#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 357#define CVMX_PCI_CFG59 CVMX_PCI_CFG59_FUNC() 358static inline uint64_t CVMX_PCI_CFG59_FUNC(void) 359{ 360 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 361 cvmx_warn("CVMX_PCI_CFG59 not supported on this chip\n"); 362 return 0x00000000000000ECull; 363} 364#else 365#define CVMX_PCI_CFG59 (0x00000000000000ECull) 366#endif 367#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 368#define CVMX_PCI_CFG60 CVMX_PCI_CFG60_FUNC() 369static inline uint64_t CVMX_PCI_CFG60_FUNC(void) 370{ 371 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 372 cvmx_warn("CVMX_PCI_CFG60 not supported on this chip\n"); 373 return 0x00000000000000F0ull; 374} 375#else 376#define CVMX_PCI_CFG60 (0x00000000000000F0ull) 377#endif 378#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 379#define CVMX_PCI_CFG61 CVMX_PCI_CFG61_FUNC() 380static inline uint64_t CVMX_PCI_CFG61_FUNC(void) 381{ 382 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 383 cvmx_warn("CVMX_PCI_CFG61 not supported on this chip\n"); 384 return 0x00000000000000F4ull; 385} 386#else 387#define CVMX_PCI_CFG61 (0x00000000000000F4ull) 388#endif 389#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 390#define CVMX_PCI_CFG62 CVMX_PCI_CFG62_FUNC() 391static inline uint64_t CVMX_PCI_CFG62_FUNC(void) 392{ 393 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 394 cvmx_warn("CVMX_PCI_CFG62 not supported on this chip\n"); 395 return 0x00000000000000F8ull; 396} 397#else 398#define CVMX_PCI_CFG62 (0x00000000000000F8ull) 399#endif 400#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 401#define CVMX_PCI_CFG63 CVMX_PCI_CFG63_FUNC() 402static inline uint64_t CVMX_PCI_CFG63_FUNC(void) 403{ 404 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 405 cvmx_warn("CVMX_PCI_CFG63 not supported on this chip\n"); 406 return 0x00000000000000FCull; 407} 408#else 409#define CVMX_PCI_CFG63 (0x00000000000000FCull) 410#endif 411#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 412#define CVMX_PCI_CNT_REG CVMX_PCI_CNT_REG_FUNC() 413static inline uint64_t CVMX_PCI_CNT_REG_FUNC(void) 414{ 415 if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 416 cvmx_warn("CVMX_PCI_CNT_REG not supported on this chip\n"); 417 return 0x00000000000001B8ull; 418} 419#else 420#define CVMX_PCI_CNT_REG (0x00000000000001B8ull) 421#endif 422#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 423#define CVMX_PCI_CTL_STATUS_2 CVMX_PCI_CTL_STATUS_2_FUNC() 424static inline uint64_t CVMX_PCI_CTL_STATUS_2_FUNC(void) 425{ 426 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 427 cvmx_warn("CVMX_PCI_CTL_STATUS_2 not supported on this chip\n"); 428 return 0x000000000000018Cull; 429} 430#else 431#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull) 432#endif 433#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 434static inline uint64_t CVMX_PCI_DBELL_X(unsigned long offset) 435{ 436 if (!( 437 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 438 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 439 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 440 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 441 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 442 cvmx_warn("CVMX_PCI_DBELL_X(%lu) is invalid on this chip\n", offset); 443 return 0x0000000000000080ull + ((offset) & 3) * 8; 444} 445#else 446#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8) 447#endif 448#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0) 449#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1) 450#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 451static inline uint64_t CVMX_PCI_DMA_CNTX(unsigned long offset) 452{ 453 if (!( 454 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 455 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 456 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 457 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 458 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 459 cvmx_warn("CVMX_PCI_DMA_CNTX(%lu) is invalid on this chip\n", offset); 460 return 0x00000000000000A0ull + ((offset) & 1) * 8; 461} 462#else 463#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8) 464#endif 465#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0) 466#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1) 467#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 468static inline uint64_t CVMX_PCI_DMA_INT_LEVX(unsigned long offset) 469{ 470 if (!( 471 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 472 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 473 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 474 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 475 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 476 cvmx_warn("CVMX_PCI_DMA_INT_LEVX(%lu) is invalid on this chip\n", offset); 477 return 0x00000000000000A4ull + ((offset) & 1) * 8; 478} 479#else 480#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8) 481#endif 482#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0) 483#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1) 484#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485static inline uint64_t CVMX_PCI_DMA_TIMEX(unsigned long offset) 486{ 487 if (!( 488 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) || 489 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 490 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 491 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 492 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 493 cvmx_warn("CVMX_PCI_DMA_TIMEX(%lu) is invalid on this chip\n", offset); 494 return 0x00000000000000B0ull + ((offset) & 1) * 4; 495} 496#else 497#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4) 498#endif 499#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0) 500#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1) 501#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2) 502#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3) 503#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 504static inline uint64_t CVMX_PCI_INSTR_COUNTX(unsigned long offset) 505{ 506 if (!( 507 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 508 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 509 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 510 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 511 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 512 cvmx_warn("CVMX_PCI_INSTR_COUNTX(%lu) is invalid on this chip\n", offset); 513 return 0x0000000000000084ull + ((offset) & 3) * 8; 514} 515#else 516#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8) 517#endif 518#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 519#define CVMX_PCI_INT_ENB CVMX_PCI_INT_ENB_FUNC() 520static inline uint64_t CVMX_PCI_INT_ENB_FUNC(void) 521{ 522 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 523 cvmx_warn("CVMX_PCI_INT_ENB not supported on this chip\n"); 524 return 0x0000000000000038ull; 525} 526#else 527#define CVMX_PCI_INT_ENB (0x0000000000000038ull) 528#endif 529#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 530#define CVMX_PCI_INT_ENB2 CVMX_PCI_INT_ENB2_FUNC() 531static inline uint64_t CVMX_PCI_INT_ENB2_FUNC(void) 532{ 533 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 534 cvmx_warn("CVMX_PCI_INT_ENB2 not supported on this chip\n"); 535 return 0x00000000000001A0ull; 536} 537#else 538#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull) 539#endif 540#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 541#define CVMX_PCI_INT_SUM CVMX_PCI_INT_SUM_FUNC() 542static inline uint64_t CVMX_PCI_INT_SUM_FUNC(void) 543{ 544 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 545 cvmx_warn("CVMX_PCI_INT_SUM not supported on this chip\n"); 546 return 0x0000000000000030ull; 547} 548#else 549#define CVMX_PCI_INT_SUM (0x0000000000000030ull) 550#endif 551#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 552#define CVMX_PCI_INT_SUM2 CVMX_PCI_INT_SUM2_FUNC() 553static inline uint64_t CVMX_PCI_INT_SUM2_FUNC(void) 554{ 555 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 556 cvmx_warn("CVMX_PCI_INT_SUM2 not supported on this chip\n"); 557 return 0x0000000000000198ull; 558} 559#else 560#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull) 561#endif 562#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 563#define CVMX_PCI_MSI_RCV CVMX_PCI_MSI_RCV_FUNC() 564static inline uint64_t CVMX_PCI_MSI_RCV_FUNC(void) 565{ 566 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 567 cvmx_warn("CVMX_PCI_MSI_RCV not supported on this chip\n"); 568 return 0x00000000000000F0ull; 569} 570#else 571#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull) 572#endif 573#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0) 574#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1) 575#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2) 576#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3) 577#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 578static inline uint64_t CVMX_PCI_PKTS_SENTX(unsigned long offset) 579{ 580 if (!( 581 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 582 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 583 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 584 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 585 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 586 cvmx_warn("CVMX_PCI_PKTS_SENTX(%lu) is invalid on this chip\n", offset); 587 return 0x0000000000000040ull + ((offset) & 3) * 16; 588} 589#else 590#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16) 591#endif 592#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0) 593#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1) 594#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2) 595#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3) 596#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 597static inline uint64_t CVMX_PCI_PKTS_SENT_INT_LEVX(unsigned long offset) 598{ 599 if (!( 600 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 601 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 602 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 603 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 604 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 605 cvmx_warn("CVMX_PCI_PKTS_SENT_INT_LEVX(%lu) is invalid on this chip\n", offset); 606 return 0x0000000000000048ull + ((offset) & 3) * 16; 607} 608#else 609#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16) 610#endif 611#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0) 612#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1) 613#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2) 614#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3) 615#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 616static inline uint64_t CVMX_PCI_PKTS_SENT_TIMEX(unsigned long offset) 617{ 618 if (!( 619 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 620 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 621 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 622 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 623 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 624 cvmx_warn("CVMX_PCI_PKTS_SENT_TIMEX(%lu) is invalid on this chip\n", offset); 625 return 0x000000000000004Cull + ((offset) & 3) * 16; 626} 627#else 628#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16) 629#endif 630#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0) 631#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1) 632#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2) 633#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3) 634#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 635static inline uint64_t CVMX_PCI_PKT_CREDITSX(unsigned long offset) 636{ 637 if (!( 638 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 639 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 640 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 641 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 642 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 643 cvmx_warn("CVMX_PCI_PKT_CREDITSX(%lu) is invalid on this chip\n", offset); 644 return 0x0000000000000044ull + ((offset) & 3) * 16; 645} 646#else 647#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16) 648#endif 649#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650#define CVMX_PCI_READ_CMD_6 CVMX_PCI_READ_CMD_6_FUNC() 651static inline uint64_t CVMX_PCI_READ_CMD_6_FUNC(void) 652{ 653 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 654 cvmx_warn("CVMX_PCI_READ_CMD_6 not supported on this chip\n"); 655 return 0x0000000000000180ull; 656} 657#else 658#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull) 659#endif 660#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661#define CVMX_PCI_READ_CMD_C CVMX_PCI_READ_CMD_C_FUNC() 662static inline uint64_t CVMX_PCI_READ_CMD_C_FUNC(void) 663{ 664 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 665 cvmx_warn("CVMX_PCI_READ_CMD_C not supported on this chip\n"); 666 return 0x0000000000000184ull; 667} 668#else 669#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull) 670#endif 671#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672#define CVMX_PCI_READ_CMD_E CVMX_PCI_READ_CMD_E_FUNC() 673static inline uint64_t CVMX_PCI_READ_CMD_E_FUNC(void) 674{ 675 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 676 cvmx_warn("CVMX_PCI_READ_CMD_E not supported on this chip\n"); 677 return 0x0000000000000188ull; 678} 679#else 680#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull) 681#endif 682#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683#define CVMX_PCI_READ_TIMEOUT CVMX_PCI_READ_TIMEOUT_FUNC() 684static inline uint64_t CVMX_PCI_READ_TIMEOUT_FUNC(void) 685{ 686 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 687 cvmx_warn("CVMX_PCI_READ_TIMEOUT not supported on this chip\n"); 688 return CVMX_ADD_IO_SEG(0x00011F00000000B0ull); 689} 690#else 691#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull)) 692#endif 693#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694#define CVMX_PCI_SCM_REG CVMX_PCI_SCM_REG_FUNC() 695static inline uint64_t CVMX_PCI_SCM_REG_FUNC(void) 696{ 697 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 698 cvmx_warn("CVMX_PCI_SCM_REG not supported on this chip\n"); 699 return 0x00000000000001A8ull; 700} 701#else 702#define CVMX_PCI_SCM_REG (0x00000000000001A8ull) 703#endif 704#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705#define CVMX_PCI_TSR_REG CVMX_PCI_TSR_REG_FUNC() 706static inline uint64_t CVMX_PCI_TSR_REG_FUNC(void) 707{ 708 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 709 cvmx_warn("CVMX_PCI_TSR_REG not supported on this chip\n"); 710 return 0x00000000000001B0ull; 711} 712#else 713#define CVMX_PCI_TSR_REG (0x00000000000001B0ull) 714#endif 715#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716#define CVMX_PCI_WIN_RD_ADDR CVMX_PCI_WIN_RD_ADDR_FUNC() 717static inline uint64_t CVMX_PCI_WIN_RD_ADDR_FUNC(void) 718{ 719 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 720 cvmx_warn("CVMX_PCI_WIN_RD_ADDR not supported on this chip\n"); 721 return 0x0000000000000008ull; 722} 723#else 724#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull) 725#endif 726#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727#define CVMX_PCI_WIN_RD_DATA CVMX_PCI_WIN_RD_DATA_FUNC() 728static inline uint64_t CVMX_PCI_WIN_RD_DATA_FUNC(void) 729{ 730 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 731 cvmx_warn("CVMX_PCI_WIN_RD_DATA not supported on this chip\n"); 732 return 0x0000000000000020ull; 733} 734#else 735#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull) 736#endif 737#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738#define CVMX_PCI_WIN_WR_ADDR CVMX_PCI_WIN_WR_ADDR_FUNC() 739static inline uint64_t CVMX_PCI_WIN_WR_ADDR_FUNC(void) 740{ 741 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 742 cvmx_warn("CVMX_PCI_WIN_WR_ADDR not supported on this chip\n"); 743 return 0x0000000000000000ull; 744} 745#else 746#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull) 747#endif 748#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749#define CVMX_PCI_WIN_WR_DATA CVMX_PCI_WIN_WR_DATA_FUNC() 750static inline uint64_t CVMX_PCI_WIN_WR_DATA_FUNC(void) 751{ 752 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 753 cvmx_warn("CVMX_PCI_WIN_WR_DATA not supported on this chip\n"); 754 return 0x0000000000000010ull; 755} 756#else 757#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull) 758#endif 759#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760#define CVMX_PCI_WIN_WR_MASK CVMX_PCI_WIN_WR_MASK_FUNC() 761static inline uint64_t CVMX_PCI_WIN_WR_MASK_FUNC(void) 762{ 763 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 764 cvmx_warn("CVMX_PCI_WIN_WR_MASK not supported on this chip\n"); 765 return 0x0000000000000018ull; 766} 767#else 768#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull) 769#endif 770 771/** 772 * cvmx_pci_bar1_index# 773 * 774 * PCI_BAR1_INDEXX = PCI IndexX Register 775 * 776 * Contains address index and control bits for access to memory ranges of Bar-1, 777 * when PCI supplied address-bits [26:22] == X. 778 */ 779union cvmx_pci_bar1_indexx { 780 uint32_t u32; 781 struct cvmx_pci_bar1_indexx_s { 782#ifdef __BIG_ENDIAN_BITFIELD 783 uint32_t reserved_18_31 : 14; 784 uint32_t addr_idx : 14; /**< Address bits [35:22] sent to L2C */ 785 uint32_t ca : 1; /**< Set '1' when access is not to be cached in L2. */ 786 uint32_t end_swp : 2; /**< Endian Swap Mode */ 787 uint32_t addr_v : 1; /**< Set '1' when the selected address range is valid. */ 788#else 789 uint32_t addr_v : 1; 790 uint32_t end_swp : 2; 791 uint32_t ca : 1; 792 uint32_t addr_idx : 14; 793 uint32_t reserved_18_31 : 14; 794#endif 795 } s; 796 struct cvmx_pci_bar1_indexx_s cn30xx; 797 struct cvmx_pci_bar1_indexx_s cn31xx; 798 struct cvmx_pci_bar1_indexx_s cn38xx; 799 struct cvmx_pci_bar1_indexx_s cn38xxp2; 800 struct cvmx_pci_bar1_indexx_s cn50xx; 801 struct cvmx_pci_bar1_indexx_s cn58xx; 802 struct cvmx_pci_bar1_indexx_s cn58xxp1; 803}; 804typedef union cvmx_pci_bar1_indexx cvmx_pci_bar1_indexx_t; 805 806/** 807 * cvmx_pci_bist_reg 808 * 809 * PCI_BIST_REG = PCI PNI BIST Status Register 810 * 811 * Contains the bist results for the PNI memories. 812 */ 813union cvmx_pci_bist_reg { 814 uint64_t u64; 815 struct cvmx_pci_bist_reg_s { 816#ifdef __BIG_ENDIAN_BITFIELD 817 uint64_t reserved_10_63 : 54; 818 uint64_t rsp_bs : 1; /**< Bist Status For b12_rsp_fifo_bist 819 The value of this register is available 100,000 820 core clocks + 21,000 pclks after: 821 Host Mode - deassertion of pci_rst_n 822 Non Host Mode - deassertion of pci_rst_n */ 823 uint64_t dma0_bs : 1; /**< Bist Status For dmao_count 824 The value of this register is available 100,000 825 core clocks + 21,000 pclks after: 826 Host Mode - deassertion of pci_rst_n 827 Non Host Mode - deassertion of pci_rst_n */ 828 uint64_t cmd0_bs : 1; /**< Bist Status For npi_cmd0_pni_am0 829 The value of this register is available 100,000 830 core clocks + 21,000 pclks after: 831 Host Mode - deassertion of pci_rst_n 832 Non Host Mode - deassertion of pci_rst_n */ 833 uint64_t cmd_bs : 1; /**< Bist Status For npi_cmd_pni_am1 834 The value of this register is available 100,000 835 core clocks + 21,000 pclks after: 836 Host Mode - deassertion of pci_rst_n 837 Non Host Mode - deassertion of pci_rst_n */ 838 uint64_t csr2p_bs : 1; /**< Bist Status For npi_csr_2_pni_am 839 The value of this register is available 100,000 840 core clocks + 21,000 pclks after: 841 Host Mode - deassertion of pci_rst_n 842 Non Host Mode - deassertion of pci_rst_n */ 843 uint64_t csrr_bs : 1; /**< Bist Status For npi_csr_rsp_2_pni_am 844 The value of this register is available 100,000 845 core clocks + 21,000 pclks after: 846 Host Mode - deassertion of pci_rst_n 847 Non Host Mode - deassertion of pci_rst_n */ 848 uint64_t rsp2p_bs : 1; /**< Bist Status For npi_rsp_2_pni_am 849 The value of this register is available 100,000 850 core clocks + 21,000 pclks after: 851 Host Mode - deassertion of pci_rst_n 852 Non Host Mode - deassertion of pci_rst_n */ 853 uint64_t csr2n_bs : 1; /**< Bist Status For pni_csr_2_npi_am 854 The value of this register is available 100,000 855 core clocks + 21,000 pclks after: 856 Host Mode - deassertion of pci_rst_n 857 Non Host Mode - deassertion of pci_rst_n */ 858 uint64_t dat2n_bs : 1; /**< Bist Status For pni_data_2_npi_am 859 The value of this register is available 100,000 860 core clocks + 21,000 pclks after: 861 Host Mode - deassertion of pci_rst_n 862 Non Host Mode - deassertion of pci_rst_n */ 863 uint64_t dbg2n_bs : 1; /**< Bist Status For pni_dbg_data_2_npi_am 864 The value of this register is available 100,000 865 core clocks + 21,000 pclks after: 866 Host Mode - deassertion of pci_rst_n 867 Non Host Mode - deassertion of pci_rst_n */ 868#else 869 uint64_t dbg2n_bs : 1; 870 uint64_t dat2n_bs : 1; 871 uint64_t csr2n_bs : 1; 872 uint64_t rsp2p_bs : 1; 873 uint64_t csrr_bs : 1; 874 uint64_t csr2p_bs : 1; 875 uint64_t cmd_bs : 1; 876 uint64_t cmd0_bs : 1; 877 uint64_t dma0_bs : 1; 878 uint64_t rsp_bs : 1; 879 uint64_t reserved_10_63 : 54; 880#endif 881 } s; 882 struct cvmx_pci_bist_reg_s cn50xx; 883}; 884typedef union cvmx_pci_bist_reg cvmx_pci_bist_reg_t; 885 886/** 887 * cvmx_pci_cfg00 888 * 889 * Registers at address 0x1000 -> 0x17FF are PNI 890 * Start at 0x100 into range 891 * these are shifted by 2 to the left to make address 892 * Registers at address 0x1800 -> 0x18FF are CFG 893 * these are shifted by 2 to the left to make address 894 * 895 * PCI_CFG00 = First 32-bits of PCI config space (PCI Vendor + Device) 896 * 897 * This register contains the first 32-bits of the PCI config space registers 898 */ 899union cvmx_pci_cfg00 { 900 uint32_t u32; 901 struct cvmx_pci_cfg00_s { 902#ifdef __BIG_ENDIAN_BITFIELD 903 uint32_t devid : 16; /**< This is the device ID for OCTEON (90nm shhrink) */ 904 uint32_t vendid : 16; /**< This is the Cavium's vendor ID */ 905#else 906 uint32_t vendid : 16; 907 uint32_t devid : 16; 908#endif 909 } s; 910 struct cvmx_pci_cfg00_s cn30xx; 911 struct cvmx_pci_cfg00_s cn31xx; 912 struct cvmx_pci_cfg00_s cn38xx; 913 struct cvmx_pci_cfg00_s cn38xxp2; 914 struct cvmx_pci_cfg00_s cn50xx; 915 struct cvmx_pci_cfg00_s cn58xx; 916 struct cvmx_pci_cfg00_s cn58xxp1; 917}; 918typedef union cvmx_pci_cfg00 cvmx_pci_cfg00_t; 919 920/** 921 * cvmx_pci_cfg01 922 * 923 * PCI_CFG01 = Second 32-bits of PCI config space (Command/Status Register) 924 * 925 */ 926union cvmx_pci_cfg01 { 927 uint32_t u32; 928 struct cvmx_pci_cfg01_s { 929#ifdef __BIG_ENDIAN_BITFIELD 930 uint32_t dpe : 1; /**< Detected Parity Error */ 931 uint32_t sse : 1; /**< Signaled System Error */ 932 uint32_t rma : 1; /**< Received Master Abort */ 933 uint32_t rta : 1; /**< Received Target Abort */ 934 uint32_t sta : 1; /**< Signaled Target Abort */ 935 uint32_t devt : 2; /**< DEVSEL# timing (for PCI only/for PCIX = don't care) */ 936 uint32_t mdpe : 1; /**< Master Data Parity Error */ 937 uint32_t fbb : 1; /**< Fast Back-to-Back Transactions Capable 938 Mode Dependent (1 = PCI Mode / 0 = PCIX Mode) */ 939 uint32_t reserved_22_22 : 1; 940 uint32_t m66 : 1; /**< 66MHz Capable */ 941 uint32_t cle : 1; /**< Capabilities List Enable */ 942 uint32_t i_stat : 1; /**< When INTx# is asserted by OCTEON this bit will be set. 943 When deasserted by OCTEON this bit will be cleared. */ 944 uint32_t reserved_11_18 : 8; 945 uint32_t i_dis : 1; /**< When asserted '1' disables the generation of INTx# 946 by OCTEON. When disabled '0' allows assertion of INTx# 947 by OCTEON. */ 948 uint32_t fbbe : 1; /**< Fast Back to Back Transaction Enable */ 949 uint32_t see : 1; /**< System Error Enable */ 950 uint32_t ads : 1; /**< Address/Data Stepping 951 NOTE: Octeon does NOT support address/data stepping. */ 952 uint32_t pee : 1; /**< PERR# Enable */ 953 uint32_t vps : 1; /**< VGA Palette Snooping */ 954 uint32_t mwice : 1; /**< Memory Write & Invalidate Command Enable */ 955 uint32_t scse : 1; /**< Special Cycle Snooping Enable */ 956 uint32_t me : 1; /**< Master Enable 957 Must be set for OCTEON to master a PCI/PCI-X 958 transaction. This should always be set any time 959 that OCTEON is connected to a PCI/PCI-X bus. */ 960 uint32_t msae : 1; /**< Memory Space Access Enable 961 Must be set to recieve a PCI/PCI-X memory space 962 transaction. This must always be set any time that 963 OCTEON is connected to a PCI/PCI-X bus. */ 964 uint32_t isae : 1; /**< I/O Space Access Enable 965 NOTE: For OCTEON, this bit MUST NEVER be set 966 (it is read-only and OCTEON does not respond to I/O 967 Space accesses). */ 968#else 969 uint32_t isae : 1; 970 uint32_t msae : 1; 971 uint32_t me : 1; 972 uint32_t scse : 1; 973 uint32_t mwice : 1; 974 uint32_t vps : 1; 975 uint32_t pee : 1; 976 uint32_t ads : 1; 977 uint32_t see : 1; 978 uint32_t fbbe : 1; 979 uint32_t i_dis : 1; 980 uint32_t reserved_11_18 : 8; 981 uint32_t i_stat : 1; 982 uint32_t cle : 1; 983 uint32_t m66 : 1; 984 uint32_t reserved_22_22 : 1; 985 uint32_t fbb : 1; 986 uint32_t mdpe : 1; 987 uint32_t devt : 2; 988 uint32_t sta : 1; 989 uint32_t rta : 1; 990 uint32_t rma : 1; 991 uint32_t sse : 1; 992 uint32_t dpe : 1; 993#endif 994 } s; 995 struct cvmx_pci_cfg01_s cn30xx; 996 struct cvmx_pci_cfg01_s cn31xx; 997 struct cvmx_pci_cfg01_s cn38xx; 998 struct cvmx_pci_cfg01_s cn38xxp2; 999 struct cvmx_pci_cfg01_s cn50xx; 1000 struct cvmx_pci_cfg01_s cn58xx; 1001 struct cvmx_pci_cfg01_s cn58xxp1; 1002}; 1003typedef union cvmx_pci_cfg01 cvmx_pci_cfg01_t; 1004 1005/** 1006 * cvmx_pci_cfg02 1007 * 1008 * PCI_CFG02 = Third 32-bits of PCI config space (Class Code / Revision ID) 1009 * 1010 */ 1011union cvmx_pci_cfg02 { 1012 uint32_t u32; 1013 struct cvmx_pci_cfg02_s { 1014#ifdef __BIG_ENDIAN_BITFIELD 1015 uint32_t cc : 24; /**< Class Code (Processor/MIPS) 1016 (was 0x100000 in pass 1 and pass 2) */ 1017 uint32_t rid : 8; /**< Revision ID 1018 (0 in pass 1, 1 in pass 1.1, 8 in pass 2.0) */ 1019#else 1020 uint32_t rid : 8; 1021 uint32_t cc : 24; 1022#endif 1023 } s; 1024 struct cvmx_pci_cfg02_s cn30xx; 1025 struct cvmx_pci_cfg02_s cn31xx; 1026 struct cvmx_pci_cfg02_s cn38xx; 1027 struct cvmx_pci_cfg02_s cn38xxp2; 1028 struct cvmx_pci_cfg02_s cn50xx; 1029 struct cvmx_pci_cfg02_s cn58xx; 1030 struct cvmx_pci_cfg02_s cn58xxp1; 1031}; 1032typedef union cvmx_pci_cfg02 cvmx_pci_cfg02_t; 1033 1034/** 1035 * cvmx_pci_cfg03 1036 * 1037 * PCI_CFG03 = Fourth 32-bits of PCI config space (BIST, HEADER Type, Latency timer, line size) 1038 * 1039 */ 1040union cvmx_pci_cfg03 { 1041 uint32_t u32; 1042 struct cvmx_pci_cfg03_s { 1043#ifdef __BIG_ENDIAN_BITFIELD 1044 uint32_t bcap : 1; /**< BIST Capable */ 1045 uint32_t brb : 1; /**< BIST Request/busy bit 1046 Note: OCTEON does not support PCI BIST, therefore 1047 this bit should remain zero. */ 1048 uint32_t reserved_28_29 : 2; 1049 uint32_t bcod : 4; /**< BIST Code */ 1050 uint32_t ht : 8; /**< Header Type (Type 0) */ 1051 uint32_t lt : 8; /**< Latency Timer 1052 (0=PCI) (0=PCI) 1053 (0x40=PCIX) (0x40=PCIX) */ 1054 uint32_t cls : 8; /**< Cache Line Size */ 1055#else 1056 uint32_t cls : 8; 1057 uint32_t lt : 8; 1058 uint32_t ht : 8; 1059 uint32_t bcod : 4; 1060 uint32_t reserved_28_29 : 2; 1061 uint32_t brb : 1; 1062 uint32_t bcap : 1; 1063#endif 1064 } s; 1065 struct cvmx_pci_cfg03_s cn30xx; 1066 struct cvmx_pci_cfg03_s cn31xx; 1067 struct cvmx_pci_cfg03_s cn38xx; 1068 struct cvmx_pci_cfg03_s cn38xxp2; 1069 struct cvmx_pci_cfg03_s cn50xx; 1070 struct cvmx_pci_cfg03_s cn58xx; 1071 struct cvmx_pci_cfg03_s cn58xxp1; 1072}; 1073typedef union cvmx_pci_cfg03 cvmx_pci_cfg03_t; 1074 1075/** 1076 * cvmx_pci_cfg04 1077 * 1078 * PCI_CFG04 = Fifth 32-bits of PCI config space (Base Address Register 0 - Low) 1079 * 1080 * Description: BAR0: 4KB 64-bit Prefetchable Memory Space 1081 * [0]: 0 (Memory Space) 1082 * [2:1]: 2 (64bit memory decoder) 1083 * [3]: 1 (Prefetchable) 1084 * [11:4]: RAZ (to imply 4KB space) 1085 * [31:12]: RW (User may define base address) 1086 */ 1087union cvmx_pci_cfg04 { 1088 uint32_t u32; 1089 struct cvmx_pci_cfg04_s { 1090#ifdef __BIG_ENDIAN_BITFIELD 1091 uint32_t lbase : 20; /**< Base Address[31:12] 1092 Base Address[30:12] read as zero if 1093 PCI_CTL_STATUS_2[BB0] is set (in pass 3+) */ 1094 uint32_t lbasez : 8; /**< Base Address[11:4] (Read as Zero) */ 1095 uint32_t pf : 1; /**< Prefetchable Space */ 1096 uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1097 uint32_t mspc : 1; /**< Memory Space Indicator */ 1098#else 1099 uint32_t mspc : 1; 1100 uint32_t typ : 2; 1101 uint32_t pf : 1; 1102 uint32_t lbasez : 8; 1103 uint32_t lbase : 20; 1104#endif 1105 } s; 1106 struct cvmx_pci_cfg04_s cn30xx; 1107 struct cvmx_pci_cfg04_s cn31xx; 1108 struct cvmx_pci_cfg04_s cn38xx; 1109 struct cvmx_pci_cfg04_s cn38xxp2; 1110 struct cvmx_pci_cfg04_s cn50xx; 1111 struct cvmx_pci_cfg04_s cn58xx; 1112 struct cvmx_pci_cfg04_s cn58xxp1; 1113}; 1114typedef union cvmx_pci_cfg04 cvmx_pci_cfg04_t; 1115 1116/** 1117 * cvmx_pci_cfg05 1118 * 1119 * PCI_CFG05 = Sixth 32-bits of PCI config space (Base Address Register 0 - High) 1120 * 1121 */ 1122union cvmx_pci_cfg05 { 1123 uint32_t u32; 1124 struct cvmx_pci_cfg05_s { 1125#ifdef __BIG_ENDIAN_BITFIELD 1126 uint32_t hbase : 32; /**< Base Address[63:32] */ 1127#else 1128 uint32_t hbase : 32; 1129#endif 1130 } s; 1131 struct cvmx_pci_cfg05_s cn30xx; 1132 struct cvmx_pci_cfg05_s cn31xx; 1133 struct cvmx_pci_cfg05_s cn38xx; 1134 struct cvmx_pci_cfg05_s cn38xxp2; 1135 struct cvmx_pci_cfg05_s cn50xx; 1136 struct cvmx_pci_cfg05_s cn58xx; 1137 struct cvmx_pci_cfg05_s cn58xxp1; 1138}; 1139typedef union cvmx_pci_cfg05 cvmx_pci_cfg05_t; 1140 1141/** 1142 * cvmx_pci_cfg06 1143 * 1144 * PCI_CFG06 = Seventh 32-bits of PCI config space (Base Address Register 1 - Low) 1145 * 1146 * Description: BAR1: 128MB 64-bit Prefetchable Memory Space 1147 * [0]: 0 (Memory Space) 1148 * [2:1]: 2 (64bit memory decoder) 1149 * [3]: 1 (Prefetchable) 1150 * [26:4]: RAZ (to imply 128MB space) 1151 * [31:27]: RW (User may define base address) 1152 */ 1153union cvmx_pci_cfg06 { 1154 uint32_t u32; 1155 struct cvmx_pci_cfg06_s { 1156#ifdef __BIG_ENDIAN_BITFIELD 1157 uint32_t lbase : 5; /**< Base Address[31:27] 1158 In pass 3+: 1159 Base Address[29:27] read as zero if 1160 PCI_CTL_STATUS_2[BB1] is set 1161 Base Address[30] reads as zero if 1162 PCI_CTL_STATUS_2[BB1] is set and 1163 PCI_CTL_STATUS_2[BB1_SIZE] is set */ 1164 uint32_t lbasez : 23; /**< Base Address[26:4] (Read as Zero) */ 1165 uint32_t pf : 1; /**< Prefetchable Space */ 1166 uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1167 uint32_t mspc : 1; /**< Memory Space Indicator */ 1168#else 1169 uint32_t mspc : 1; 1170 uint32_t typ : 2; 1171 uint32_t pf : 1; 1172 uint32_t lbasez : 23; 1173 uint32_t lbase : 5; 1174#endif 1175 } s; 1176 struct cvmx_pci_cfg06_s cn30xx; 1177 struct cvmx_pci_cfg06_s cn31xx; 1178 struct cvmx_pci_cfg06_s cn38xx; 1179 struct cvmx_pci_cfg06_s cn38xxp2; 1180 struct cvmx_pci_cfg06_s cn50xx; 1181 struct cvmx_pci_cfg06_s cn58xx; 1182 struct cvmx_pci_cfg06_s cn58xxp1; 1183}; 1184typedef union cvmx_pci_cfg06 cvmx_pci_cfg06_t; 1185 1186/** 1187 * cvmx_pci_cfg07 1188 * 1189 * PCI_CFG07 = Eighth 32-bits of PCI config space (Base Address Register 1 - High) 1190 * 1191 */ 1192union cvmx_pci_cfg07 { 1193 uint32_t u32; 1194 struct cvmx_pci_cfg07_s { 1195#ifdef __BIG_ENDIAN_BITFIELD 1196 uint32_t hbase : 32; /**< Base Address[63:32] */ 1197#else 1198 uint32_t hbase : 32; 1199#endif 1200 } s; 1201 struct cvmx_pci_cfg07_s cn30xx; 1202 struct cvmx_pci_cfg07_s cn31xx; 1203 struct cvmx_pci_cfg07_s cn38xx; 1204 struct cvmx_pci_cfg07_s cn38xxp2; 1205 struct cvmx_pci_cfg07_s cn50xx; 1206 struct cvmx_pci_cfg07_s cn58xx; 1207 struct cvmx_pci_cfg07_s cn58xxp1; 1208}; 1209typedef union cvmx_pci_cfg07 cvmx_pci_cfg07_t; 1210 1211/** 1212 * cvmx_pci_cfg08 1213 * 1214 * PCI_CFG08 = Ninth 32-bits of PCI config space (Base Address Register 2 - Low) 1215 * 1216 * Description: BAR1: 2^39 (512GB) 64-bit Prefetchable Memory Space 1217 * [0]: 0 (Memory Space) 1218 * [2:1]: 2 (64bit memory decoder) 1219 * [3]: 1 (Prefetchable) 1220 * [31:4]: RAZ 1221 */ 1222union cvmx_pci_cfg08 { 1223 uint32_t u32; 1224 struct cvmx_pci_cfg08_s { 1225#ifdef __BIG_ENDIAN_BITFIELD 1226 uint32_t lbasez : 28; /**< Base Address[31:4] (Read as Zero) */ 1227 uint32_t pf : 1; /**< Prefetchable Space */ 1228 uint32_t typ : 2; /**< Type (00=32b/01=below 1MB/10=64b/11=RSV) */ 1229 uint32_t mspc : 1; /**< Memory Space Indicator */ 1230#else 1231 uint32_t mspc : 1; 1232 uint32_t typ : 2; 1233 uint32_t pf : 1; 1234 uint32_t lbasez : 28; 1235#endif 1236 } s; 1237 struct cvmx_pci_cfg08_s cn30xx; 1238 struct cvmx_pci_cfg08_s cn31xx; 1239 struct cvmx_pci_cfg08_s cn38xx; 1240 struct cvmx_pci_cfg08_s cn38xxp2; 1241 struct cvmx_pci_cfg08_s cn50xx; 1242 struct cvmx_pci_cfg08_s cn58xx; 1243 struct cvmx_pci_cfg08_s cn58xxp1; 1244}; 1245typedef union cvmx_pci_cfg08 cvmx_pci_cfg08_t; 1246 1247/** 1248 * cvmx_pci_cfg09 1249 * 1250 * PCI_CFG09 = Tenth 32-bits of PCI config space (Base Address Register 2 - High) 1251 * 1252 */ 1253union cvmx_pci_cfg09 { 1254 uint32_t u32; 1255 struct cvmx_pci_cfg09_s { 1256#ifdef __BIG_ENDIAN_BITFIELD 1257 uint32_t hbase : 25; /**< Base Address[63:39] */ 1258 uint32_t hbasez : 7; /**< Base Address[38:31] (Read as Zero) */ 1259#else 1260 uint32_t hbasez : 7; 1261 uint32_t hbase : 25; 1262#endif 1263 } s; 1264 struct cvmx_pci_cfg09_s cn30xx; 1265 struct cvmx_pci_cfg09_s cn31xx; 1266 struct cvmx_pci_cfg09_s cn38xx; 1267 struct cvmx_pci_cfg09_s cn38xxp2; 1268 struct cvmx_pci_cfg09_s cn50xx; 1269 struct cvmx_pci_cfg09_s cn58xx; 1270 struct cvmx_pci_cfg09_s cn58xxp1; 1271}; 1272typedef union cvmx_pci_cfg09 cvmx_pci_cfg09_t; 1273 1274/** 1275 * cvmx_pci_cfg10 1276 * 1277 * PCI_CFG10 = Eleventh 32-bits of PCI config space (Card Bus CIS Pointer) 1278 * 1279 */ 1280union cvmx_pci_cfg10 { 1281 uint32_t u32; 1282 struct cvmx_pci_cfg10_s { 1283#ifdef __BIG_ENDIAN_BITFIELD 1284 uint32_t cisp : 32; /**< CardBus CIS Pointer (UNUSED) */ 1285#else 1286 uint32_t cisp : 32; 1287#endif 1288 } s; 1289 struct cvmx_pci_cfg10_s cn30xx; 1290 struct cvmx_pci_cfg10_s cn31xx; 1291 struct cvmx_pci_cfg10_s cn38xx; 1292 struct cvmx_pci_cfg10_s cn38xxp2; 1293 struct cvmx_pci_cfg10_s cn50xx; 1294 struct cvmx_pci_cfg10_s cn58xx; 1295 struct cvmx_pci_cfg10_s cn58xxp1; 1296}; 1297typedef union cvmx_pci_cfg10 cvmx_pci_cfg10_t; 1298 1299/** 1300 * cvmx_pci_cfg11 1301 * 1302 * PCI_CFG11 = Twelfth 32-bits of PCI config space (SubSystem ID/Subsystem Vendor ID Register) 1303 * 1304 */ 1305union cvmx_pci_cfg11 { 1306 uint32_t u32; 1307 struct cvmx_pci_cfg11_s { 1308#ifdef __BIG_ENDIAN_BITFIELD 1309 uint32_t ssid : 16; /**< SubSystem ID */ 1310 uint32_t ssvid : 16; /**< Subsystem Vendor ID */ 1311#else 1312 uint32_t ssvid : 16; 1313 uint32_t ssid : 16; 1314#endif 1315 } s; 1316 struct cvmx_pci_cfg11_s cn30xx; 1317 struct cvmx_pci_cfg11_s cn31xx; 1318 struct cvmx_pci_cfg11_s cn38xx; 1319 struct cvmx_pci_cfg11_s cn38xxp2; 1320 struct cvmx_pci_cfg11_s cn50xx; 1321 struct cvmx_pci_cfg11_s cn58xx; 1322 struct cvmx_pci_cfg11_s cn58xxp1; 1323}; 1324typedef union cvmx_pci_cfg11 cvmx_pci_cfg11_t; 1325 1326/** 1327 * cvmx_pci_cfg12 1328 * 1329 * PCI_CFG12 = Thirteenth 32-bits of PCI config space (Expansion ROM Base Address Register) 1330 * 1331 */ 1332union cvmx_pci_cfg12 { 1333 uint32_t u32; 1334 struct cvmx_pci_cfg12_s { 1335#ifdef __BIG_ENDIAN_BITFIELD 1336 uint32_t erbar : 16; /**< Expansion ROM Base Address[31:16] 64KB in size */ 1337 uint32_t erbarz : 5; /**< Expansion ROM Base Base Address (Read as Zero) */ 1338 uint32_t reserved_1_10 : 10; 1339 uint32_t erbar_en : 1; /**< Expansion ROM Address Decode Enable */ 1340#else 1341 uint32_t erbar_en : 1; 1342 uint32_t reserved_1_10 : 10; 1343 uint32_t erbarz : 5; 1344 uint32_t erbar : 16; 1345#endif 1346 } s; 1347 struct cvmx_pci_cfg12_s cn30xx; 1348 struct cvmx_pci_cfg12_s cn31xx; 1349 struct cvmx_pci_cfg12_s cn38xx; 1350 struct cvmx_pci_cfg12_s cn38xxp2; 1351 struct cvmx_pci_cfg12_s cn50xx; 1352 struct cvmx_pci_cfg12_s cn58xx; 1353 struct cvmx_pci_cfg12_s cn58xxp1; 1354}; 1355typedef union cvmx_pci_cfg12 cvmx_pci_cfg12_t; 1356 1357/** 1358 * cvmx_pci_cfg13 1359 * 1360 * PCI_CFG13 = Fourteenth 32-bits of PCI config space (Capabilities Pointer Register) 1361 * 1362 */ 1363union cvmx_pci_cfg13 { 1364 uint32_t u32; 1365 struct cvmx_pci_cfg13_s { 1366#ifdef __BIG_ENDIAN_BITFIELD 1367 uint32_t reserved_8_31 : 24; 1368 uint32_t cp : 8; /**< Capabilities Pointer */ 1369#else 1370 uint32_t cp : 8; 1371 uint32_t reserved_8_31 : 24; 1372#endif 1373 } s; 1374 struct cvmx_pci_cfg13_s cn30xx; 1375 struct cvmx_pci_cfg13_s cn31xx; 1376 struct cvmx_pci_cfg13_s cn38xx; 1377 struct cvmx_pci_cfg13_s cn38xxp2; 1378 struct cvmx_pci_cfg13_s cn50xx; 1379 struct cvmx_pci_cfg13_s cn58xx; 1380 struct cvmx_pci_cfg13_s cn58xxp1; 1381}; 1382typedef union cvmx_pci_cfg13 cvmx_pci_cfg13_t; 1383 1384/** 1385 * cvmx_pci_cfg15 1386 * 1387 * PCI_CFG15 = Sixteenth 32-bits of PCI config space (INT/ARB/LATENCY Register) 1388 * 1389 */ 1390union cvmx_pci_cfg15 { 1391 uint32_t u32; 1392 struct cvmx_pci_cfg15_s { 1393#ifdef __BIG_ENDIAN_BITFIELD 1394 uint32_t ml : 8; /**< Maximum Latency */ 1395 uint32_t mg : 8; /**< Minimum Grant */ 1396 uint32_t inta : 8; /**< Interrupt Pin (INTA#) */ 1397 uint32_t il : 8; /**< Interrupt Line */ 1398#else 1399 uint32_t il : 8; 1400 uint32_t inta : 8; 1401 uint32_t mg : 8; 1402 uint32_t ml : 8; 1403#endif 1404 } s; 1405 struct cvmx_pci_cfg15_s cn30xx; 1406 struct cvmx_pci_cfg15_s cn31xx; 1407 struct cvmx_pci_cfg15_s cn38xx; 1408 struct cvmx_pci_cfg15_s cn38xxp2; 1409 struct cvmx_pci_cfg15_s cn50xx; 1410 struct cvmx_pci_cfg15_s cn58xx; 1411 struct cvmx_pci_cfg15_s cn58xxp1; 1412}; 1413typedef union cvmx_pci_cfg15 cvmx_pci_cfg15_t; 1414 1415/** 1416 * cvmx_pci_cfg16 1417 * 1418 * PCI_CFG16 = Seventeenth 32-bits of PCI config space (Target Implementation Register) 1419 * 1420 */ 1421union cvmx_pci_cfg16 { 1422 uint32_t u32; 1423 struct cvmx_pci_cfg16_s { 1424#ifdef __BIG_ENDIAN_BITFIELD 1425 uint32_t trdnpr : 1; /**< Target Read Delayed Transaction for I/O and 1426 non-prefetchable regions discarded. */ 1427 uint32_t trdard : 1; /**< Target Read Delayed Transaction for all regions 1428 discarded. */ 1429 uint32_t rdsati : 1; /**< Target(I/O and Memory) Read Delayed/Split at 1430 timeout/immediately (default timeout). 1431 Note: OCTEON requires that this bit MBZ(must be zero). */ 1432 uint32_t trdrs : 1; /**< Target(I/O and Memory) Read Delayed/Split or Retry 1433 select (of the application interface is not ready) 1434 0 = Delayed Split Transaction 1435 1 = Retry Transaction (always Immediate Retry, no 1436 AT_REQ to application). */ 1437 uint32_t trtae : 1; /**< Target(I/O and Memory) Read Target Abort Enable 1438 (if application interface is not ready at the 1439 latency timeout). 1440 Note: OCTEON as target will never target-abort, 1441 therefore this bit should never be set. */ 1442 uint32_t twsei : 1; /**< Target(I/O) Write Split Enable (at timeout / 1443 immediately; default timeout) */ 1444 uint32_t twsen : 1; /**< T(I/O) write split Enable (if the application 1445 interface is not ready) */ 1446 uint32_t twtae : 1; /**< Target(I/O and Memory) Write Target Abort Enable 1447 (if the application interface is not ready at the 1448 start of the cycle). 1449 Note: OCTEON as target will never target-abort, 1450 therefore this bit should never be set. */ 1451 uint32_t tmae : 1; /**< Target(Read/Write) Master Abort Enable; check 1452 at the start of each transaction. 1453 Note: This bit can be used to force a Master 1454 Abort when OCTEON is acting as the intended target 1455 device. */ 1456 uint32_t tslte : 3; /**< Target Subsequent(2nd-last) Latency Timeout Enable 1457 Valid range: [1..7] and 0=8. */ 1458 uint32_t tilt : 4; /**< Target Initial(1st data) Latency Timeout in PCI 1459 ModeValid range: [8..15] and 0=16. */ 1460 uint32_t pbe : 12; /**< Programmable Boundary Enable to disconnect/prefetch 1461 for target burst read cycles to prefetchable 1462 region in PCI. A value of 1 indicates end of 1463 boundary (64 KB down to 16 Bytes). */ 1464 uint32_t dppmr : 1; /**< Disconnect/Prefetch to prefetchable memory 1465 regions Enable. Prefetchable memory regions 1466 are always disconnected on a region boundary. 1467 Non-prefetchable regions for PCI are always 1468 disconnected on the first transfer. 1469 Note: OCTEON as target will never target-disconnect, 1470 therefore this bit should never be set. */ 1471 uint32_t reserved_2_2 : 1; 1472 uint32_t tswc : 1; /**< Target Split Write Control 1473 0 = Blocks all requests except PMW 1474 1 = Blocks all requests including PMW until 1475 split completion occurs. */ 1476 uint32_t mltd : 1; /**< Master Latency Timer Disable 1477 Note: For OCTEON, it is recommended that this bit 1478 be set(to disable the Master Latency timer). */ 1479#else 1480 uint32_t mltd : 1; 1481 uint32_t tswc : 1; 1482 uint32_t reserved_2_2 : 1; 1483 uint32_t dppmr : 1; 1484 uint32_t pbe : 12; 1485 uint32_t tilt : 4; 1486 uint32_t tslte : 3; 1487 uint32_t tmae : 1; 1488 uint32_t twtae : 1; 1489 uint32_t twsen : 1; 1490 uint32_t twsei : 1; 1491 uint32_t trtae : 1; 1492 uint32_t trdrs : 1; 1493 uint32_t rdsati : 1; 1494 uint32_t trdard : 1; 1495 uint32_t trdnpr : 1; 1496#endif 1497 } s; 1498 struct cvmx_pci_cfg16_s cn30xx; 1499 struct cvmx_pci_cfg16_s cn31xx; 1500 struct cvmx_pci_cfg16_s cn38xx; 1501 struct cvmx_pci_cfg16_s cn38xxp2; 1502 struct cvmx_pci_cfg16_s cn50xx; 1503 struct cvmx_pci_cfg16_s cn58xx; 1504 struct cvmx_pci_cfg16_s cn58xxp1; 1505}; 1506typedef union cvmx_pci_cfg16 cvmx_pci_cfg16_t; 1507 1508/** 1509 * cvmx_pci_cfg17 1510 * 1511 * PCI_CFG17 = Eighteenth 32-bits of PCI config space (Target Split Completion Message 1512 * Enable Register) 1513 */ 1514union cvmx_pci_cfg17 { 1515 uint32_t u32; 1516 struct cvmx_pci_cfg17_s { 1517#ifdef __BIG_ENDIAN_BITFIELD 1518 uint32_t tscme : 32; /**< Target Split Completion Message Enable 1519 [31:30]: 00 1520 [29]: Split Completion Error Indication 1521 [28]: 0 1522 [27:20]: Split Completion Message Index 1523 [19:0]: 0x00000 1524 For OCTEON, this register is intended for debug use 1525 only. (as such, it is recommended NOT to be written 1526 with anything other than ZEROES). */ 1527#else 1528 uint32_t tscme : 32; 1529#endif 1530 } s; 1531 struct cvmx_pci_cfg17_s cn30xx; 1532 struct cvmx_pci_cfg17_s cn31xx; 1533 struct cvmx_pci_cfg17_s cn38xx; 1534 struct cvmx_pci_cfg17_s cn38xxp2; 1535 struct cvmx_pci_cfg17_s cn50xx; 1536 struct cvmx_pci_cfg17_s cn58xx; 1537 struct cvmx_pci_cfg17_s cn58xxp1; 1538}; 1539typedef union cvmx_pci_cfg17 cvmx_pci_cfg17_t; 1540 1541/** 1542 * cvmx_pci_cfg18 1543 * 1544 * PCI_CFG18 = Nineteenth 32-bits of PCI config space (Target Delayed/Split Request 1545 * Pending Sequences) 1546 */ 1547union cvmx_pci_cfg18 { 1548 uint32_t u32; 1549 struct cvmx_pci_cfg18_s { 1550#ifdef __BIG_ENDIAN_BITFIELD 1551 uint32_t tdsrps : 32; /**< Target Delayed/Split Request Pending Sequences 1552 The application uses this address to remove a 1553 pending split sequence from the target queue by 1554 clearing the appropriate bit. Example: Clearing [14] 1555 clears the pending sequence \#14. An application 1556 or configuration write to this address can clear this 1557 register. 1558 For OCTEON, this register is intended for debug use 1559 only and MUST NEVER be written with anything other 1560 than ZEROES. */ 1561#else 1562 uint32_t tdsrps : 32; 1563#endif 1564 } s; 1565 struct cvmx_pci_cfg18_s cn30xx; 1566 struct cvmx_pci_cfg18_s cn31xx; 1567 struct cvmx_pci_cfg18_s cn38xx; 1568 struct cvmx_pci_cfg18_s cn38xxp2; 1569 struct cvmx_pci_cfg18_s cn50xx; 1570 struct cvmx_pci_cfg18_s cn58xx; 1571 struct cvmx_pci_cfg18_s cn58xxp1; 1572}; 1573typedef union cvmx_pci_cfg18 cvmx_pci_cfg18_t; 1574 1575/** 1576 * cvmx_pci_cfg19 1577 * 1578 * PCI_CFG19 = Twentieth 32-bits of PCI config space (Master/Target Implementation Register) 1579 * 1580 */ 1581union cvmx_pci_cfg19 { 1582 uint32_t u32; 1583 struct cvmx_pci_cfg19_s { 1584#ifdef __BIG_ENDIAN_BITFIELD 1585 uint32_t mrbcm : 1; /**< Master Request (Memory Read) Byte Count/Byte 1586 Enable select. 1587 0 = Byte Enables valid. In PCI mode, a burst 1588 transaction cannot be performed using 1589 Memory Read command=4'h6. 1590 1 = DWORD Byte Count valid (default). In PCI 1591 Mode, the memory read byte enables are 1592 automatically generated by the core. 1593 NOTE: For OCTEON, this bit must always be one 1594 for proper operation. */ 1595 uint32_t mrbci : 1; /**< Master Request (I/O and CR cycles) byte count/byte 1596 enable select. 1597 0 = Byte Enables valid (default) 1598 1 = DWORD byte count valid 1599 NOTE: For OCTEON, this bit must always be zero 1600 for proper operation (in support of 1601 Type0/1 Cfg Space accesses which require byte 1602 enable generation directly from a read mask). */ 1603 uint32_t mdwe : 1; /**< Master (Retry) Deferred Write Enable (allow 1604 read requests to pass). 1605 NOTE: Applicable to PCI Mode I/O and memory 1606 transactions only. 1607 0 = New read requests are NOT accepted until 1608 the current write cycle completes. [Reads 1609 cannot pass writes] 1610 1 = New read requests are accepted, even when 1611 there is a write cycle pending [Reads can 1612 pass writes]. 1613 NOTE: For OCTEON, this bit must always be zero 1614 for proper operation. */ 1615 uint32_t mdre : 1; /**< Master (Retry) Deferred Read Enable (Allows 1616 read/write requests to pass). 1617 NOTE: Applicable to PCI mode I/O and memory 1618 transactions only. 1619 0 = New read/write requests are NOT accepted 1620 until the current read cycle completes. 1621 [Read/write requests CANNOT pass reads] 1622 1 = New read/write requests are accepted, even 1623 when there is a read cycle pending. 1624 [Read/write requests CAN pass reads] 1625 NOTE: For OCTEON, this bit must always be zero 1626 for proper operation. */ 1627 uint32_t mdrimc : 1; /**< Master I/O Deferred/Split Request Outstanding 1628 Maximum Count 1629 0 = MDRRMC[26:24] 1630 1 = 1 */ 1631 uint32_t mdrrmc : 3; /**< Master Deferred Read Request Outstanding Max 1632 Count (PCI only). 1633 CR4C[26:24] Max SAC cycles MAX DAC cycles 1634 000 8 4 1635 001 1 0 1636 010 2 1 1637 011 3 1 1638 100 4 2 1639 101 5 2 1640 110 6 3 1641 111 7 3 1642 For example, if these bits are programmed to 1643 100, the core can support 2 DAC cycles, 4 SAC 1644 cycles or a combination of 1 DAC and 2 SAC cycles. 1645 NOTE: For the PCI-X maximum outstanding split 1646 transactions, refer to CRE0[22:20] */ 1647 uint32_t tmes : 8; /**< Target/Master Error Sequence \# */ 1648 uint32_t teci : 1; /**< Target Error Command Indication 1649 0 = Delayed/Split 1650 1 = Others */ 1651 uint32_t tmei : 1; /**< Target/Master Error Indication 1652 0 = Target 1653 1 = Master */ 1654 uint32_t tmse : 1; /**< Target/Master System Error. This bit is set 1655 whenever ATM_SERR_O is active. */ 1656 uint32_t tmdpes : 1; /**< Target/Master Data PERR# error status. This 1657 bit is set whenever ATM_DATA_PERR_O is active. */ 1658 uint32_t tmapes : 1; /**< Target/Master Address PERR# error status. This 1659 bit is set whenever ATM_ADDR_PERR_O is active. */ 1660 uint32_t reserved_9_10 : 2; 1661 uint32_t tibcd : 1; /**< Target Illegal I/O DWORD byte combinations detected. */ 1662 uint32_t tibde : 1; /**< Target Illegal I/O DWORD byte detection enable */ 1663 uint32_t reserved_6_6 : 1; 1664 uint32_t tidomc : 1; /**< Target I/O Delayed/Split request outstanding 1665 maximum count. 1666 0 = TDOMC[4:0] 1667 1 = 1 */ 1668 uint32_t tdomc : 5; /**< Target Delayed/Split request outstanding maximum 1669 count. [1..31] and 0=32. 1670 NOTE: If the user programs these bits beyond the 1671 Designed Maximum outstanding count, then the 1672 designed maximum table depth will be used instead. 1673 No additional Deferred/Split transactions will be 1674 accepted if this outstanding maximum count 1675 is reached. Furthermore, no additional 1676 deferred/split transactions will be accepted if 1677 the I/O delay/ I/O Split Request outstanding 1678 maximum is reached. 1679 NOTE: For OCTEON in PCI Mode, this field MUST BE 1680 programmed to 1. (OCTEON can only handle 1 delayed 1681 read at a time). 1682 For OCTEON in PCIX Mode, this field can range from 1683 1-4. (The designed maximum table depth is 4 1684 for PCIX mode splits). */ 1685#else 1686 uint32_t tdomc : 5; 1687 uint32_t tidomc : 1; 1688 uint32_t reserved_6_6 : 1; 1689 uint32_t tibde : 1; 1690 uint32_t tibcd : 1; 1691 uint32_t reserved_9_10 : 2; 1692 uint32_t tmapes : 1; 1693 uint32_t tmdpes : 1; 1694 uint32_t tmse : 1; 1695 uint32_t tmei : 1; 1696 uint32_t teci : 1; 1697 uint32_t tmes : 8; 1698 uint32_t mdrrmc : 3; 1699 uint32_t mdrimc : 1; 1700 uint32_t mdre : 1; 1701 uint32_t mdwe : 1; 1702 uint32_t mrbci : 1; 1703 uint32_t mrbcm : 1; 1704#endif 1705 } s; 1706 struct cvmx_pci_cfg19_s cn30xx; 1707 struct cvmx_pci_cfg19_s cn31xx; 1708 struct cvmx_pci_cfg19_s cn38xx; 1709 struct cvmx_pci_cfg19_s cn38xxp2; 1710 struct cvmx_pci_cfg19_s cn50xx; 1711 struct cvmx_pci_cfg19_s cn58xx; 1712 struct cvmx_pci_cfg19_s cn58xxp1; 1713}; 1714typedef union cvmx_pci_cfg19 cvmx_pci_cfg19_t; 1715 1716/** 1717 * cvmx_pci_cfg20 1718 * 1719 * PCI_CFG20 = Twenty-first 32-bits of PCI config space (Master Deferred/Split Sequence Pending) 1720 * 1721 */ 1722union cvmx_pci_cfg20 { 1723 uint32_t u32; 1724 struct cvmx_pci_cfg20_s { 1725#ifdef __BIG_ENDIAN_BITFIELD 1726 uint32_t mdsp : 32; /**< Master Deferred/Split sequence Pending 1727 For OCTEON, this register is intended for debug use 1728 only and MUST NEVER be written with anything other 1729 than ZEROES. */ 1730#else 1731 uint32_t mdsp : 32; 1732#endif 1733 } s; 1734 struct cvmx_pci_cfg20_s cn30xx; 1735 struct cvmx_pci_cfg20_s cn31xx; 1736 struct cvmx_pci_cfg20_s cn38xx; 1737 struct cvmx_pci_cfg20_s cn38xxp2; 1738 struct cvmx_pci_cfg20_s cn50xx; 1739 struct cvmx_pci_cfg20_s cn58xx; 1740 struct cvmx_pci_cfg20_s cn58xxp1; 1741}; 1742typedef union cvmx_pci_cfg20 cvmx_pci_cfg20_t; 1743 1744/** 1745 * cvmx_pci_cfg21 1746 * 1747 * PCI_CFG21 = Twenty-second 32-bits of PCI config space (Master Split Completion Message Register) 1748 * 1749 */ 1750union cvmx_pci_cfg21 { 1751 uint32_t u32; 1752 struct cvmx_pci_cfg21_s { 1753#ifdef __BIG_ENDIAN_BITFIELD 1754 uint32_t scmre : 32; /**< Master Split Completion message received with 1755 error message. 1756 For OCTEON, this register is intended for debug use 1757 only and MUST NEVER be written with anything other 1758 than ZEROES. */ 1759#else 1760 uint32_t scmre : 32; 1761#endif 1762 } s; 1763 struct cvmx_pci_cfg21_s cn30xx; 1764 struct cvmx_pci_cfg21_s cn31xx; 1765 struct cvmx_pci_cfg21_s cn38xx; 1766 struct cvmx_pci_cfg21_s cn38xxp2; 1767 struct cvmx_pci_cfg21_s cn50xx; 1768 struct cvmx_pci_cfg21_s cn58xx; 1769 struct cvmx_pci_cfg21_s cn58xxp1; 1770}; 1771typedef union cvmx_pci_cfg21 cvmx_pci_cfg21_t; 1772 1773/** 1774 * cvmx_pci_cfg22 1775 * 1776 * PCI_CFG22 = Twenty-third 32-bits of PCI config space (Master Arbiter Control Register) 1777 * 1778 */ 1779union cvmx_pci_cfg22 { 1780 uint32_t u32; 1781 struct cvmx_pci_cfg22_s { 1782#ifdef __BIG_ENDIAN_BITFIELD 1783 uint32_t mac : 7; /**< Master Arbiter Control 1784 [31:26]: Used only in Fixed Priority mode 1785 (when [25]=1) 1786 [31:30]: MSI Request 1787 00 = Highest Priority 1788 01 = Medium Priority 1789 10 = Lowest Priority 1790 11 = RESERVED 1791 [29:28]: Target Split Completion 1792 00 = Highest Priority 1793 01 = Medium Priority 1794 10 = Lowest Priority 1795 11 = RESERVED 1796 [27:26]: New Request; Deferred Read,Deferred Write 1797 00 = Highest Priority 1798 01 = Medium Priority 1799 10 = Lowest Priority 1800 11 = RESERVED 1801 [25]: Fixed/Round Robin Priority Selector 1802 0 = Round Robin 1803 1 = Fixed 1804 NOTE: When [25]=1(fixed priority), the three levels 1805 [31:26] MUST BE programmed to have mutually exclusive 1806 priority levels for proper operation. (Failure to do 1807 so may result in PCI hangs). */ 1808 uint32_t reserved_19_24 : 6; 1809 uint32_t flush : 1; /**< AM_DO_FLUSH_I control 1810 NOTE: This bit MUST BE ONE for proper OCTEON operation */ 1811 uint32_t mra : 1; /**< Master Retry Aborted */ 1812 uint32_t mtta : 1; /**< Master TRDY timeout aborted */ 1813 uint32_t mrv : 8; /**< Master Retry Value [1..255] and 0=infinite */ 1814 uint32_t mttv : 8; /**< Master TRDY timeout value [1..255] and 0=disabled 1815 NOTE: For OCTEON, this bit must always be zero 1816 for proper operation. (OCTEON does not support 1817 master TRDY timeout - target is expected to be 1818 well behaved). */ 1819#else 1820 uint32_t mttv : 8; 1821 uint32_t mrv : 8; 1822 uint32_t mtta : 1; 1823 uint32_t mra : 1; 1824 uint32_t flush : 1; 1825 uint32_t reserved_19_24 : 6; 1826 uint32_t mac : 7; 1827#endif 1828 } s; 1829 struct cvmx_pci_cfg22_s cn30xx; 1830 struct cvmx_pci_cfg22_s cn31xx; 1831 struct cvmx_pci_cfg22_s cn38xx; 1832 struct cvmx_pci_cfg22_s cn38xxp2; 1833 struct cvmx_pci_cfg22_s cn50xx; 1834 struct cvmx_pci_cfg22_s cn58xx; 1835 struct cvmx_pci_cfg22_s cn58xxp1; 1836}; 1837typedef union cvmx_pci_cfg22 cvmx_pci_cfg22_t; 1838 1839/** 1840 * cvmx_pci_cfg56 1841 * 1842 * PCI_CFG56 = Fifty-seventh 32-bits of PCI config space (PCIX Capabilities Register) 1843 * 1844 */ 1845union cvmx_pci_cfg56 { 1846 uint32_t u32; 1847 struct cvmx_pci_cfg56_s { 1848#ifdef __BIG_ENDIAN_BITFIELD 1849 uint32_t reserved_23_31 : 9; 1850 uint32_t most : 3; /**< Maximum outstanding Split transactions 1851 Encoded Value \#Max outstanding splits 1852 000 1 1853 001 2 1854 010 3 1855 011 4 1856 100 8 1857 101 8(clamped) 1858 110 8(clamped) 1859 111 8(clamped) 1860 NOTE: OCTEON only supports upto a MAXIMUM of 8 1861 outstanding master split transactions. */ 1862 uint32_t mmbc : 2; /**< Maximum Memory Byte Count 1863 [0=512B,1=1024B,2=2048B,3=4096B] 1864 NOTE: OCTEON does not support this field and has 1865 no effect on limiting the maximum memory byte count. */ 1866 uint32_t roe : 1; /**< Relaxed Ordering Enable */ 1867 uint32_t dpere : 1; /**< Data Parity Error Recovery Enable */ 1868 uint32_t ncp : 8; /**< Next Capability Pointer */ 1869 uint32_t pxcid : 8; /**< PCI-X Capability ID */ 1870#else 1871 uint32_t pxcid : 8; 1872 uint32_t ncp : 8; 1873 uint32_t dpere : 1; 1874 uint32_t roe : 1; 1875 uint32_t mmbc : 2; 1876 uint32_t most : 3; 1877 uint32_t reserved_23_31 : 9; 1878#endif 1879 } s; 1880 struct cvmx_pci_cfg56_s cn30xx; 1881 struct cvmx_pci_cfg56_s cn31xx; 1882 struct cvmx_pci_cfg56_s cn38xx; 1883 struct cvmx_pci_cfg56_s cn38xxp2; 1884 struct cvmx_pci_cfg56_s cn50xx; 1885 struct cvmx_pci_cfg56_s cn58xx; 1886 struct cvmx_pci_cfg56_s cn58xxp1; 1887}; 1888typedef union cvmx_pci_cfg56 cvmx_pci_cfg56_t; 1889 1890/** 1891 * cvmx_pci_cfg57 1892 * 1893 * PCI_CFG57 = Fifty-eigth 32-bits of PCI config space (PCIX Status Register) 1894 * 1895 */ 1896union cvmx_pci_cfg57 { 1897 uint32_t u32; 1898 struct cvmx_pci_cfg57_s { 1899#ifdef __BIG_ENDIAN_BITFIELD 1900 uint32_t reserved_30_31 : 2; 1901 uint32_t scemr : 1; /**< Split Completion Error Message Received */ 1902 uint32_t mcrsd : 3; /**< Maximum Cumulative Read Size designed */ 1903 uint32_t mostd : 3; /**< Maximum Outstanding Split transaction designed */ 1904 uint32_t mmrbcd : 2; /**< Maximum Memory Read byte count designed */ 1905 uint32_t dc : 1; /**< Device Complexity 1906 0 = Simple Device 1907 1 = Bridge Device */ 1908 uint32_t usc : 1; /**< Unexpected Split Completion */ 1909 uint32_t scd : 1; /**< Split Completion Discarded */ 1910 uint32_t m133 : 1; /**< 133MHz Capable */ 1911 uint32_t w64 : 1; /**< Indicates a 32b(=0) or 64b(=1) device */ 1912 uint32_t bn : 8; /**< Bus Number. Updated on all configuration write 1913 (0x11=PCI) cycles. Its value is dependent upon the PCI/X 1914 (0xFF=PCIX) mode. */ 1915 uint32_t dn : 5; /**< Device Number. Updated on all configuration 1916 write cycles. */ 1917 uint32_t fn : 3; /**< Function Number */ 1918#else 1919 uint32_t fn : 3; 1920 uint32_t dn : 5; 1921 uint32_t bn : 8; 1922 uint32_t w64 : 1; 1923 uint32_t m133 : 1; 1924 uint32_t scd : 1; 1925 uint32_t usc : 1; 1926 uint32_t dc : 1; 1927 uint32_t mmrbcd : 2; 1928 uint32_t mostd : 3; 1929 uint32_t mcrsd : 3; 1930 uint32_t scemr : 1; 1931 uint32_t reserved_30_31 : 2; 1932#endif 1933 } s; 1934 struct cvmx_pci_cfg57_s cn30xx; 1935 struct cvmx_pci_cfg57_s cn31xx; 1936 struct cvmx_pci_cfg57_s cn38xx; 1937 struct cvmx_pci_cfg57_s cn38xxp2; 1938 struct cvmx_pci_cfg57_s cn50xx; 1939 struct cvmx_pci_cfg57_s cn58xx; 1940 struct cvmx_pci_cfg57_s cn58xxp1; 1941}; 1942typedef union cvmx_pci_cfg57 cvmx_pci_cfg57_t; 1943 1944/** 1945 * cvmx_pci_cfg58 1946 * 1947 * PCI_CFG58 = Fifty-ninth 32-bits of PCI config space (Power Management Capabilities Register) 1948 * 1949 */ 1950union cvmx_pci_cfg58 { 1951 uint32_t u32; 1952 struct cvmx_pci_cfg58_s { 1953#ifdef __BIG_ENDIAN_BITFIELD 1954 uint32_t pmes : 5; /**< PME Support (D0 to D3cold) */ 1955 uint32_t d2s : 1; /**< D2_Support */ 1956 uint32_t d1s : 1; /**< D1_Support */ 1957 uint32_t auxc : 3; /**< AUX_Current (0..375mA) */ 1958 uint32_t dsi : 1; /**< Device Specific Initialization */ 1959 uint32_t reserved_20_20 : 1; 1960 uint32_t pmec : 1; /**< PME Clock */ 1961 uint32_t pcimiv : 3; /**< Indicates the version of the PCI 1962 Management 1963 Interface Specification with which the core 1964 complies. 1965 010b = Complies with PCI Management Interface 1966 Specification Revision 1.1 */ 1967 uint32_t ncp : 8; /**< Next Capability Pointer */ 1968 uint32_t pmcid : 8; /**< Power Management Capability ID */ 1969#else 1970 uint32_t pmcid : 8; 1971 uint32_t ncp : 8; 1972 uint32_t pcimiv : 3; 1973 uint32_t pmec : 1; 1974 uint32_t reserved_20_20 : 1; 1975 uint32_t dsi : 1; 1976 uint32_t auxc : 3; 1977 uint32_t d1s : 1; 1978 uint32_t d2s : 1; 1979 uint32_t pmes : 5; 1980#endif 1981 } s; 1982 struct cvmx_pci_cfg58_s cn30xx; 1983 struct cvmx_pci_cfg58_s cn31xx; 1984 struct cvmx_pci_cfg58_s cn38xx; 1985 struct cvmx_pci_cfg58_s cn38xxp2; 1986 struct cvmx_pci_cfg58_s cn50xx; 1987 struct cvmx_pci_cfg58_s cn58xx; 1988 struct cvmx_pci_cfg58_s cn58xxp1; 1989}; 1990typedef union cvmx_pci_cfg58 cvmx_pci_cfg58_t; 1991 1992/** 1993 * cvmx_pci_cfg59 1994 * 1995 * PCI_CFG59 = Sixtieth 32-bits of PCI config space (Power Management Data/PMCSR Register(s)) 1996 * 1997 */ 1998union cvmx_pci_cfg59 { 1999 uint32_t u32; 2000 struct cvmx_pci_cfg59_s { 2001#ifdef __BIG_ENDIAN_BITFIELD 2002 uint32_t pmdia : 8; /**< Power Management data input from application 2003 (PME_DATA) */ 2004 uint32_t bpccen : 1; /**< BPCC_En (bus power/clock control) enable */ 2005 uint32_t bd3h : 1; /**< B2_B3\#, B2/B3 Support for D3hot */ 2006 uint32_t reserved_16_21 : 6; 2007 uint32_t pmess : 1; /**< PME_Status sticky bit */ 2008 uint32_t pmedsia : 2; /**< PME_Data_Scale input from application 2009 Device (PME_DATA_SCALE[1:0]) 2010 Specific */ 2011 uint32_t pmds : 4; /**< Power Management Data_select */ 2012 uint32_t pmeens : 1; /**< PME_En sticky bit */ 2013 uint32_t reserved_2_7 : 6; 2014 uint32_t ps : 2; /**< Power State (D0 to D3) 2015 The N2 DOES NOT support D1/D2 Power Management 2016 states, therefore writing to this register has 2017 no effect (please refer to the PCI Power 2018 Management 2019 Specification v1.1 for further details about 2020 it?s R/W nature. This is not a conventional 2021 R/W style register. */ 2022#else 2023 uint32_t ps : 2; 2024 uint32_t reserved_2_7 : 6; 2025 uint32_t pmeens : 1; 2026 uint32_t pmds : 4; 2027 uint32_t pmedsia : 2; 2028 uint32_t pmess : 1; 2029 uint32_t reserved_16_21 : 6; 2030 uint32_t bd3h : 1; 2031 uint32_t bpccen : 1; 2032 uint32_t pmdia : 8; 2033#endif 2034 } s; 2035 struct cvmx_pci_cfg59_s cn30xx; 2036 struct cvmx_pci_cfg59_s cn31xx; 2037 struct cvmx_pci_cfg59_s cn38xx; 2038 struct cvmx_pci_cfg59_s cn38xxp2; 2039 struct cvmx_pci_cfg59_s cn50xx; 2040 struct cvmx_pci_cfg59_s cn58xx; 2041 struct cvmx_pci_cfg59_s cn58xxp1; 2042}; 2043typedef union cvmx_pci_cfg59 cvmx_pci_cfg59_t; 2044 2045/** 2046 * cvmx_pci_cfg60 2047 * 2048 * PCI_CFG60 = Sixty-first 32-bits of PCI config space (MSI Capabilities Register) 2049 * 2050 */ 2051union cvmx_pci_cfg60 { 2052 uint32_t u32; 2053 struct cvmx_pci_cfg60_s { 2054#ifdef __BIG_ENDIAN_BITFIELD 2055 uint32_t reserved_24_31 : 8; 2056 uint32_t m64 : 1; /**< 32/64 b message */ 2057 uint32_t mme : 3; /**< Multiple Message Enable(1,2,4,8,16,32) */ 2058 uint32_t mmc : 3; /**< Multiple Message Capable(0=1,1=2,2=4,3=8,4=16,5=32) */ 2059 uint32_t msien : 1; /**< MSI Enable */ 2060 uint32_t ncp : 8; /**< Next Capability Pointer */ 2061 uint32_t msicid : 8; /**< MSI Capability ID */ 2062#else 2063 uint32_t msicid : 8; 2064 uint32_t ncp : 8; 2065 uint32_t msien : 1; 2066 uint32_t mmc : 3; 2067 uint32_t mme : 3; 2068 uint32_t m64 : 1; 2069 uint32_t reserved_24_31 : 8; 2070#endif 2071 } s; 2072 struct cvmx_pci_cfg60_s cn30xx; 2073 struct cvmx_pci_cfg60_s cn31xx; 2074 struct cvmx_pci_cfg60_s cn38xx; 2075 struct cvmx_pci_cfg60_s cn38xxp2; 2076 struct cvmx_pci_cfg60_s cn50xx; 2077 struct cvmx_pci_cfg60_s cn58xx; 2078 struct cvmx_pci_cfg60_s cn58xxp1; 2079}; 2080typedef union cvmx_pci_cfg60 cvmx_pci_cfg60_t; 2081 2082/** 2083 * cvmx_pci_cfg61 2084 * 2085 * PCI_CFG61 = Sixty-second 32-bits of PCI config space (MSI Lower Address Register) 2086 * 2087 */ 2088union cvmx_pci_cfg61 { 2089 uint32_t u32; 2090 struct cvmx_pci_cfg61_s { 2091#ifdef __BIG_ENDIAN_BITFIELD 2092 uint32_t msi31t2 : 30; /**< App Specific MSI Address [31:2] */ 2093 uint32_t reserved_0_1 : 2; 2094#else 2095 uint32_t reserved_0_1 : 2; 2096 uint32_t msi31t2 : 30; 2097#endif 2098 } s; 2099 struct cvmx_pci_cfg61_s cn30xx; 2100 struct cvmx_pci_cfg61_s cn31xx; 2101 struct cvmx_pci_cfg61_s cn38xx; 2102 struct cvmx_pci_cfg61_s cn38xxp2; 2103 struct cvmx_pci_cfg61_s cn50xx; 2104 struct cvmx_pci_cfg61_s cn58xx; 2105 struct cvmx_pci_cfg61_s cn58xxp1; 2106}; 2107typedef union cvmx_pci_cfg61 cvmx_pci_cfg61_t; 2108 2109/** 2110 * cvmx_pci_cfg62 2111 * 2112 * PCI_CFG62 = Sixty-third 32-bits of PCI config space (MSI Upper Address Register) 2113 * 2114 */ 2115union cvmx_pci_cfg62 { 2116 uint32_t u32; 2117 struct cvmx_pci_cfg62_s { 2118#ifdef __BIG_ENDIAN_BITFIELD 2119 uint32_t msi : 32; /**< MSI Address [63:32] */ 2120#else 2121 uint32_t msi : 32; 2122#endif 2123 } s; 2124 struct cvmx_pci_cfg62_s cn30xx; 2125 struct cvmx_pci_cfg62_s cn31xx; 2126 struct cvmx_pci_cfg62_s cn38xx; 2127 struct cvmx_pci_cfg62_s cn38xxp2; 2128 struct cvmx_pci_cfg62_s cn50xx; 2129 struct cvmx_pci_cfg62_s cn58xx; 2130 struct cvmx_pci_cfg62_s cn58xxp1; 2131}; 2132typedef union cvmx_pci_cfg62 cvmx_pci_cfg62_t; 2133 2134/** 2135 * cvmx_pci_cfg63 2136 * 2137 * PCI_CFG63 = Sixty-fourth 32-bits of PCI config space (MSI Message Data Register) 2138 * 2139 */ 2140union cvmx_pci_cfg63 { 2141 uint32_t u32; 2142 struct cvmx_pci_cfg63_s { 2143#ifdef __BIG_ENDIAN_BITFIELD 2144 uint32_t reserved_16_31 : 16; 2145 uint32_t msimd : 16; /**< MSI Message Data */ 2146#else 2147 uint32_t msimd : 16; 2148 uint32_t reserved_16_31 : 16; 2149#endif 2150 } s; 2151 struct cvmx_pci_cfg63_s cn30xx; 2152 struct cvmx_pci_cfg63_s cn31xx; 2153 struct cvmx_pci_cfg63_s cn38xx; 2154 struct cvmx_pci_cfg63_s cn38xxp2; 2155 struct cvmx_pci_cfg63_s cn50xx; 2156 struct cvmx_pci_cfg63_s cn58xx; 2157 struct cvmx_pci_cfg63_s cn58xxp1; 2158}; 2159typedef union cvmx_pci_cfg63 cvmx_pci_cfg63_t; 2160 2161/** 2162 * cvmx_pci_cnt_reg 2163 * 2164 * PCI_CNT_REG = PCI Clock Count Register 2165 * 2166 * This register is provided to software as a means to determine PCI Bus Type/Speed. 2167 */ 2168union cvmx_pci_cnt_reg { 2169 uint64_t u64; 2170 struct cvmx_pci_cnt_reg_s { 2171#ifdef __BIG_ENDIAN_BITFIELD 2172 uint64_t reserved_38_63 : 26; 2173 uint64_t hm_pcix : 1; /**< PCI Host Mode Sampled Bus Type (0:PCI/1:PCIX) 2174 This field represents what OCTEON(in Host mode) 2175 sampled as the 'intended' PCI Bus Type based on 2176 the PCI_PCIXCAP pin. (see HM_SPEED Bus Type/Speed 2177 encoding table). */ 2178 uint64_t hm_speed : 2; /**< PCI Host Mode Sampled Bus Speed 2179 This field represents what OCTEON(in Host mode) 2180 sampled as the 'intended' PCI Bus Speed based on 2181 the PCI100, PCI_M66EN and PCI_PCIXCAP pins. 2182 NOTE: This DOES NOT reflect what the actual PCI 2183 Bus Type/Speed values are. They only indicate what 2184 OCTEON sampled as the 'intended' values. 2185 PCI Host Mode Sampled Bus Type/Speed Table: 2186 M66EN | PCIXCAP | PCI100 | HM_PCIX | HM_SPEED[1:0] 2187 ---------+---------+---------+----------+------------- 2188 0 | 0 | 0 | 0=PCI | 00=33 MHz 2189 0 | 0 | 1 | 0=PCI | 00=33 MHz 2190 0 | Z | 0 | 0=PCI | 01=66 MHz 2191 0 | Z | 1 | 0=PCI | 01=66 MHz 2192 1 | 0 | 0 | 0=PCI | 01=66 MHz 2193 1 | 0 | 1 | 0=PCI | 01=66 MHz 2194 1 | Z | 0 | 0=PCI | 01=66 MHz 2195 1 | Z | 1 | 0=PCI | 01=66 MHz 2196 0 | 1 | 1 | 1=PCIX | 10=100 MHz 2197 1 | 1 | 1 | 1=PCIX | 10=100 MHz 2198 0 | 1 | 0 | 1=PCIX | 11=133 MHz 2199 1 | 1 | 0 | 1=PCIX | 11=133 MHz 2200 NOTE: PCIXCAP has tri-level value (0,1,Z). See PCI specification 2201 for more details on board level hookup to achieve these 2202 values. 2203 NOTE: Software can use the NPI_PCI_INT_ARB_CFG[PCI_OVR] 2204 to override the 'sampled' PCI Bus Type/Speed. 2205 NOTE: Software can also use the PCI_CNT_REG[PCICNT] to determine 2206 the exact PCI(X) Bus speed. 2207 Example: PCI_REF_CLKIN=133MHz 2208 PCI_HOST_MODE=1 2209 PCI_M66EN=0 2210 PCI_PCIXCAP=1 2211 PCI_PCI100=1 2212 For this example, OCTEON will generate 2213 PCI_CLK_OUT=100MHz and drive the proper PCI 2214 Initialization sequence (DEVSEL#=Deasserted, 2215 STOP#=Asserted, TRDY#=Asserted) during PCI_RST_N 2216 deassertion. 2217 NOTE: The HM_SPEED field is only valid after 2218 PLL_REF_CLK is active and PLL_DCOK is asserted. 2219 (see HRM description for power-on/reset sequence). 2220 NOTE: PCI_REF_CLKIN input must be 133MHz (and is used 2221 to generate the PCI_CLK_OUT pin in Host Mode). */ 2222 uint64_t ap_pcix : 1; /**< PCI(X) Bus Type (0:PCI/1:PCIX) 2223 At PCI_RST_N de-assertion, the PCI Initialization 2224 pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is 2225 captured to provide information to software regarding 2226 the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. */ 2227 uint64_t ap_speed : 2; /**< PCI(X) Bus Speed (0:33/1:66/2:100/3:133) 2228 At PCI_RST_N de-assertion, the PCI Initialization 2229 pattern(PCI_DEVSEL_N, PCI_STOP_N, PCI_TRDY_N) is 2230 captured to provide information to software regarding 2231 the PCI Bus Type(PCI/PCIX) and PCI Bus Speed Range. 2232 PCI-X Initialization Pattern(see PCIX Spec): 2233 PCI_DEVSEL_N PCI_STOP_N PCI_TRDY_N Mode MaxClk(ns) MinClk(ns) MinClk(MHz) MaxClk(MHz) 2234 -------------+----------+----------+-------+---------+----------+----------+------------------ 2235 Deasserted Deasserted Deasserted PCI 33 -- 30 0 33 2236 PCI 66 30 15 33 66 2237 Deasserted Deasserted Asserted PCI-X 20 15 50 66 2238 Deasserted Asserted Deasserted PCI-X 15 10 66 100 2239 Deasserted Asserted Asserted PCI-X 10 7.5 100 133 2240 Asserted Deasserted Deasserted PCI-X Reserved Reserved Reserved Reserved 2241 Asserted Deasserted Asserted PCI-X Reserved Reserved Reserved Reserved 2242 Asserted Asserted Deasserted PCI-X Reserved Reserved Reserved Reserved 2243 Asserted Asserted Asserted PCI-X Reserved Reserved Reserved Reserved 2244 NOTE: The PCI Bus speed 'assumed' from the initialization 2245 pattern is really intended for an operational range. 2246 For example: If PINIT=100, this indicates PCI-X in the 2247 100-133MHz range. The PCI_CNT field can be used to further 2248 determine a more exacting PCI Bus frequency value if 2249 required. */ 2250 uint64_t pcicnt : 32; /**< Free Running PCI Clock counter. 2251 At PCI Reset, the PCICNT=0, and is auto-incremented 2252 on every PCI clock and will auto-wrap back to zero 2253 when saturated. 2254 NOTE: Writes override the auto-increment to allow 2255 software to preload any initial value. 2256 The PCICNT field is provided to software as a means 2257 to determine the PCI Bus Speed. 2258 Assuming software has knowledge of the core frequency 2259 (eclk), this register can be written with a value X, 2260 wait 'n' core clocks(eclk) and then read later(Y) to 2261 determine \#PCI clocks(Y-X) have elapsed within 'n' core 2262 clocks to determine the PCI input Clock frequency. */ 2263#else 2264 uint64_t pcicnt : 32; 2265 uint64_t ap_speed : 2; 2266 uint64_t ap_pcix : 1; 2267 uint64_t hm_speed : 2; 2268 uint64_t hm_pcix : 1; 2269 uint64_t reserved_38_63 : 26; 2270#endif 2271 } s; 2272 struct cvmx_pci_cnt_reg_s cn50xx; 2273 struct cvmx_pci_cnt_reg_s cn58xx; 2274 struct cvmx_pci_cnt_reg_s cn58xxp1; 2275}; 2276typedef union cvmx_pci_cnt_reg cvmx_pci_cnt_reg_t; 2277 2278/** 2279 * cvmx_pci_ctl_status_2 2280 * 2281 * PCI_CTL_STATUS_2 = PCI Control Status 2 Register 2282 * 2283 * Control status register accessable from both PCI and NCB. 2284 */ 2285union cvmx_pci_ctl_status_2 { 2286 uint32_t u32; 2287 struct cvmx_pci_ctl_status_2_s { 2288#ifdef __BIG_ENDIAN_BITFIELD 2289 uint32_t reserved_29_31 : 3; 2290 uint32_t bb1_hole : 3; /**< Big BAR 1 Hole 2291 NOT IN PASS 1 NOR PASS 2 2292 When PCI_CTL_STATUS_2[BB1]=1, this field defines 2293 an encoded size of the upper BAR1 region which 2294 OCTEON will mask out (ie: not respond to). 2295 (see definition of BB1_HOLE and BB1_SIZ encodings 2296 in the PCI_CTL_STATUS_2[BB1] definition below). */ 2297 uint32_t bb1_siz : 1; /**< Big BAR 1 Size 2298 NOT IN PASS 1 NOR PASS 2 2299 When PCI_CTL_STATUS_2[BB1]=1, this field defines 2300 the programmable SIZE of BAR 1. 2301 - 0: 1GB / 1: 2GB */ 2302 uint32_t bb_ca : 1; /**< Set to '1' for Big Bar Mode to do STT/LDT L2C 2303 operations. 2304 NOT IN PASS 1 NOR PASS 2 */ 2305 uint32_t bb_es : 2; /**< Big Bar Node Endian Swap Mode 2306 - 0: No Swizzle 2307 - 1: Byte Swizzle (per-QW) 2308 - 2: Byte Swizzle (per-LW) 2309 - 3: LongWord Swizzle 2310 NOT IN PASS 1 NOR PASS 2 */ 2311 uint32_t bb1 : 1; /**< Big Bar 1 Enable 2312 NOT IN PASS 1 NOR PASS 2 2313 When PCI_CTL_STATUS_2[BB1] is set, the following differences 2314 occur: 2315 - OCTEON's BAR1 becomes somewhere in the range 512-2048 MB rather 2316 than the default 128MB. 2317 - The following table indicates the effective size of 2318 BAR1 when BB1 is set: 2319 BB1_SIZ BB1_HOLE Effective size Comment 2320 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2321 0 0 1024 MB Normal 1GB BAR 2322 0 1 1008 MB 1 GB, 16 MB hole 2323 0 2 992 MB 1 GB, 32 MB hole 2324 0 3 960 MB 1 GB, 64 MB hole 2325 0 4 896 MB 1 GB,128 MB hole 2326 0 5 768 MB 1 GB,256 MB hole 2327 0 6 512 MB 1 GB,512 MB hole 2328 0 7 Illegal 2329 1 0 2048 MB Normal 2GB BAR 2330 1 1 2032 MB 2 GB, 16 MB hole 2331 1 2 2016 MB 2 GB, 32 MB hole 2332 1 3 1984 MB 2 GB, 64 MB hole 2333 1 4 1920 MB 2 GB,128 MB hole 2334 1 5 1792 MB 2 GB,256 MB hole 2335 1 6 1536 MB 2 GB,512 MB hole 2336 1 7 Illegal 2337 - When BB1_SIZ is 0: PCI_CFG06[LBASE<2:0>] reads as zero 2338 and are ignored on write. BAR1 is an entirely ordinary 2339 1 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0. 2340 When BB1_HOLE is not zero, BAR1 addresses are programmed 2341 as if the BAR were 1GB, but, OCTEON does not respond 2342 to addresses in the programmed holes. 2343 - When BB1_SIZ is 1: PCI_CFG06[LBASE<3:0>] reads as zero 2344 and are ignored on write. BAR1 is an entirely ordinary 2345 2 GB (power-of-two) BAR in all aspects when BB1_HOLE is 0. 2346 When BB1_HOLE is not zero, BAR1 addresses are programmed 2347 as if the BAR were 2GB, but, OCTEON does not respond 2348 to addresses in the programmed holes. 2349 - Note that the BB1_HOLE value has no effect on the 2350 PCI_CFG06[LBASE] behavior. BB1_HOLE only affects whether 2351 OCTEON accepts an address. BB1_SIZ does affect PCI_CFG06[LBASE] 2352 behavior, however. 2353 - The first 128MB, i.e. addresses on the PCI bus in the range 2354 BAR1+0 .. BAR1+0x07FFFFFF 2355 access OCTEON's DRAM addresses with PCI_BAR1_INDEX CSR's 2356 as before 2357 - The remaining address space, i.e. addresses 2358 on the PCI bus in the range 2359 BAR1+0x08000000 .. BAR1+size-1, 2360 where size is the size of BAR1 as selected by the above 2361 table (based on the BB1_SIZ and BB1_HOLE values), are mapped to 2362 OCTEON physical DRAM addresses as follows: 2363 PCI Address Range OCTEON Physical Address Range 2364 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2365 BAR1+0x08000000 .. BAR1+size-1 | 0x88000000 .. 0x7FFFFFFF+size 2366 and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and 2367 PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit 2368 for these references. 2369 The consequences of any burst that crosses the end of the PCI 2370 Address Range for BAR1 are unpredicable. 2371 - The consequences of any burst access that crosses the boundary 2372 between BAR1+0x07FFFFFF and BAR1+0x08000000 are unpredictable in PCI-X 2373 mode. OCTEON may disconnect PCI references at this boundary. */ 2374 uint32_t bb0 : 1; /**< Big Bar 0 Enable 2375 NOT IN PASS 1 NOR PASS 2 2376 When PCI_CTL_STATUS_2[BB0] is set, the following 2377 differences occur: 2378 - OCTEON's BAR0 becomes 2GB rather than the default 4KB. 2379 PCI_CFG04[LBASE<18:0>] reads as zero and is ignored on write. 2380 - OCTEON's BAR0 becomes burstable. (When BB0 is clear, OCTEON 2381 single-phase disconnects PCI BAR0 reads and PCI/PCI-X BAR0 2382 writes, and splits (burstably) PCI-X BAR0 reads.) 2383 - The first 4KB, i.e. addresses on the PCI bus in the range 2384 BAR0+0 .. BAR0+0xFFF 2385 access OCTEON's PCI-type CSR's as when BB0 is clear. 2386 - The remaining address space, i.e. addresses on the PCI bus 2387 in the range 2388 BAR0+0x1000 .. BAR0+0x7FFFFFFF 2389 are mapped to OCTEON physical DRAM addresses as follows: 2390 PCI Address Range OCTEON Physical Address Range 2391 ------------------------------------+------------------------------ 2392 BAR0+0x00001000 .. BAR0+0x0FFFFFFF | 0x000001000 .. 0x00FFFFFFF 2393 BAR0+0x10000000 .. BAR0+0x1FFFFFFF | 0x410000000 .. 0x41FFFFFFF 2394 BAR0+0x20000000 .. BAR0+0x7FFFFFFF | 0x020000000 .. 0x07FFFFFFF 2395 and PCI_CTL_STATUS_2[BB_ES] is the endian-swap and 2396 PCI_CTL_STATUS_2[BB_CA] is the L2 cache allocation bit 2397 for these references. 2398 The consequences of any burst that crosses the end of the PCI 2399 Address Range for BAR0 are unpredicable. 2400 - The consequences of any burst access that crosses the boundary 2401 between BAR0+0xFFF and BAR0+0x1000 are unpredictable in PCI-X 2402 mode. OCTEON may disconnect PCI references at this boundary. 2403 - The results of any burst read that crosses the boundary 2404 between BAR0+0x0FFFFFFF and BAR0+0x10000000 are unpredictable. 2405 The consequences of any burst write that crosses this same 2406 boundary are unpredictable. 2407 - The results of any burst read that crosses the boundary 2408 between BAR0+0x1FFFFFFF and BAR0+0x20000000 are unpredictable. 2409 The consequences of any burst write that crosses this same 2410 boundary are unpredictable. */ 2411 uint32_t erst_n : 1; /**< Reset active Low. PASS-2 */ 2412 uint32_t bar2pres : 1; /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN]) 2413 is NOT blown the value of this field is '0' after 2414 reset and BAR2 is NOT present. When the fuse IS 2415 blown the value of this field is '1' after reset 2416 and BAR2 is present. Note that SW can change this 2417 field after reset. This is a PASS-2 field. */ 2418 uint32_t scmtyp : 1; /**< Split Completion Message CMD Type (0=RD/1=WR) 2419 When SCM=1, SCMTYP specifies the CMD intent (R/W) */ 2420 uint32_t scm : 1; /**< Split Completion Message Detected (Read or Write) */ 2421 uint32_t en_wfilt : 1; /**< When '1' the window-access filter is enabled. 2422 Unfilter writes are: 2423 MIO, SubId0 2424 MIO, SubId7 2425 NPI, SubId0 2426 NPI, SubId7 2427 POW, SubId7 2428 DFA, SubId7 2429 IPD, SubId7 2430 Unfiltered Reads are: 2431 MIO, SubId0 2432 MIO, SubId7 2433 NPI, SubId0 2434 NPI, SubId7 2435 POW, SubId1 2436 POW, SubId2 2437 POW, SubId3 2438 POW, SubId7 2439 DFA, SubId7 2440 IPD, SubId7 */ 2441 uint32_t reserved_14_14 : 1; 2442 uint32_t ap_pcix : 1; /**< PCX Core Mode status (0=PCI Bus/1=PCIX) 2443 If one or more of PCI_DEVSEL_N, PCI_STOP_N, and 2444 PCI_TRDY_N are asserted at the rising edge of 2445 PCI_RST_N, the device enters PCI-X mode. 2446 Otherwise, the device enters conventional PCI 2447 mode at the rising edge of RST#. */ 2448 uint32_t ap_64ad : 1; /**< PCX Core Bus status (0=32b Bus/1=64b Bus) 2449 When PCI_RST_N pin is de-asserted, the state 2450 of PCI_REQ64_N(driven by central agent) determines 2451 the width of the PCI/X bus. */ 2452 uint32_t b12_bist : 1; /**< Bist Status For Memeory In B12 */ 2453 uint32_t pmo_amod : 1; /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */ 2454 uint32_t pmo_fpc : 3; /**< PMO-ARB Fixed Priority Counter 2455 When PMO_AMOD=0 (FP mode), this field represents 2456 the \# of CMD1 requests that are issued (at higher 2457 priority) before a single lower priority CMD0 2458 is allowed to issue (to ensure foward progress). 2459 - 0: 1 CMD1 Request issued before CMD0 allowed 2460 - ... 2461 - 7: 8 CMD1 Requests issued before CMD0 allowed */ 2462 uint32_t tsr_hwm : 3; /**< Target Split-Read ADB(allowable disconnect boundary) 2463 High Water Mark. 2464 Specifies the number of ADBs(128 Byte aligned chunks) 2465 that are accumulated(pending) BEFORE the Target Split 2466 completion is attempted on the PCI bus. 2467 - 0: RESERVED/ILLEGAL 2468 - 1: 2 Pending ADBs (129B-256B) 2469 - 2: 3 Pending ADBs (257B-384B) 2470 - 3: 4 Pending ADBs (385B-512B) 2471 - 4: 5 Pending ADBs (513B-640B) 2472 - 5: 6 Pending ADBs (641B-768B) 2473 - 6: 7 Pending ADBs (769B-896B) 2474 - 7: 8 Pending ADBs (897B-1024B) 2475 Example: Suppose a 1KB target memory request with 2476 starting byte offset address[6:0]=0x7F is split by 2477 the OCTEON and the TSR_HWM=1(2 ADBs). 2478 The OCTEON will start the target split completion 2479 on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B 2480 of data have been received from memory (even though 2481 the remaining 895B has not yet been received). The 2482 OCTEON will continue the split completion until it 2483 has consumed all of the pended split data. If the 2484 full transaction length(1KB) of data was NOT entirely 2485 transferred, then OCTEON will terminate the split 2486 completion and again wait for another 2 ADB-aligned data 2487 chunks(256B) of pended split data to be received from 2488 memory before starting another split completion request. 2489 This allows Octeon (as split completer), to send back 2490 multiple split completions for a given large split 2491 transaction without having to wait for the entire 2492 transaction length to be received from memory. 2493 NOTE: For split transaction sizes 'smaller' than the 2494 specified TSR_HWM value, the split completion 2495 is started when the last datum has been received from 2496 memory. 2497 NOTE: It is IMPERATIVE that this field NEVER BE 2498 written to a ZERO value. A value of zero is 2499 reserved/illegal and can result in PCIX bus hangs). */ 2500 uint32_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 2501 clear '0' BAR2 access will be target-aborted. */ 2502 uint32_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 2503 determine the endian swap mode. */ 2504 uint32_t bar2_cax : 1; /**< Value will be XORed with pci-address[38] to 2505 determine the L2 cache attribute. 2506 When XOR result is 1, not cached in L2 */ 2507#else 2508 uint32_t bar2_cax : 1; 2509 uint32_t bar2_esx : 2; 2510 uint32_t bar2_enb : 1; 2511 uint32_t tsr_hwm : 3; 2512 uint32_t pmo_fpc : 3; 2513 uint32_t pmo_amod : 1; 2514 uint32_t b12_bist : 1; 2515 uint32_t ap_64ad : 1; 2516 uint32_t ap_pcix : 1; 2517 uint32_t reserved_14_14 : 1; 2518 uint32_t en_wfilt : 1; 2519 uint32_t scm : 1; 2520 uint32_t scmtyp : 1; 2521 uint32_t bar2pres : 1; 2522 uint32_t erst_n : 1; 2523 uint32_t bb0 : 1; 2524 uint32_t bb1 : 1; 2525 uint32_t bb_es : 2; 2526 uint32_t bb_ca : 1; 2527 uint32_t bb1_siz : 1; 2528 uint32_t bb1_hole : 3; 2529 uint32_t reserved_29_31 : 3; 2530#endif 2531 } s; 2532 struct cvmx_pci_ctl_status_2_s cn30xx; 2533 struct cvmx_pci_ctl_status_2_cn31xx { 2534#ifdef __BIG_ENDIAN_BITFIELD 2535 uint32_t reserved_20_31 : 12; 2536 uint32_t erst_n : 1; /**< Reset active Low. */ 2537 uint32_t bar2pres : 1; /**< From fuse block. When fuse(MIO_FUS_DAT3[BAR2_EN]) 2538 is NOT blown the value of this field is '0' after 2539 reset and BAR2 is NOT present. When the fuse IS 2540 blown the value of this field is '1' after reset 2541 and BAR2 is present. Note that SW can change this 2542 field after reset. */ 2543 uint32_t scmtyp : 1; /**< Split Completion Message CMD Type (0=RD/1=WR) 2544 When SCM=1, SCMTYP specifies the CMD intent (R/W) */ 2545 uint32_t scm : 1; /**< Split Completion Message Detected (Read or Write) */ 2546 uint32_t en_wfilt : 1; /**< When '1' the window-access filter is enabled. 2547 Unfilter writes are: 2548 MIO, SubId0 2549 MIO, SubId7 2550 NPI, SubId0 2551 NPI, SubId7 2552 POW, SubId7 2553 DFA, SubId7 2554 IPD, SubId7 2555 USBN, SubId7 2556 Unfiltered Reads are: 2557 MIO, SubId0 2558 MIO, SubId7 2559 NPI, SubId0 2560 NPI, SubId7 2561 POW, SubId1 2562 POW, SubId2 2563 POW, SubId3 2564 POW, SubId7 2565 DFA, SubId7 2566 IPD, SubId7 2567 USBN, SubId7 */ 2568 uint32_t reserved_14_14 : 1; 2569 uint32_t ap_pcix : 1; /**< PCX Core Mode status (0=PCI Bus/1=PCIX) */ 2570 uint32_t ap_64ad : 1; /**< PCX Core Bus status (0=32b Bus/1=64b Bus) */ 2571 uint32_t b12_bist : 1; /**< Bist Status For Memeory In B12 */ 2572 uint32_t pmo_amod : 1; /**< PMO-ARB Mode (0=FP[HP=CMD1,LP=CMD0]/1=RR) */ 2573 uint32_t pmo_fpc : 3; /**< PMO-ARB Fixed Priority Counter 2574 When PMO_AMOD=0 (FP mode), this field represents 2575 the \# of CMD1 requests that are issued (at higher 2576 priority) before a single lower priority CMD0 2577 is allowed to issue (to ensure foward progress). 2578 - 0: 1 CMD1 Request issued before CMD0 allowed 2579 - ... 2580 - 7: 8 CMD1 Requests issued before CMD0 allowed */ 2581 uint32_t tsr_hwm : 3; /**< Target Split-Read ADB(allowable disconnect boundary) 2582 High Water Mark. 2583 Specifies the number of ADBs(128 Byte aligned chunks) 2584 that are accumulated(pending) BEFORE the Target Split 2585 completion is attempted on the PCI bus. 2586 - 0: RESERVED/ILLEGAL 2587 - 1: 2 Pending ADBs (129B-256B) 2588 - 2: 3 Pending ADBs (257B-384B) 2589 - 3: 4 Pending ADBs (385B-512B) 2590 - 4: 5 Pending ADBs (513B-640B) 2591 - 5: 6 Pending ADBs (641B-768B) 2592 - 6: 7 Pending ADBs (769B-896B) 2593 - 7: 8 Pending ADBs (897B-1024B) 2594 Example: Suppose a 1KB target memory request with 2595 starting byte offset address[6:0]=0x7F is split by 2596 the OCTEON and the TSR_HWM=1(2 ADBs). 2597 The OCTEON will start the target split completion 2598 on the PCI Bus after 1B(1st ADB)+128B(2nd ADB)=129B 2599 of data have been received from memory (even though 2600 the remaining 895B has not yet been received). The 2601 OCTEON will continue the split completion until it 2602 has consumed all of the pended split data. If the 2603 full transaction length(1KB) of data was NOT entirely 2604 transferred, then OCTEON will terminate the split 2605 completion and again wait for another 2 ADB-aligned data 2606 chunks(256B) of pended split data to be received from 2607 memory before starting another split completion request. 2608 This allows Octeon (as split completer), to send back 2609 multiple split completions for a given large split 2610 transaction without having to wait for the entire 2611 transaction length to be received from memory. 2612 NOTE: For split transaction sizes 'smaller' than the 2613 specified TSR_HWM value, the split completion 2614 is started when the last datum has been received from 2615 memory. 2616 NOTE: It is IMPERATIVE that this field NEVER BE 2617 written to a ZERO value. A value of zero is 2618 reserved/illegal and can result in PCIX bus hangs). */ 2619 uint32_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when 2620 clear '0' BAR2 access will be target-aborted. */ 2621 uint32_t bar2_esx : 2; /**< Value will be XORed with pci-address[37:36] to 2622 determine the endian swap mode. */ 2623 uint32_t bar2_cax : 1; /**< Value will be XORed with pci-address[38] to 2624 determine the L2 cache attribute. 2625 When XOR result is 1, not allocated in L2 cache */ 2626#else 2627 uint32_t bar2_cax : 1; 2628 uint32_t bar2_esx : 2; 2629 uint32_t bar2_enb : 1; 2630 uint32_t tsr_hwm : 3; 2631 uint32_t pmo_fpc : 3; 2632 uint32_t pmo_amod : 1; 2633 uint32_t b12_bist : 1; 2634 uint32_t ap_64ad : 1; 2635 uint32_t ap_pcix : 1; 2636 uint32_t reserved_14_14 : 1; 2637 uint32_t en_wfilt : 1; 2638 uint32_t scm : 1; 2639 uint32_t scmtyp : 1; 2640 uint32_t bar2pres : 1; 2641 uint32_t erst_n : 1; 2642 uint32_t reserved_20_31 : 12; 2643#endif 2644 } cn31xx; 2645 struct cvmx_pci_ctl_status_2_s cn38xx; 2646 struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2; 2647 struct cvmx_pci_ctl_status_2_s cn50xx; 2648 struct cvmx_pci_ctl_status_2_s cn58xx; 2649 struct cvmx_pci_ctl_status_2_s cn58xxp1; 2650}; 2651typedef union cvmx_pci_ctl_status_2 cvmx_pci_ctl_status_2_t; 2652 2653/** 2654 * cvmx_pci_dbell# 2655 * 2656 * PCI_DBELL0 = PCI Doorbell-0 2657 * 2658 * The value to write to the doorbell 0 register. The value in this register is acted upon when the 2659 * least-significant-byte of this register is written. 2660 */ 2661union cvmx_pci_dbellx { 2662 uint32_t u32; 2663 struct cvmx_pci_dbellx_s { 2664#ifdef __BIG_ENDIAN_BITFIELD 2665 uint32_t reserved_16_31 : 16; 2666 uint32_t inc_val : 16; /**< Software writes this register with the 2667 number of new Instructions to be processed 2668 on the Instruction Queue. When read this 2669 register contains the last write value. */ 2670#else 2671 uint32_t inc_val : 16; 2672 uint32_t reserved_16_31 : 16; 2673#endif 2674 } s; 2675 struct cvmx_pci_dbellx_s cn30xx; 2676 struct cvmx_pci_dbellx_s cn31xx; 2677 struct cvmx_pci_dbellx_s cn38xx; 2678 struct cvmx_pci_dbellx_s cn38xxp2; 2679 struct cvmx_pci_dbellx_s cn50xx; 2680 struct cvmx_pci_dbellx_s cn58xx; 2681 struct cvmx_pci_dbellx_s cn58xxp1; 2682}; 2683typedef union cvmx_pci_dbellx cvmx_pci_dbellx_t; 2684 2685/** 2686 * cvmx_pci_dma_cnt# 2687 * 2688 * PCI_DMA_CNT0 = PCI DMA Count0 2689 * 2690 * Keeps track of the number of DMAs or bytes sent by DMAs. The value in this register is acted upon when the 2691 * least-significant-byte of this register is written. 2692 */ 2693union cvmx_pci_dma_cntx { 2694 uint32_t u32; 2695 struct cvmx_pci_dma_cntx_s { 2696#ifdef __BIG_ENDIAN_BITFIELD 2697 uint32_t dma_cnt : 32; /**< Update with the number of DMAs completed or the 2698 number of bytes sent for DMA's associated with 2699 this counter. When this register is written the 2700 value written to [15:0] will be subtracted from 2701 the value in this register. */ 2702#else 2703 uint32_t dma_cnt : 32; 2704#endif 2705 } s; 2706 struct cvmx_pci_dma_cntx_s cn30xx; 2707 struct cvmx_pci_dma_cntx_s cn31xx; 2708 struct cvmx_pci_dma_cntx_s cn38xx; 2709 struct cvmx_pci_dma_cntx_s cn38xxp2; 2710 struct cvmx_pci_dma_cntx_s cn50xx; 2711 struct cvmx_pci_dma_cntx_s cn58xx; 2712 struct cvmx_pci_dma_cntx_s cn58xxp1; 2713}; 2714typedef union cvmx_pci_dma_cntx cvmx_pci_dma_cntx_t; 2715 2716/** 2717 * cvmx_pci_dma_int_lev# 2718 * 2719 * PCI_DMA_INT_LEV0 = PCI DMA Sent Interrupt Level For DMA 0 2720 * 2721 * Interrupt when the value in PCI_DMA_CNT0 is equal to or greater than the register value. 2722 */ 2723union cvmx_pci_dma_int_levx { 2724 uint32_t u32; 2725 struct cvmx_pci_dma_int_levx_s { 2726#ifdef __BIG_ENDIAN_BITFIELD 2727 uint32_t pkt_cnt : 32; /**< When PCI_DMA_CNT0 exceeds the value in this 2728 DCNT0 will be set in PCI_INT_SUM and PCI_INT_SUM2. */ 2729#else 2730 uint32_t pkt_cnt : 32; 2731#endif 2732 } s; 2733 struct cvmx_pci_dma_int_levx_s cn30xx; 2734 struct cvmx_pci_dma_int_levx_s cn31xx; 2735 struct cvmx_pci_dma_int_levx_s cn38xx; 2736 struct cvmx_pci_dma_int_levx_s cn38xxp2; 2737 struct cvmx_pci_dma_int_levx_s cn50xx; 2738 struct cvmx_pci_dma_int_levx_s cn58xx; 2739 struct cvmx_pci_dma_int_levx_s cn58xxp1; 2740}; 2741typedef union cvmx_pci_dma_int_levx cvmx_pci_dma_int_levx_t; 2742 2743/** 2744 * cvmx_pci_dma_time# 2745 * 2746 * PCI_DMA_TIME0 = PCI DMA Sent Timer For DMA0 2747 * 2748 * Time to wait from DMA being sent before issuing an interrupt. 2749 */ 2750union cvmx_pci_dma_timex { 2751 uint32_t u32; 2752 struct cvmx_pci_dma_timex_s { 2753#ifdef __BIG_ENDIAN_BITFIELD 2754 uint32_t dma_time : 32; /**< Number of PCI clock cycle to wait before 2755 setting DTIME0 in PCI_INT_SUM and PCI_INT_SUM2. 2756 After PCI_DMA_CNT0 becomes non-zero. 2757 The timer is reset when the 2758 PCI_INT_SUM[27] register is cleared. */ 2759#else 2760 uint32_t dma_time : 32; 2761#endif 2762 } s; 2763 struct cvmx_pci_dma_timex_s cn30xx; 2764 struct cvmx_pci_dma_timex_s cn31xx; 2765 struct cvmx_pci_dma_timex_s cn38xx; 2766 struct cvmx_pci_dma_timex_s cn38xxp2; 2767 struct cvmx_pci_dma_timex_s cn50xx; 2768 struct cvmx_pci_dma_timex_s cn58xx; 2769 struct cvmx_pci_dma_timex_s cn58xxp1; 2770}; 2771typedef union cvmx_pci_dma_timex cvmx_pci_dma_timex_t; 2772 2773/** 2774 * cvmx_pci_instr_count# 2775 * 2776 * PCI_INSTR_COUNT0 = PCI Instructions Outstanding Request Count 2777 * 2778 * The number of instructions to be fetched by the Instruction-0 Engine. 2779 */ 2780union cvmx_pci_instr_countx { 2781 uint32_t u32; 2782 struct cvmx_pci_instr_countx_s { 2783#ifdef __BIG_ENDIAN_BITFIELD 2784 uint32_t icnt : 32; /**< Number of Instructions to be fetched by the 2785 Instruction Engine. 2786 A write of any non zero value to this register 2787 will clear the value of this register. */ 2788#else 2789 uint32_t icnt : 32; 2790#endif 2791 } s; 2792 struct cvmx_pci_instr_countx_s cn30xx; 2793 struct cvmx_pci_instr_countx_s cn31xx; 2794 struct cvmx_pci_instr_countx_s cn38xx; 2795 struct cvmx_pci_instr_countx_s cn38xxp2; 2796 struct cvmx_pci_instr_countx_s cn50xx; 2797 struct cvmx_pci_instr_countx_s cn58xx; 2798 struct cvmx_pci_instr_countx_s cn58xxp1; 2799}; 2800typedef union cvmx_pci_instr_countx cvmx_pci_instr_countx_t; 2801 2802/** 2803 * cvmx_pci_int_enb 2804 * 2805 * PCI_INT_ENB = PCI Interrupt Enable 2806 * 2807 * Enables interrupt bits in the PCI_INT_SUM register. 2808 */ 2809union cvmx_pci_int_enb { 2810 uint64_t u64; 2811 struct cvmx_pci_int_enb_s { 2812#ifdef __BIG_ENDIAN_BITFIELD 2813 uint64_t reserved_34_63 : 30; 2814 uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 2815 uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 2816 uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 2817 uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 2818 uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 2819 uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 2820 uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 2821 uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 2822 uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 2823 uint64_t iptime3 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[24] */ 2824 uint64_t iptime2 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[23] */ 2825 uint64_t iptime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */ 2826 uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 2827 uint64_t ipcnt3 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[20] */ 2828 uint64_t ipcnt2 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[19] */ 2829 uint64_t ipcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */ 2830 uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 2831 uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 2832 uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 2833 uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 2834 uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 2835 uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 2836 uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 2837 uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 2838 uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 2839 uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 2840 uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 2841 uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 2842 uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 2843 uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 2844 uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 2845 uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 2846 uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 2847 uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 2848#else 2849 uint64_t itr_wabt : 1; 2850 uint64_t imr_wabt : 1; 2851 uint64_t imr_wtto : 1; 2852 uint64_t itr_abt : 1; 2853 uint64_t imr_abt : 1; 2854 uint64_t imr_tto : 1; 2855 uint64_t imsi_per : 1; 2856 uint64_t imsi_tabt : 1; 2857 uint64_t imsi_mabt : 1; 2858 uint64_t imsc_msg : 1; 2859 uint64_t itsr_abt : 1; 2860 uint64_t iserr : 1; 2861 uint64_t iaperr : 1; 2862 uint64_t idperr : 1; 2863 uint64_t ill_rwr : 1; 2864 uint64_t ill_rrd : 1; 2865 uint64_t irsl_int : 1; 2866 uint64_t ipcnt0 : 1; 2867 uint64_t ipcnt1 : 1; 2868 uint64_t ipcnt2 : 1; 2869 uint64_t ipcnt3 : 1; 2870 uint64_t iptime0 : 1; 2871 uint64_t iptime1 : 1; 2872 uint64_t iptime2 : 1; 2873 uint64_t iptime3 : 1; 2874 uint64_t idcnt0 : 1; 2875 uint64_t idcnt1 : 1; 2876 uint64_t idtime0 : 1; 2877 uint64_t idtime1 : 1; 2878 uint64_t dma0_fi : 1; 2879 uint64_t dma1_fi : 1; 2880 uint64_t win_wr : 1; 2881 uint64_t ill_wr : 1; 2882 uint64_t ill_rd : 1; 2883 uint64_t reserved_34_63 : 30; 2884#endif 2885 } s; 2886 struct cvmx_pci_int_enb_cn30xx { 2887#ifdef __BIG_ENDIAN_BITFIELD 2888 uint64_t reserved_34_63 : 30; 2889 uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 2890 uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 2891 uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 2892 uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 2893 uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 2894 uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 2895 uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 2896 uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 2897 uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 2898 uint64_t reserved_22_24 : 3; 2899 uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 2900 uint64_t reserved_18_20 : 3; 2901 uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 2902 uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 2903 uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 2904 uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 2905 uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 2906 uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 2907 uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 2908 uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 2909 uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 2910 uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 2911 uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 2912 uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 2913 uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 2914 uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 2915 uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 2916 uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 2917 uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 2918 uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 2919#else 2920 uint64_t itr_wabt : 1; 2921 uint64_t imr_wabt : 1; 2922 uint64_t imr_wtto : 1; 2923 uint64_t itr_abt : 1; 2924 uint64_t imr_abt : 1; 2925 uint64_t imr_tto : 1; 2926 uint64_t imsi_per : 1; 2927 uint64_t imsi_tabt : 1; 2928 uint64_t imsi_mabt : 1; 2929 uint64_t imsc_msg : 1; 2930 uint64_t itsr_abt : 1; 2931 uint64_t iserr : 1; 2932 uint64_t iaperr : 1; 2933 uint64_t idperr : 1; 2934 uint64_t ill_rwr : 1; 2935 uint64_t ill_rrd : 1; 2936 uint64_t irsl_int : 1; 2937 uint64_t ipcnt0 : 1; 2938 uint64_t reserved_18_20 : 3; 2939 uint64_t iptime0 : 1; 2940 uint64_t reserved_22_24 : 3; 2941 uint64_t idcnt0 : 1; 2942 uint64_t idcnt1 : 1; 2943 uint64_t idtime0 : 1; 2944 uint64_t idtime1 : 1; 2945 uint64_t dma0_fi : 1; 2946 uint64_t dma1_fi : 1; 2947 uint64_t win_wr : 1; 2948 uint64_t ill_wr : 1; 2949 uint64_t ill_rd : 1; 2950 uint64_t reserved_34_63 : 30; 2951#endif 2952 } cn30xx; 2953 struct cvmx_pci_int_enb_cn31xx { 2954#ifdef __BIG_ENDIAN_BITFIELD 2955 uint64_t reserved_34_63 : 30; 2956 uint64_t ill_rd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[33] */ 2957 uint64_t ill_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[32] */ 2958 uint64_t win_wr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[31] */ 2959 uint64_t dma1_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[30] */ 2960 uint64_t dma0_fi : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[29] */ 2961 uint64_t idtime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[28] */ 2962 uint64_t idtime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[27] */ 2963 uint64_t idcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[26] */ 2964 uint64_t idcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[25] */ 2965 uint64_t reserved_23_24 : 2; 2966 uint64_t iptime1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[22] */ 2967 uint64_t iptime0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[21] */ 2968 uint64_t reserved_19_20 : 2; 2969 uint64_t ipcnt1 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[18] */ 2970 uint64_t ipcnt0 : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[17] */ 2971 uint64_t irsl_int : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[16] */ 2972 uint64_t ill_rrd : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[15] */ 2973 uint64_t ill_rwr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[14] */ 2974 uint64_t idperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[13] */ 2975 uint64_t iaperr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[12] */ 2976 uint64_t iserr : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[11] */ 2977 uint64_t itsr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[10] */ 2978 uint64_t imsc_msg : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[9] */ 2979 uint64_t imsi_mabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[8] */ 2980 uint64_t imsi_tabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[7] */ 2981 uint64_t imsi_per : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[6] */ 2982 uint64_t imr_tto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[5] */ 2983 uint64_t imr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[4] */ 2984 uint64_t itr_abt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[3] */ 2985 uint64_t imr_wtto : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[2] */ 2986 uint64_t imr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[1] */ 2987 uint64_t itr_wabt : 1; /**< INTA# Pin Interrupt Enable for PCI_INT_SUM[0] */ 2988#else 2989 uint64_t itr_wabt : 1; 2990 uint64_t imr_wabt : 1; 2991 uint64_t imr_wtto : 1; 2992 uint64_t itr_abt : 1; 2993 uint64_t imr_abt : 1; 2994 uint64_t imr_tto : 1; 2995 uint64_t imsi_per : 1; 2996 uint64_t imsi_tabt : 1; 2997 uint64_t imsi_mabt : 1; 2998 uint64_t imsc_msg : 1; 2999 uint64_t itsr_abt : 1; 3000 uint64_t iserr : 1; 3001 uint64_t iaperr : 1; 3002 uint64_t idperr : 1; 3003 uint64_t ill_rwr : 1; 3004 uint64_t ill_rrd : 1; 3005 uint64_t irsl_int : 1; 3006 uint64_t ipcnt0 : 1; 3007 uint64_t ipcnt1 : 1; 3008 uint64_t reserved_19_20 : 2; 3009 uint64_t iptime0 : 1; 3010 uint64_t iptime1 : 1; 3011 uint64_t reserved_23_24 : 2; 3012 uint64_t idcnt0 : 1; 3013 uint64_t idcnt1 : 1; 3014 uint64_t idtime0 : 1; 3015 uint64_t idtime1 : 1; 3016 uint64_t dma0_fi : 1; 3017 uint64_t dma1_fi : 1; 3018 uint64_t win_wr : 1; 3019 uint64_t ill_wr : 1; 3020 uint64_t ill_rd : 1; 3021 uint64_t reserved_34_63 : 30; 3022#endif 3023 } cn31xx; 3024 struct cvmx_pci_int_enb_s cn38xx; 3025 struct cvmx_pci_int_enb_s cn38xxp2; 3026 struct cvmx_pci_int_enb_cn31xx cn50xx; 3027 struct cvmx_pci_int_enb_s cn58xx; 3028 struct cvmx_pci_int_enb_s cn58xxp1; 3029}; 3030typedef union cvmx_pci_int_enb cvmx_pci_int_enb_t; 3031 3032/** 3033 * cvmx_pci_int_enb2 3034 * 3035 * PCI_INT_ENB2 = PCI Interrupt Enable2 Register 3036 * 3037 * Enables interrupt bits in the PCI_INT_SUM2 register. 3038 */ 3039union cvmx_pci_int_enb2 { 3040 uint64_t u64; 3041 struct cvmx_pci_int_enb2_s { 3042#ifdef __BIG_ENDIAN_BITFIELD 3043 uint64_t reserved_34_63 : 30; 3044 uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3045 uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3046 uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3047 uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3048 uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3049 uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3050 uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3051 uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3052 uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3053 uint64_t rptime3 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[24] */ 3054 uint64_t rptime2 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[23] */ 3055 uint64_t rptime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */ 3056 uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3057 uint64_t rpcnt3 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[20] */ 3058 uint64_t rpcnt2 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[19] */ 3059 uint64_t rpcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */ 3060 uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3061 uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3062 uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3063 uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3064 uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3065 uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3066 uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3067 uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3068 uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3069 uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3070 uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3071 uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3072 uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3073 uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3074 uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3075 uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3076 uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3077 uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3078#else 3079 uint64_t rtr_wabt : 1; 3080 uint64_t rmr_wabt : 1; 3081 uint64_t rmr_wtto : 1; 3082 uint64_t rtr_abt : 1; 3083 uint64_t rmr_abt : 1; 3084 uint64_t rmr_tto : 1; 3085 uint64_t rmsi_per : 1; 3086 uint64_t rmsi_tabt : 1; 3087 uint64_t rmsi_mabt : 1; 3088 uint64_t rmsc_msg : 1; 3089 uint64_t rtsr_abt : 1; 3090 uint64_t rserr : 1; 3091 uint64_t raperr : 1; 3092 uint64_t rdperr : 1; 3093 uint64_t ill_rwr : 1; 3094 uint64_t ill_rrd : 1; 3095 uint64_t rrsl_int : 1; 3096 uint64_t rpcnt0 : 1; 3097 uint64_t rpcnt1 : 1; 3098 uint64_t rpcnt2 : 1; 3099 uint64_t rpcnt3 : 1; 3100 uint64_t rptime0 : 1; 3101 uint64_t rptime1 : 1; 3102 uint64_t rptime2 : 1; 3103 uint64_t rptime3 : 1; 3104 uint64_t rdcnt0 : 1; 3105 uint64_t rdcnt1 : 1; 3106 uint64_t rdtime0 : 1; 3107 uint64_t rdtime1 : 1; 3108 uint64_t dma0_fi : 1; 3109 uint64_t dma1_fi : 1; 3110 uint64_t win_wr : 1; 3111 uint64_t ill_wr : 1; 3112 uint64_t ill_rd : 1; 3113 uint64_t reserved_34_63 : 30; 3114#endif 3115 } s; 3116 struct cvmx_pci_int_enb2_cn30xx { 3117#ifdef __BIG_ENDIAN_BITFIELD 3118 uint64_t reserved_34_63 : 30; 3119 uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3120 uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3121 uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3122 uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3123 uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3124 uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3125 uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3126 uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3127 uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3128 uint64_t reserved_22_24 : 3; 3129 uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3130 uint64_t reserved_18_20 : 3; 3131 uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3132 uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3133 uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3134 uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3135 uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3136 uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3137 uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3138 uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3139 uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3140 uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3141 uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3142 uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3143 uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3144 uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3145 uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3146 uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3147 uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3148 uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3149#else 3150 uint64_t rtr_wabt : 1; 3151 uint64_t rmr_wabt : 1; 3152 uint64_t rmr_wtto : 1; 3153 uint64_t rtr_abt : 1; 3154 uint64_t rmr_abt : 1; 3155 uint64_t rmr_tto : 1; 3156 uint64_t rmsi_per : 1; 3157 uint64_t rmsi_tabt : 1; 3158 uint64_t rmsi_mabt : 1; 3159 uint64_t rmsc_msg : 1; 3160 uint64_t rtsr_abt : 1; 3161 uint64_t rserr : 1; 3162 uint64_t raperr : 1; 3163 uint64_t rdperr : 1; 3164 uint64_t ill_rwr : 1; 3165 uint64_t ill_rrd : 1; 3166 uint64_t rrsl_int : 1; 3167 uint64_t rpcnt0 : 1; 3168 uint64_t reserved_18_20 : 3; 3169 uint64_t rptime0 : 1; 3170 uint64_t reserved_22_24 : 3; 3171 uint64_t rdcnt0 : 1; 3172 uint64_t rdcnt1 : 1; 3173 uint64_t rdtime0 : 1; 3174 uint64_t rdtime1 : 1; 3175 uint64_t dma0_fi : 1; 3176 uint64_t dma1_fi : 1; 3177 uint64_t win_wr : 1; 3178 uint64_t ill_wr : 1; 3179 uint64_t ill_rd : 1; 3180 uint64_t reserved_34_63 : 30; 3181#endif 3182 } cn30xx; 3183 struct cvmx_pci_int_enb2_cn31xx { 3184#ifdef __BIG_ENDIAN_BITFIELD 3185 uint64_t reserved_34_63 : 30; 3186 uint64_t ill_rd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[33] */ 3187 uint64_t ill_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[32] */ 3188 uint64_t win_wr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[31] */ 3189 uint64_t dma1_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[30] */ 3190 uint64_t dma0_fi : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[29] */ 3191 uint64_t rdtime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[28] */ 3192 uint64_t rdtime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[27] */ 3193 uint64_t rdcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[26] */ 3194 uint64_t rdcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[25] */ 3195 uint64_t reserved_23_24 : 2; 3196 uint64_t rptime1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[22] */ 3197 uint64_t rptime0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[21] */ 3198 uint64_t reserved_19_20 : 2; 3199 uint64_t rpcnt1 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[18] */ 3200 uint64_t rpcnt0 : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[17] */ 3201 uint64_t rrsl_int : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[16] */ 3202 uint64_t ill_rrd : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[15] */ 3203 uint64_t ill_rwr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[14] */ 3204 uint64_t rdperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[13] */ 3205 uint64_t raperr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[12] */ 3206 uint64_t rserr : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[11] */ 3207 uint64_t rtsr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[10] */ 3208 uint64_t rmsc_msg : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[9] */ 3209 uint64_t rmsi_mabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[8] */ 3210 uint64_t rmsi_tabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[7] */ 3211 uint64_t rmsi_per : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[6] */ 3212 uint64_t rmr_tto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[5] */ 3213 uint64_t rmr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[4] */ 3214 uint64_t rtr_abt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[3] */ 3215 uint64_t rmr_wtto : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[2] */ 3216 uint64_t rmr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[1] */ 3217 uint64_t rtr_wabt : 1; /**< RSL Chain Interrupt Enable for PCI_INT_SUM2[0] */ 3218#else 3219 uint64_t rtr_wabt : 1; 3220 uint64_t rmr_wabt : 1; 3221 uint64_t rmr_wtto : 1; 3222 uint64_t rtr_abt : 1; 3223 uint64_t rmr_abt : 1; 3224 uint64_t rmr_tto : 1; 3225 uint64_t rmsi_per : 1; 3226 uint64_t rmsi_tabt : 1; 3227 uint64_t rmsi_mabt : 1; 3228 uint64_t rmsc_msg : 1; 3229 uint64_t rtsr_abt : 1; 3230 uint64_t rserr : 1; 3231 uint64_t raperr : 1; 3232 uint64_t rdperr : 1; 3233 uint64_t ill_rwr : 1; 3234 uint64_t ill_rrd : 1; 3235 uint64_t rrsl_int : 1; 3236 uint64_t rpcnt0 : 1; 3237 uint64_t rpcnt1 : 1; 3238 uint64_t reserved_19_20 : 2; 3239 uint64_t rptime0 : 1; 3240 uint64_t rptime1 : 1; 3241 uint64_t reserved_23_24 : 2; 3242 uint64_t rdcnt0 : 1; 3243 uint64_t rdcnt1 : 1; 3244 uint64_t rdtime0 : 1; 3245 uint64_t rdtime1 : 1; 3246 uint64_t dma0_fi : 1; 3247 uint64_t dma1_fi : 1; 3248 uint64_t win_wr : 1; 3249 uint64_t ill_wr : 1; 3250 uint64_t ill_rd : 1; 3251 uint64_t reserved_34_63 : 30; 3252#endif 3253 } cn31xx; 3254 struct cvmx_pci_int_enb2_s cn38xx; 3255 struct cvmx_pci_int_enb2_s cn38xxp2; 3256 struct cvmx_pci_int_enb2_cn31xx cn50xx; 3257 struct cvmx_pci_int_enb2_s cn58xx; 3258 struct cvmx_pci_int_enb2_s cn58xxp1; 3259}; 3260typedef union cvmx_pci_int_enb2 cvmx_pci_int_enb2_t; 3261 3262/** 3263 * cvmx_pci_int_sum 3264 * 3265 * PCI_INT_SUM = PCI Interrupt Summary 3266 * 3267 * The PCI Interrupt Summary Register. 3268 */ 3269union cvmx_pci_int_sum { 3270 uint64_t u64; 3271 struct cvmx_pci_int_sum_s { 3272#ifdef __BIG_ENDIAN_BITFIELD 3273 uint64_t reserved_34_63 : 30; 3274 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3275 when the mem area is disabled. */ 3276 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3277 when the mem area is disabled. */ 3278 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3279 Read-Address Register took place. */ 3280 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3281 required to set the FORCE-INT bit for counter 1. */ 3282 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3283 required to set the FORCE-INT bit for counter 0. */ 3284 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3285 register is not 0 the DMA_CNT1 timer counts. 3286 When the DMA1_CNT timer has a value greater 3287 than the PCI_DMA_TIME1 register this 3288 bit is set. The timer is reset when bit is 3289 written with a one. */ 3290 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3291 register is not 0 the DMA_CNT0 timer counts. 3292 When the DMA0_CNT timer has a value greater 3293 than the PCI_DMA_TIME0 register this 3294 bit is set. The timer is reset when bit is 3295 written with a one. */ 3296 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3297 value is greater than the value 3298 in the PCI_DMA_INT_LEV1 register. */ 3299 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3300 value is greater than the value 3301 in the PCI_DMA_INT_LEV0 register. */ 3302 uint64_t ptime3 : 1; /**< When the value in the PCI_PKTS_SENT3 3303 register is not 0 the Sent-3 timer counts. 3304 When the Sent-3 timer has a value greater 3305 than the PCI_PKTS_SENT_TIME3 register this 3306 bit is set. The timer is reset when bit is 3307 written with a one. */ 3308 uint64_t ptime2 : 1; /**< When the value in the PCI_PKTS_SENT2 3309 register is not 0 the Sent-2 timer counts. 3310 When the Sent-2 timer has a value greater 3311 than the PCI_PKTS_SENT_TIME2 register this 3312 bit is set. The timer is reset when bit is 3313 written with a one. */ 3314 uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3315 register is not 0 the Sent-1 timer counts. 3316 When the Sent-1 timer has a value greater 3317 than the PCI_PKTS_SENT_TIME1 register this 3318 bit is set. The timer is reset when bit is 3319 written with a one. */ 3320 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3321 register is not 0 the Sent-0 timer counts. 3322 When the Sent-0 timer has a value greater 3323 than the PCI_PKTS_SENT_TIME0 register this 3324 bit is set. The timer is reset when bit is 3325 written with a one. */ 3326 uint64_t pcnt3 : 1; /**< This bit indicates that PCI_PKTS_SENT3 3327 value is greater than the value 3328 in the PCI_PKTS_SENT_INT_LEV3 register. */ 3329 uint64_t pcnt2 : 1; /**< This bit indicates that PCI_PKTS_SENT2 3330 value is greater than the value 3331 in the PCI_PKTS_SENT_INT_LEV2 register. */ 3332 uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3333 value is greater than the value 3334 in the PCI_PKTS_SENT_INT_LEV1 register. */ 3335 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3336 value is greater than the value 3337 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3338 uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3339 is asserted by the MIO. */ 3340 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3341 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3342 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3343 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3344 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3345 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3346 CN58XX (as completer), has encountered an error 3347 which prevents the split transaction from 3348 completing. In this event, the CN58XX (as completer), 3349 sends a SCM (Split Completion Message) to the 3350 initiator. See: PCIX Spec v1.0a Fig 2-40. 3351 [31:28]: Message Class = 2(completer error) 3352 [27:20]: Message Index = 0x80 3353 [18:12]: Remaining Lower Address 3354 [11:0]: Remaining Byte Count */ 3355 uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3356 for either a Split-Read/Write error case. 3357 Set if: 3358 a) A Split-Write SCM is detected with SCE=1. 3359 b) A Split-Read SCM is detected (regardless 3360 of SCE status). 3361 The Split completion message(SCM) 3362 is also latched into the PCI_SCM_REG[SCM] to 3363 assist SW with error recovery. */ 3364 uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3365 uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3366 uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3367 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3368 uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3369 uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3370 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3371 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3372 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3373#else 3374 uint64_t tr_wabt : 1; 3375 uint64_t mr_wabt : 1; 3376 uint64_t mr_wtto : 1; 3377 uint64_t tr_abt : 1; 3378 uint64_t mr_abt : 1; 3379 uint64_t mr_tto : 1; 3380 uint64_t msi_per : 1; 3381 uint64_t msi_tabt : 1; 3382 uint64_t msi_mabt : 1; 3383 uint64_t msc_msg : 1; 3384 uint64_t tsr_abt : 1; 3385 uint64_t serr : 1; 3386 uint64_t aperr : 1; 3387 uint64_t dperr : 1; 3388 uint64_t ill_rwr : 1; 3389 uint64_t ill_rrd : 1; 3390 uint64_t rsl_int : 1; 3391 uint64_t pcnt0 : 1; 3392 uint64_t pcnt1 : 1; 3393 uint64_t pcnt2 : 1; 3394 uint64_t pcnt3 : 1; 3395 uint64_t ptime0 : 1; 3396 uint64_t ptime1 : 1; 3397 uint64_t ptime2 : 1; 3398 uint64_t ptime3 : 1; 3399 uint64_t dcnt0 : 1; 3400 uint64_t dcnt1 : 1; 3401 uint64_t dtime0 : 1; 3402 uint64_t dtime1 : 1; 3403 uint64_t dma0_fi : 1; 3404 uint64_t dma1_fi : 1; 3405 uint64_t win_wr : 1; 3406 uint64_t ill_wr : 1; 3407 uint64_t ill_rd : 1; 3408 uint64_t reserved_34_63 : 30; 3409#endif 3410 } s; 3411 struct cvmx_pci_int_sum_cn30xx { 3412#ifdef __BIG_ENDIAN_BITFIELD 3413 uint64_t reserved_34_63 : 30; 3414 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3415 when the mem area is disabled. */ 3416 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3417 when the mem area is disabled. */ 3418 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3419 Read-Address Register took place. */ 3420 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3421 required to set the FORCE-INT bit for counter 1. */ 3422 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3423 required to set the FORCE-INT bit for counter 0. */ 3424 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3425 register is not 0 the DMA_CNT1 timer counts. 3426 When the DMA1_CNT timer has a value greater 3427 than the PCI_DMA_TIME1 register this 3428 bit is set. The timer is reset when bit is 3429 written with a one. */ 3430 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3431 register is not 0 the DMA_CNT0 timer counts. 3432 When the DMA0_CNT timer has a value greater 3433 than the PCI_DMA_TIME0 register this 3434 bit is set. The timer is reset when bit is 3435 written with a one. */ 3436 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3437 value is greater than the value 3438 in the PCI_DMA_INT_LEV1 register. */ 3439 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3440 value is greater than the value 3441 in the PCI_DMA_INT_LEV0 register. */ 3442 uint64_t reserved_22_24 : 3; 3443 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3444 register is not 0 the Sent-0 timer counts. 3445 When the Sent-0 timer has a value greater 3446 than the PCI_PKTS_SENT_TIME0 register this 3447 bit is set. The timer is reset when bit is 3448 written with a one. */ 3449 uint64_t reserved_18_20 : 3; 3450 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3451 value is greater than the value 3452 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3453 uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3454 is asserted by the MIO */ 3455 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3456 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3457 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3458 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3459 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3460 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3461 N3K (as completer), has encountered an error 3462 which prevents the split transaction from 3463 completing. In this event, the N3K (as completer), 3464 sends a SCM (Split Completion Message) to the 3465 initiator. See: PCIX Spec v1.0a Fig 2-40. 3466 [31:28]: Message Class = 2(completer error) 3467 [27:20]: Message Index = 0x80 3468 [18:12]: Remaining Lower Address 3469 [11:0]: Remaining Byte Count */ 3470 uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3471 for either a Split-Read/Write error case. 3472 Set if: 3473 a) A Split-Write SCM is detected with SCE=1. 3474 b) A Split-Read SCM is detected (regardless 3475 of SCE status). 3476 The Split completion message(SCM) 3477 is also latched into the PCI_SCM_REG[SCM] to 3478 assist SW with error recovery. */ 3479 uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3480 uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3481 uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3482 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3483 uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3484 uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3485 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3486 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3487 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3488#else 3489 uint64_t tr_wabt : 1; 3490 uint64_t mr_wabt : 1; 3491 uint64_t mr_wtto : 1; 3492 uint64_t tr_abt : 1; 3493 uint64_t mr_abt : 1; 3494 uint64_t mr_tto : 1; 3495 uint64_t msi_per : 1; 3496 uint64_t msi_tabt : 1; 3497 uint64_t msi_mabt : 1; 3498 uint64_t msc_msg : 1; 3499 uint64_t tsr_abt : 1; 3500 uint64_t serr : 1; 3501 uint64_t aperr : 1; 3502 uint64_t dperr : 1; 3503 uint64_t ill_rwr : 1; 3504 uint64_t ill_rrd : 1; 3505 uint64_t rsl_int : 1; 3506 uint64_t pcnt0 : 1; 3507 uint64_t reserved_18_20 : 3; 3508 uint64_t ptime0 : 1; 3509 uint64_t reserved_22_24 : 3; 3510 uint64_t dcnt0 : 1; 3511 uint64_t dcnt1 : 1; 3512 uint64_t dtime0 : 1; 3513 uint64_t dtime1 : 1; 3514 uint64_t dma0_fi : 1; 3515 uint64_t dma1_fi : 1; 3516 uint64_t win_wr : 1; 3517 uint64_t ill_wr : 1; 3518 uint64_t ill_rd : 1; 3519 uint64_t reserved_34_63 : 30; 3520#endif 3521 } cn30xx; 3522 struct cvmx_pci_int_sum_cn31xx { 3523#ifdef __BIG_ENDIAN_BITFIELD 3524 uint64_t reserved_34_63 : 30; 3525 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3526 when the mem area is disabled. */ 3527 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3528 when the mem area is disabled. */ 3529 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3530 Read-Address Register took place. */ 3531 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3532 required to set the FORCE-INT bit for counter 1. */ 3533 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3534 required to set the FORCE-INT bit for counter 0. */ 3535 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3536 register is not 0 the DMA_CNT1 timer counts. 3537 When the DMA1_CNT timer has a value greater 3538 than the PCI_DMA_TIME1 register this 3539 bit is set. The timer is reset when bit is 3540 written with a one. */ 3541 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3542 register is not 0 the DMA_CNT0 timer counts. 3543 When the DMA0_CNT timer has a value greater 3544 than the PCI_DMA_TIME0 register this 3545 bit is set. The timer is reset when bit is 3546 written with a one. */ 3547 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3548 value is greater than the value 3549 in the PCI_DMA_INT_LEV1 register. */ 3550 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3551 value is greater than the value 3552 in the PCI_DMA_INT_LEV0 register. */ 3553 uint64_t reserved_23_24 : 2; 3554 uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3555 register is not 0 the Sent-1 timer counts. 3556 When the Sent-1 timer has a value greater 3557 than the PCI_PKTS_SENT_TIME1 register this 3558 bit is set. The timer is reset when bit is 3559 written with a one. */ 3560 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3561 register is not 0 the Sent-0 timer counts. 3562 When the Sent-0 timer has a value greater 3563 than the PCI_PKTS_SENT_TIME0 register this 3564 bit is set. The timer is reset when bit is 3565 written with a one. */ 3566 uint64_t reserved_19_20 : 2; 3567 uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3568 value is greater than the value 3569 in the PCI_PKTS_SENT_INT_LEV1 register. */ 3570 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3571 value is greater than the value 3572 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3573 uint64_t rsl_int : 1; /**< This bit is set when the mio_pci_inta_dr wire 3574 is asserted by the MIO */ 3575 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3576 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3577 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3578 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3579 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3580 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected 3581 N3K (as completer), has encountered an error 3582 which prevents the split transaction from 3583 completing. In this event, the N3K (as completer), 3584 sends a SCM (Split Completion Message) to the 3585 initiator. See: PCIX Spec v1.0a Fig 2-40. 3586 [31:28]: Message Class = 2(completer error) 3587 [27:20]: Message Index = 0x80 3588 [18:12]: Remaining Lower Address 3589 [11:0]: Remaining Byte Count */ 3590 uint64_t msc_msg : 1; /**< Master Split Completion Message (SCM) Detected 3591 for either a Split-Read/Write error case. 3592 Set if: 3593 a) A Split-Write SCM is detected with SCE=1. 3594 b) A Split-Read SCM is detected (regardless 3595 of SCE status). 3596 The Split completion message(SCM) 3597 is also latched into the PCI_SCM_REG[SCM] to 3598 assist SW with error recovery. */ 3599 uint64_t msi_mabt : 1; /**< PCI Master Abort on Master MSI */ 3600 uint64_t msi_tabt : 1; /**< PCI Target-Abort on Master MSI */ 3601 uint64_t msi_per : 1; /**< PCI Parity Error on Master MSI */ 3602 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Master-Read */ 3603 uint64_t mr_abt : 1; /**< PCI Master Abort On Master-Read */ 3604 uint64_t tr_abt : 1; /**< PCI Target Abort On Master-Read */ 3605 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on Master-write */ 3606 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on Master-write */ 3607 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on Master-write */ 3608#else 3609 uint64_t tr_wabt : 1; 3610 uint64_t mr_wabt : 1; 3611 uint64_t mr_wtto : 1; 3612 uint64_t tr_abt : 1; 3613 uint64_t mr_abt : 1; 3614 uint64_t mr_tto : 1; 3615 uint64_t msi_per : 1; 3616 uint64_t msi_tabt : 1; 3617 uint64_t msi_mabt : 1; 3618 uint64_t msc_msg : 1; 3619 uint64_t tsr_abt : 1; 3620 uint64_t serr : 1; 3621 uint64_t aperr : 1; 3622 uint64_t dperr : 1; 3623 uint64_t ill_rwr : 1; 3624 uint64_t ill_rrd : 1; 3625 uint64_t rsl_int : 1; 3626 uint64_t pcnt0 : 1; 3627 uint64_t pcnt1 : 1; 3628 uint64_t reserved_19_20 : 2; 3629 uint64_t ptime0 : 1; 3630 uint64_t ptime1 : 1; 3631 uint64_t reserved_23_24 : 2; 3632 uint64_t dcnt0 : 1; 3633 uint64_t dcnt1 : 1; 3634 uint64_t dtime0 : 1; 3635 uint64_t dtime1 : 1; 3636 uint64_t dma0_fi : 1; 3637 uint64_t dma1_fi : 1; 3638 uint64_t win_wr : 1; 3639 uint64_t ill_wr : 1; 3640 uint64_t ill_rd : 1; 3641 uint64_t reserved_34_63 : 30; 3642#endif 3643 } cn31xx; 3644 struct cvmx_pci_int_sum_s cn38xx; 3645 struct cvmx_pci_int_sum_s cn38xxp2; 3646 struct cvmx_pci_int_sum_cn31xx cn50xx; 3647 struct cvmx_pci_int_sum_s cn58xx; 3648 struct cvmx_pci_int_sum_s cn58xxp1; 3649}; 3650typedef union cvmx_pci_int_sum cvmx_pci_int_sum_t; 3651 3652/** 3653 * cvmx_pci_int_sum2 3654 * 3655 * PCI_INT_SUM2 = PCI Interrupt Summary2 Register 3656 * 3657 * The PCI Interrupt Summary2 Register copy used for RSL interrupts. 3658 */ 3659union cvmx_pci_int_sum2 { 3660 uint64_t u64; 3661 struct cvmx_pci_int_sum2_s { 3662#ifdef __BIG_ENDIAN_BITFIELD 3663 uint64_t reserved_34_63 : 30; 3664 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3665 when the mem area is disabled. */ 3666 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3667 when the mem area is disabled. */ 3668 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3669 Read-Address Register took place. */ 3670 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3671 required to set the FORCE-INT bit for counter 1. */ 3672 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3673 required to set the FORCE-INT bit for counter 0. */ 3674 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3675 register is not 0 the DMA_CNT1 timer counts. 3676 When the DMA1_CNT timer has a value greater 3677 than the PCI_DMA_TIME1 register this 3678 bit is set. The timer is reset when bit is 3679 written with a one. */ 3680 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3681 register is not 0 the DMA_CNT0 timer counts. 3682 When the DMA0_CNT timer has a value greater 3683 than the PCI_DMA_TIME0 register this 3684 bit is set. The timer is reset when bit is 3685 written with a one. */ 3686 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3687 value is greater than the value 3688 in the PCI_DMA_INT_LEV1 register. */ 3689 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3690 value is greater than the value 3691 in the PCI_DMA_INT_LEV0 register. */ 3692 uint64_t ptime3 : 1; /**< When the value in the PCI_PKTS_SENT3 3693 register is not 0 the Sent-3 timer counts. 3694 When the Sent-3 timer has a value greater 3695 than the PCI_PKTS_SENT_TIME3 register this 3696 bit is set. The timer is reset when bit is 3697 written with a one. */ 3698 uint64_t ptime2 : 1; /**< When the value in the PCI_PKTS_SENT2 3699 register is not 0 the Sent-2 timer counts. 3700 When the Sent-2 timer has a value greater 3701 than the PCI_PKTS_SENT_TIME2 register this 3702 bit is set. The timer is reset when bit is 3703 written with a one. */ 3704 uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3705 register is not 0 the Sent-1 timer counts. 3706 When the Sent-1 timer has a value greater 3707 than the PCI_PKTS_SENT_TIME1 register this 3708 bit is set. The timer is reset when bit is 3709 written with a one. */ 3710 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3711 register is not 0 the Sent-0 timer counts. 3712 When the Sent-0 timer has a value greater 3713 than the PCI_PKTS_SENT_TIME0 register this 3714 bit is set. The timer is reset when bit is 3715 written with a one. */ 3716 uint64_t pcnt3 : 1; /**< This bit indicates that PCI_PKTS_SENT3 3717 value is greater than the value 3718 in the PCI_PKTS_SENT_INT_LEV3 register. */ 3719 uint64_t pcnt2 : 1; /**< This bit indicates that PCI_PKTS_SENT2 3720 value is greater than the value 3721 in the PCI_PKTS_SENT_INT_LEV2 register. */ 3722 uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3723 value is greater than the value 3724 in the PCI_PKTS_SENT_INT_LEV1 register. */ 3725 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3726 value is greater than the value 3727 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3728 uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 3729 generated an interrupt. */ 3730 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3731 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3732 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3733 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3734 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3735 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 3736 uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 3737 uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 3738 uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 3739 uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 3740 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 3741 uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 3742 uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 3743 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 3744 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 3745 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 3746#else 3747 uint64_t tr_wabt : 1; 3748 uint64_t mr_wabt : 1; 3749 uint64_t mr_wtto : 1; 3750 uint64_t tr_abt : 1; 3751 uint64_t mr_abt : 1; 3752 uint64_t mr_tto : 1; 3753 uint64_t msi_per : 1; 3754 uint64_t msi_tabt : 1; 3755 uint64_t msi_mabt : 1; 3756 uint64_t msc_msg : 1; 3757 uint64_t tsr_abt : 1; 3758 uint64_t serr : 1; 3759 uint64_t aperr : 1; 3760 uint64_t dperr : 1; 3761 uint64_t ill_rwr : 1; 3762 uint64_t ill_rrd : 1; 3763 uint64_t rsl_int : 1; 3764 uint64_t pcnt0 : 1; 3765 uint64_t pcnt1 : 1; 3766 uint64_t pcnt2 : 1; 3767 uint64_t pcnt3 : 1; 3768 uint64_t ptime0 : 1; 3769 uint64_t ptime1 : 1; 3770 uint64_t ptime2 : 1; 3771 uint64_t ptime3 : 1; 3772 uint64_t dcnt0 : 1; 3773 uint64_t dcnt1 : 1; 3774 uint64_t dtime0 : 1; 3775 uint64_t dtime1 : 1; 3776 uint64_t dma0_fi : 1; 3777 uint64_t dma1_fi : 1; 3778 uint64_t win_wr : 1; 3779 uint64_t ill_wr : 1; 3780 uint64_t ill_rd : 1; 3781 uint64_t reserved_34_63 : 30; 3782#endif 3783 } s; 3784 struct cvmx_pci_int_sum2_cn30xx { 3785#ifdef __BIG_ENDIAN_BITFIELD 3786 uint64_t reserved_34_63 : 30; 3787 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3788 when the mem area is disabled. */ 3789 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3790 when the mem area is disabled. */ 3791 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3792 Read-Address Register took place. */ 3793 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3794 required to set the FORCE-INT bit for counter 1. */ 3795 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3796 required to set the FORCE-INT bit for counter 0. */ 3797 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3798 register is not 0 the DMA_CNT1 timer counts. 3799 When the DMA1_CNT timer has a value greater 3800 than the PCI_DMA_TIME1 register this 3801 bit is set. The timer is reset when bit is 3802 written with a one. */ 3803 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3804 register is not 0 the DMA_CNT0 timer counts. 3805 When the DMA0_CNT timer has a value greater 3806 than the PCI_DMA_TIME0 register this 3807 bit is set. The timer is reset when bit is 3808 written with a one. */ 3809 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3810 value is greater than the value 3811 in the PCI_DMA_INT_LEV1 register. */ 3812 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3813 value is greater than the value 3814 in the PCI_DMA_INT_LEV0 register. */ 3815 uint64_t reserved_22_24 : 3; 3816 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3817 register is not 0 the Sent-0 timer counts. 3818 When the Sent-0 timer has a value greater 3819 than the PCI_PKTS_SENT_TIME0 register this 3820 bit is set. The timer is reset when bit is 3821 written with a one. */ 3822 uint64_t reserved_18_20 : 3; 3823 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3824 value is greater than the value 3825 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3826 uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 3827 generated an interrupt. */ 3828 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3829 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3830 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3831 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3832 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3833 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 3834 uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 3835 uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 3836 uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 3837 uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 3838 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 3839 uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 3840 uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 3841 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 3842 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 3843 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 3844#else 3845 uint64_t tr_wabt : 1; 3846 uint64_t mr_wabt : 1; 3847 uint64_t mr_wtto : 1; 3848 uint64_t tr_abt : 1; 3849 uint64_t mr_abt : 1; 3850 uint64_t mr_tto : 1; 3851 uint64_t msi_per : 1; 3852 uint64_t msi_tabt : 1; 3853 uint64_t msi_mabt : 1; 3854 uint64_t msc_msg : 1; 3855 uint64_t tsr_abt : 1; 3856 uint64_t serr : 1; 3857 uint64_t aperr : 1; 3858 uint64_t dperr : 1; 3859 uint64_t ill_rwr : 1; 3860 uint64_t ill_rrd : 1; 3861 uint64_t rsl_int : 1; 3862 uint64_t pcnt0 : 1; 3863 uint64_t reserved_18_20 : 3; 3864 uint64_t ptime0 : 1; 3865 uint64_t reserved_22_24 : 3; 3866 uint64_t dcnt0 : 1; 3867 uint64_t dcnt1 : 1; 3868 uint64_t dtime0 : 1; 3869 uint64_t dtime1 : 1; 3870 uint64_t dma0_fi : 1; 3871 uint64_t dma1_fi : 1; 3872 uint64_t win_wr : 1; 3873 uint64_t ill_wr : 1; 3874 uint64_t ill_rd : 1; 3875 uint64_t reserved_34_63 : 30; 3876#endif 3877 } cn30xx; 3878 struct cvmx_pci_int_sum2_cn31xx { 3879#ifdef __BIG_ENDIAN_BITFIELD 3880 uint64_t reserved_34_63 : 30; 3881 uint64_t ill_rd : 1; /**< A read to a disabled area of bar1 or bar2, 3882 when the mem area is disabled. */ 3883 uint64_t ill_wr : 1; /**< A write to a disabled area of bar1 or bar2, 3884 when the mem area is disabled. */ 3885 uint64_t win_wr : 1; /**< A write to the disabled Window Write Data or 3886 Read-Address Register took place. */ 3887 uint64_t dma1_fi : 1; /**< A DMA operation operation finished that was 3888 required to set the FORCE-INT bit for counter 1. */ 3889 uint64_t dma0_fi : 1; /**< A DMA operation operation finished that was 3890 required to set the FORCE-INT bit for counter 0. */ 3891 uint64_t dtime1 : 1; /**< When the value in the PCI_DMA_CNT1 3892 register is not 0 the DMA_CNT1 timer counts. 3893 When the DMA1_CNT timer has a value greater 3894 than the PCI_DMA_TIME1 register this 3895 bit is set. The timer is reset when bit is 3896 written with a one. */ 3897 uint64_t dtime0 : 1; /**< When the value in the PCI_DMA_CNT0 3898 register is not 0 the DMA_CNT0 timer counts. 3899 When the DMA0_CNT timer has a value greater 3900 than the PCI_DMA_TIME0 register this 3901 bit is set. The timer is reset when bit is 3902 written with a one. */ 3903 uint64_t dcnt1 : 1; /**< This bit indicates that PCI_DMA_CNT1 3904 value is greater than the value 3905 in the PCI_DMA_INT_LEV1 register. */ 3906 uint64_t dcnt0 : 1; /**< This bit indicates that PCI_DMA_CNT0 3907 value is greater than the value 3908 in the PCI_DMA_INT_LEV0 register. */ 3909 uint64_t reserved_23_24 : 2; 3910 uint64_t ptime1 : 1; /**< When the value in the PCI_PKTS_SENT1 3911 register is not 0 the Sent-1 timer counts. 3912 When the Sent-1 timer has a value greater 3913 than the PCI_PKTS_SENT_TIME1 register this 3914 bit is set. The timer is reset when bit is 3915 written with a one. */ 3916 uint64_t ptime0 : 1; /**< When the value in the PCI_PKTS_SENT0 3917 register is not 0 the Sent-0 timer counts. 3918 When the Sent-0 timer has a value greater 3919 than the PCI_PKTS_SENT_TIME0 register this 3920 bit is set. The timer is reset when bit is 3921 written with a one. */ 3922 uint64_t reserved_19_20 : 2; 3923 uint64_t pcnt1 : 1; /**< This bit indicates that PCI_PKTS_SENT1 3924 value is greater than the value 3925 in the PCI_PKTS_SENT_INT_LEV1 register. */ 3926 uint64_t pcnt0 : 1; /**< This bit indicates that PCI_PKTS_SENT0 3927 value is greater than the value 3928 in the PCI_PKTS_SENT_INT_LEV0 register. */ 3929 uint64_t rsl_int : 1; /**< This bit is set when the RSL Chain has 3930 generated an interrupt. */ 3931 uint64_t ill_rrd : 1; /**< A read to the disabled PCI registers took place. */ 3932 uint64_t ill_rwr : 1; /**< A write to the disabled PCI registers took place. */ 3933 uint64_t dperr : 1; /**< Data Parity Error detected by PCX Core */ 3934 uint64_t aperr : 1; /**< Address Parity Error detected by PCX Core */ 3935 uint64_t serr : 1; /**< SERR# detected by PCX Core */ 3936 uint64_t tsr_abt : 1; /**< Target Split-Read Abort Detected */ 3937 uint64_t msc_msg : 1; /**< Master Split Completion Message Detected */ 3938 uint64_t msi_mabt : 1; /**< PCI MSI Master Abort. */ 3939 uint64_t msi_tabt : 1; /**< PCI MSI Target Abort. */ 3940 uint64_t msi_per : 1; /**< PCI MSI Parity Error. */ 3941 uint64_t mr_tto : 1; /**< PCI Master Retry Timeout On Read. */ 3942 uint64_t mr_abt : 1; /**< PCI Master Abort On Read. */ 3943 uint64_t tr_abt : 1; /**< PCI Target Abort On Read. */ 3944 uint64_t mr_wtto : 1; /**< PCI Master Retry Timeout on write. */ 3945 uint64_t mr_wabt : 1; /**< PCI Master Abort detected on write. */ 3946 uint64_t tr_wabt : 1; /**< PCI Target Abort detected on write. */ 3947#else 3948 uint64_t tr_wabt : 1; 3949 uint64_t mr_wabt : 1; 3950 uint64_t mr_wtto : 1; 3951 uint64_t tr_abt : 1; 3952 uint64_t mr_abt : 1; 3953 uint64_t mr_tto : 1; 3954 uint64_t msi_per : 1; 3955 uint64_t msi_tabt : 1; 3956 uint64_t msi_mabt : 1; 3957 uint64_t msc_msg : 1; 3958 uint64_t tsr_abt : 1; 3959 uint64_t serr : 1; 3960 uint64_t aperr : 1; 3961 uint64_t dperr : 1; 3962 uint64_t ill_rwr : 1; 3963 uint64_t ill_rrd : 1; 3964 uint64_t rsl_int : 1; 3965 uint64_t pcnt0 : 1; 3966 uint64_t pcnt1 : 1; 3967 uint64_t reserved_19_20 : 2; 3968 uint64_t ptime0 : 1; 3969 uint64_t ptime1 : 1; 3970 uint64_t reserved_23_24 : 2; 3971 uint64_t dcnt0 : 1; 3972 uint64_t dcnt1 : 1; 3973 uint64_t dtime0 : 1; 3974 uint64_t dtime1 : 1; 3975 uint64_t dma0_fi : 1; 3976 uint64_t dma1_fi : 1; 3977 uint64_t win_wr : 1; 3978 uint64_t ill_wr : 1; 3979 uint64_t ill_rd : 1; 3980 uint64_t reserved_34_63 : 30; 3981#endif 3982 } cn31xx; 3983 struct cvmx_pci_int_sum2_s cn38xx; 3984 struct cvmx_pci_int_sum2_s cn38xxp2; 3985 struct cvmx_pci_int_sum2_cn31xx cn50xx; 3986 struct cvmx_pci_int_sum2_s cn58xx; 3987 struct cvmx_pci_int_sum2_s cn58xxp1; 3988}; 3989typedef union cvmx_pci_int_sum2 cvmx_pci_int_sum2_t; 3990 3991/** 3992 * cvmx_pci_msi_rcv 3993 * 3994 * PCI_MSI_RCV = PCI's MSI Received Vector Register 3995 * 3996 * A bit is set in this register relative to the vector received during a MSI. The value in this 3997 * register is acted upon when the least-significant-byte of this register is written. 3998 */ 3999union cvmx_pci_msi_rcv { 4000 uint32_t u32; 4001 struct cvmx_pci_msi_rcv_s { 4002#ifdef __BIG_ENDIAN_BITFIELD 4003 uint32_t reserved_6_31 : 26; 4004 uint32_t intr : 6; /**< When an MSI is received on the PCI the bit selected 4005 by data [5:0] will be set in this register. To 4006 clear this bit a write must take place to the 4007 NPI_MSI_RCV register where any bit set to 1 is 4008 cleared. Reading this address will return an 4009 unpredicatable value. */ 4010#else 4011 uint32_t intr : 6; 4012 uint32_t reserved_6_31 : 26; 4013#endif 4014 } s; 4015 struct cvmx_pci_msi_rcv_s cn30xx; 4016 struct cvmx_pci_msi_rcv_s cn31xx; 4017 struct cvmx_pci_msi_rcv_s cn38xx; 4018 struct cvmx_pci_msi_rcv_s cn38xxp2; 4019 struct cvmx_pci_msi_rcv_s cn50xx; 4020 struct cvmx_pci_msi_rcv_s cn58xx; 4021 struct cvmx_pci_msi_rcv_s cn58xxp1; 4022}; 4023typedef union cvmx_pci_msi_rcv cvmx_pci_msi_rcv_t; 4024 4025/** 4026 * cvmx_pci_pkt_credits# 4027 * 4028 * PCI_PKT_CREDITS0 = PCI Packet Credits For Output 0 4029 * 4030 * Used to decrease the number of packets to be processed by the host from Output-0 and return 4031 * buffer/info pointer pairs to OCTEON Output-0. The value in this register is acted upon when the 4032 * least-significant-byte of this register is written. 4033 */ 4034union cvmx_pci_pkt_creditsx { 4035 uint32_t u32; 4036 struct cvmx_pci_pkt_creditsx_s { 4037#ifdef __BIG_ENDIAN_BITFIELD 4038 uint32_t pkt_cnt : 16; /**< The value written to this field will be 4039 subtracted from PCI_PKTS_SENT0[PKT_CNT]. */ 4040 uint32_t ptr_cnt : 16; /**< This field value is added to the 4041 NPI's internal Buffer/Info Pointer Pair count. */ 4042#else 4043 uint32_t ptr_cnt : 16; 4044 uint32_t pkt_cnt : 16; 4045#endif 4046 } s; 4047 struct cvmx_pci_pkt_creditsx_s cn30xx; 4048 struct cvmx_pci_pkt_creditsx_s cn31xx; 4049 struct cvmx_pci_pkt_creditsx_s cn38xx; 4050 struct cvmx_pci_pkt_creditsx_s cn38xxp2; 4051 struct cvmx_pci_pkt_creditsx_s cn50xx; 4052 struct cvmx_pci_pkt_creditsx_s cn58xx; 4053 struct cvmx_pci_pkt_creditsx_s cn58xxp1; 4054}; 4055typedef union cvmx_pci_pkt_creditsx cvmx_pci_pkt_creditsx_t; 4056 4057/** 4058 * cvmx_pci_pkts_sent# 4059 * 4060 * PCI_PKTS_SENT0 = PCI Packets Sent 0 4061 * 4062 * Number of packets sent to the host memory from PCI Output 0 4063 */ 4064union cvmx_pci_pkts_sentx { 4065 uint32_t u32; 4066 struct cvmx_pci_pkts_sentx_s { 4067#ifdef __BIG_ENDIAN_BITFIELD 4068 uint32_t pkt_cnt : 32; /**< Each time a packet is written to the memory via 4069 PCI from PCI Output 0, this counter is 4070 incremented by 1 or the byte count of the packet 4071 as set in NPI_OUTPUT_CONTROL[P0_BMODE]. */ 4072#else 4073 uint32_t pkt_cnt : 32; 4074#endif 4075 } s; 4076 struct cvmx_pci_pkts_sentx_s cn30xx; 4077 struct cvmx_pci_pkts_sentx_s cn31xx; 4078 struct cvmx_pci_pkts_sentx_s cn38xx; 4079 struct cvmx_pci_pkts_sentx_s cn38xxp2; 4080 struct cvmx_pci_pkts_sentx_s cn50xx; 4081 struct cvmx_pci_pkts_sentx_s cn58xx; 4082 struct cvmx_pci_pkts_sentx_s cn58xxp1; 4083}; 4084typedef union cvmx_pci_pkts_sentx cvmx_pci_pkts_sentx_t; 4085 4086/** 4087 * cvmx_pci_pkts_sent_int_lev# 4088 * 4089 * PCI_PKTS_SENT_INT_LEV0 = PCI Packets Sent Interrupt Level For Output 0 4090 * 4091 * Interrupt when number of packets sent is equal to or greater than the register value. 4092 */ 4093union cvmx_pci_pkts_sent_int_levx { 4094 uint32_t u32; 4095 struct cvmx_pci_pkts_sent_int_levx_s { 4096#ifdef __BIG_ENDIAN_BITFIELD 4097 uint32_t pkt_cnt : 32; /**< When corresponding port's PCI_PKTS_SENT0 value 4098 exceeds the value in this register, PCNT0 of the 4099 PCI_INT_SUM and PCI_INT_SUM2 will be set. */ 4100#else 4101 uint32_t pkt_cnt : 32; 4102#endif 4103 } s; 4104 struct cvmx_pci_pkts_sent_int_levx_s cn30xx; 4105 struct cvmx_pci_pkts_sent_int_levx_s cn31xx; 4106 struct cvmx_pci_pkts_sent_int_levx_s cn38xx; 4107 struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2; 4108 struct cvmx_pci_pkts_sent_int_levx_s cn50xx; 4109 struct cvmx_pci_pkts_sent_int_levx_s cn58xx; 4110 struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1; 4111}; 4112typedef union cvmx_pci_pkts_sent_int_levx cvmx_pci_pkts_sent_int_levx_t; 4113 4114/** 4115 * cvmx_pci_pkts_sent_time# 4116 * 4117 * PCI_PKTS_SENT_TIME0 = PCI Packets Sent Timer For Output-0 4118 * 4119 * Time to wait from packet being sent to host from Output-0 before issuing an interrupt. 4120 */ 4121union cvmx_pci_pkts_sent_timex { 4122 uint32_t u32; 4123 struct cvmx_pci_pkts_sent_timex_s { 4124#ifdef __BIG_ENDIAN_BITFIELD 4125 uint32_t pkt_time : 32; /**< Number of PCI clock cycle to wait before 4126 issuing an interrupt to the host when a 4127 packet from this port has been sent to the 4128 host. The timer is reset when the 4129 PCI_INT_SUM[21] register is cleared. */ 4130#else 4131 uint32_t pkt_time : 32; 4132#endif 4133 } s; 4134 struct cvmx_pci_pkts_sent_timex_s cn30xx; 4135 struct cvmx_pci_pkts_sent_timex_s cn31xx; 4136 struct cvmx_pci_pkts_sent_timex_s cn38xx; 4137 struct cvmx_pci_pkts_sent_timex_s cn38xxp2; 4138 struct cvmx_pci_pkts_sent_timex_s cn50xx; 4139 struct cvmx_pci_pkts_sent_timex_s cn58xx; 4140 struct cvmx_pci_pkts_sent_timex_s cn58xxp1; 4141}; 4142typedef union cvmx_pci_pkts_sent_timex cvmx_pci_pkts_sent_timex_t; 4143 4144/** 4145 * cvmx_pci_read_cmd_6 4146 * 4147 * PCI_READ_CMD_6 = PCI Read Command 6 Register 4148 * 4149 * Contains control inforamtion related to a received PCI Command 6. 4150 */ 4151union cvmx_pci_read_cmd_6 { 4152 uint32_t u32; 4153 struct cvmx_pci_read_cmd_6_s { 4154#ifdef __BIG_ENDIAN_BITFIELD 4155 uint32_t reserved_9_31 : 23; 4156 uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4157 before informing the PCIX-Core that we have 4158 read data available for the outstanding Delayed 4159 read. 0 is treated as a 64. 4160 For reads to the expansion this value is not used. */ 4161 uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4162 this type of bhmstREAD command is received. 4163 0 = 1 32/64 bit word. 4164 1 = From address to end of 128B block. 4165 2 = From address to end of 128B block plus 128B. 4166 3 = From address to end of 128B block plus 256B. 4167 4 = From address to end of 128B block plus 384B. 4168 For reads to the expansion this value is not used. */ 4169#else 4170 uint32_t prefetch : 3; 4171 uint32_t min_data : 6; 4172 uint32_t reserved_9_31 : 23; 4173#endif 4174 } s; 4175 struct cvmx_pci_read_cmd_6_s cn30xx; 4176 struct cvmx_pci_read_cmd_6_s cn31xx; 4177 struct cvmx_pci_read_cmd_6_s cn38xx; 4178 struct cvmx_pci_read_cmd_6_s cn38xxp2; 4179 struct cvmx_pci_read_cmd_6_s cn50xx; 4180 struct cvmx_pci_read_cmd_6_s cn58xx; 4181 struct cvmx_pci_read_cmd_6_s cn58xxp1; 4182}; 4183typedef union cvmx_pci_read_cmd_6 cvmx_pci_read_cmd_6_t; 4184 4185/** 4186 * cvmx_pci_read_cmd_c 4187 * 4188 * PCI_READ_CMD_C = PCI Read Command C Register 4189 * 4190 * Contains control inforamtion related to a received PCI Command C. 4191 */ 4192union cvmx_pci_read_cmd_c { 4193 uint32_t u32; 4194 struct cvmx_pci_read_cmd_c_s { 4195#ifdef __BIG_ENDIAN_BITFIELD 4196 uint32_t reserved_9_31 : 23; 4197 uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4198 before informing the PCIX-Core that we have 4199 read data available for the outstanding Delayed 4200 read. 0 is treated as a 64. 4201 For reads to the expansion this value is not used. */ 4202 uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4203 this type of READ command is received. 4204 0 = 1 32/64 bit word. 4205 1 = From address to end of 128B block. 4206 2 = From address to end of 128B block plus 128B. 4207 3 = From address to end of 128B block plus 256B. 4208 4 = From address to end of 128B block plus 384B. 4209 For reads to the expansion this value is not used. */ 4210#else 4211 uint32_t prefetch : 3; 4212 uint32_t min_data : 6; 4213 uint32_t reserved_9_31 : 23; 4214#endif 4215 } s; 4216 struct cvmx_pci_read_cmd_c_s cn30xx; 4217 struct cvmx_pci_read_cmd_c_s cn31xx; 4218 struct cvmx_pci_read_cmd_c_s cn38xx; 4219 struct cvmx_pci_read_cmd_c_s cn38xxp2; 4220 struct cvmx_pci_read_cmd_c_s cn50xx; 4221 struct cvmx_pci_read_cmd_c_s cn58xx; 4222 struct cvmx_pci_read_cmd_c_s cn58xxp1; 4223}; 4224typedef union cvmx_pci_read_cmd_c cvmx_pci_read_cmd_c_t; 4225 4226/** 4227 * cvmx_pci_read_cmd_e 4228 * 4229 * PCI_READ_CMD_E = PCI Read Command E Register 4230 * 4231 * Contains control inforamtion related to a received PCI Command 6. 4232 */ 4233union cvmx_pci_read_cmd_e { 4234 uint32_t u32; 4235 struct cvmx_pci_read_cmd_e_s { 4236#ifdef __BIG_ENDIAN_BITFIELD 4237 uint32_t reserved_9_31 : 23; 4238 uint32_t min_data : 6; /**< The number of words to have buffered in the PNI 4239 before informaing the PCIX-Core that we have 4240 read data available for the outstanding Delayed 4241 read. 0 is treated as a 64. 4242 For reads to the expansion this value is not used. */ 4243 uint32_t prefetch : 3; /**< Control the amount of data to be preteched when 4244 this type of READ command is received. 4245 0 = 1 32/64 bit word. 4246 1 = From address to end of 128B block. 4247 2 = From address to end of 128B block plus 128B. 4248 3 = From address to end of 128B block plus 256B. 4249 4 = From address to end of 128B block plus 384B. 4250 For reads to the expansion this value is not used. */ 4251#else 4252 uint32_t prefetch : 3; 4253 uint32_t min_data : 6; 4254 uint32_t reserved_9_31 : 23; 4255#endif 4256 } s; 4257 struct cvmx_pci_read_cmd_e_s cn30xx; 4258 struct cvmx_pci_read_cmd_e_s cn31xx; 4259 struct cvmx_pci_read_cmd_e_s cn38xx; 4260 struct cvmx_pci_read_cmd_e_s cn38xxp2; 4261 struct cvmx_pci_read_cmd_e_s cn50xx; 4262 struct cvmx_pci_read_cmd_e_s cn58xx; 4263 struct cvmx_pci_read_cmd_e_s cn58xxp1; 4264}; 4265typedef union cvmx_pci_read_cmd_e cvmx_pci_read_cmd_e_t; 4266 4267/** 4268 * cvmx_pci_read_timeout 4269 * 4270 * PCI_READ_TIMEOUT = PCI Read Timeour Register 4271 * 4272 * The address to start reading Instructions from for Input-3. 4273 */ 4274union cvmx_pci_read_timeout { 4275 uint64_t u64; 4276 struct cvmx_pci_read_timeout_s { 4277#ifdef __BIG_ENDIAN_BITFIELD 4278 uint64_t reserved_32_63 : 32; 4279 uint64_t enb : 1; /**< Enable the use of the Timeout function. */ 4280 uint64_t cnt : 31; /**< The number of eclk cycles to wait after issuing 4281 a read request to the PNI before setting a 4282 timeout and not expecting the data to return. 4283 This is considered a fatal condition by the NPI. */ 4284#else 4285 uint64_t cnt : 31; 4286 uint64_t enb : 1; 4287 uint64_t reserved_32_63 : 32; 4288#endif 4289 } s; 4290 struct cvmx_pci_read_timeout_s cn30xx; 4291 struct cvmx_pci_read_timeout_s cn31xx; 4292 struct cvmx_pci_read_timeout_s cn38xx; 4293 struct cvmx_pci_read_timeout_s cn38xxp2; 4294 struct cvmx_pci_read_timeout_s cn50xx; 4295 struct cvmx_pci_read_timeout_s cn58xx; 4296 struct cvmx_pci_read_timeout_s cn58xxp1; 4297}; 4298typedef union cvmx_pci_read_timeout cvmx_pci_read_timeout_t; 4299 4300/** 4301 * cvmx_pci_scm_reg 4302 * 4303 * PCI_SCM_REG = PCI Master Split Completion Message Register 4304 * 4305 * This register contains the Master Split Completion Message(SCM) generated when a master split 4306 * transaction is aborted. 4307 */ 4308union cvmx_pci_scm_reg { 4309 uint64_t u64; 4310 struct cvmx_pci_scm_reg_s { 4311#ifdef __BIG_ENDIAN_BITFIELD 4312 uint64_t reserved_32_63 : 32; 4313 uint64_t scm : 32; /**< Contains the Split Completion Message (SCM) 4314 driven when a master-split transaction is aborted. 4315 [31:28]: Message Class 4316 [27:20]: Message Index 4317 [19]: Reserved 4318 [18:12]: Remaining Lower Address 4319 [11:8]: Upper Remaining Byte Count 4320 [7:0]: Lower Remaining Byte Count 4321 Refer to the PCIX1.0a specification, Fig 2-40 4322 for additional details for the split completion 4323 message format. */ 4324#else 4325 uint64_t scm : 32; 4326 uint64_t reserved_32_63 : 32; 4327#endif 4328 } s; 4329 struct cvmx_pci_scm_reg_s cn30xx; 4330 struct cvmx_pci_scm_reg_s cn31xx; 4331 struct cvmx_pci_scm_reg_s cn38xx; 4332 struct cvmx_pci_scm_reg_s cn38xxp2; 4333 struct cvmx_pci_scm_reg_s cn50xx; 4334 struct cvmx_pci_scm_reg_s cn58xx; 4335 struct cvmx_pci_scm_reg_s cn58xxp1; 4336}; 4337typedef union cvmx_pci_scm_reg cvmx_pci_scm_reg_t; 4338 4339/** 4340 * cvmx_pci_tsr_reg 4341 * 4342 * PCI_TSR_REG = PCI Target Split Attribute Register 4343 * 4344 * This register contains the Attribute field Master Split Completion Message(SCM) generated when a master split 4345 * transaction is aborted. 4346 */ 4347union cvmx_pci_tsr_reg { 4348 uint64_t u64; 4349 struct cvmx_pci_tsr_reg_s { 4350#ifdef __BIG_ENDIAN_BITFIELD 4351 uint64_t reserved_36_63 : 28; 4352 uint64_t tsr : 36; /**< Contains the Target Split Attribute field when a 4353 target-split transaction is aborted. 4354 [35:32]: Upper Byte Count 4355 [31]: BCM=Byte Count Modified 4356 [30]: SCE=Split Completion Error 4357 [29]: SCM=Split Completion Message 4358 [28:24]: RESERVED 4359 [23:16]: Completer Bus Number 4360 [15:11]: Completer Device Number 4361 [10:8]: Completer Function Number 4362 [7:0]: Lower Byte Count 4363 Refer to the PCIX1.0a specification, Fig 2-39 4364 for additional details on the completer attribute 4365 bit assignments. */ 4366#else 4367 uint64_t tsr : 36; 4368 uint64_t reserved_36_63 : 28; 4369#endif 4370 } s; 4371 struct cvmx_pci_tsr_reg_s cn30xx; 4372 struct cvmx_pci_tsr_reg_s cn31xx; 4373 struct cvmx_pci_tsr_reg_s cn38xx; 4374 struct cvmx_pci_tsr_reg_s cn38xxp2; 4375 struct cvmx_pci_tsr_reg_s cn50xx; 4376 struct cvmx_pci_tsr_reg_s cn58xx; 4377 struct cvmx_pci_tsr_reg_s cn58xxp1; 4378}; 4379typedef union cvmx_pci_tsr_reg cvmx_pci_tsr_reg_t; 4380 4381/** 4382 * cvmx_pci_win_rd_addr 4383 * 4384 * PCI_WIN_RD_ADDR = PCI Window Read Address Register 4385 * 4386 * Writing the least-significant-byte of this register will cause a read operation to take place, 4387 * UNLESS, a read operation is already taking place. A read is consider to end when the PCI_WIN_RD_DATA 4388 * register is read. 4389 */ 4390union cvmx_pci_win_rd_addr { 4391 uint64_t u64; 4392 struct cvmx_pci_win_rd_addr_s { 4393#ifdef __BIG_ENDIAN_BITFIELD 4394 uint64_t reserved_49_63 : 15; 4395 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4396 read as '0'. */ 4397 uint64_t reserved_0_47 : 48; 4398#else 4399 uint64_t reserved_0_47 : 48; 4400 uint64_t iobit : 1; 4401 uint64_t reserved_49_63 : 15; 4402#endif 4403 } s; 4404 struct cvmx_pci_win_rd_addr_cn30xx { 4405#ifdef __BIG_ENDIAN_BITFIELD 4406 uint64_t reserved_49_63 : 15; 4407 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4408 read as '0'. */ 4409 uint64_t rd_addr : 46; /**< The address to be read from. Whenever the LSB of 4410 this register is written, the Read Operation will 4411 take place. 4412 [47:40] = NCB_ID 4413 [39:3] = Address 4414 When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4415 [39:32] == x, Not Used 4416 [31:27] == RSL_ID 4417 [12:2] == RSL Register Offset 4418 [1:0] == x, Not Used */ 4419 uint64_t reserved_0_1 : 2; 4420#else 4421 uint64_t reserved_0_1 : 2; 4422 uint64_t rd_addr : 46; 4423 uint64_t iobit : 1; 4424 uint64_t reserved_49_63 : 15; 4425#endif 4426 } cn30xx; 4427 struct cvmx_pci_win_rd_addr_cn30xx cn31xx; 4428 struct cvmx_pci_win_rd_addr_cn38xx { 4429#ifdef __BIG_ENDIAN_BITFIELD 4430 uint64_t reserved_49_63 : 15; 4431 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4432 read as '0'. */ 4433 uint64_t rd_addr : 45; /**< The address to be read from. Whenever the LSB of 4434 this register is written, the Read Operation will 4435 take place. 4436 [47:40] = NCB_ID 4437 [39:3] = Address 4438 When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4439 [39:32] == x, Not Used 4440 [31:27] == RSL_ID 4441 [12:3] == RSL Register Offset 4442 [2:0] == x, Not Used */ 4443 uint64_t reserved_0_2 : 3; 4444#else 4445 uint64_t reserved_0_2 : 3; 4446 uint64_t rd_addr : 45; 4447 uint64_t iobit : 1; 4448 uint64_t reserved_49_63 : 15; 4449#endif 4450 } cn38xx; 4451 struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2; 4452 struct cvmx_pci_win_rd_addr_cn30xx cn50xx; 4453 struct cvmx_pci_win_rd_addr_cn38xx cn58xx; 4454 struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1; 4455}; 4456typedef union cvmx_pci_win_rd_addr cvmx_pci_win_rd_addr_t; 4457 4458/** 4459 * cvmx_pci_win_rd_data 4460 * 4461 * PCI_WIN_RD_DATA = PCI Window Read Data Register 4462 * 4463 * Contains the result from the read operation that took place when the LSB of the PCI_WIN_RD_ADDR 4464 * register was written. 4465 */ 4466union cvmx_pci_win_rd_data { 4467 uint64_t u64; 4468 struct cvmx_pci_win_rd_data_s { 4469#ifdef __BIG_ENDIAN_BITFIELD 4470 uint64_t rd_data : 64; /**< The read data. */ 4471#else 4472 uint64_t rd_data : 64; 4473#endif 4474 } s; 4475 struct cvmx_pci_win_rd_data_s cn30xx; 4476 struct cvmx_pci_win_rd_data_s cn31xx; 4477 struct cvmx_pci_win_rd_data_s cn38xx; 4478 struct cvmx_pci_win_rd_data_s cn38xxp2; 4479 struct cvmx_pci_win_rd_data_s cn50xx; 4480 struct cvmx_pci_win_rd_data_s cn58xx; 4481 struct cvmx_pci_win_rd_data_s cn58xxp1; 4482}; 4483typedef union cvmx_pci_win_rd_data cvmx_pci_win_rd_data_t; 4484 4485/** 4486 * cvmx_pci_win_wr_addr 4487 * 4488 * PCI_WIN_WR_ADDR = PCI Window Write Address Register 4489 * 4490 * Contains the address to be writen to when a write operation is started by writing the 4491 * PCI_WIN_WR_DATA register (see below). 4492 */ 4493union cvmx_pci_win_wr_addr { 4494 uint64_t u64; 4495 struct cvmx_pci_win_wr_addr_s { 4496#ifdef __BIG_ENDIAN_BITFIELD 4497 uint64_t reserved_49_63 : 15; 4498 uint64_t iobit : 1; /**< A 1 or 0 can be written here but this will always 4499 read as '0'. */ 4500 uint64_t wr_addr : 45; /**< The address that will be written to when the 4501 PCI_WIN_WR_DATA register is written. 4502 [47:40] = NCB_ID 4503 [39:3] = Address 4504 When [47:43] == NPI & [42:0] == 0 bits [39:0] are: 4505 [39:32] == x, Not Used 4506 [31:27] == RSL_ID 4507 [12:3] == RSL Register Offset 4508 [2:0] == x, Not Used */ 4509 uint64_t reserved_0_2 : 3; 4510#else 4511 uint64_t reserved_0_2 : 3; 4512 uint64_t wr_addr : 45; 4513 uint64_t iobit : 1; 4514 uint64_t reserved_49_63 : 15; 4515#endif 4516 } s; 4517 struct cvmx_pci_win_wr_addr_s cn30xx; 4518 struct cvmx_pci_win_wr_addr_s cn31xx; 4519 struct cvmx_pci_win_wr_addr_s cn38xx; 4520 struct cvmx_pci_win_wr_addr_s cn38xxp2; 4521 struct cvmx_pci_win_wr_addr_s cn50xx; 4522 struct cvmx_pci_win_wr_addr_s cn58xx; 4523 struct cvmx_pci_win_wr_addr_s cn58xxp1; 4524}; 4525typedef union cvmx_pci_win_wr_addr cvmx_pci_win_wr_addr_t; 4526 4527/** 4528 * cvmx_pci_win_wr_data 4529 * 4530 * PCI_WIN_WR_DATA = PCI Window Write Data Register 4531 * 4532 * Contains the data to write to the address located in the PCI_WIN_WR_ADDR Register. 4533 * Writing the least-significant-byte of this register will cause a write operation to take place. 4534 */ 4535union cvmx_pci_win_wr_data { 4536 uint64_t u64; 4537 struct cvmx_pci_win_wr_data_s { 4538#ifdef __BIG_ENDIAN_BITFIELD 4539 uint64_t wr_data : 64; /**< The data to be written. Whenever the LSB of this 4540 register is written, the Window Write will take 4541 place. */ 4542#else 4543 uint64_t wr_data : 64; 4544#endif 4545 } s; 4546 struct cvmx_pci_win_wr_data_s cn30xx; 4547 struct cvmx_pci_win_wr_data_s cn31xx; 4548 struct cvmx_pci_win_wr_data_s cn38xx; 4549 struct cvmx_pci_win_wr_data_s cn38xxp2; 4550 struct cvmx_pci_win_wr_data_s cn50xx; 4551 struct cvmx_pci_win_wr_data_s cn58xx; 4552 struct cvmx_pci_win_wr_data_s cn58xxp1; 4553}; 4554typedef union cvmx_pci_win_wr_data cvmx_pci_win_wr_data_t; 4555 4556/** 4557 * cvmx_pci_win_wr_mask 4558 * 4559 * PCI_WIN_WR_MASK = PCI Window Write Mask Register 4560 * 4561 * Contains the mask for the data in the PCI_WIN_WR_DATA Register. 4562 */ 4563union cvmx_pci_win_wr_mask { 4564 uint64_t u64; 4565 struct cvmx_pci_win_wr_mask_s { 4566#ifdef __BIG_ENDIAN_BITFIELD 4567 uint64_t reserved_8_63 : 56; 4568 uint64_t wr_mask : 8; /**< The data to be written. When a bit is set '1' 4569 the corresponding byte will not be written. */ 4570#else 4571 uint64_t wr_mask : 8; 4572 uint64_t reserved_8_63 : 56; 4573#endif 4574 } s; 4575 struct cvmx_pci_win_wr_mask_s cn30xx; 4576 struct cvmx_pci_win_wr_mask_s cn31xx; 4577 struct cvmx_pci_win_wr_mask_s cn38xx; 4578 struct cvmx_pci_win_wr_mask_s cn38xxp2; 4579 struct cvmx_pci_win_wr_mask_s cn50xx; 4580 struct cvmx_pci_win_wr_mask_s cn58xx; 4581 struct cvmx_pci_win_wr_mask_s cn58xxp1; 4582}; 4583typedef union cvmx_pci_win_wr_mask cvmx_pci_win_wr_mask_t; 4584 4585#endif 4586