1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-iob-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon iob. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_IOB_DEFS_H__ 53232812Sjmallett#define __CVMX_IOB_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull)) 56215976Sjmallett#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull)) 57215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 58215976Sjmallett#define CVMX_IOB_DWB_PRI_CNT CVMX_IOB_DWB_PRI_CNT_FUNC() 59215976Sjmallettstatic inline uint64_t CVMX_IOB_DWB_PRI_CNT_FUNC(void) 60215976Sjmallett{ 61232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 62215976Sjmallett cvmx_warn("CVMX_IOB_DWB_PRI_CNT not supported on this chip\n"); 63215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000028ull); 64215976Sjmallett} 65215976Sjmallett#else 66215976Sjmallett#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull)) 67215976Sjmallett#endif 68215976Sjmallett#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull)) 69215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 70215976Sjmallett#define CVMX_IOB_I2C_PRI_CNT CVMX_IOB_I2C_PRI_CNT_FUNC() 71215976Sjmallettstatic inline uint64_t CVMX_IOB_I2C_PRI_CNT_FUNC(void) 72215976Sjmallett{ 73232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 74215976Sjmallett cvmx_warn("CVMX_IOB_I2C_PRI_CNT not supported on this chip\n"); 75215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000010ull); 76215976Sjmallett} 77215976Sjmallett#else 78215976Sjmallett#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull)) 79215976Sjmallett#endif 80215976Sjmallett#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull)) 81215976Sjmallett#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull)) 82215976Sjmallett#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull)) 83215976Sjmallett#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull)) 84215976Sjmallett#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull)) 85215976Sjmallett#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull)) 86215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 87215976Sjmallett#define CVMX_IOB_N2C_L2C_PRI_CNT CVMX_IOB_N2C_L2C_PRI_CNT_FUNC() 88215976Sjmallettstatic inline uint64_t CVMX_IOB_N2C_L2C_PRI_CNT_FUNC(void) 89215976Sjmallett{ 90232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 91215976Sjmallett cvmx_warn("CVMX_IOB_N2C_L2C_PRI_CNT not supported on this chip\n"); 92215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000020ull); 93215976Sjmallett} 94215976Sjmallett#else 95215976Sjmallett#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull)) 96215976Sjmallett#endif 97215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 98215976Sjmallett#define CVMX_IOB_N2C_RSP_PRI_CNT CVMX_IOB_N2C_RSP_PRI_CNT_FUNC() 99215976Sjmallettstatic inline uint64_t CVMX_IOB_N2C_RSP_PRI_CNT_FUNC(void) 100215976Sjmallett{ 101232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 102215976Sjmallett cvmx_warn("CVMX_IOB_N2C_RSP_PRI_CNT not supported on this chip\n"); 103215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000008ull); 104215976Sjmallett} 105215976Sjmallett#else 106215976Sjmallett#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull)) 107215976Sjmallett#endif 108215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 109215976Sjmallett#define CVMX_IOB_OUTB_COM_PRI_CNT CVMX_IOB_OUTB_COM_PRI_CNT_FUNC() 110215976Sjmallettstatic inline uint64_t CVMX_IOB_OUTB_COM_PRI_CNT_FUNC(void) 111215976Sjmallett{ 112232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 113215976Sjmallett cvmx_warn("CVMX_IOB_OUTB_COM_PRI_CNT not supported on this chip\n"); 114215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000040ull); 115215976Sjmallett} 116215976Sjmallett#else 117215976Sjmallett#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull)) 118215976Sjmallett#endif 119215976Sjmallett#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull)) 120215976Sjmallett#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull)) 121215976Sjmallett#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull)) 122215976Sjmallett#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull)) 123215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 124215976Sjmallett#define CVMX_IOB_OUTB_FPA_PRI_CNT CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC() 125215976Sjmallettstatic inline uint64_t CVMX_IOB_OUTB_FPA_PRI_CNT_FUNC(void) 126215976Sjmallett{ 127232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 128215976Sjmallett cvmx_warn("CVMX_IOB_OUTB_FPA_PRI_CNT not supported on this chip\n"); 129215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000048ull); 130215976Sjmallett} 131215976Sjmallett#else 132215976Sjmallett#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull)) 133215976Sjmallett#endif 134215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 135215976Sjmallett#define CVMX_IOB_OUTB_REQ_PRI_CNT CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC() 136215976Sjmallettstatic inline uint64_t CVMX_IOB_OUTB_REQ_PRI_CNT_FUNC(void) 137215976Sjmallett{ 138232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 139215976Sjmallett cvmx_warn("CVMX_IOB_OUTB_REQ_PRI_CNT not supported on this chip\n"); 140215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000038ull); 141215976Sjmallett} 142215976Sjmallett#else 143215976Sjmallett#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull)) 144215976Sjmallett#endif 145215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146215976Sjmallett#define CVMX_IOB_P2C_REQ_PRI_CNT CVMX_IOB_P2C_REQ_PRI_CNT_FUNC() 147215976Sjmallettstatic inline uint64_t CVMX_IOB_P2C_REQ_PRI_CNT_FUNC(void) 148215976Sjmallett{ 149232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 150215976Sjmallett cvmx_warn("CVMX_IOB_P2C_REQ_PRI_CNT not supported on this chip\n"); 151215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000018ull); 152215976Sjmallett} 153215976Sjmallett#else 154215976Sjmallett#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull)) 155215976Sjmallett#endif 156232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 157232812Sjmallett#define CVMX_IOB_PKT_ERR CVMX_IOB_PKT_ERR_FUNC() 158232812Sjmallettstatic inline uint64_t CVMX_IOB_PKT_ERR_FUNC(void) 159232812Sjmallett{ 160232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 161232812Sjmallett cvmx_warn("CVMX_IOB_PKT_ERR not supported on this chip\n"); 162232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000068ull); 163232812Sjmallett} 164232812Sjmallett#else 165215976Sjmallett#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull)) 166232812Sjmallett#endif 167215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 168215976Sjmallett#define CVMX_IOB_TO_CMB_CREDITS CVMX_IOB_TO_CMB_CREDITS_FUNC() 169215976Sjmallettstatic inline uint64_t CVMX_IOB_TO_CMB_CREDITS_FUNC(void) 170215976Sjmallett{ 171232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 172215976Sjmallett cvmx_warn("CVMX_IOB_TO_CMB_CREDITS not supported on this chip\n"); 173215976Sjmallett return CVMX_ADD_IO_SEG(0x00011800F00000B0ull); 174215976Sjmallett} 175215976Sjmallett#else 176215976Sjmallett#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull)) 177215976Sjmallett#endif 178232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 179232812Sjmallett#define CVMX_IOB_TO_NCB_DID_00_CREDITS CVMX_IOB_TO_NCB_DID_00_CREDITS_FUNC() 180232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_00_CREDITS_FUNC(void) 181232812Sjmallett{ 182232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 183232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_00_CREDITS not supported on this chip\n"); 184232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000800ull); 185232812Sjmallett} 186232812Sjmallett#else 187232812Sjmallett#define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull)) 188232812Sjmallett#endif 189232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 190232812Sjmallett#define CVMX_IOB_TO_NCB_DID_111_CREDITS CVMX_IOB_TO_NCB_DID_111_CREDITS_FUNC() 191232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_111_CREDITS_FUNC(void) 192232812Sjmallett{ 193232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 194232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_111_CREDITS not supported on this chip\n"); 195232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000B78ull); 196232812Sjmallett} 197232812Sjmallett#else 198232812Sjmallett#define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull)) 199232812Sjmallett#endif 200232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 201232812Sjmallett#define CVMX_IOB_TO_NCB_DID_223_CREDITS CVMX_IOB_TO_NCB_DID_223_CREDITS_FUNC() 202232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_223_CREDITS_FUNC(void) 203232812Sjmallett{ 204232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 205232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_223_CREDITS not supported on this chip\n"); 206232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000EF8ull); 207232812Sjmallett} 208232812Sjmallett#else 209232812Sjmallett#define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull)) 210232812Sjmallett#endif 211232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212232812Sjmallett#define CVMX_IOB_TO_NCB_DID_24_CREDITS CVMX_IOB_TO_NCB_DID_24_CREDITS_FUNC() 213232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_24_CREDITS_FUNC(void) 214232812Sjmallett{ 215232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 216232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_24_CREDITS not supported on this chip\n"); 217232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F00008C0ull); 218232812Sjmallett} 219232812Sjmallett#else 220232812Sjmallett#define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull)) 221232812Sjmallett#endif 222232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 223232812Sjmallett#define CVMX_IOB_TO_NCB_DID_32_CREDITS CVMX_IOB_TO_NCB_DID_32_CREDITS_FUNC() 224232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_32_CREDITS_FUNC(void) 225232812Sjmallett{ 226232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 227232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_32_CREDITS not supported on this chip\n"); 228232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000900ull); 229232812Sjmallett} 230232812Sjmallett#else 231232812Sjmallett#define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull)) 232232812Sjmallett#endif 233232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 234232812Sjmallett#define CVMX_IOB_TO_NCB_DID_40_CREDITS CVMX_IOB_TO_NCB_DID_40_CREDITS_FUNC() 235232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_40_CREDITS_FUNC(void) 236232812Sjmallett{ 237232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 238232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_40_CREDITS not supported on this chip\n"); 239232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000940ull); 240232812Sjmallett} 241232812Sjmallett#else 242232812Sjmallett#define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull)) 243232812Sjmallett#endif 244232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 245232812Sjmallett#define CVMX_IOB_TO_NCB_DID_55_CREDITS CVMX_IOB_TO_NCB_DID_55_CREDITS_FUNC() 246232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_55_CREDITS_FUNC(void) 247232812Sjmallett{ 248232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 249232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_55_CREDITS not supported on this chip\n"); 250232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F00009B8ull); 251232812Sjmallett} 252232812Sjmallett#else 253232812Sjmallett#define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull)) 254232812Sjmallett#endif 255232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 256232812Sjmallett#define CVMX_IOB_TO_NCB_DID_64_CREDITS CVMX_IOB_TO_NCB_DID_64_CREDITS_FUNC() 257232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_64_CREDITS_FUNC(void) 258232812Sjmallett{ 259232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 260232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_64_CREDITS not supported on this chip\n"); 261232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000A00ull); 262232812Sjmallett} 263232812Sjmallett#else 264232812Sjmallett#define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull)) 265232812Sjmallett#endif 266232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 267232812Sjmallett#define CVMX_IOB_TO_NCB_DID_79_CREDITS CVMX_IOB_TO_NCB_DID_79_CREDITS_FUNC() 268232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_79_CREDITS_FUNC(void) 269232812Sjmallett{ 270232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 271232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_79_CREDITS not supported on this chip\n"); 272232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000A78ull); 273232812Sjmallett} 274232812Sjmallett#else 275232812Sjmallett#define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull)) 276232812Sjmallett#endif 277232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 278232812Sjmallett#define CVMX_IOB_TO_NCB_DID_96_CREDITS CVMX_IOB_TO_NCB_DID_96_CREDITS_FUNC() 279232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_96_CREDITS_FUNC(void) 280232812Sjmallett{ 281232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 282232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_96_CREDITS not supported on this chip\n"); 283232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000B00ull); 284232812Sjmallett} 285232812Sjmallett#else 286232812Sjmallett#define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull)) 287232812Sjmallett#endif 288232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 289232812Sjmallett#define CVMX_IOB_TO_NCB_DID_98_CREDITS CVMX_IOB_TO_NCB_DID_98_CREDITS_FUNC() 290232812Sjmallettstatic inline uint64_t CVMX_IOB_TO_NCB_DID_98_CREDITS_FUNC(void) 291232812Sjmallett{ 292232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 293232812Sjmallett cvmx_warn("CVMX_IOB_TO_NCB_DID_98_CREDITS not supported on this chip\n"); 294232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800F0000B10ull); 295232812Sjmallett} 296232812Sjmallett#else 297232812Sjmallett#define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull)) 298232812Sjmallett#endif 299215976Sjmallett 300215976Sjmallett/** 301215976Sjmallett * cvmx_iob_bist_status 302215976Sjmallett * 303215976Sjmallett * IOB_BIST_STATUS = BIST Status of IOB Memories 304215976Sjmallett * 305215976Sjmallett * The result of the BIST run on the IOB memories. 306215976Sjmallett */ 307232812Sjmallettunion cvmx_iob_bist_status { 308215976Sjmallett uint64_t u64; 309232812Sjmallett struct cvmx_iob_bist_status_s { 310232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 311232812Sjmallett uint64_t reserved_2_63 : 62; 312232812Sjmallett uint64_t ibd : 1; /**< ibd_bist_mem0_status */ 313232812Sjmallett uint64_t icd : 1; /**< icd_ncb_fifo_bist_status */ 314232812Sjmallett#else 315232812Sjmallett uint64_t icd : 1; 316232812Sjmallett uint64_t ibd : 1; 317232812Sjmallett uint64_t reserved_2_63 : 62; 318232812Sjmallett#endif 319232812Sjmallett } s; 320232812Sjmallett struct cvmx_iob_bist_status_cn30xx { 321232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 322232812Sjmallett uint64_t reserved_18_63 : 46; 323232812Sjmallett uint64_t icnrcb : 1; /**< Reserved */ 324232812Sjmallett uint64_t icr0 : 1; /**< Reserved */ 325232812Sjmallett uint64_t icr1 : 1; /**< Reserved */ 326232812Sjmallett uint64_t icnr1 : 1; /**< Reserved */ 327232812Sjmallett uint64_t icnr0 : 1; /**< icnr_reg_mem0_bist_status */ 328232812Sjmallett uint64_t ibdr0 : 1; /**< ibdr_bist_req_fifo0_status */ 329232812Sjmallett uint64_t ibdr1 : 1; /**< ibdr_bist_req_fifo1_status */ 330232812Sjmallett uint64_t ibr0 : 1; /**< ibr_bist_rsp_fifo0_status */ 331232812Sjmallett uint64_t ibr1 : 1; /**< ibr_bist_rsp_fifo1_status */ 332232812Sjmallett uint64_t icnrt : 1; /**< Reserved */ 333232812Sjmallett uint64_t ibrq0 : 1; /**< ibrq_bist_req_fifo0_status */ 334232812Sjmallett uint64_t ibrq1 : 1; /**< ibrq_bist_req_fifo1_status */ 335232812Sjmallett uint64_t icrn0 : 1; /**< icr_ncb_bist_mem0_status */ 336232812Sjmallett uint64_t icrn1 : 1; /**< icr_ncb_bist_mem1_status */ 337232812Sjmallett uint64_t icrp0 : 1; /**< icr_pko_bist_mem0_status */ 338232812Sjmallett uint64_t icrp1 : 1; /**< icr_pko_bist_mem1_status */ 339232812Sjmallett uint64_t ibd : 1; /**< ibd_bist_mem0_status */ 340232812Sjmallett uint64_t icd : 1; /**< icd_ncb_fifo_bist_status */ 341232812Sjmallett#else 342232812Sjmallett uint64_t icd : 1; 343232812Sjmallett uint64_t ibd : 1; 344232812Sjmallett uint64_t icrp1 : 1; 345232812Sjmallett uint64_t icrp0 : 1; 346232812Sjmallett uint64_t icrn1 : 1; 347232812Sjmallett uint64_t icrn0 : 1; 348232812Sjmallett uint64_t ibrq1 : 1; 349232812Sjmallett uint64_t ibrq0 : 1; 350232812Sjmallett uint64_t icnrt : 1; 351232812Sjmallett uint64_t ibr1 : 1; 352232812Sjmallett uint64_t ibr0 : 1; 353232812Sjmallett uint64_t ibdr1 : 1; 354232812Sjmallett uint64_t ibdr0 : 1; 355232812Sjmallett uint64_t icnr0 : 1; 356232812Sjmallett uint64_t icnr1 : 1; 357232812Sjmallett uint64_t icr1 : 1; 358232812Sjmallett uint64_t icr0 : 1; 359232812Sjmallett uint64_t icnrcb : 1; 360232812Sjmallett uint64_t reserved_18_63 : 46; 361232812Sjmallett#endif 362232812Sjmallett } cn30xx; 363232812Sjmallett struct cvmx_iob_bist_status_cn30xx cn31xx; 364232812Sjmallett struct cvmx_iob_bist_status_cn30xx cn38xx; 365232812Sjmallett struct cvmx_iob_bist_status_cn30xx cn38xxp2; 366232812Sjmallett struct cvmx_iob_bist_status_cn30xx cn50xx; 367232812Sjmallett struct cvmx_iob_bist_status_cn30xx cn52xx; 368232812Sjmallett struct cvmx_iob_bist_status_cn30xx cn52xxp1; 369232812Sjmallett struct cvmx_iob_bist_status_cn30xx cn56xx; 370232812Sjmallett struct cvmx_iob_bist_status_cn30xx cn56xxp1; 371232812Sjmallett struct cvmx_iob_bist_status_cn30xx cn58xx; 372232812Sjmallett struct cvmx_iob_bist_status_cn30xx cn58xxp1; 373232812Sjmallett struct cvmx_iob_bist_status_cn61xx { 374232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 375215976Sjmallett uint64_t reserved_23_63 : 41; 376215976Sjmallett uint64_t xmdfif : 1; /**< xmdfif_bist_status */ 377215976Sjmallett uint64_t xmcfif : 1; /**< xmcfif_bist_status */ 378215976Sjmallett uint64_t iorfif : 1; /**< iorfif_bist_status */ 379215976Sjmallett uint64_t rsdfif : 1; /**< rsdfif_bist_status */ 380215976Sjmallett uint64_t iocfif : 1; /**< iocfif_bist_status */ 381215976Sjmallett uint64_t icnrcb : 1; /**< icnr_cb_reg_fifo_bist_status */ 382215976Sjmallett uint64_t icr0 : 1; /**< icr_bist_req_fifo0_status */ 383215976Sjmallett uint64_t icr1 : 1; /**< icr_bist_req_fifo1_status */ 384215976Sjmallett uint64_t icnr1 : 1; /**< Reserved */ 385215976Sjmallett uint64_t icnr0 : 1; /**< icnr_reg_mem0_bist_status */ 386215976Sjmallett uint64_t ibdr0 : 1; /**< ibdr_bist_req_fifo0_status */ 387215976Sjmallett uint64_t ibdr1 : 1; /**< ibdr_bist_req_fifo1_status */ 388215976Sjmallett uint64_t ibr0 : 1; /**< ibr_bist_rsp_fifo0_status */ 389215976Sjmallett uint64_t ibr1 : 1; /**< ibr_bist_rsp_fifo1_status */ 390215976Sjmallett uint64_t icnrt : 1; /**< icnr_tag_cb_reg_fifo_bist_status */ 391215976Sjmallett uint64_t ibrq0 : 1; /**< ibrq_bist_req_fifo0_status */ 392215976Sjmallett uint64_t ibrq1 : 1; /**< ibrq_bist_req_fifo1_status */ 393215976Sjmallett uint64_t icrn0 : 1; /**< icr_ncb_bist_mem0_status */ 394215976Sjmallett uint64_t icrn1 : 1; /**< icr_ncb_bist_mem1_status */ 395215976Sjmallett uint64_t icrp0 : 1; /**< icr_pko_bist_mem0_status */ 396215976Sjmallett uint64_t icrp1 : 1; /**< icr_pko_bist_mem1_status */ 397215976Sjmallett uint64_t ibd : 1; /**< ibd_bist_mem0_status */ 398215976Sjmallett uint64_t icd : 1; /**< icd_ncb_fifo_bist_status */ 399215976Sjmallett#else 400215976Sjmallett uint64_t icd : 1; 401215976Sjmallett uint64_t ibd : 1; 402215976Sjmallett uint64_t icrp1 : 1; 403215976Sjmallett uint64_t icrp0 : 1; 404215976Sjmallett uint64_t icrn1 : 1; 405215976Sjmallett uint64_t icrn0 : 1; 406215976Sjmallett uint64_t ibrq1 : 1; 407215976Sjmallett uint64_t ibrq0 : 1; 408215976Sjmallett uint64_t icnrt : 1; 409215976Sjmallett uint64_t ibr1 : 1; 410215976Sjmallett uint64_t ibr0 : 1; 411215976Sjmallett uint64_t ibdr1 : 1; 412215976Sjmallett uint64_t ibdr0 : 1; 413215976Sjmallett uint64_t icnr0 : 1; 414215976Sjmallett uint64_t icnr1 : 1; 415215976Sjmallett uint64_t icr1 : 1; 416215976Sjmallett uint64_t icr0 : 1; 417215976Sjmallett uint64_t icnrcb : 1; 418215976Sjmallett uint64_t iocfif : 1; 419215976Sjmallett uint64_t rsdfif : 1; 420215976Sjmallett uint64_t iorfif : 1; 421215976Sjmallett uint64_t xmcfif : 1; 422215976Sjmallett uint64_t xmdfif : 1; 423215976Sjmallett uint64_t reserved_23_63 : 41; 424215976Sjmallett#endif 425232812Sjmallett } cn61xx; 426232812Sjmallett struct cvmx_iob_bist_status_cn61xx cn63xx; 427232812Sjmallett struct cvmx_iob_bist_status_cn61xx cn63xxp1; 428232812Sjmallett struct cvmx_iob_bist_status_cn61xx cn66xx; 429232812Sjmallett struct cvmx_iob_bist_status_cn68xx { 430232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 431215976Sjmallett uint64_t reserved_18_63 : 46; 432232812Sjmallett uint64_t xmdfif : 1; /**< xmdfif_bist_status */ 433232812Sjmallett uint64_t xmcfif : 1; /**< xmcfif_bist_status */ 434232812Sjmallett uint64_t iorfif : 1; /**< iorfif_bist_status */ 435232812Sjmallett uint64_t rsdfif : 1; /**< rsdfif_bist_status */ 436232812Sjmallett uint64_t iocfif : 1; /**< iocfif_bist_status */ 437232812Sjmallett uint64_t icnrcb : 1; /**< icnr_cb_reg_fifo_bist_status */ 438232812Sjmallett uint64_t icr0 : 1; /**< icr_bist_req_fifo0_status */ 439232812Sjmallett uint64_t icr1 : 1; /**< icr_bist_req_fifo1_status */ 440215976Sjmallett uint64_t icnr0 : 1; /**< icnr_reg_mem0_bist_status */ 441215976Sjmallett uint64_t ibr0 : 1; /**< ibr_bist_rsp_fifo0_status */ 442215976Sjmallett uint64_t ibr1 : 1; /**< ibr_bist_rsp_fifo1_status */ 443232812Sjmallett uint64_t icnrt : 1; /**< icnr_tag_cb_reg_fifo_bist_status */ 444215976Sjmallett uint64_t ibrq0 : 1; /**< ibrq_bist_req_fifo0_status */ 445215976Sjmallett uint64_t ibrq1 : 1; /**< ibrq_bist_req_fifo1_status */ 446215976Sjmallett uint64_t icrn0 : 1; /**< icr_ncb_bist_mem0_status */ 447215976Sjmallett uint64_t icrn1 : 1; /**< icr_ncb_bist_mem1_status */ 448215976Sjmallett uint64_t ibd : 1; /**< ibd_bist_mem0_status */ 449215976Sjmallett uint64_t icd : 1; /**< icd_ncb_fifo_bist_status */ 450215976Sjmallett#else 451215976Sjmallett uint64_t icd : 1; 452215976Sjmallett uint64_t ibd : 1; 453215976Sjmallett uint64_t icrn1 : 1; 454215976Sjmallett uint64_t icrn0 : 1; 455215976Sjmallett uint64_t ibrq1 : 1; 456215976Sjmallett uint64_t ibrq0 : 1; 457215976Sjmallett uint64_t icnrt : 1; 458215976Sjmallett uint64_t ibr1 : 1; 459215976Sjmallett uint64_t ibr0 : 1; 460215976Sjmallett uint64_t icnr0 : 1; 461215976Sjmallett uint64_t icr1 : 1; 462215976Sjmallett uint64_t icr0 : 1; 463215976Sjmallett uint64_t icnrcb : 1; 464232812Sjmallett uint64_t iocfif : 1; 465232812Sjmallett uint64_t rsdfif : 1; 466232812Sjmallett uint64_t iorfif : 1; 467232812Sjmallett uint64_t xmcfif : 1; 468232812Sjmallett uint64_t xmdfif : 1; 469215976Sjmallett uint64_t reserved_18_63 : 46; 470215976Sjmallett#endif 471232812Sjmallett } cn68xx; 472232812Sjmallett struct cvmx_iob_bist_status_cn68xx cn68xxp1; 473232812Sjmallett struct cvmx_iob_bist_status_cn61xx cnf71xx; 474215976Sjmallett}; 475215976Sjmalletttypedef union cvmx_iob_bist_status cvmx_iob_bist_status_t; 476215976Sjmallett 477215976Sjmallett/** 478215976Sjmallett * cvmx_iob_ctl_status 479215976Sjmallett * 480215976Sjmallett * IOB Control Status = IOB Control and Status Register 481215976Sjmallett * 482215976Sjmallett * Provides control for IOB functions. 483215976Sjmallett */ 484232812Sjmallettunion cvmx_iob_ctl_status { 485215976Sjmallett uint64_t u64; 486232812Sjmallett struct cvmx_iob_ctl_status_s { 487232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 488232812Sjmallett uint64_t reserved_11_63 : 53; 489232812Sjmallett uint64_t fif_dly : 1; /**< Delay async FIFO counts to be used when clock ratio 490232812Sjmallett is greater then 3:1. Writes should be followed by an 491232812Sjmallett immediate read. */ 492215976Sjmallett uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */ 493232812Sjmallett uint64_t reserved_5_5 : 1; 494215976Sjmallett uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern 495215976Sjmallett matchers. PASS2 FIELD. */ 496215976Sjmallett uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern 497215976Sjmallett matchers. PASS2 FIELD. */ 498215976Sjmallett uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO. 499215976Sjmallett '0' is for big-endian and '1' is for little-endian. */ 500215976Sjmallett uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */ 501215976Sjmallett uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for 502215976Sjmallett big-endian and '1' is for little-endian. */ 503215976Sjmallett#else 504215976Sjmallett uint64_t fau_end : 1; 505215976Sjmallett uint64_t dwb_enb : 1; 506215976Sjmallett uint64_t pko_enb : 1; 507215976Sjmallett uint64_t inb_mat : 1; 508215976Sjmallett uint64_t outb_mat : 1; 509232812Sjmallett uint64_t reserved_5_5 : 1; 510215976Sjmallett uint64_t xmc_per : 4; 511232812Sjmallett uint64_t fif_dly : 1; 512232812Sjmallett uint64_t reserved_11_63 : 53; 513215976Sjmallett#endif 514215976Sjmallett } s; 515232812Sjmallett struct cvmx_iob_ctl_status_cn30xx { 516232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 517215976Sjmallett uint64_t reserved_5_63 : 59; 518215976Sjmallett uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern 519215976Sjmallett matchers. */ 520215976Sjmallett uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern 521215976Sjmallett matchers. */ 522215976Sjmallett uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO. 523215976Sjmallett '0' is for big-endian and '1' is for little-endian. */ 524215976Sjmallett uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */ 525215976Sjmallett uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for 526215976Sjmallett big-endian and '1' is for little-endian. */ 527215976Sjmallett#else 528215976Sjmallett uint64_t fau_end : 1; 529215976Sjmallett uint64_t dwb_enb : 1; 530215976Sjmallett uint64_t pko_enb : 1; 531215976Sjmallett uint64_t inb_mat : 1; 532215976Sjmallett uint64_t outb_mat : 1; 533215976Sjmallett uint64_t reserved_5_63 : 59; 534215976Sjmallett#endif 535215976Sjmallett } cn30xx; 536215976Sjmallett struct cvmx_iob_ctl_status_cn30xx cn31xx; 537215976Sjmallett struct cvmx_iob_ctl_status_cn30xx cn38xx; 538215976Sjmallett struct cvmx_iob_ctl_status_cn30xx cn38xxp2; 539215976Sjmallett struct cvmx_iob_ctl_status_cn30xx cn50xx; 540232812Sjmallett struct cvmx_iob_ctl_status_cn52xx { 541232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 542215976Sjmallett uint64_t reserved_6_63 : 58; 543215976Sjmallett uint64_t rr_mode : 1; /**< When set to '1' will enable Round-Robin mode of next 544215976Sjmallett transaction that could arbitrate for the XMB. */ 545215976Sjmallett uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern 546215976Sjmallett matchers. PASS2 FIELD. */ 547215976Sjmallett uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern 548215976Sjmallett matchers. PASS2 FIELD. */ 549215976Sjmallett uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO. 550215976Sjmallett '0' is for big-endian and '1' is for little-endian. */ 551215976Sjmallett uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */ 552215976Sjmallett uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for 553215976Sjmallett big-endian and '1' is for little-endian. */ 554215976Sjmallett#else 555215976Sjmallett uint64_t fau_end : 1; 556215976Sjmallett uint64_t dwb_enb : 1; 557215976Sjmallett uint64_t pko_enb : 1; 558215976Sjmallett uint64_t inb_mat : 1; 559215976Sjmallett uint64_t outb_mat : 1; 560215976Sjmallett uint64_t rr_mode : 1; 561215976Sjmallett uint64_t reserved_6_63 : 58; 562215976Sjmallett#endif 563215976Sjmallett } cn52xx; 564215976Sjmallett struct cvmx_iob_ctl_status_cn30xx cn52xxp1; 565215976Sjmallett struct cvmx_iob_ctl_status_cn30xx cn56xx; 566215976Sjmallett struct cvmx_iob_ctl_status_cn30xx cn56xxp1; 567215976Sjmallett struct cvmx_iob_ctl_status_cn30xx cn58xx; 568215976Sjmallett struct cvmx_iob_ctl_status_cn30xx cn58xxp1; 569232812Sjmallett struct cvmx_iob_ctl_status_cn61xx { 570232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 571232812Sjmallett uint64_t reserved_11_63 : 53; 572232812Sjmallett uint64_t fif_dly : 1; /**< Delay async FIFO counts to be used when clock ratio 573232812Sjmallett is greater then 3:1. Writes should be followed by an 574232812Sjmallett immediate read. */ 575232812Sjmallett uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */ 576232812Sjmallett uint64_t rr_mode : 1; /**< When set to '1' will enable Round-Robin mode of next 577232812Sjmallett transaction that could arbitrate for the XMB. */ 578232812Sjmallett uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern 579232812Sjmallett matchers. PASS2 FIELD. */ 580232812Sjmallett uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern 581232812Sjmallett matchers. PASS2 FIELD. */ 582232812Sjmallett uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO. 583232812Sjmallett '0' is for big-endian and '1' is for little-endian. */ 584232812Sjmallett uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */ 585232812Sjmallett uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for 586232812Sjmallett big-endian and '1' is for little-endian. */ 587232812Sjmallett#else 588232812Sjmallett uint64_t fau_end : 1; 589232812Sjmallett uint64_t dwb_enb : 1; 590232812Sjmallett uint64_t pko_enb : 1; 591232812Sjmallett uint64_t inb_mat : 1; 592232812Sjmallett uint64_t outb_mat : 1; 593232812Sjmallett uint64_t rr_mode : 1; 594232812Sjmallett uint64_t xmc_per : 4; 595232812Sjmallett uint64_t fif_dly : 1; 596232812Sjmallett uint64_t reserved_11_63 : 53; 597232812Sjmallett#endif 598232812Sjmallett } cn61xx; 599232812Sjmallett struct cvmx_iob_ctl_status_cn63xx { 600232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 601232812Sjmallett uint64_t reserved_10_63 : 54; 602232812Sjmallett uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */ 603232812Sjmallett uint64_t rr_mode : 1; /**< When set to '1' will enable Round-Robin mode of next 604232812Sjmallett transaction that could arbitrate for the XMB. */ 605232812Sjmallett uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern 606232812Sjmallett matchers. PASS2 FIELD. */ 607232812Sjmallett uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern 608232812Sjmallett matchers. PASS2 FIELD. */ 609232812Sjmallett uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO. 610232812Sjmallett '0' is for big-endian and '1' is for little-endian. */ 611232812Sjmallett uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */ 612232812Sjmallett uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for 613232812Sjmallett big-endian and '1' is for little-endian. */ 614232812Sjmallett#else 615232812Sjmallett uint64_t fau_end : 1; 616232812Sjmallett uint64_t dwb_enb : 1; 617232812Sjmallett uint64_t pko_enb : 1; 618232812Sjmallett uint64_t inb_mat : 1; 619232812Sjmallett uint64_t outb_mat : 1; 620232812Sjmallett uint64_t rr_mode : 1; 621232812Sjmallett uint64_t xmc_per : 4; 622232812Sjmallett uint64_t reserved_10_63 : 54; 623232812Sjmallett#endif 624232812Sjmallett } cn63xx; 625232812Sjmallett struct cvmx_iob_ctl_status_cn63xx cn63xxp1; 626232812Sjmallett struct cvmx_iob_ctl_status_cn61xx cn66xx; 627232812Sjmallett struct cvmx_iob_ctl_status_cn68xx { 628232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 629232812Sjmallett uint64_t reserved_11_63 : 53; 630232812Sjmallett uint64_t fif_dly : 1; /**< Delay async FIFO counts to be used when clock ratio 631232812Sjmallett is greater then 3:1. Writes should be followed by an 632232812Sjmallett immediate read. */ 633232812Sjmallett uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */ 634232812Sjmallett uint64_t rsvr5 : 1; /**< Reserved */ 635232812Sjmallett uint64_t outb_mat : 1; /**< Was a match on the outbound bus to the inb pattern 636232812Sjmallett matchers. */ 637232812Sjmallett uint64_t inb_mat : 1; /**< Was a match on the inbound bus to the inb pattern 638232812Sjmallett matchers. */ 639232812Sjmallett uint64_t pko_enb : 1; /**< Toggles the endian style of the FAU for the PKO. 640232812Sjmallett '0' is for big-endian and '1' is for little-endian. */ 641232812Sjmallett uint64_t dwb_enb : 1; /**< Enables the DWB function of the IOB. */ 642232812Sjmallett uint64_t fau_end : 1; /**< Toggles the endian style of the FAU. '0' is for 643232812Sjmallett big-endian and '1' is for little-endian. */ 644232812Sjmallett#else 645232812Sjmallett uint64_t fau_end : 1; 646232812Sjmallett uint64_t dwb_enb : 1; 647232812Sjmallett uint64_t pko_enb : 1; 648232812Sjmallett uint64_t inb_mat : 1; 649232812Sjmallett uint64_t outb_mat : 1; 650232812Sjmallett uint64_t rsvr5 : 1; 651232812Sjmallett uint64_t xmc_per : 4; 652232812Sjmallett uint64_t fif_dly : 1; 653232812Sjmallett uint64_t reserved_11_63 : 53; 654232812Sjmallett#endif 655232812Sjmallett } cn68xx; 656232812Sjmallett struct cvmx_iob_ctl_status_cn68xx cn68xxp1; 657232812Sjmallett struct cvmx_iob_ctl_status_cn61xx cnf71xx; 658215976Sjmallett}; 659215976Sjmalletttypedef union cvmx_iob_ctl_status cvmx_iob_ctl_status_t; 660215976Sjmallett 661215976Sjmallett/** 662215976Sjmallett * cvmx_iob_dwb_pri_cnt 663215976Sjmallett * 664215976Sjmallett * DWB To CMB Priority Counter = Don't Write Back to CMB Priority Counter Enable and Timer Value 665215976Sjmallett * 666215976Sjmallett * Enables and supplies the timeout count for raising the priority of Don't Write Back request to the L2C. 667215976Sjmallett */ 668232812Sjmallettunion cvmx_iob_dwb_pri_cnt { 669215976Sjmallett uint64_t u64; 670232812Sjmallett struct cvmx_iob_dwb_pri_cnt_s { 671232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 672215976Sjmallett uint64_t reserved_16_63 : 48; 673215976Sjmallett uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority 674215976Sjmallett when CNT_VAL is reached. */ 675215976Sjmallett uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising 676215976Sjmallett the priority for access to CMB. */ 677215976Sjmallett#else 678215976Sjmallett uint64_t cnt_val : 15; 679215976Sjmallett uint64_t cnt_enb : 1; 680215976Sjmallett uint64_t reserved_16_63 : 48; 681215976Sjmallett#endif 682215976Sjmallett } s; 683215976Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn38xx; 684215976Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn38xxp2; 685215976Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn52xx; 686215976Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn52xxp1; 687215976Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn56xx; 688215976Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn56xxp1; 689215976Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn58xx; 690215976Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn58xxp1; 691232812Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn61xx; 692215976Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn63xx; 693215976Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn63xxp1; 694232812Sjmallett struct cvmx_iob_dwb_pri_cnt_s cn66xx; 695232812Sjmallett struct cvmx_iob_dwb_pri_cnt_s cnf71xx; 696215976Sjmallett}; 697215976Sjmalletttypedef union cvmx_iob_dwb_pri_cnt cvmx_iob_dwb_pri_cnt_t; 698215976Sjmallett 699215976Sjmallett/** 700215976Sjmallett * cvmx_iob_fau_timeout 701215976Sjmallett * 702215976Sjmallett * FAU Timeout = Fetch and Add Unit Tag-Switch Timeout 703215976Sjmallett * 704215976Sjmallett * How many clokc ticks the FAU unit will wait for a tag-switch before timeing out. 705215976Sjmallett * for Queue 0. 706215976Sjmallett */ 707232812Sjmallettunion cvmx_iob_fau_timeout { 708215976Sjmallett uint64_t u64; 709232812Sjmallett struct cvmx_iob_fau_timeout_s { 710232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 711215976Sjmallett uint64_t reserved_13_63 : 51; 712215976Sjmallett uint64_t tout_enb : 1; /**< The enable for the FAU timeout feature. 713215976Sjmallett '1' will enable the timeout, '0' will disable. */ 714215976Sjmallett uint64_t tout_val : 12; /**< When a tag request arrives from the PP a timer is 715215976Sjmallett started associate with that PP. The timer which 716215976Sjmallett increments every 256 eclks is compared to TOUT_VAL. 717215976Sjmallett When the two are equal the IOB will flag the tag 718215976Sjmallett request to complete as a time-out tag operation. 719215976Sjmallett The 256 count timer used to increment the PP 720215976Sjmallett associated timer is always running so the first 721215976Sjmallett increment of the PP associated timer may occur any 722215976Sjmallett where within the first 256 eclks. Note that '0' 723215976Sjmallett is an illegal value. */ 724215976Sjmallett#else 725215976Sjmallett uint64_t tout_val : 12; 726215976Sjmallett uint64_t tout_enb : 1; 727215976Sjmallett uint64_t reserved_13_63 : 51; 728215976Sjmallett#endif 729215976Sjmallett } s; 730215976Sjmallett struct cvmx_iob_fau_timeout_s cn30xx; 731215976Sjmallett struct cvmx_iob_fau_timeout_s cn31xx; 732215976Sjmallett struct cvmx_iob_fau_timeout_s cn38xx; 733215976Sjmallett struct cvmx_iob_fau_timeout_s cn38xxp2; 734215976Sjmallett struct cvmx_iob_fau_timeout_s cn50xx; 735215976Sjmallett struct cvmx_iob_fau_timeout_s cn52xx; 736215976Sjmallett struct cvmx_iob_fau_timeout_s cn52xxp1; 737215976Sjmallett struct cvmx_iob_fau_timeout_s cn56xx; 738215976Sjmallett struct cvmx_iob_fau_timeout_s cn56xxp1; 739215976Sjmallett struct cvmx_iob_fau_timeout_s cn58xx; 740215976Sjmallett struct cvmx_iob_fau_timeout_s cn58xxp1; 741232812Sjmallett struct cvmx_iob_fau_timeout_s cn61xx; 742215976Sjmallett struct cvmx_iob_fau_timeout_s cn63xx; 743215976Sjmallett struct cvmx_iob_fau_timeout_s cn63xxp1; 744232812Sjmallett struct cvmx_iob_fau_timeout_s cn66xx; 745232812Sjmallett struct cvmx_iob_fau_timeout_s cn68xx; 746232812Sjmallett struct cvmx_iob_fau_timeout_s cn68xxp1; 747232812Sjmallett struct cvmx_iob_fau_timeout_s cnf71xx; 748215976Sjmallett}; 749215976Sjmalletttypedef union cvmx_iob_fau_timeout cvmx_iob_fau_timeout_t; 750215976Sjmallett 751215976Sjmallett/** 752215976Sjmallett * cvmx_iob_i2c_pri_cnt 753215976Sjmallett * 754215976Sjmallett * IPD To CMB Store Priority Counter = IPD to CMB Store Priority Counter Enable and Timer Value 755215976Sjmallett * 756215976Sjmallett * Enables and supplies the timeout count for raising the priority of IPD Store access to the CMB. 757215976Sjmallett */ 758232812Sjmallettunion cvmx_iob_i2c_pri_cnt { 759215976Sjmallett uint64_t u64; 760232812Sjmallett struct cvmx_iob_i2c_pri_cnt_s { 761232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 762215976Sjmallett uint64_t reserved_16_63 : 48; 763215976Sjmallett uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority 764215976Sjmallett when CNT_VAL is reached. */ 765215976Sjmallett uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising 766215976Sjmallett the priority for access to CMB. */ 767215976Sjmallett#else 768215976Sjmallett uint64_t cnt_val : 15; 769215976Sjmallett uint64_t cnt_enb : 1; 770215976Sjmallett uint64_t reserved_16_63 : 48; 771215976Sjmallett#endif 772215976Sjmallett } s; 773215976Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn38xx; 774215976Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn38xxp2; 775215976Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn52xx; 776215976Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn52xxp1; 777215976Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn56xx; 778215976Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn56xxp1; 779215976Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn58xx; 780215976Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn58xxp1; 781232812Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn61xx; 782215976Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn63xx; 783215976Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn63xxp1; 784232812Sjmallett struct cvmx_iob_i2c_pri_cnt_s cn66xx; 785232812Sjmallett struct cvmx_iob_i2c_pri_cnt_s cnf71xx; 786215976Sjmallett}; 787215976Sjmalletttypedef union cvmx_iob_i2c_pri_cnt cvmx_iob_i2c_pri_cnt_t; 788215976Sjmallett 789215976Sjmallett/** 790215976Sjmallett * cvmx_iob_inb_control_match 791215976Sjmallett * 792215976Sjmallett * IOB_INB_CONTROL_MATCH = IOB Inbound Control Match 793215976Sjmallett * 794215976Sjmallett * Match pattern for the inbound control to set the INB_MATCH_BIT. PASS-2 Register 795215976Sjmallett */ 796232812Sjmallettunion cvmx_iob_inb_control_match { 797215976Sjmallett uint64_t u64; 798232812Sjmallett struct cvmx_iob_inb_control_match_s { 799232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 800215976Sjmallett uint64_t reserved_29_63 : 35; 801215976Sjmallett uint64_t mask : 8; /**< Pattern to match on the inbound NCB. */ 802215976Sjmallett uint64_t opc : 4; /**< Pattern to match on the inbound NCB. */ 803215976Sjmallett uint64_t dst : 9; /**< Pattern to match on the inbound NCB. */ 804215976Sjmallett uint64_t src : 8; /**< Pattern to match on the inbound NCB. */ 805215976Sjmallett#else 806215976Sjmallett uint64_t src : 8; 807215976Sjmallett uint64_t dst : 9; 808215976Sjmallett uint64_t opc : 4; 809215976Sjmallett uint64_t mask : 8; 810215976Sjmallett uint64_t reserved_29_63 : 35; 811215976Sjmallett#endif 812215976Sjmallett } s; 813215976Sjmallett struct cvmx_iob_inb_control_match_s cn30xx; 814215976Sjmallett struct cvmx_iob_inb_control_match_s cn31xx; 815215976Sjmallett struct cvmx_iob_inb_control_match_s cn38xx; 816215976Sjmallett struct cvmx_iob_inb_control_match_s cn38xxp2; 817215976Sjmallett struct cvmx_iob_inb_control_match_s cn50xx; 818215976Sjmallett struct cvmx_iob_inb_control_match_s cn52xx; 819215976Sjmallett struct cvmx_iob_inb_control_match_s cn52xxp1; 820215976Sjmallett struct cvmx_iob_inb_control_match_s cn56xx; 821215976Sjmallett struct cvmx_iob_inb_control_match_s cn56xxp1; 822215976Sjmallett struct cvmx_iob_inb_control_match_s cn58xx; 823215976Sjmallett struct cvmx_iob_inb_control_match_s cn58xxp1; 824232812Sjmallett struct cvmx_iob_inb_control_match_s cn61xx; 825215976Sjmallett struct cvmx_iob_inb_control_match_s cn63xx; 826215976Sjmallett struct cvmx_iob_inb_control_match_s cn63xxp1; 827232812Sjmallett struct cvmx_iob_inb_control_match_s cn66xx; 828232812Sjmallett struct cvmx_iob_inb_control_match_s cn68xx; 829232812Sjmallett struct cvmx_iob_inb_control_match_s cn68xxp1; 830232812Sjmallett struct cvmx_iob_inb_control_match_s cnf71xx; 831215976Sjmallett}; 832215976Sjmalletttypedef union cvmx_iob_inb_control_match cvmx_iob_inb_control_match_t; 833215976Sjmallett 834215976Sjmallett/** 835215976Sjmallett * cvmx_iob_inb_control_match_enb 836215976Sjmallett * 837215976Sjmallett * IOB_INB_CONTROL_MATCH_ENB = IOB Inbound Control Match Enable 838215976Sjmallett * 839215976Sjmallett * Enables the match of the corresponding bit in the IOB_INB_CONTROL_MATCH reister. PASS-2 Register 840215976Sjmallett */ 841232812Sjmallettunion cvmx_iob_inb_control_match_enb { 842215976Sjmallett uint64_t u64; 843232812Sjmallett struct cvmx_iob_inb_control_match_enb_s { 844232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 845215976Sjmallett uint64_t reserved_29_63 : 35; 846215976Sjmallett uint64_t mask : 8; /**< Pattern to match on the inbound NCB. */ 847215976Sjmallett uint64_t opc : 4; /**< Pattern to match on the inbound NCB. */ 848215976Sjmallett uint64_t dst : 9; /**< Pattern to match on the inbound NCB. */ 849215976Sjmallett uint64_t src : 8; /**< Pattern to match on the inbound NCB. */ 850215976Sjmallett#else 851215976Sjmallett uint64_t src : 8; 852215976Sjmallett uint64_t dst : 9; 853215976Sjmallett uint64_t opc : 4; 854215976Sjmallett uint64_t mask : 8; 855215976Sjmallett uint64_t reserved_29_63 : 35; 856215976Sjmallett#endif 857215976Sjmallett } s; 858215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn30xx; 859215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn31xx; 860215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn38xx; 861215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn38xxp2; 862215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn50xx; 863215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn52xx; 864215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn52xxp1; 865215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn56xx; 866215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn56xxp1; 867215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn58xx; 868215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn58xxp1; 869232812Sjmallett struct cvmx_iob_inb_control_match_enb_s cn61xx; 870215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn63xx; 871215976Sjmallett struct cvmx_iob_inb_control_match_enb_s cn63xxp1; 872232812Sjmallett struct cvmx_iob_inb_control_match_enb_s cn66xx; 873232812Sjmallett struct cvmx_iob_inb_control_match_enb_s cn68xx; 874232812Sjmallett struct cvmx_iob_inb_control_match_enb_s cn68xxp1; 875232812Sjmallett struct cvmx_iob_inb_control_match_enb_s cnf71xx; 876215976Sjmallett}; 877215976Sjmalletttypedef union cvmx_iob_inb_control_match_enb cvmx_iob_inb_control_match_enb_t; 878215976Sjmallett 879215976Sjmallett/** 880215976Sjmallett * cvmx_iob_inb_data_match 881215976Sjmallett * 882215976Sjmallett * IOB_INB_DATA_MATCH = IOB Inbound Data Match 883215976Sjmallett * 884215976Sjmallett * Match pattern for the inbound data to set the INB_MATCH_BIT. PASS-2 Register 885215976Sjmallett */ 886232812Sjmallettunion cvmx_iob_inb_data_match { 887215976Sjmallett uint64_t u64; 888232812Sjmallett struct cvmx_iob_inb_data_match_s { 889232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 890215976Sjmallett uint64_t data : 64; /**< Pattern to match on the inbound NCB. */ 891215976Sjmallett#else 892215976Sjmallett uint64_t data : 64; 893215976Sjmallett#endif 894215976Sjmallett } s; 895215976Sjmallett struct cvmx_iob_inb_data_match_s cn30xx; 896215976Sjmallett struct cvmx_iob_inb_data_match_s cn31xx; 897215976Sjmallett struct cvmx_iob_inb_data_match_s cn38xx; 898215976Sjmallett struct cvmx_iob_inb_data_match_s cn38xxp2; 899215976Sjmallett struct cvmx_iob_inb_data_match_s cn50xx; 900215976Sjmallett struct cvmx_iob_inb_data_match_s cn52xx; 901215976Sjmallett struct cvmx_iob_inb_data_match_s cn52xxp1; 902215976Sjmallett struct cvmx_iob_inb_data_match_s cn56xx; 903215976Sjmallett struct cvmx_iob_inb_data_match_s cn56xxp1; 904215976Sjmallett struct cvmx_iob_inb_data_match_s cn58xx; 905215976Sjmallett struct cvmx_iob_inb_data_match_s cn58xxp1; 906232812Sjmallett struct cvmx_iob_inb_data_match_s cn61xx; 907215976Sjmallett struct cvmx_iob_inb_data_match_s cn63xx; 908215976Sjmallett struct cvmx_iob_inb_data_match_s cn63xxp1; 909232812Sjmallett struct cvmx_iob_inb_data_match_s cn66xx; 910232812Sjmallett struct cvmx_iob_inb_data_match_s cn68xx; 911232812Sjmallett struct cvmx_iob_inb_data_match_s cn68xxp1; 912232812Sjmallett struct cvmx_iob_inb_data_match_s cnf71xx; 913215976Sjmallett}; 914215976Sjmalletttypedef union cvmx_iob_inb_data_match cvmx_iob_inb_data_match_t; 915215976Sjmallett 916215976Sjmallett/** 917215976Sjmallett * cvmx_iob_inb_data_match_enb 918215976Sjmallett * 919215976Sjmallett * IOB_INB_DATA_MATCH_ENB = IOB Inbound Data Match Enable 920215976Sjmallett * 921215976Sjmallett * Enables the match of the corresponding bit in the IOB_INB_DATA_MATCH reister. PASS-2 Register 922215976Sjmallett */ 923232812Sjmallettunion cvmx_iob_inb_data_match_enb { 924215976Sjmallett uint64_t u64; 925232812Sjmallett struct cvmx_iob_inb_data_match_enb_s { 926232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 927215976Sjmallett uint64_t data : 64; /**< Bit to enable match of. */ 928215976Sjmallett#else 929215976Sjmallett uint64_t data : 64; 930215976Sjmallett#endif 931215976Sjmallett } s; 932215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn30xx; 933215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn31xx; 934215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn38xx; 935215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn38xxp2; 936215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn50xx; 937215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn52xx; 938215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn52xxp1; 939215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn56xx; 940215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn56xxp1; 941215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn58xx; 942215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn58xxp1; 943232812Sjmallett struct cvmx_iob_inb_data_match_enb_s cn61xx; 944215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn63xx; 945215976Sjmallett struct cvmx_iob_inb_data_match_enb_s cn63xxp1; 946232812Sjmallett struct cvmx_iob_inb_data_match_enb_s cn66xx; 947232812Sjmallett struct cvmx_iob_inb_data_match_enb_s cn68xx; 948232812Sjmallett struct cvmx_iob_inb_data_match_enb_s cn68xxp1; 949232812Sjmallett struct cvmx_iob_inb_data_match_enb_s cnf71xx; 950215976Sjmallett}; 951215976Sjmalletttypedef union cvmx_iob_inb_data_match_enb cvmx_iob_inb_data_match_enb_t; 952215976Sjmallett 953215976Sjmallett/** 954215976Sjmallett * cvmx_iob_int_enb 955215976Sjmallett * 956215976Sjmallett * IOB_INT_ENB = IOB's Interrupt Enable 957215976Sjmallett * 958215976Sjmallett * The IOB's interrupt enable register. This is a PASS-2 register. 959215976Sjmallett */ 960232812Sjmallettunion cvmx_iob_int_enb { 961215976Sjmallett uint64_t u64; 962232812Sjmallett struct cvmx_iob_int_enb_s { 963232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 964215976Sjmallett uint64_t reserved_6_63 : 58; 965215976Sjmallett uint64_t p_dat : 1; /**< When set (1) and bit 5 of the IOB_INT_SUM 966215976Sjmallett register is asserted the IOB will assert an 967215976Sjmallett interrupt. */ 968215976Sjmallett uint64_t np_dat : 1; /**< When set (1) and bit 4 of the IOB_INT_SUM 969215976Sjmallett register is asserted the IOB will assert an 970215976Sjmallett interrupt. */ 971215976Sjmallett uint64_t p_eop : 1; /**< When set (1) and bit 3 of the IOB_INT_SUM 972215976Sjmallett register is asserted the IOB will assert an 973215976Sjmallett interrupt. */ 974215976Sjmallett uint64_t p_sop : 1; /**< When set (1) and bit 2 of the IOB_INT_SUM 975215976Sjmallett register is asserted the IOB will assert an 976215976Sjmallett interrupt. */ 977215976Sjmallett uint64_t np_eop : 1; /**< When set (1) and bit 1 of the IOB_INT_SUM 978215976Sjmallett register is asserted the IOB will assert an 979215976Sjmallett interrupt. */ 980215976Sjmallett uint64_t np_sop : 1; /**< When set (1) and bit 0 of the IOB_INT_SUM 981215976Sjmallett register is asserted the IOB will assert an 982215976Sjmallett interrupt. */ 983215976Sjmallett#else 984215976Sjmallett uint64_t np_sop : 1; 985215976Sjmallett uint64_t np_eop : 1; 986215976Sjmallett uint64_t p_sop : 1; 987215976Sjmallett uint64_t p_eop : 1; 988215976Sjmallett uint64_t np_dat : 1; 989215976Sjmallett uint64_t p_dat : 1; 990215976Sjmallett uint64_t reserved_6_63 : 58; 991215976Sjmallett#endif 992215976Sjmallett } s; 993232812Sjmallett struct cvmx_iob_int_enb_cn30xx { 994232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 995215976Sjmallett uint64_t reserved_4_63 : 60; 996215976Sjmallett uint64_t p_eop : 1; /**< When set (1) and bit 3 of the IOB_INT_SUM 997215976Sjmallett register is asserted the IOB will assert an 998215976Sjmallett interrupt. */ 999215976Sjmallett uint64_t p_sop : 1; /**< When set (1) and bit 2 of the IOB_INT_SUM 1000215976Sjmallett register is asserted the IOB will assert an 1001215976Sjmallett interrupt. */ 1002215976Sjmallett uint64_t np_eop : 1; /**< When set (1) and bit 1 of the IOB_INT_SUM 1003215976Sjmallett register is asserted the IOB will assert an 1004215976Sjmallett interrupt. */ 1005215976Sjmallett uint64_t np_sop : 1; /**< When set (1) and bit 0 of the IOB_INT_SUM 1006215976Sjmallett register is asserted the IOB will assert an 1007215976Sjmallett interrupt. */ 1008215976Sjmallett#else 1009215976Sjmallett uint64_t np_sop : 1; 1010215976Sjmallett uint64_t np_eop : 1; 1011215976Sjmallett uint64_t p_sop : 1; 1012215976Sjmallett uint64_t p_eop : 1; 1013215976Sjmallett uint64_t reserved_4_63 : 60; 1014215976Sjmallett#endif 1015215976Sjmallett } cn30xx; 1016215976Sjmallett struct cvmx_iob_int_enb_cn30xx cn31xx; 1017215976Sjmallett struct cvmx_iob_int_enb_cn30xx cn38xx; 1018215976Sjmallett struct cvmx_iob_int_enb_cn30xx cn38xxp2; 1019215976Sjmallett struct cvmx_iob_int_enb_s cn50xx; 1020215976Sjmallett struct cvmx_iob_int_enb_s cn52xx; 1021215976Sjmallett struct cvmx_iob_int_enb_s cn52xxp1; 1022215976Sjmallett struct cvmx_iob_int_enb_s cn56xx; 1023215976Sjmallett struct cvmx_iob_int_enb_s cn56xxp1; 1024215976Sjmallett struct cvmx_iob_int_enb_s cn58xx; 1025215976Sjmallett struct cvmx_iob_int_enb_s cn58xxp1; 1026232812Sjmallett struct cvmx_iob_int_enb_s cn61xx; 1027215976Sjmallett struct cvmx_iob_int_enb_s cn63xx; 1028215976Sjmallett struct cvmx_iob_int_enb_s cn63xxp1; 1029232812Sjmallett struct cvmx_iob_int_enb_s cn66xx; 1030232812Sjmallett struct cvmx_iob_int_enb_cn68xx { 1031232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1032232812Sjmallett uint64_t reserved_0_63 : 64; 1033232812Sjmallett#else 1034232812Sjmallett uint64_t reserved_0_63 : 64; 1035232812Sjmallett#endif 1036232812Sjmallett } cn68xx; 1037232812Sjmallett struct cvmx_iob_int_enb_cn68xx cn68xxp1; 1038232812Sjmallett struct cvmx_iob_int_enb_s cnf71xx; 1039215976Sjmallett}; 1040215976Sjmalletttypedef union cvmx_iob_int_enb cvmx_iob_int_enb_t; 1041215976Sjmallett 1042215976Sjmallett/** 1043215976Sjmallett * cvmx_iob_int_sum 1044215976Sjmallett * 1045215976Sjmallett * IOB_INT_SUM = IOB's Interrupt Summary Register 1046215976Sjmallett * 1047215976Sjmallett * Contains the diffrent interrupt summary bits of the IOB. This is a PASS-2 register. 1048215976Sjmallett */ 1049232812Sjmallettunion cvmx_iob_int_sum { 1050215976Sjmallett uint64_t u64; 1051232812Sjmallett struct cvmx_iob_int_sum_s { 1052232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1053215976Sjmallett uint64_t reserved_6_63 : 58; 1054215976Sjmallett uint64_t p_dat : 1; /**< Set when a data arrives before a SOP for the same 1055215976Sjmallett port for a passthrough packet. 1056215976Sjmallett The first detected error associated with bits [5:0] 1057215976Sjmallett of this register will only be set here. A new bit 1058215976Sjmallett can be set when the previous reported bit is cleared. */ 1059215976Sjmallett uint64_t np_dat : 1; /**< Set when a data arrives before a SOP for the same 1060215976Sjmallett port for a non-passthrough packet. 1061215976Sjmallett The first detected error associated with bits [5:0] 1062215976Sjmallett of this register will only be set here. A new bit 1063215976Sjmallett can be set when the previous reported bit is cleared. */ 1064215976Sjmallett uint64_t p_eop : 1; /**< Set when a EOP is followed by an EOP for the same 1065215976Sjmallett port for a passthrough packet. 1066215976Sjmallett The first detected error associated with bits [5:0] 1067215976Sjmallett of this register will only be set here. A new bit 1068215976Sjmallett can be set when the previous reported bit is cleared. */ 1069215976Sjmallett uint64_t p_sop : 1; /**< Set when a SOP is followed by an SOP for the same 1070215976Sjmallett port for a passthrough packet. 1071215976Sjmallett The first detected error associated with bits [5:0] 1072215976Sjmallett of this register will only be set here. A new bit 1073215976Sjmallett can be set when the previous reported bit is cleared. */ 1074215976Sjmallett uint64_t np_eop : 1; /**< Set when a EOP is followed by an EOP for the same 1075215976Sjmallett port for a non-passthrough packet. 1076215976Sjmallett The first detected error associated with bits [5:0] 1077215976Sjmallett of this register will only be set here. A new bit 1078215976Sjmallett can be set when the previous reported bit is cleared. */ 1079215976Sjmallett uint64_t np_sop : 1; /**< Set when a SOP is followed by an SOP for the same 1080215976Sjmallett port for a non-passthrough packet. 1081215976Sjmallett The first detected error associated with bits [5:0] 1082215976Sjmallett of this register will only be set here. A new bit 1083215976Sjmallett can be set when the previous reported bit is cleared. */ 1084215976Sjmallett#else 1085215976Sjmallett uint64_t np_sop : 1; 1086215976Sjmallett uint64_t np_eop : 1; 1087215976Sjmallett uint64_t p_sop : 1; 1088215976Sjmallett uint64_t p_eop : 1; 1089215976Sjmallett uint64_t np_dat : 1; 1090215976Sjmallett uint64_t p_dat : 1; 1091215976Sjmallett uint64_t reserved_6_63 : 58; 1092215976Sjmallett#endif 1093215976Sjmallett } s; 1094232812Sjmallett struct cvmx_iob_int_sum_cn30xx { 1095232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1096215976Sjmallett uint64_t reserved_4_63 : 60; 1097215976Sjmallett uint64_t p_eop : 1; /**< Set when a EOP is followed by an EOP for the same 1098215976Sjmallett port for a passthrough packet. 1099215976Sjmallett The first detected error associated with bits [3:0] 1100215976Sjmallett of this register will only be set here. A new bit 1101215976Sjmallett can be set when the previous reported bit is cleared. */ 1102215976Sjmallett uint64_t p_sop : 1; /**< Set when a SOP is followed by an SOP for the same 1103215976Sjmallett port for a passthrough packet. 1104215976Sjmallett The first detected error associated with bits [3:0] 1105215976Sjmallett of this register will only be set here. A new bit 1106215976Sjmallett can be set when the previous reported bit is cleared. */ 1107215976Sjmallett uint64_t np_eop : 1; /**< Set when a EOP is followed by an EOP for the same 1108215976Sjmallett port for a non-passthrough packet. 1109215976Sjmallett The first detected error associated with bits [3:0] 1110215976Sjmallett of this register will only be set here. A new bit 1111215976Sjmallett can be set when the previous reported bit is cleared. */ 1112215976Sjmallett uint64_t np_sop : 1; /**< Set when a SOP is followed by an SOP for the same 1113215976Sjmallett port for a non-passthrough packet. 1114215976Sjmallett The first detected error associated with bits [3:0] 1115215976Sjmallett of this register will only be set here. A new bit 1116215976Sjmallett can be set when the previous reported bit is cleared. */ 1117215976Sjmallett#else 1118215976Sjmallett uint64_t np_sop : 1; 1119215976Sjmallett uint64_t np_eop : 1; 1120215976Sjmallett uint64_t p_sop : 1; 1121215976Sjmallett uint64_t p_eop : 1; 1122215976Sjmallett uint64_t reserved_4_63 : 60; 1123215976Sjmallett#endif 1124215976Sjmallett } cn30xx; 1125215976Sjmallett struct cvmx_iob_int_sum_cn30xx cn31xx; 1126215976Sjmallett struct cvmx_iob_int_sum_cn30xx cn38xx; 1127215976Sjmallett struct cvmx_iob_int_sum_cn30xx cn38xxp2; 1128215976Sjmallett struct cvmx_iob_int_sum_s cn50xx; 1129215976Sjmallett struct cvmx_iob_int_sum_s cn52xx; 1130215976Sjmallett struct cvmx_iob_int_sum_s cn52xxp1; 1131215976Sjmallett struct cvmx_iob_int_sum_s cn56xx; 1132215976Sjmallett struct cvmx_iob_int_sum_s cn56xxp1; 1133215976Sjmallett struct cvmx_iob_int_sum_s cn58xx; 1134215976Sjmallett struct cvmx_iob_int_sum_s cn58xxp1; 1135232812Sjmallett struct cvmx_iob_int_sum_s cn61xx; 1136215976Sjmallett struct cvmx_iob_int_sum_s cn63xx; 1137215976Sjmallett struct cvmx_iob_int_sum_s cn63xxp1; 1138232812Sjmallett struct cvmx_iob_int_sum_s cn66xx; 1139232812Sjmallett struct cvmx_iob_int_sum_cn68xx { 1140232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1141232812Sjmallett uint64_t reserved_0_63 : 64; 1142232812Sjmallett#else 1143232812Sjmallett uint64_t reserved_0_63 : 64; 1144232812Sjmallett#endif 1145232812Sjmallett } cn68xx; 1146232812Sjmallett struct cvmx_iob_int_sum_cn68xx cn68xxp1; 1147232812Sjmallett struct cvmx_iob_int_sum_s cnf71xx; 1148215976Sjmallett}; 1149215976Sjmalletttypedef union cvmx_iob_int_sum cvmx_iob_int_sum_t; 1150215976Sjmallett 1151215976Sjmallett/** 1152215976Sjmallett * cvmx_iob_n2c_l2c_pri_cnt 1153215976Sjmallett * 1154215976Sjmallett * NCB To CMB L2C Priority Counter = NCB to CMB L2C Priority Counter Enable and Timer Value 1155215976Sjmallett * 1156215976Sjmallett * Enables and supplies the timeout count for raising the priority of NCB Store/Load access to the CMB. 1157215976Sjmallett */ 1158232812Sjmallettunion cvmx_iob_n2c_l2c_pri_cnt { 1159215976Sjmallett uint64_t u64; 1160232812Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s { 1161232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1162215976Sjmallett uint64_t reserved_16_63 : 48; 1163215976Sjmallett uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority 1164215976Sjmallett when CNT_VAL is reached. */ 1165215976Sjmallett uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising 1166215976Sjmallett the priority for access to CMB. */ 1167215976Sjmallett#else 1168215976Sjmallett uint64_t cnt_val : 15; 1169215976Sjmallett uint64_t cnt_enb : 1; 1170215976Sjmallett uint64_t reserved_16_63 : 48; 1171215976Sjmallett#endif 1172215976Sjmallett } s; 1173215976Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx; 1174215976Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2; 1175215976Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xx; 1176215976Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xxp1; 1177215976Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xx; 1178215976Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1; 1179215976Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx; 1180215976Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1; 1181232812Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn61xx; 1182215976Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx; 1183215976Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1; 1184232812Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cn66xx; 1185232812Sjmallett struct cvmx_iob_n2c_l2c_pri_cnt_s cnf71xx; 1186215976Sjmallett}; 1187215976Sjmalletttypedef union cvmx_iob_n2c_l2c_pri_cnt cvmx_iob_n2c_l2c_pri_cnt_t; 1188215976Sjmallett 1189215976Sjmallett/** 1190215976Sjmallett * cvmx_iob_n2c_rsp_pri_cnt 1191215976Sjmallett * 1192215976Sjmallett * NCB To CMB Response Priority Counter = NCB to CMB Response Priority Counter Enable and Timer Value 1193215976Sjmallett * 1194215976Sjmallett * Enables and supplies the timeout count for raising the priority of NCB Responses access to the CMB. 1195215976Sjmallett */ 1196232812Sjmallettunion cvmx_iob_n2c_rsp_pri_cnt { 1197215976Sjmallett uint64_t u64; 1198232812Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s { 1199232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1200215976Sjmallett uint64_t reserved_16_63 : 48; 1201215976Sjmallett uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority 1202215976Sjmallett when CNT_VAL is reached. */ 1203215976Sjmallett uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising 1204215976Sjmallett the priority for access to CMB. */ 1205215976Sjmallett#else 1206215976Sjmallett uint64_t cnt_val : 15; 1207215976Sjmallett uint64_t cnt_enb : 1; 1208215976Sjmallett uint64_t reserved_16_63 : 48; 1209215976Sjmallett#endif 1210215976Sjmallett } s; 1211215976Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx; 1212215976Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2; 1213215976Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xx; 1214215976Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xxp1; 1215215976Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xx; 1216215976Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1; 1217215976Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx; 1218215976Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1; 1219232812Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn61xx; 1220215976Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx; 1221215976Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1; 1222232812Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cn66xx; 1223232812Sjmallett struct cvmx_iob_n2c_rsp_pri_cnt_s cnf71xx; 1224215976Sjmallett}; 1225215976Sjmalletttypedef union cvmx_iob_n2c_rsp_pri_cnt cvmx_iob_n2c_rsp_pri_cnt_t; 1226215976Sjmallett 1227215976Sjmallett/** 1228215976Sjmallett * cvmx_iob_outb_com_pri_cnt 1229215976Sjmallett * 1230215976Sjmallett * Commit To NCB Priority Counter = Commit to NCB Priority Counter Enable and Timer Value 1231215976Sjmallett * 1232215976Sjmallett * Enables and supplies the timeout count for raising the priority of Commit request to the Outbound NCB. 1233215976Sjmallett */ 1234232812Sjmallettunion cvmx_iob_outb_com_pri_cnt { 1235215976Sjmallett uint64_t u64; 1236232812Sjmallett struct cvmx_iob_outb_com_pri_cnt_s { 1237232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1238215976Sjmallett uint64_t reserved_16_63 : 48; 1239215976Sjmallett uint64_t cnt_enb : 1; /**< Enables the raising of NCB access priority 1240215976Sjmallett when CNT_VAL is reached. */ 1241215976Sjmallett uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising 1242215976Sjmallett the priority for access to NCB. */ 1243215976Sjmallett#else 1244215976Sjmallett uint64_t cnt_val : 15; 1245215976Sjmallett uint64_t cnt_enb : 1; 1246215976Sjmallett uint64_t reserved_16_63 : 48; 1247215976Sjmallett#endif 1248215976Sjmallett } s; 1249215976Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn38xx; 1250215976Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2; 1251215976Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn52xx; 1252215976Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn52xxp1; 1253215976Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn56xx; 1254215976Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1; 1255215976Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn58xx; 1256215976Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1; 1257232812Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn61xx; 1258215976Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn63xx; 1259215976Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1; 1260232812Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn66xx; 1261232812Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn68xx; 1262232812Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cn68xxp1; 1263232812Sjmallett struct cvmx_iob_outb_com_pri_cnt_s cnf71xx; 1264215976Sjmallett}; 1265215976Sjmalletttypedef union cvmx_iob_outb_com_pri_cnt cvmx_iob_outb_com_pri_cnt_t; 1266215976Sjmallett 1267215976Sjmallett/** 1268215976Sjmallett * cvmx_iob_outb_control_match 1269215976Sjmallett * 1270215976Sjmallett * IOB_OUTB_CONTROL_MATCH = IOB Outbound Control Match 1271215976Sjmallett * 1272215976Sjmallett * Match pattern for the outbound control to set the OUTB_MATCH_BIT. PASS-2 Register 1273215976Sjmallett */ 1274232812Sjmallettunion cvmx_iob_outb_control_match { 1275215976Sjmallett uint64_t u64; 1276232812Sjmallett struct cvmx_iob_outb_control_match_s { 1277232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1278215976Sjmallett uint64_t reserved_26_63 : 38; 1279215976Sjmallett uint64_t mask : 8; /**< Pattern to match on the outbound NCB. */ 1280215976Sjmallett uint64_t eot : 1; /**< Pattern to match on the outbound NCB. */ 1281215976Sjmallett uint64_t dst : 8; /**< Pattern to match on the outbound NCB. */ 1282215976Sjmallett uint64_t src : 9; /**< Pattern to match on the outbound NCB. */ 1283215976Sjmallett#else 1284215976Sjmallett uint64_t src : 9; 1285215976Sjmallett uint64_t dst : 8; 1286215976Sjmallett uint64_t eot : 1; 1287215976Sjmallett uint64_t mask : 8; 1288215976Sjmallett uint64_t reserved_26_63 : 38; 1289215976Sjmallett#endif 1290215976Sjmallett } s; 1291215976Sjmallett struct cvmx_iob_outb_control_match_s cn30xx; 1292215976Sjmallett struct cvmx_iob_outb_control_match_s cn31xx; 1293215976Sjmallett struct cvmx_iob_outb_control_match_s cn38xx; 1294215976Sjmallett struct cvmx_iob_outb_control_match_s cn38xxp2; 1295215976Sjmallett struct cvmx_iob_outb_control_match_s cn50xx; 1296215976Sjmallett struct cvmx_iob_outb_control_match_s cn52xx; 1297215976Sjmallett struct cvmx_iob_outb_control_match_s cn52xxp1; 1298215976Sjmallett struct cvmx_iob_outb_control_match_s cn56xx; 1299215976Sjmallett struct cvmx_iob_outb_control_match_s cn56xxp1; 1300215976Sjmallett struct cvmx_iob_outb_control_match_s cn58xx; 1301215976Sjmallett struct cvmx_iob_outb_control_match_s cn58xxp1; 1302232812Sjmallett struct cvmx_iob_outb_control_match_s cn61xx; 1303215976Sjmallett struct cvmx_iob_outb_control_match_s cn63xx; 1304215976Sjmallett struct cvmx_iob_outb_control_match_s cn63xxp1; 1305232812Sjmallett struct cvmx_iob_outb_control_match_s cn66xx; 1306232812Sjmallett struct cvmx_iob_outb_control_match_s cn68xx; 1307232812Sjmallett struct cvmx_iob_outb_control_match_s cn68xxp1; 1308232812Sjmallett struct cvmx_iob_outb_control_match_s cnf71xx; 1309215976Sjmallett}; 1310215976Sjmalletttypedef union cvmx_iob_outb_control_match cvmx_iob_outb_control_match_t; 1311215976Sjmallett 1312215976Sjmallett/** 1313215976Sjmallett * cvmx_iob_outb_control_match_enb 1314215976Sjmallett * 1315215976Sjmallett * IOB_OUTB_CONTROL_MATCH_ENB = IOB Outbound Control Match Enable 1316215976Sjmallett * 1317215976Sjmallett * Enables the match of the corresponding bit in the IOB_OUTB_CONTROL_MATCH reister. PASS-2 Register 1318215976Sjmallett */ 1319232812Sjmallettunion cvmx_iob_outb_control_match_enb { 1320215976Sjmallett uint64_t u64; 1321232812Sjmallett struct cvmx_iob_outb_control_match_enb_s { 1322232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1323215976Sjmallett uint64_t reserved_26_63 : 38; 1324215976Sjmallett uint64_t mask : 8; /**< Pattern to match on the outbound NCB. */ 1325215976Sjmallett uint64_t eot : 1; /**< Pattern to match on the outbound NCB. */ 1326215976Sjmallett uint64_t dst : 8; /**< Pattern to match on the outbound NCB. */ 1327215976Sjmallett uint64_t src : 9; /**< Pattern to match on the outbound NCB. */ 1328215976Sjmallett#else 1329215976Sjmallett uint64_t src : 9; 1330215976Sjmallett uint64_t dst : 8; 1331215976Sjmallett uint64_t eot : 1; 1332215976Sjmallett uint64_t mask : 8; 1333215976Sjmallett uint64_t reserved_26_63 : 38; 1334215976Sjmallett#endif 1335215976Sjmallett } s; 1336215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn30xx; 1337215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn31xx; 1338215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn38xx; 1339215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn38xxp2; 1340215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn50xx; 1341215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn52xx; 1342215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn52xxp1; 1343215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn56xx; 1344215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn56xxp1; 1345215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn58xx; 1346215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn58xxp1; 1347232812Sjmallett struct cvmx_iob_outb_control_match_enb_s cn61xx; 1348215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn63xx; 1349215976Sjmallett struct cvmx_iob_outb_control_match_enb_s cn63xxp1; 1350232812Sjmallett struct cvmx_iob_outb_control_match_enb_s cn66xx; 1351232812Sjmallett struct cvmx_iob_outb_control_match_enb_s cn68xx; 1352232812Sjmallett struct cvmx_iob_outb_control_match_enb_s cn68xxp1; 1353232812Sjmallett struct cvmx_iob_outb_control_match_enb_s cnf71xx; 1354215976Sjmallett}; 1355215976Sjmalletttypedef union cvmx_iob_outb_control_match_enb cvmx_iob_outb_control_match_enb_t; 1356215976Sjmallett 1357215976Sjmallett/** 1358215976Sjmallett * cvmx_iob_outb_data_match 1359215976Sjmallett * 1360215976Sjmallett * IOB_OUTB_DATA_MATCH = IOB Outbound Data Match 1361215976Sjmallett * 1362215976Sjmallett * Match pattern for the outbound data to set the OUTB_MATCH_BIT. PASS-2 Register 1363215976Sjmallett */ 1364232812Sjmallettunion cvmx_iob_outb_data_match { 1365215976Sjmallett uint64_t u64; 1366232812Sjmallett struct cvmx_iob_outb_data_match_s { 1367232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1368215976Sjmallett uint64_t data : 64; /**< Pattern to match on the outbound NCB. */ 1369215976Sjmallett#else 1370215976Sjmallett uint64_t data : 64; 1371215976Sjmallett#endif 1372215976Sjmallett } s; 1373215976Sjmallett struct cvmx_iob_outb_data_match_s cn30xx; 1374215976Sjmallett struct cvmx_iob_outb_data_match_s cn31xx; 1375215976Sjmallett struct cvmx_iob_outb_data_match_s cn38xx; 1376215976Sjmallett struct cvmx_iob_outb_data_match_s cn38xxp2; 1377215976Sjmallett struct cvmx_iob_outb_data_match_s cn50xx; 1378215976Sjmallett struct cvmx_iob_outb_data_match_s cn52xx; 1379215976Sjmallett struct cvmx_iob_outb_data_match_s cn52xxp1; 1380215976Sjmallett struct cvmx_iob_outb_data_match_s cn56xx; 1381215976Sjmallett struct cvmx_iob_outb_data_match_s cn56xxp1; 1382215976Sjmallett struct cvmx_iob_outb_data_match_s cn58xx; 1383215976Sjmallett struct cvmx_iob_outb_data_match_s cn58xxp1; 1384232812Sjmallett struct cvmx_iob_outb_data_match_s cn61xx; 1385215976Sjmallett struct cvmx_iob_outb_data_match_s cn63xx; 1386215976Sjmallett struct cvmx_iob_outb_data_match_s cn63xxp1; 1387232812Sjmallett struct cvmx_iob_outb_data_match_s cn66xx; 1388232812Sjmallett struct cvmx_iob_outb_data_match_s cn68xx; 1389232812Sjmallett struct cvmx_iob_outb_data_match_s cn68xxp1; 1390232812Sjmallett struct cvmx_iob_outb_data_match_s cnf71xx; 1391215976Sjmallett}; 1392215976Sjmalletttypedef union cvmx_iob_outb_data_match cvmx_iob_outb_data_match_t; 1393215976Sjmallett 1394215976Sjmallett/** 1395215976Sjmallett * cvmx_iob_outb_data_match_enb 1396215976Sjmallett * 1397215976Sjmallett * IOB_OUTB_DATA_MATCH_ENB = IOB Outbound Data Match Enable 1398215976Sjmallett * 1399215976Sjmallett * Enables the match of the corresponding bit in the IOB_OUTB_DATA_MATCH reister. PASS-2 Register 1400215976Sjmallett */ 1401232812Sjmallettunion cvmx_iob_outb_data_match_enb { 1402215976Sjmallett uint64_t u64; 1403232812Sjmallett struct cvmx_iob_outb_data_match_enb_s { 1404232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1405215976Sjmallett uint64_t data : 64; /**< Bit to enable match of. */ 1406215976Sjmallett#else 1407215976Sjmallett uint64_t data : 64; 1408215976Sjmallett#endif 1409215976Sjmallett } s; 1410215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn30xx; 1411215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn31xx; 1412215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn38xx; 1413215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn38xxp2; 1414215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn50xx; 1415215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn52xx; 1416215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn52xxp1; 1417215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn56xx; 1418215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn56xxp1; 1419215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn58xx; 1420215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn58xxp1; 1421232812Sjmallett struct cvmx_iob_outb_data_match_enb_s cn61xx; 1422215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn63xx; 1423215976Sjmallett struct cvmx_iob_outb_data_match_enb_s cn63xxp1; 1424232812Sjmallett struct cvmx_iob_outb_data_match_enb_s cn66xx; 1425232812Sjmallett struct cvmx_iob_outb_data_match_enb_s cn68xx; 1426232812Sjmallett struct cvmx_iob_outb_data_match_enb_s cn68xxp1; 1427232812Sjmallett struct cvmx_iob_outb_data_match_enb_s cnf71xx; 1428215976Sjmallett}; 1429215976Sjmalletttypedef union cvmx_iob_outb_data_match_enb cvmx_iob_outb_data_match_enb_t; 1430215976Sjmallett 1431215976Sjmallett/** 1432215976Sjmallett * cvmx_iob_outb_fpa_pri_cnt 1433215976Sjmallett * 1434215976Sjmallett * FPA To NCB Priority Counter = FPA Returns to NCB Priority Counter Enable and Timer Value 1435215976Sjmallett * 1436215976Sjmallett * Enables and supplies the timeout count for raising the priority of FPA Rreturn Page request to the Outbound NCB. 1437215976Sjmallett */ 1438232812Sjmallettunion cvmx_iob_outb_fpa_pri_cnt { 1439215976Sjmallett uint64_t u64; 1440232812Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s { 1441232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1442215976Sjmallett uint64_t reserved_16_63 : 48; 1443215976Sjmallett uint64_t cnt_enb : 1; /**< Enables the raising of NCB access priority 1444215976Sjmallett when CNT_VAL is reached. */ 1445215976Sjmallett uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising 1446215976Sjmallett the priority for access to NCB. */ 1447215976Sjmallett#else 1448215976Sjmallett uint64_t cnt_val : 15; 1449215976Sjmallett uint64_t cnt_enb : 1; 1450215976Sjmallett uint64_t reserved_16_63 : 48; 1451215976Sjmallett#endif 1452215976Sjmallett } s; 1453215976Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx; 1454215976Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2; 1455215976Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn52xx; 1456215976Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn52xxp1; 1457215976Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn56xx; 1458215976Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1; 1459215976Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx; 1460215976Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1; 1461232812Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn61xx; 1462215976Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx; 1463215976Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1; 1464232812Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn66xx; 1465232812Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn68xx; 1466232812Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cn68xxp1; 1467232812Sjmallett struct cvmx_iob_outb_fpa_pri_cnt_s cnf71xx; 1468215976Sjmallett}; 1469215976Sjmalletttypedef union cvmx_iob_outb_fpa_pri_cnt cvmx_iob_outb_fpa_pri_cnt_t; 1470215976Sjmallett 1471215976Sjmallett/** 1472215976Sjmallett * cvmx_iob_outb_req_pri_cnt 1473215976Sjmallett * 1474215976Sjmallett * Request To NCB Priority Counter = Request to NCB Priority Counter Enable and Timer Value 1475215976Sjmallett * 1476215976Sjmallett * Enables and supplies the timeout count for raising the priority of Request transfers to the Outbound NCB. 1477215976Sjmallett */ 1478232812Sjmallettunion cvmx_iob_outb_req_pri_cnt { 1479215976Sjmallett uint64_t u64; 1480232812Sjmallett struct cvmx_iob_outb_req_pri_cnt_s { 1481232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1482215976Sjmallett uint64_t reserved_16_63 : 48; 1483215976Sjmallett uint64_t cnt_enb : 1; /**< Enables the raising of NCB access priority 1484215976Sjmallett when CNT_VAL is reached. */ 1485215976Sjmallett uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising 1486215976Sjmallett the priority for access to NCB. */ 1487215976Sjmallett#else 1488215976Sjmallett uint64_t cnt_val : 15; 1489215976Sjmallett uint64_t cnt_enb : 1; 1490215976Sjmallett uint64_t reserved_16_63 : 48; 1491215976Sjmallett#endif 1492215976Sjmallett } s; 1493215976Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn38xx; 1494215976Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2; 1495215976Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn52xx; 1496215976Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn52xxp1; 1497215976Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn56xx; 1498215976Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1; 1499215976Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn58xx; 1500215976Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1; 1501232812Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn61xx; 1502215976Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn63xx; 1503215976Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1; 1504232812Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn66xx; 1505232812Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn68xx; 1506232812Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cn68xxp1; 1507232812Sjmallett struct cvmx_iob_outb_req_pri_cnt_s cnf71xx; 1508215976Sjmallett}; 1509215976Sjmalletttypedef union cvmx_iob_outb_req_pri_cnt cvmx_iob_outb_req_pri_cnt_t; 1510215976Sjmallett 1511215976Sjmallett/** 1512215976Sjmallett * cvmx_iob_p2c_req_pri_cnt 1513215976Sjmallett * 1514215976Sjmallett * PKO To CMB Response Priority Counter = PKO to CMB Response Priority Counter Enable and Timer Value 1515215976Sjmallett * 1516215976Sjmallett * Enables and supplies the timeout count for raising the priority of PKO Load access to the CMB. 1517215976Sjmallett */ 1518232812Sjmallettunion cvmx_iob_p2c_req_pri_cnt { 1519215976Sjmallett uint64_t u64; 1520232812Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s { 1521232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1522215976Sjmallett uint64_t reserved_16_63 : 48; 1523215976Sjmallett uint64_t cnt_enb : 1; /**< Enables the raising of CMB access priority 1524215976Sjmallett when CNT_VAL is reached. */ 1525215976Sjmallett uint64_t cnt_val : 15; /**< Number of core clocks to wait before raising 1526215976Sjmallett the priority for access to CMB. */ 1527215976Sjmallett#else 1528215976Sjmallett uint64_t cnt_val : 15; 1529215976Sjmallett uint64_t cnt_enb : 1; 1530215976Sjmallett uint64_t reserved_16_63 : 48; 1531215976Sjmallett#endif 1532215976Sjmallett } s; 1533215976Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn38xx; 1534215976Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2; 1535215976Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn52xx; 1536215976Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn52xxp1; 1537215976Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn56xx; 1538215976Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1; 1539215976Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn58xx; 1540215976Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1; 1541232812Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn61xx; 1542215976Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn63xx; 1543215976Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1; 1544232812Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cn66xx; 1545232812Sjmallett struct cvmx_iob_p2c_req_pri_cnt_s cnf71xx; 1546215976Sjmallett}; 1547215976Sjmalletttypedef union cvmx_iob_p2c_req_pri_cnt cvmx_iob_p2c_req_pri_cnt_t; 1548215976Sjmallett 1549215976Sjmallett/** 1550215976Sjmallett * cvmx_iob_pkt_err 1551215976Sjmallett * 1552215976Sjmallett * IOB_PKT_ERR = IOB Packet Error Register 1553215976Sjmallett * 1554215976Sjmallett * Provides status about the failing packet recevie error. This is a PASS-2 register. 1555215976Sjmallett */ 1556232812Sjmallettunion cvmx_iob_pkt_err { 1557215976Sjmallett uint64_t u64; 1558232812Sjmallett struct cvmx_iob_pkt_err_s { 1559232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1560215976Sjmallett uint64_t reserved_12_63 : 52; 1561215976Sjmallett uint64_t vport : 6; /**< When IOB_INT_SUM[3:0] bit is set, this field 1562215976Sjmallett latches the failing vport associate with the 1563215976Sjmallett IOB_INT_SUM[3:0] bit set. */ 1564215976Sjmallett uint64_t port : 6; /**< When IOB_INT_SUM[3:0] bit is set, this field 1565215976Sjmallett latches the failing port associate with the 1566215976Sjmallett IOB_INT_SUM[3:0] bit set. */ 1567215976Sjmallett#else 1568215976Sjmallett uint64_t port : 6; 1569215976Sjmallett uint64_t vport : 6; 1570215976Sjmallett uint64_t reserved_12_63 : 52; 1571215976Sjmallett#endif 1572215976Sjmallett } s; 1573232812Sjmallett struct cvmx_iob_pkt_err_cn30xx { 1574232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1575215976Sjmallett uint64_t reserved_6_63 : 58; 1576215976Sjmallett uint64_t port : 6; /**< When IOB_INT_SUM[3:0] bit is set, this field 1577215976Sjmallett latches the failing port associate with the 1578215976Sjmallett IOB_INT_SUM[3:0] bit set. */ 1579215976Sjmallett#else 1580215976Sjmallett uint64_t port : 6; 1581215976Sjmallett uint64_t reserved_6_63 : 58; 1582215976Sjmallett#endif 1583215976Sjmallett } cn30xx; 1584215976Sjmallett struct cvmx_iob_pkt_err_cn30xx cn31xx; 1585215976Sjmallett struct cvmx_iob_pkt_err_cn30xx cn38xx; 1586215976Sjmallett struct cvmx_iob_pkt_err_cn30xx cn38xxp2; 1587215976Sjmallett struct cvmx_iob_pkt_err_cn30xx cn50xx; 1588215976Sjmallett struct cvmx_iob_pkt_err_cn30xx cn52xx; 1589215976Sjmallett struct cvmx_iob_pkt_err_cn30xx cn52xxp1; 1590215976Sjmallett struct cvmx_iob_pkt_err_cn30xx cn56xx; 1591215976Sjmallett struct cvmx_iob_pkt_err_cn30xx cn56xxp1; 1592215976Sjmallett struct cvmx_iob_pkt_err_cn30xx cn58xx; 1593215976Sjmallett struct cvmx_iob_pkt_err_cn30xx cn58xxp1; 1594232812Sjmallett struct cvmx_iob_pkt_err_s cn61xx; 1595215976Sjmallett struct cvmx_iob_pkt_err_s cn63xx; 1596215976Sjmallett struct cvmx_iob_pkt_err_s cn63xxp1; 1597232812Sjmallett struct cvmx_iob_pkt_err_s cn66xx; 1598232812Sjmallett struct cvmx_iob_pkt_err_s cnf71xx; 1599215976Sjmallett}; 1600215976Sjmalletttypedef union cvmx_iob_pkt_err cvmx_iob_pkt_err_t; 1601215976Sjmallett 1602215976Sjmallett/** 1603215976Sjmallett * cvmx_iob_to_cmb_credits 1604215976Sjmallett * 1605215976Sjmallett * IOB_TO_CMB_CREDITS = IOB To CMB Credits 1606215976Sjmallett * 1607215976Sjmallett * Controls the number of reads and writes that may be outstanding to the L2C (via the CMB). 1608215976Sjmallett */ 1609232812Sjmallettunion cvmx_iob_to_cmb_credits { 1610215976Sjmallett uint64_t u64; 1611232812Sjmallett struct cvmx_iob_to_cmb_credits_s { 1612232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1613232812Sjmallett uint64_t reserved_6_63 : 58; 1614232812Sjmallett uint64_t ncb_rd : 3; /**< Number of NCB reads that can be out to L2C where 1615232812Sjmallett 0 == 8-credits. */ 1616232812Sjmallett uint64_t ncb_wr : 3; /**< Number of NCB/PKI writes that can be out to L2C 1617232812Sjmallett where 0 == 8-credits. */ 1618232812Sjmallett#else 1619232812Sjmallett uint64_t ncb_wr : 3; 1620232812Sjmallett uint64_t ncb_rd : 3; 1621232812Sjmallett uint64_t reserved_6_63 : 58; 1622232812Sjmallett#endif 1623232812Sjmallett } s; 1624232812Sjmallett struct cvmx_iob_to_cmb_credits_cn52xx { 1625232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1626215976Sjmallett uint64_t reserved_9_63 : 55; 1627215976Sjmallett uint64_t pko_rd : 3; /**< Number of PKO reads that can be out to L2C where 1628215976Sjmallett 0 == 8-credits. */ 1629215976Sjmallett uint64_t ncb_rd : 3; /**< Number of NCB reads that can be out to L2C where 1630215976Sjmallett 0 == 8-credits. */ 1631215976Sjmallett uint64_t ncb_wr : 3; /**< Number of NCB/PKI writes that can be out to L2C 1632215976Sjmallett where 0 == 8-credits. */ 1633215976Sjmallett#else 1634215976Sjmallett uint64_t ncb_wr : 3; 1635215976Sjmallett uint64_t ncb_rd : 3; 1636215976Sjmallett uint64_t pko_rd : 3; 1637215976Sjmallett uint64_t reserved_9_63 : 55; 1638215976Sjmallett#endif 1639232812Sjmallett } cn52xx; 1640232812Sjmallett struct cvmx_iob_to_cmb_credits_cn52xx cn61xx; 1641232812Sjmallett struct cvmx_iob_to_cmb_credits_cn52xx cn63xx; 1642232812Sjmallett struct cvmx_iob_to_cmb_credits_cn52xx cn63xxp1; 1643232812Sjmallett struct cvmx_iob_to_cmb_credits_cn52xx cn66xx; 1644232812Sjmallett struct cvmx_iob_to_cmb_credits_cn68xx { 1645232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1646232812Sjmallett uint64_t reserved_9_63 : 55; 1647232812Sjmallett uint64_t dwb : 3; /**< Number of DWBs that can be out to L2C where 1648232812Sjmallett 0 == 8-credits. */ 1649232812Sjmallett uint64_t ncb_rd : 3; /**< Number of NCB reads that can be out to L2C where 1650232812Sjmallett 0 == 8-credits. */ 1651232812Sjmallett uint64_t ncb_wr : 3; /**< Number of NCB/PKI writes that can be out to L2C 1652232812Sjmallett where 0 == 8-credits. */ 1653232812Sjmallett#else 1654232812Sjmallett uint64_t ncb_wr : 3; 1655232812Sjmallett uint64_t ncb_rd : 3; 1656232812Sjmallett uint64_t dwb : 3; 1657232812Sjmallett uint64_t reserved_9_63 : 55; 1658232812Sjmallett#endif 1659232812Sjmallett } cn68xx; 1660232812Sjmallett struct cvmx_iob_to_cmb_credits_cn68xx cn68xxp1; 1661232812Sjmallett struct cvmx_iob_to_cmb_credits_cn52xx cnf71xx; 1662215976Sjmallett}; 1663215976Sjmalletttypedef union cvmx_iob_to_cmb_credits cvmx_iob_to_cmb_credits_t; 1664215976Sjmallett 1665232812Sjmallett/** 1666232812Sjmallett * cvmx_iob_to_ncb_did_00_credits 1667232812Sjmallett * 1668232812Sjmallett * IOB_TO_NCB_DID_00_CREDITS = IOB NCB DID 00 Credits 1669232812Sjmallett * 1670232812Sjmallett * Number of credits for NCB DID 00. 1671232812Sjmallett */ 1672232812Sjmallettunion cvmx_iob_to_ncb_did_00_credits { 1673232812Sjmallett uint64_t u64; 1674232812Sjmallett struct cvmx_iob_to_ncb_did_00_credits_s { 1675232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1676232812Sjmallett uint64_t reserved_7_63 : 57; 1677232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1678232812Sjmallett casuse the credits to be set to the value written. 1679232812Sjmallett Reading this field will give the number of credits 1680232812Sjmallett PRESENTLY available. */ 1681232812Sjmallett#else 1682232812Sjmallett uint64_t crd : 7; 1683232812Sjmallett uint64_t reserved_7_63 : 57; 1684215976Sjmallett#endif 1685232812Sjmallett } s; 1686232812Sjmallett struct cvmx_iob_to_ncb_did_00_credits_s cn68xx; 1687232812Sjmallett struct cvmx_iob_to_ncb_did_00_credits_s cn68xxp1; 1688232812Sjmallett}; 1689232812Sjmalletttypedef union cvmx_iob_to_ncb_did_00_credits cvmx_iob_to_ncb_did_00_credits_t; 1690232812Sjmallett 1691232812Sjmallett/** 1692232812Sjmallett * cvmx_iob_to_ncb_did_111_credits 1693232812Sjmallett * 1694232812Sjmallett * IOB_TO_NCB_DID_111_CREDITS = IOB NCB DID 111 Credits 1695232812Sjmallett * 1696232812Sjmallett * Number of credits for NCB DID 111. 1697232812Sjmallett */ 1698232812Sjmallettunion cvmx_iob_to_ncb_did_111_credits { 1699232812Sjmallett uint64_t u64; 1700232812Sjmallett struct cvmx_iob_to_ncb_did_111_credits_s { 1701232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1702232812Sjmallett uint64_t reserved_7_63 : 57; 1703232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1704232812Sjmallett casuse the credits to be set to the value written. 1705232812Sjmallett Reading this field will give the number of credits 1706232812Sjmallett PRESENTLY available. */ 1707232812Sjmallett#else 1708232812Sjmallett uint64_t crd : 7; 1709232812Sjmallett uint64_t reserved_7_63 : 57; 1710232812Sjmallett#endif 1711232812Sjmallett } s; 1712232812Sjmallett struct cvmx_iob_to_ncb_did_111_credits_s cn68xx; 1713232812Sjmallett struct cvmx_iob_to_ncb_did_111_credits_s cn68xxp1; 1714232812Sjmallett}; 1715232812Sjmalletttypedef union cvmx_iob_to_ncb_did_111_credits cvmx_iob_to_ncb_did_111_credits_t; 1716232812Sjmallett 1717232812Sjmallett/** 1718232812Sjmallett * cvmx_iob_to_ncb_did_223_credits 1719232812Sjmallett * 1720232812Sjmallett * IOB_TO_NCB_DID_223_CREDITS = IOB NCB DID 223 Credits 1721232812Sjmallett * 1722232812Sjmallett * Number of credits for NCB DID 223. 1723232812Sjmallett */ 1724232812Sjmallettunion cvmx_iob_to_ncb_did_223_credits { 1725232812Sjmallett uint64_t u64; 1726232812Sjmallett struct cvmx_iob_to_ncb_did_223_credits_s { 1727232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1728232812Sjmallett uint64_t reserved_7_63 : 57; 1729232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1730232812Sjmallett casuse the credits to be set to the value written. 1731232812Sjmallett Reading this field will give the number of credits 1732232812Sjmallett PRESENTLY available. */ 1733232812Sjmallett#else 1734232812Sjmallett uint64_t crd : 7; 1735232812Sjmallett uint64_t reserved_7_63 : 57; 1736232812Sjmallett#endif 1737232812Sjmallett } s; 1738232812Sjmallett struct cvmx_iob_to_ncb_did_223_credits_s cn68xx; 1739232812Sjmallett struct cvmx_iob_to_ncb_did_223_credits_s cn68xxp1; 1740232812Sjmallett}; 1741232812Sjmalletttypedef union cvmx_iob_to_ncb_did_223_credits cvmx_iob_to_ncb_did_223_credits_t; 1742232812Sjmallett 1743232812Sjmallett/** 1744232812Sjmallett * cvmx_iob_to_ncb_did_24_credits 1745232812Sjmallett * 1746232812Sjmallett * IOB_TO_NCB_DID_24_CREDITS = IOB NCB DID 24 Credits 1747232812Sjmallett * 1748232812Sjmallett * Number of credits for NCB DID 24. 1749232812Sjmallett */ 1750232812Sjmallettunion cvmx_iob_to_ncb_did_24_credits { 1751232812Sjmallett uint64_t u64; 1752232812Sjmallett struct cvmx_iob_to_ncb_did_24_credits_s { 1753232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1754232812Sjmallett uint64_t reserved_7_63 : 57; 1755232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1756232812Sjmallett casuse the credits to be set to the value written. 1757232812Sjmallett Reading this field will give the number of credits 1758232812Sjmallett PRESENTLY available. */ 1759232812Sjmallett#else 1760232812Sjmallett uint64_t crd : 7; 1761232812Sjmallett uint64_t reserved_7_63 : 57; 1762232812Sjmallett#endif 1763232812Sjmallett } s; 1764232812Sjmallett struct cvmx_iob_to_ncb_did_24_credits_s cn68xx; 1765232812Sjmallett struct cvmx_iob_to_ncb_did_24_credits_s cn68xxp1; 1766232812Sjmallett}; 1767232812Sjmalletttypedef union cvmx_iob_to_ncb_did_24_credits cvmx_iob_to_ncb_did_24_credits_t; 1768232812Sjmallett 1769232812Sjmallett/** 1770232812Sjmallett * cvmx_iob_to_ncb_did_32_credits 1771232812Sjmallett * 1772232812Sjmallett * IOB_TO_NCB_DID_32_CREDITS = IOB NCB DID 32 Credits 1773232812Sjmallett * 1774232812Sjmallett * Number of credits for NCB DID 32. 1775232812Sjmallett */ 1776232812Sjmallettunion cvmx_iob_to_ncb_did_32_credits { 1777232812Sjmallett uint64_t u64; 1778232812Sjmallett struct cvmx_iob_to_ncb_did_32_credits_s { 1779232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1780232812Sjmallett uint64_t reserved_7_63 : 57; 1781232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1782232812Sjmallett casuse the credits to be set to the value written. 1783232812Sjmallett Reading this field will give the number of credits 1784232812Sjmallett PRESENTLY available. */ 1785232812Sjmallett#else 1786232812Sjmallett uint64_t crd : 7; 1787232812Sjmallett uint64_t reserved_7_63 : 57; 1788232812Sjmallett#endif 1789232812Sjmallett } s; 1790232812Sjmallett struct cvmx_iob_to_ncb_did_32_credits_s cn68xx; 1791232812Sjmallett struct cvmx_iob_to_ncb_did_32_credits_s cn68xxp1; 1792232812Sjmallett}; 1793232812Sjmalletttypedef union cvmx_iob_to_ncb_did_32_credits cvmx_iob_to_ncb_did_32_credits_t; 1794232812Sjmallett 1795232812Sjmallett/** 1796232812Sjmallett * cvmx_iob_to_ncb_did_40_credits 1797232812Sjmallett * 1798232812Sjmallett * IOB_TO_NCB_DID_40_CREDITS = IOB NCB DID 40 Credits 1799232812Sjmallett * 1800232812Sjmallett * Number of credits for NCB DID 40. 1801232812Sjmallett */ 1802232812Sjmallettunion cvmx_iob_to_ncb_did_40_credits { 1803232812Sjmallett uint64_t u64; 1804232812Sjmallett struct cvmx_iob_to_ncb_did_40_credits_s { 1805232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1806232812Sjmallett uint64_t reserved_7_63 : 57; 1807232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1808232812Sjmallett casuse the credits to be set to the value written. 1809232812Sjmallett Reading this field will give the number of credits 1810232812Sjmallett PRESENTLY available. */ 1811232812Sjmallett#else 1812232812Sjmallett uint64_t crd : 7; 1813232812Sjmallett uint64_t reserved_7_63 : 57; 1814232812Sjmallett#endif 1815232812Sjmallett } s; 1816232812Sjmallett struct cvmx_iob_to_ncb_did_40_credits_s cn68xx; 1817232812Sjmallett struct cvmx_iob_to_ncb_did_40_credits_s cn68xxp1; 1818232812Sjmallett}; 1819232812Sjmalletttypedef union cvmx_iob_to_ncb_did_40_credits cvmx_iob_to_ncb_did_40_credits_t; 1820232812Sjmallett 1821232812Sjmallett/** 1822232812Sjmallett * cvmx_iob_to_ncb_did_55_credits 1823232812Sjmallett * 1824232812Sjmallett * IOB_TO_NCB_DID_55_CREDITS = IOB NCB DID 55 Credits 1825232812Sjmallett * 1826232812Sjmallett * Number of credits for NCB DID 55. 1827232812Sjmallett */ 1828232812Sjmallettunion cvmx_iob_to_ncb_did_55_credits { 1829232812Sjmallett uint64_t u64; 1830232812Sjmallett struct cvmx_iob_to_ncb_did_55_credits_s { 1831232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1832232812Sjmallett uint64_t reserved_7_63 : 57; 1833232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1834232812Sjmallett casuse the credits to be set to the value written. 1835232812Sjmallett Reading this field will give the number of credits 1836232812Sjmallett PRESENTLY available. */ 1837232812Sjmallett#else 1838232812Sjmallett uint64_t crd : 7; 1839232812Sjmallett uint64_t reserved_7_63 : 57; 1840232812Sjmallett#endif 1841232812Sjmallett } s; 1842232812Sjmallett struct cvmx_iob_to_ncb_did_55_credits_s cn68xx; 1843232812Sjmallett struct cvmx_iob_to_ncb_did_55_credits_s cn68xxp1; 1844232812Sjmallett}; 1845232812Sjmalletttypedef union cvmx_iob_to_ncb_did_55_credits cvmx_iob_to_ncb_did_55_credits_t; 1846232812Sjmallett 1847232812Sjmallett/** 1848232812Sjmallett * cvmx_iob_to_ncb_did_64_credits 1849232812Sjmallett * 1850232812Sjmallett * IOB_TO_NCB_DID_64_CREDITS = IOB NCB DID 64 Credits 1851232812Sjmallett * 1852232812Sjmallett * Number of credits for NCB DID 64. 1853232812Sjmallett */ 1854232812Sjmallettunion cvmx_iob_to_ncb_did_64_credits { 1855232812Sjmallett uint64_t u64; 1856232812Sjmallett struct cvmx_iob_to_ncb_did_64_credits_s { 1857232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1858232812Sjmallett uint64_t reserved_7_63 : 57; 1859232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1860232812Sjmallett casuse the credits to be set to the value written. 1861232812Sjmallett Reading this field will give the number of credits 1862232812Sjmallett PRESENTLY available. */ 1863232812Sjmallett#else 1864232812Sjmallett uint64_t crd : 7; 1865232812Sjmallett uint64_t reserved_7_63 : 57; 1866232812Sjmallett#endif 1867232812Sjmallett } s; 1868232812Sjmallett struct cvmx_iob_to_ncb_did_64_credits_s cn68xx; 1869232812Sjmallett struct cvmx_iob_to_ncb_did_64_credits_s cn68xxp1; 1870232812Sjmallett}; 1871232812Sjmalletttypedef union cvmx_iob_to_ncb_did_64_credits cvmx_iob_to_ncb_did_64_credits_t; 1872232812Sjmallett 1873232812Sjmallett/** 1874232812Sjmallett * cvmx_iob_to_ncb_did_79_credits 1875232812Sjmallett * 1876232812Sjmallett * IOB_TO_NCB_DID_79_CREDITS = IOB NCB DID 79 Credits 1877232812Sjmallett * 1878232812Sjmallett * Number of credits for NCB DID 79. 1879232812Sjmallett */ 1880232812Sjmallettunion cvmx_iob_to_ncb_did_79_credits { 1881232812Sjmallett uint64_t u64; 1882232812Sjmallett struct cvmx_iob_to_ncb_did_79_credits_s { 1883232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1884232812Sjmallett uint64_t reserved_7_63 : 57; 1885232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1886232812Sjmallett casuse the credits to be set to the value written. 1887232812Sjmallett Reading this field will give the number of credits 1888232812Sjmallett PRESENTLY available. */ 1889232812Sjmallett#else 1890232812Sjmallett uint64_t crd : 7; 1891232812Sjmallett uint64_t reserved_7_63 : 57; 1892232812Sjmallett#endif 1893232812Sjmallett } s; 1894232812Sjmallett struct cvmx_iob_to_ncb_did_79_credits_s cn68xx; 1895232812Sjmallett struct cvmx_iob_to_ncb_did_79_credits_s cn68xxp1; 1896232812Sjmallett}; 1897232812Sjmalletttypedef union cvmx_iob_to_ncb_did_79_credits cvmx_iob_to_ncb_did_79_credits_t; 1898232812Sjmallett 1899232812Sjmallett/** 1900232812Sjmallett * cvmx_iob_to_ncb_did_96_credits 1901232812Sjmallett * 1902232812Sjmallett * IOB_TO_NCB_DID_96_CREDITS = IOB NCB DID 96 Credits 1903232812Sjmallett * 1904232812Sjmallett * Number of credits for NCB DID 96. 1905232812Sjmallett */ 1906232812Sjmallettunion cvmx_iob_to_ncb_did_96_credits { 1907232812Sjmallett uint64_t u64; 1908232812Sjmallett struct cvmx_iob_to_ncb_did_96_credits_s { 1909232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1910232812Sjmallett uint64_t reserved_7_63 : 57; 1911232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1912232812Sjmallett casuse the credits to be set to the value written. 1913232812Sjmallett Reading this field will give the number of credits 1914232812Sjmallett PRESENTLY available. */ 1915232812Sjmallett#else 1916232812Sjmallett uint64_t crd : 7; 1917232812Sjmallett uint64_t reserved_7_63 : 57; 1918232812Sjmallett#endif 1919232812Sjmallett } s; 1920232812Sjmallett struct cvmx_iob_to_ncb_did_96_credits_s cn68xx; 1921232812Sjmallett struct cvmx_iob_to_ncb_did_96_credits_s cn68xxp1; 1922232812Sjmallett}; 1923232812Sjmalletttypedef union cvmx_iob_to_ncb_did_96_credits cvmx_iob_to_ncb_did_96_credits_t; 1924232812Sjmallett 1925232812Sjmallett/** 1926232812Sjmallett * cvmx_iob_to_ncb_did_98_credits 1927232812Sjmallett * 1928232812Sjmallett * IOB_TO_NCB_DID_98_CREDITS = IOB NCB DID 96 Credits 1929232812Sjmallett * 1930232812Sjmallett * Number of credits for NCB DID 98. 1931232812Sjmallett */ 1932232812Sjmallettunion cvmx_iob_to_ncb_did_98_credits { 1933232812Sjmallett uint64_t u64; 1934232812Sjmallett struct cvmx_iob_to_ncb_did_98_credits_s { 1935232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1936232812Sjmallett uint64_t reserved_7_63 : 57; 1937232812Sjmallett uint64_t crd : 7; /**< Number of credits for DID. Writing this field will 1938232812Sjmallett casuse the credits to be set to the value written. 1939232812Sjmallett Reading this field will give the number of credits 1940232812Sjmallett PRESENTLY available. */ 1941232812Sjmallett#else 1942232812Sjmallett uint64_t crd : 7; 1943232812Sjmallett uint64_t reserved_7_63 : 57; 1944232812Sjmallett#endif 1945232812Sjmallett } s; 1946232812Sjmallett struct cvmx_iob_to_ncb_did_98_credits_s cn68xx; 1947232812Sjmallett struct cvmx_iob_to_ncb_did_98_credits_s cn68xxp1; 1948232812Sjmallett}; 1949232812Sjmalletttypedef union cvmx_iob_to_ncb_did_98_credits cvmx_iob_to_ncb_did_98_credits_t; 1950232812Sjmallett 1951232812Sjmallett#endif 1952