1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Interface to the Mips interrupts. 50 * 51 * <hr>$Revision: 70030 $<hr> 52 */ 53#ifndef __CVMX_INTERRUPT_H__ 54#define __CVMX_INTERRUPT_H__ 55 56#ifdef __cplusplus 57extern "C" { 58#endif 59 60/** 61 * Enumeration of Interrupt numbers 62 */ 63typedef enum 64{ 65 /* 0 - 7 represent the 8 MIPS standard interrupt sources */ 66 CVMX_IRQ_SW0 = 0, 67 CVMX_IRQ_SW1, 68 CVMX_IRQ_MIPS2, 69 CVMX_IRQ_MIPS3, 70 CVMX_IRQ_MIPS4, 71 CVMX_IRQ_MIPS5, 72 CVMX_IRQ_MIPS6, 73 CVMX_IRQ_MIPS7, 74 /* 64 WORKQ interrupts. */ 75 CVMX_IRQ_WORKQ0, 76 /* 16 GPIO interrupts. */ 77 CVMX_IRQ_GPIO0 = CVMX_IRQ_WORKQ0 + 64, 78 /* 4 MBOX interrupts. */ 79 CVMX_IRQ_MBOX0 = CVMX_IRQ_GPIO0 + 16, 80 /* 3 UART interrupts. */ 81 CVMX_IRQ_UART0 = CVMX_IRQ_MBOX0 + 4, 82 CVMX_IRQ_PCI_INT0 = CVMX_IRQ_UART0 + 3, 83 CVMX_IRQ_PCI_INT1, 84 CVMX_IRQ_PCI_INT2, 85 CVMX_IRQ_PCI_INT3, 86 CVMX_IRQ_PCI_MSI0, 87 CVMX_IRQ_PCI_MSI1, 88 CVMX_IRQ_PCI_MSI2, 89 CVMX_IRQ_PCI_MSI3, 90 /* 2 TWSI interrupts */ 91 CVMX_IRQ_TWSI0, 92 CVMX_IRQ_RML = CVMX_IRQ_TWSI0 + 2, 93 /* 4 TRACE interrupts added in CN68XX */ 94 CVMX_IRQ_TRACE0, 95 /* 5 GMX_DRP interrupts added in CN68XX */ 96 CVMX_IRQ_GMX_DRP0 = CVMX_IRQ_TRACE0 + 4, 97 CVMX_IRQ_GMX_DRP1, /* Doesn't apply on CN52XX or CN63XX */ 98 CVMX_IRQ_IPD_DRP = CVMX_IRQ_GMX_DRP0 + 5, 99 CVMX_IRQ_KEY_ZERO, /* Doesn't apply on CN52XX or CN63XX */ 100 /* 4 TIMER interrupts. */ 101 CVMX_IRQ_TIMER0, 102 /* 2 USB interrupts. */ 103 CVMX_IRQ_USB0 = CVMX_IRQ_TIMER0 + 4, /* Doesn't apply on CN38XX or CN58XX */ 104 CVMX_IRQ_PCM = CVMX_IRQ_USB0 + 2, /* Doesn't apply on CN52XX or CN63XX */ 105 CVMX_IRQ_MPI, /* Doesn't apply on CN52XX or CN63XX */ 106 CVMX_IRQ_POWIQ, /* Added in CN56XX */ 107 CVMX_IRQ_IPDPPTHR, /* Added in CN56XX */ 108 /* 2 MII interrupts. */ 109 CVMX_IRQ_MII0, /* Added in CN56XX */ 110 CVMX_IRQ_BOOTDMA = CVMX_IRQ_MII0 + 2, /* Added in CN56XX */ 111 112 /* 32 WDOG interrupts. */ 113 CVMX_IRQ_WDOG0, 114 CVMX_IRQ_NAND = CVMX_IRQ_WDOG0 + 32, /* Added in CN52XX */ 115 CVMX_IRQ_MIO, /* Added in CN63XX */ 116 CVMX_IRQ_IOB, /* Added in CN63XX */ 117 CVMX_IRQ_FPA, /* Added in CN63XX */ 118 CVMX_IRQ_POW, /* Added in CN63XX */ 119 CVMX_IRQ_L2C, /* Added in CN63XX */ 120 CVMX_IRQ_IPD, /* Added in CN63XX */ 121 CVMX_IRQ_PIP, /* Added in CN63XX */ 122 CVMX_IRQ_PKO, /* Added in CN63XX */ 123 CVMX_IRQ_ZIP, /* Added in CN63XX */ 124 CVMX_IRQ_TIM, /* Added in CN63XX */ 125 CVMX_IRQ_RAD, /* Added in CN63XX */ 126 CVMX_IRQ_KEY, /* Added in CN63XX */ 127 CVMX_IRQ_DFA, /* Added in CN63XX */ 128 CVMX_IRQ_USBCTL, /* Added in CN63XX */ 129 CVMX_IRQ_SLI, /* Added in CN63XX */ 130 CVMX_IRQ_DPI, /* Added in CN63XX */ 131 /* 5 AGX interrupts added in CN68XX. */ 132 CVMX_IRQ_AGX0, /* Added in CN63XX */ 133 134 CVMX_IRQ_AGL = CVMX_IRQ_AGX0 + 5, /* Added in CN63XX */ 135 CVMX_IRQ_PTP, /* Added in CN63XX */ 136 CVMX_IRQ_PEM0, /* Added in CN63XX */ 137 CVMX_IRQ_PEM1, /* Added in CN63XX */ 138 CVMX_IRQ_SRIO0, /* Added in CN63XX */ 139 CVMX_IRQ_SRIO1, /* Added in CN63XX */ 140 CVMX_IRQ_LMC0, /* Added in CN63XX */ 141 /* 4 LMC interrupts added in CN68XX. */ 142 CVMX_IRQ_DFM = CVMX_IRQ_LMC0 + 4, /* Added in CN63XX */ 143 CVMX_IRQ_RST, /* Added in CN63XX */ 144 CVMX_IRQ_ILK, /* Added for CN68XX */ 145 CVMX_IRQ_SRIO2, /* Added in CN66XX */ 146 CVMX_IRQ_DPI_DMA, /* Added in CN61XX */ 147 /* 6 addition timers added in CN61XX */ 148 CVMX_IRQ_TIMER4, /* Added in CN61XX */ 149 CVMX_IRQ_MAX = CVMX_IRQ_TIMER4 + 6 /* One greater than the last valid number.*/ 150} cvmx_irq_t; 151 152/** 153 * Function prototype for the exception handler 154 */ 155typedef void (*cvmx_interrupt_exception_t)(uint64_t *registers); 156 157/** 158 * Function prototype for interrupt handlers 159 */ 160typedef void (*cvmx_interrupt_func_t)(int irq_number, uint64_t *registers, void *user_arg); 161 162/** 163 * Register an interrupt handler for the specified interrupt number. 164 * 165 * @param irq_number Interrupt number to register for (0-135) 166 * @param func Function to call on interrupt. 167 * @param user_arg User data to pass to the interrupt handler 168 */ 169void cvmx_interrupt_register(int irq_number, cvmx_interrupt_func_t func, void *user_arg); 170 171/** 172 * Set the exception handler for all non interrupt sources. 173 * 174 * @param handler New exception handler 175 * @return Old exception handler 176 */ 177cvmx_interrupt_exception_t cvmx_interrupt_set_exception(cvmx_interrupt_exception_t handler); 178 179 180/** 181 * Masks a given interrupt number. 182 * 183 * @param irq_number interrupt number to mask 184 */ 185extern void (*cvmx_interrupt_mask_irq)(int irq_number); 186 187 188/** 189 * Unmasks a given interrupt number 190 * 191 * @param irq_number interrupt number to unmask 192 */ 193extern void (*cvmx_interrupt_unmask_irq)(int irq_number); 194 195 196/* Disable interrupts by clearing bit 0 of the COP0 status register, 197** and return the previous contents of the status register. 198** Note: this is only used to track interrupt status. */ 199static inline uint32_t cvmx_interrupt_disable_save(void) 200{ 201 uint32_t flags; 202 asm volatile ( 203 "DI %[flags]\n" 204 : [flags]"=r" (flags)); 205 return(flags); 206} 207 208/* Restore the contents of the cop0 status register. Used with 209** cvmx_interrupt_disable_save to allow recursive interrupt disabling */ 210static inline void cvmx_interrupt_restore(uint32_t flags) 211{ 212 /* If flags value indicates interrupts should be enabled, then enable them */ 213 if (flags & 1) 214 { 215 asm volatile ( 216 "EI \n" 217 ::); 218 } 219} 220 221#define cvmx_local_irq_save(x) ({x = cvmx_interrupt_disable_save();}) 222#define cvmx_local_irq_restore(x) cvmx_interrupt_restore(x) 223 224/** 225 * Utility function to do interrupt safe printf 226 */ 227#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 228 #define cvmx_safe_printf printk 229#elif defined(CVMX_BUILD_FOR_LINUX_USER) 230 #define cvmx_safe_printf printf 231#else 232 extern void cvmx_safe_printf(const char* format, ... ) __attribute__ ((format(printf, 1, 2))); 233#endif 234 235#define PRINT_ERROR(format, ...) cvmx_safe_printf("ERROR " format, ##__VA_ARGS__) 236 237#ifdef __cplusplus 238} 239#endif 240 241#endif 242