1232809Sjmallett/***********************license start*************** 2232809Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3232809Sjmallett * reserved. 4232809Sjmallett * 5232809Sjmallett * 6232809Sjmallett * Redistribution and use in source and binary forms, with or without 7232809Sjmallett * modification, are permitted provided that the following conditions are 8232809Sjmallett * met: 9232809Sjmallett * 10232809Sjmallett * * Redistributions of source code must retain the above copyright 11232809Sjmallett * notice, this list of conditions and the following disclaimer. 12232809Sjmallett * 13232809Sjmallett * * Redistributions in binary form must reproduce the above 14232809Sjmallett * copyright notice, this list of conditions and the following 15232809Sjmallett * disclaimer in the documentation and/or other materials provided 16232809Sjmallett * with the distribution. 17232809Sjmallett 18232809Sjmallett * * Neither the name of Cavium Inc. nor the names of 19232809Sjmallett * its contributors may be used to endorse or promote products 20232809Sjmallett * derived from this software without specific prior written 21232809Sjmallett * permission. 22232809Sjmallett 23232809Sjmallett * This Software, including technical data, may be subject to U.S. export control 24232809Sjmallett * laws, including the U.S. Export Administration Act and its associated 25232809Sjmallett * regulations, and may be subject to export or import regulations in other 26232809Sjmallett * countries. 27232809Sjmallett 28232809Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232809Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30232809Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31232809Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32232809Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33232809Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34232809Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35232809Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36232809Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37232809Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38232809Sjmallett ***********************license end**************************************/ 39232809Sjmallett 40232809Sjmallett 41232809Sjmallett/** 42232809Sjmallett * cvmx-ilk-defs.h 43232809Sjmallett * 44232809Sjmallett * Configuration and status register (CSR) type definitions for 45232809Sjmallett * Octeon ilk. 46232809Sjmallett * 47232809Sjmallett * This file is auto generated. Do not edit. 48232809Sjmallett * 49232809Sjmallett * <hr>$Revision$<hr> 50232809Sjmallett * 51232809Sjmallett */ 52232809Sjmallett#ifndef __CVMX_ILK_DEFS_H__ 53232809Sjmallett#define __CVMX_ILK_DEFS_H__ 54232809Sjmallett 55232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56232809Sjmallett#define CVMX_ILK_BIST_SUM CVMX_ILK_BIST_SUM_FUNC() 57232809Sjmallettstatic inline uint64_t CVMX_ILK_BIST_SUM_FUNC(void) 58232809Sjmallett{ 59232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 60232809Sjmallett cvmx_warn("CVMX_ILK_BIST_SUM not supported on this chip\n"); 61232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014000038ull); 62232809Sjmallett} 63232809Sjmallett#else 64232809Sjmallett#define CVMX_ILK_BIST_SUM (CVMX_ADD_IO_SEG(0x0001180014000038ull)) 65232809Sjmallett#endif 66232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67232809Sjmallett#define CVMX_ILK_GBL_CFG CVMX_ILK_GBL_CFG_FUNC() 68232809Sjmallettstatic inline uint64_t CVMX_ILK_GBL_CFG_FUNC(void) 69232809Sjmallett{ 70232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 71232809Sjmallett cvmx_warn("CVMX_ILK_GBL_CFG not supported on this chip\n"); 72232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014000000ull); 73232809Sjmallett} 74232809Sjmallett#else 75232809Sjmallett#define CVMX_ILK_GBL_CFG (CVMX_ADD_IO_SEG(0x0001180014000000ull)) 76232809Sjmallett#endif 77232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78232809Sjmallett#define CVMX_ILK_GBL_INT CVMX_ILK_GBL_INT_FUNC() 79232809Sjmallettstatic inline uint64_t CVMX_ILK_GBL_INT_FUNC(void) 80232809Sjmallett{ 81232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 82232809Sjmallett cvmx_warn("CVMX_ILK_GBL_INT not supported on this chip\n"); 83232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014000008ull); 84232809Sjmallett} 85232809Sjmallett#else 86232809Sjmallett#define CVMX_ILK_GBL_INT (CVMX_ADD_IO_SEG(0x0001180014000008ull)) 87232809Sjmallett#endif 88232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89232809Sjmallett#define CVMX_ILK_GBL_INT_EN CVMX_ILK_GBL_INT_EN_FUNC() 90232809Sjmallettstatic inline uint64_t CVMX_ILK_GBL_INT_EN_FUNC(void) 91232809Sjmallett{ 92232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 93232809Sjmallett cvmx_warn("CVMX_ILK_GBL_INT_EN not supported on this chip\n"); 94232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014000010ull); 95232809Sjmallett} 96232809Sjmallett#else 97232809Sjmallett#define CVMX_ILK_GBL_INT_EN (CVMX_ADD_IO_SEG(0x0001180014000010ull)) 98232809Sjmallett#endif 99232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100232809Sjmallett#define CVMX_ILK_INT_SUM CVMX_ILK_INT_SUM_FUNC() 101232809Sjmallettstatic inline uint64_t CVMX_ILK_INT_SUM_FUNC(void) 102232809Sjmallett{ 103232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 104232809Sjmallett cvmx_warn("CVMX_ILK_INT_SUM not supported on this chip\n"); 105232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014000030ull); 106232809Sjmallett} 107232809Sjmallett#else 108232809Sjmallett#define CVMX_ILK_INT_SUM (CVMX_ADD_IO_SEG(0x0001180014000030ull)) 109232809Sjmallett#endif 110232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111232809Sjmallett#define CVMX_ILK_LNE_DBG CVMX_ILK_LNE_DBG_FUNC() 112232809Sjmallettstatic inline uint64_t CVMX_ILK_LNE_DBG_FUNC(void) 113232809Sjmallett{ 114232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 115232809Sjmallett cvmx_warn("CVMX_ILK_LNE_DBG not supported on this chip\n"); 116232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014030008ull); 117232809Sjmallett} 118232809Sjmallett#else 119232809Sjmallett#define CVMX_ILK_LNE_DBG (CVMX_ADD_IO_SEG(0x0001180014030008ull)) 120232809Sjmallett#endif 121232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122232809Sjmallett#define CVMX_ILK_LNE_STS_MSG CVMX_ILK_LNE_STS_MSG_FUNC() 123232809Sjmallettstatic inline uint64_t CVMX_ILK_LNE_STS_MSG_FUNC(void) 124232809Sjmallett{ 125232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 126232809Sjmallett cvmx_warn("CVMX_ILK_LNE_STS_MSG not supported on this chip\n"); 127232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014030000ull); 128232809Sjmallett} 129232809Sjmallett#else 130232809Sjmallett#define CVMX_ILK_LNE_STS_MSG (CVMX_ADD_IO_SEG(0x0001180014030000ull)) 131232809Sjmallett#endif 132232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133232809Sjmallett#define CVMX_ILK_RXF_IDX_PMAP CVMX_ILK_RXF_IDX_PMAP_FUNC() 134232809Sjmallettstatic inline uint64_t CVMX_ILK_RXF_IDX_PMAP_FUNC(void) 135232809Sjmallett{ 136232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 137232809Sjmallett cvmx_warn("CVMX_ILK_RXF_IDX_PMAP not supported on this chip\n"); 138232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014000020ull); 139232809Sjmallett} 140232809Sjmallett#else 141232809Sjmallett#define CVMX_ILK_RXF_IDX_PMAP (CVMX_ADD_IO_SEG(0x0001180014000020ull)) 142232809Sjmallett#endif 143232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144232809Sjmallett#define CVMX_ILK_RXF_MEM_PMAP CVMX_ILK_RXF_MEM_PMAP_FUNC() 145232809Sjmallettstatic inline uint64_t CVMX_ILK_RXF_MEM_PMAP_FUNC(void) 146232809Sjmallett{ 147232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 148232809Sjmallett cvmx_warn("CVMX_ILK_RXF_MEM_PMAP not supported on this chip\n"); 149232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014000028ull); 150232809Sjmallett} 151232809Sjmallett#else 152232809Sjmallett#define CVMX_ILK_RXF_MEM_PMAP (CVMX_ADD_IO_SEG(0x0001180014000028ull)) 153232809Sjmallett#endif 154232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 155232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_CFG0(unsigned long offset) 156232809Sjmallett{ 157232809Sjmallett if (!( 158232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 159232809Sjmallett cvmx_warn("CVMX_ILK_RXX_CFG0(%lu) is invalid on this chip\n", offset); 160232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020000ull) + ((offset) & 1) * 16384; 161232809Sjmallett} 162232809Sjmallett#else 163232809Sjmallett#define CVMX_ILK_RXX_CFG0(offset) (CVMX_ADD_IO_SEG(0x0001180014020000ull) + ((offset) & 1) * 16384) 164232809Sjmallett#endif 165232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 166232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_CFG1(unsigned long offset) 167232809Sjmallett{ 168232809Sjmallett if (!( 169232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 170232809Sjmallett cvmx_warn("CVMX_ILK_RXX_CFG1(%lu) is invalid on this chip\n", offset); 171232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020008ull) + ((offset) & 1) * 16384; 172232809Sjmallett} 173232809Sjmallett#else 174232809Sjmallett#define CVMX_ILK_RXX_CFG1(offset) (CVMX_ADD_IO_SEG(0x0001180014020008ull) + ((offset) & 1) * 16384) 175232809Sjmallett#endif 176232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 177232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_FLOW_CTL0(unsigned long offset) 178232809Sjmallett{ 179232809Sjmallett if (!( 180232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 181232809Sjmallett cvmx_warn("CVMX_ILK_RXX_FLOW_CTL0(%lu) is invalid on this chip\n", offset); 182232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020090ull) + ((offset) & 1) * 16384; 183232809Sjmallett} 184232809Sjmallett#else 185232809Sjmallett#define CVMX_ILK_RXX_FLOW_CTL0(offset) (CVMX_ADD_IO_SEG(0x0001180014020090ull) + ((offset) & 1) * 16384) 186232809Sjmallett#endif 187232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 188232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_FLOW_CTL1(unsigned long offset) 189232809Sjmallett{ 190232809Sjmallett if (!( 191232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 192232809Sjmallett cvmx_warn("CVMX_ILK_RXX_FLOW_CTL1(%lu) is invalid on this chip\n", offset); 193232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020098ull) + ((offset) & 1) * 16384; 194232809Sjmallett} 195232809Sjmallett#else 196232809Sjmallett#define CVMX_ILK_RXX_FLOW_CTL1(offset) (CVMX_ADD_IO_SEG(0x0001180014020098ull) + ((offset) & 1) * 16384) 197232809Sjmallett#endif 198232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 199232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_IDX_CAL(unsigned long offset) 200232809Sjmallett{ 201232809Sjmallett if (!( 202232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 203232809Sjmallett cvmx_warn("CVMX_ILK_RXX_IDX_CAL(%lu) is invalid on this chip\n", offset); 204232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800140200A0ull) + ((offset) & 1) * 16384; 205232809Sjmallett} 206232809Sjmallett#else 207232809Sjmallett#define CVMX_ILK_RXX_IDX_CAL(offset) (CVMX_ADD_IO_SEG(0x00011800140200A0ull) + ((offset) & 1) * 16384) 208232809Sjmallett#endif 209232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 210232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_IDX_STAT0(unsigned long offset) 211232809Sjmallett{ 212232809Sjmallett if (!( 213232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 214232809Sjmallett cvmx_warn("CVMX_ILK_RXX_IDX_STAT0(%lu) is invalid on this chip\n", offset); 215232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020070ull) + ((offset) & 1) * 16384; 216232809Sjmallett} 217232809Sjmallett#else 218232809Sjmallett#define CVMX_ILK_RXX_IDX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014020070ull) + ((offset) & 1) * 16384) 219232809Sjmallett#endif 220232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_IDX_STAT1(unsigned long offset) 222232809Sjmallett{ 223232809Sjmallett if (!( 224232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 225232809Sjmallett cvmx_warn("CVMX_ILK_RXX_IDX_STAT1(%lu) is invalid on this chip\n", offset); 226232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020078ull) + ((offset) & 1) * 16384; 227232809Sjmallett} 228232809Sjmallett#else 229232809Sjmallett#define CVMX_ILK_RXX_IDX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014020078ull) + ((offset) & 1) * 16384) 230232809Sjmallett#endif 231232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_INT(unsigned long offset) 233232809Sjmallett{ 234232809Sjmallett if (!( 235232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 236232809Sjmallett cvmx_warn("CVMX_ILK_RXX_INT(%lu) is invalid on this chip\n", offset); 237232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020010ull) + ((offset) & 1) * 16384; 238232809Sjmallett} 239232809Sjmallett#else 240232809Sjmallett#define CVMX_ILK_RXX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180014020010ull) + ((offset) & 1) * 16384) 241232809Sjmallett#endif 242232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_INT_EN(unsigned long offset) 244232809Sjmallett{ 245232809Sjmallett if (!( 246232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 247232809Sjmallett cvmx_warn("CVMX_ILK_RXX_INT_EN(%lu) is invalid on this chip\n", offset); 248232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020018ull) + ((offset) & 1) * 16384; 249232809Sjmallett} 250232809Sjmallett#else 251232809Sjmallett#define CVMX_ILK_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x0001180014020018ull) + ((offset) & 1) * 16384) 252232809Sjmallett#endif 253232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 254232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_JABBER(unsigned long offset) 255232809Sjmallett{ 256232809Sjmallett if (!( 257232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 258232809Sjmallett cvmx_warn("CVMX_ILK_RXX_JABBER(%lu) is invalid on this chip\n", offset); 259232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800140200B8ull) + ((offset) & 1) * 16384; 260232809Sjmallett} 261232809Sjmallett#else 262232809Sjmallett#define CVMX_ILK_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800140200B8ull) + ((offset) & 1) * 16384) 263232809Sjmallett#endif 264232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 265232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_MEM_CAL0(unsigned long offset) 266232809Sjmallett{ 267232809Sjmallett if (!( 268232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 269232809Sjmallett cvmx_warn("CVMX_ILK_RXX_MEM_CAL0(%lu) is invalid on this chip\n", offset); 270232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800140200A8ull) + ((offset) & 1) * 16384; 271232809Sjmallett} 272232809Sjmallett#else 273232809Sjmallett#define CVMX_ILK_RXX_MEM_CAL0(offset) (CVMX_ADD_IO_SEG(0x00011800140200A8ull) + ((offset) & 1) * 16384) 274232809Sjmallett#endif 275232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 276232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_MEM_CAL1(unsigned long offset) 277232809Sjmallett{ 278232809Sjmallett if (!( 279232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 280232809Sjmallett cvmx_warn("CVMX_ILK_RXX_MEM_CAL1(%lu) is invalid on this chip\n", offset); 281232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800140200B0ull) + ((offset) & 1) * 16384; 282232809Sjmallett} 283232809Sjmallett#else 284232809Sjmallett#define CVMX_ILK_RXX_MEM_CAL1(offset) (CVMX_ADD_IO_SEG(0x00011800140200B0ull) + ((offset) & 1) * 16384) 285232809Sjmallett#endif 286232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 287232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_MEM_STAT0(unsigned long offset) 288232809Sjmallett{ 289232809Sjmallett if (!( 290232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 291232809Sjmallett cvmx_warn("CVMX_ILK_RXX_MEM_STAT0(%lu) is invalid on this chip\n", offset); 292232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020080ull) + ((offset) & 1) * 16384; 293232809Sjmallett} 294232809Sjmallett#else 295232809Sjmallett#define CVMX_ILK_RXX_MEM_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014020080ull) + ((offset) & 1) * 16384) 296232809Sjmallett#endif 297232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 298232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_MEM_STAT1(unsigned long offset) 299232809Sjmallett{ 300232809Sjmallett if (!( 301232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 302232809Sjmallett cvmx_warn("CVMX_ILK_RXX_MEM_STAT1(%lu) is invalid on this chip\n", offset); 303232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020088ull) + ((offset) & 1) * 16384; 304232809Sjmallett} 305232809Sjmallett#else 306232809Sjmallett#define CVMX_ILK_RXX_MEM_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014020088ull) + ((offset) & 1) * 16384) 307232809Sjmallett#endif 308232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 309232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_RID(unsigned long offset) 310232809Sjmallett{ 311232809Sjmallett if (!( 312232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 313232809Sjmallett cvmx_warn("CVMX_ILK_RXX_RID(%lu) is invalid on this chip\n", offset); 314232809Sjmallett return CVMX_ADD_IO_SEG(0x00011800140200C0ull) + ((offset) & 1) * 16384; 315232809Sjmallett} 316232809Sjmallett#else 317232809Sjmallett#define CVMX_ILK_RXX_RID(offset) (CVMX_ADD_IO_SEG(0x00011800140200C0ull) + ((offset) & 1) * 16384) 318232809Sjmallett#endif 319232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 320232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_STAT0(unsigned long offset) 321232809Sjmallett{ 322232809Sjmallett if (!( 323232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 324232809Sjmallett cvmx_warn("CVMX_ILK_RXX_STAT0(%lu) is invalid on this chip\n", offset); 325232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020020ull) + ((offset) & 1) * 16384; 326232809Sjmallett} 327232809Sjmallett#else 328232809Sjmallett#define CVMX_ILK_RXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014020020ull) + ((offset) & 1) * 16384) 329232809Sjmallett#endif 330232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 331232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_STAT1(unsigned long offset) 332232809Sjmallett{ 333232809Sjmallett if (!( 334232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 335232809Sjmallett cvmx_warn("CVMX_ILK_RXX_STAT1(%lu) is invalid on this chip\n", offset); 336232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020028ull) + ((offset) & 1) * 16384; 337232809Sjmallett} 338232809Sjmallett#else 339232809Sjmallett#define CVMX_ILK_RXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014020028ull) + ((offset) & 1) * 16384) 340232809Sjmallett#endif 341232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 342232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_STAT2(unsigned long offset) 343232809Sjmallett{ 344232809Sjmallett if (!( 345232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 346232809Sjmallett cvmx_warn("CVMX_ILK_RXX_STAT2(%lu) is invalid on this chip\n", offset); 347232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020030ull) + ((offset) & 1) * 16384; 348232809Sjmallett} 349232809Sjmallett#else 350232809Sjmallett#define CVMX_ILK_RXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x0001180014020030ull) + ((offset) & 1) * 16384) 351232809Sjmallett#endif 352232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 353232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_STAT3(unsigned long offset) 354232809Sjmallett{ 355232809Sjmallett if (!( 356232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 357232809Sjmallett cvmx_warn("CVMX_ILK_RXX_STAT3(%lu) is invalid on this chip\n", offset); 358232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020038ull) + ((offset) & 1) * 16384; 359232809Sjmallett} 360232809Sjmallett#else 361232809Sjmallett#define CVMX_ILK_RXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x0001180014020038ull) + ((offset) & 1) * 16384) 362232809Sjmallett#endif 363232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 364232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_STAT4(unsigned long offset) 365232809Sjmallett{ 366232809Sjmallett if (!( 367232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 368232809Sjmallett cvmx_warn("CVMX_ILK_RXX_STAT4(%lu) is invalid on this chip\n", offset); 369232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020040ull) + ((offset) & 1) * 16384; 370232809Sjmallett} 371232809Sjmallett#else 372232809Sjmallett#define CVMX_ILK_RXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x0001180014020040ull) + ((offset) & 1) * 16384) 373232809Sjmallett#endif 374232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 375232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_STAT5(unsigned long offset) 376232809Sjmallett{ 377232809Sjmallett if (!( 378232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 379232809Sjmallett cvmx_warn("CVMX_ILK_RXX_STAT5(%lu) is invalid on this chip\n", offset); 380232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020048ull) + ((offset) & 1) * 16384; 381232809Sjmallett} 382232809Sjmallett#else 383232809Sjmallett#define CVMX_ILK_RXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x0001180014020048ull) + ((offset) & 1) * 16384) 384232809Sjmallett#endif 385232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_STAT6(unsigned long offset) 387232809Sjmallett{ 388232809Sjmallett if (!( 389232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 390232809Sjmallett cvmx_warn("CVMX_ILK_RXX_STAT6(%lu) is invalid on this chip\n", offset); 391232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020050ull) + ((offset) & 1) * 16384; 392232809Sjmallett} 393232809Sjmallett#else 394232809Sjmallett#define CVMX_ILK_RXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x0001180014020050ull) + ((offset) & 1) * 16384) 395232809Sjmallett#endif 396232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 397232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_STAT7(unsigned long offset) 398232809Sjmallett{ 399232809Sjmallett if (!( 400232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 401232809Sjmallett cvmx_warn("CVMX_ILK_RXX_STAT7(%lu) is invalid on this chip\n", offset); 402232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020058ull) + ((offset) & 1) * 16384; 403232809Sjmallett} 404232809Sjmallett#else 405232809Sjmallett#define CVMX_ILK_RXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x0001180014020058ull) + ((offset) & 1) * 16384) 406232809Sjmallett#endif 407232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 408232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_STAT8(unsigned long offset) 409232809Sjmallett{ 410232809Sjmallett if (!( 411232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 412232809Sjmallett cvmx_warn("CVMX_ILK_RXX_STAT8(%lu) is invalid on this chip\n", offset); 413232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020060ull) + ((offset) & 1) * 16384; 414232809Sjmallett} 415232809Sjmallett#else 416232809Sjmallett#define CVMX_ILK_RXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x0001180014020060ull) + ((offset) & 1) * 16384) 417232809Sjmallett#endif 418232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 419232809Sjmallettstatic inline uint64_t CVMX_ILK_RXX_STAT9(unsigned long offset) 420232809Sjmallett{ 421232809Sjmallett if (!( 422232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 423232809Sjmallett cvmx_warn("CVMX_ILK_RXX_STAT9(%lu) is invalid on this chip\n", offset); 424232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014020068ull) + ((offset) & 1) * 16384; 425232809Sjmallett} 426232809Sjmallett#else 427232809Sjmallett#define CVMX_ILK_RXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x0001180014020068ull) + ((offset) & 1) * 16384) 428232809Sjmallett#endif 429232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_CFG(unsigned long offset) 431232809Sjmallett{ 432232809Sjmallett if (!( 433232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 434232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_CFG(%lu) is invalid on this chip\n", offset); 435232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038000ull) + ((offset) & 7) * 1024; 436232809Sjmallett} 437232809Sjmallett#else 438232809Sjmallett#define CVMX_ILK_RX_LNEX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180014038000ull) + ((offset) & 7) * 1024) 439232809Sjmallett#endif 440232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 441232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_INT(unsigned long offset) 442232809Sjmallett{ 443232809Sjmallett if (!( 444232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 445232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_INT(%lu) is invalid on this chip\n", offset); 446232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038008ull) + ((offset) & 7) * 1024; 447232809Sjmallett} 448232809Sjmallett#else 449232809Sjmallett#define CVMX_ILK_RX_LNEX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180014038008ull) + ((offset) & 7) * 1024) 450232809Sjmallett#endif 451232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 452232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_INT_EN(unsigned long offset) 453232809Sjmallett{ 454232809Sjmallett if (!( 455232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 456232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_INT_EN(%lu) is invalid on this chip\n", offset); 457232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038010ull) + ((offset) & 7) * 1024; 458232809Sjmallett} 459232809Sjmallett#else 460232809Sjmallett#define CVMX_ILK_RX_LNEX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x0001180014038010ull) + ((offset) & 7) * 1024) 461232809Sjmallett#endif 462232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 463232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_STAT0(unsigned long offset) 464232809Sjmallett{ 465232809Sjmallett if (!( 466232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 467232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_STAT0(%lu) is invalid on this chip\n", offset); 468232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038018ull) + ((offset) & 7) * 1024; 469232809Sjmallett} 470232809Sjmallett#else 471232809Sjmallett#define CVMX_ILK_RX_LNEX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014038018ull) + ((offset) & 7) * 1024) 472232809Sjmallett#endif 473232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 474232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_STAT1(unsigned long offset) 475232809Sjmallett{ 476232809Sjmallett if (!( 477232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 478232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_STAT1(%lu) is invalid on this chip\n", offset); 479232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038020ull) + ((offset) & 7) * 1024; 480232809Sjmallett} 481232809Sjmallett#else 482232809Sjmallett#define CVMX_ILK_RX_LNEX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014038020ull) + ((offset) & 7) * 1024) 483232809Sjmallett#endif 484232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 485232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_STAT2(unsigned long offset) 486232809Sjmallett{ 487232809Sjmallett if (!( 488232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 489232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_STAT2(%lu) is invalid on this chip\n", offset); 490232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038028ull) + ((offset) & 7) * 1024; 491232809Sjmallett} 492232809Sjmallett#else 493232809Sjmallett#define CVMX_ILK_RX_LNEX_STAT2(offset) (CVMX_ADD_IO_SEG(0x0001180014038028ull) + ((offset) & 7) * 1024) 494232809Sjmallett#endif 495232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 496232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_STAT3(unsigned long offset) 497232809Sjmallett{ 498232809Sjmallett if (!( 499232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 500232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_STAT3(%lu) is invalid on this chip\n", offset); 501232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038030ull) + ((offset) & 7) * 1024; 502232809Sjmallett} 503232809Sjmallett#else 504232809Sjmallett#define CVMX_ILK_RX_LNEX_STAT3(offset) (CVMX_ADD_IO_SEG(0x0001180014038030ull) + ((offset) & 7) * 1024) 505232809Sjmallett#endif 506232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 507232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_STAT4(unsigned long offset) 508232809Sjmallett{ 509232809Sjmallett if (!( 510232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 511232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_STAT4(%lu) is invalid on this chip\n", offset); 512232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038038ull) + ((offset) & 7) * 1024; 513232809Sjmallett} 514232809Sjmallett#else 515232809Sjmallett#define CVMX_ILK_RX_LNEX_STAT4(offset) (CVMX_ADD_IO_SEG(0x0001180014038038ull) + ((offset) & 7) * 1024) 516232809Sjmallett#endif 517232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 518232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_STAT5(unsigned long offset) 519232809Sjmallett{ 520232809Sjmallett if (!( 521232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 522232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_STAT5(%lu) is invalid on this chip\n", offset); 523232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038040ull) + ((offset) & 7) * 1024; 524232809Sjmallett} 525232809Sjmallett#else 526232809Sjmallett#define CVMX_ILK_RX_LNEX_STAT5(offset) (CVMX_ADD_IO_SEG(0x0001180014038040ull) + ((offset) & 7) * 1024) 527232809Sjmallett#endif 528232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 529232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_STAT6(unsigned long offset) 530232809Sjmallett{ 531232809Sjmallett if (!( 532232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 533232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_STAT6(%lu) is invalid on this chip\n", offset); 534232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038048ull) + ((offset) & 7) * 1024; 535232809Sjmallett} 536232809Sjmallett#else 537232809Sjmallett#define CVMX_ILK_RX_LNEX_STAT6(offset) (CVMX_ADD_IO_SEG(0x0001180014038048ull) + ((offset) & 7) * 1024) 538232809Sjmallett#endif 539232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 540232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_STAT7(unsigned long offset) 541232809Sjmallett{ 542232809Sjmallett if (!( 543232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 544232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_STAT7(%lu) is invalid on this chip\n", offset); 545232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038050ull) + ((offset) & 7) * 1024; 546232809Sjmallett} 547232809Sjmallett#else 548232809Sjmallett#define CVMX_ILK_RX_LNEX_STAT7(offset) (CVMX_ADD_IO_SEG(0x0001180014038050ull) + ((offset) & 7) * 1024) 549232809Sjmallett#endif 550232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_STAT8(unsigned long offset) 552232809Sjmallett{ 553232809Sjmallett if (!( 554232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 555232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_STAT8(%lu) is invalid on this chip\n", offset); 556232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038058ull) + ((offset) & 7) * 1024; 557232809Sjmallett} 558232809Sjmallett#else 559232809Sjmallett#define CVMX_ILK_RX_LNEX_STAT8(offset) (CVMX_ADD_IO_SEG(0x0001180014038058ull) + ((offset) & 7) * 1024) 560232809Sjmallett#endif 561232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 562232809Sjmallettstatic inline uint64_t CVMX_ILK_RX_LNEX_STAT9(unsigned long offset) 563232809Sjmallett{ 564232809Sjmallett if (!( 565232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))))) 566232809Sjmallett cvmx_warn("CVMX_ILK_RX_LNEX_STAT9(%lu) is invalid on this chip\n", offset); 567232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014038060ull) + ((offset) & 7) * 1024; 568232809Sjmallett} 569232809Sjmallett#else 570232809Sjmallett#define CVMX_ILK_RX_LNEX_STAT9(offset) (CVMX_ADD_IO_SEG(0x0001180014038060ull) + ((offset) & 7) * 1024) 571232809Sjmallett#endif 572232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 573232809Sjmallett#define CVMX_ILK_SER_CFG CVMX_ILK_SER_CFG_FUNC() 574232809Sjmallettstatic inline uint64_t CVMX_ILK_SER_CFG_FUNC(void) 575232809Sjmallett{ 576232809Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 577232809Sjmallett cvmx_warn("CVMX_ILK_SER_CFG not supported on this chip\n"); 578232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014000018ull); 579232809Sjmallett} 580232809Sjmallett#else 581232809Sjmallett#define CVMX_ILK_SER_CFG (CVMX_ADD_IO_SEG(0x0001180014000018ull)) 582232809Sjmallett#endif 583232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 584232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_CFG0(unsigned long offset) 585232809Sjmallett{ 586232809Sjmallett if (!( 587232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 588232809Sjmallett cvmx_warn("CVMX_ILK_TXX_CFG0(%lu) is invalid on this chip\n", offset); 589232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010000ull) + ((offset) & 1) * 16384; 590232809Sjmallett} 591232809Sjmallett#else 592232809Sjmallett#define CVMX_ILK_TXX_CFG0(offset) (CVMX_ADD_IO_SEG(0x0001180014010000ull) + ((offset) & 1) * 16384) 593232809Sjmallett#endif 594232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 595232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_CFG1(unsigned long offset) 596232809Sjmallett{ 597232809Sjmallett if (!( 598232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 599232809Sjmallett cvmx_warn("CVMX_ILK_TXX_CFG1(%lu) is invalid on this chip\n", offset); 600232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010008ull) + ((offset) & 1) * 16384; 601232809Sjmallett} 602232809Sjmallett#else 603232809Sjmallett#define CVMX_ILK_TXX_CFG1(offset) (CVMX_ADD_IO_SEG(0x0001180014010008ull) + ((offset) & 1) * 16384) 604232809Sjmallett#endif 605232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 606232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_DBG(unsigned long offset) 607232809Sjmallett{ 608232809Sjmallett if (!( 609232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 610232809Sjmallett cvmx_warn("CVMX_ILK_TXX_DBG(%lu) is invalid on this chip\n", offset); 611232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010070ull) + ((offset) & 1) * 16384; 612232809Sjmallett} 613232809Sjmallett#else 614232809Sjmallett#define CVMX_ILK_TXX_DBG(offset) (CVMX_ADD_IO_SEG(0x0001180014010070ull) + ((offset) & 1) * 16384) 615232809Sjmallett#endif 616232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_FLOW_CTL0(unsigned long offset) 618232809Sjmallett{ 619232809Sjmallett if (!( 620232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 621232809Sjmallett cvmx_warn("CVMX_ILK_TXX_FLOW_CTL0(%lu) is invalid on this chip\n", offset); 622232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010048ull) + ((offset) & 1) * 16384; 623232809Sjmallett} 624232809Sjmallett#else 625232809Sjmallett#define CVMX_ILK_TXX_FLOW_CTL0(offset) (CVMX_ADD_IO_SEG(0x0001180014010048ull) + ((offset) & 1) * 16384) 626232809Sjmallett#endif 627232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 628232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_FLOW_CTL1(unsigned long offset) 629232809Sjmallett{ 630232809Sjmallett if (!( 631232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 632232809Sjmallett cvmx_warn("CVMX_ILK_TXX_FLOW_CTL1(%lu) is invalid on this chip\n", offset); 633232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010050ull) + ((offset) & 1) * 16384; 634232809Sjmallett} 635232809Sjmallett#else 636232809Sjmallett#define CVMX_ILK_TXX_FLOW_CTL1(offset) (CVMX_ADD_IO_SEG(0x0001180014010050ull) + ((offset) & 1) * 16384) 637232809Sjmallett#endif 638232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 639232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_IDX_CAL(unsigned long offset) 640232809Sjmallett{ 641232809Sjmallett if (!( 642232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 643232809Sjmallett cvmx_warn("CVMX_ILK_TXX_IDX_CAL(%lu) is invalid on this chip\n", offset); 644232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010058ull) + ((offset) & 1) * 16384; 645232809Sjmallett} 646232809Sjmallett#else 647232809Sjmallett#define CVMX_ILK_TXX_IDX_CAL(offset) (CVMX_ADD_IO_SEG(0x0001180014010058ull) + ((offset) & 1) * 16384) 648232809Sjmallett#endif 649232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 650232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_IDX_PMAP(unsigned long offset) 651232809Sjmallett{ 652232809Sjmallett if (!( 653232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 654232809Sjmallett cvmx_warn("CVMX_ILK_TXX_IDX_PMAP(%lu) is invalid on this chip\n", offset); 655232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010010ull) + ((offset) & 1) * 16384; 656232809Sjmallett} 657232809Sjmallett#else 658232809Sjmallett#define CVMX_ILK_TXX_IDX_PMAP(offset) (CVMX_ADD_IO_SEG(0x0001180014010010ull) + ((offset) & 1) * 16384) 659232809Sjmallett#endif 660232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 661232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_IDX_STAT0(unsigned long offset) 662232809Sjmallett{ 663232809Sjmallett if (!( 664232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 665232809Sjmallett cvmx_warn("CVMX_ILK_TXX_IDX_STAT0(%lu) is invalid on this chip\n", offset); 666232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010020ull) + ((offset) & 1) * 16384; 667232809Sjmallett} 668232809Sjmallett#else 669232809Sjmallett#define CVMX_ILK_TXX_IDX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014010020ull) + ((offset) & 1) * 16384) 670232809Sjmallett#endif 671232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 672232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_IDX_STAT1(unsigned long offset) 673232809Sjmallett{ 674232809Sjmallett if (!( 675232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 676232809Sjmallett cvmx_warn("CVMX_ILK_TXX_IDX_STAT1(%lu) is invalid on this chip\n", offset); 677232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010028ull) + ((offset) & 1) * 16384; 678232809Sjmallett} 679232809Sjmallett#else 680232809Sjmallett#define CVMX_ILK_TXX_IDX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014010028ull) + ((offset) & 1) * 16384) 681232809Sjmallett#endif 682232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 683232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_INT(unsigned long offset) 684232809Sjmallett{ 685232809Sjmallett if (!( 686232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 687232809Sjmallett cvmx_warn("CVMX_ILK_TXX_INT(%lu) is invalid on this chip\n", offset); 688232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010078ull) + ((offset) & 1) * 16384; 689232809Sjmallett} 690232809Sjmallett#else 691232809Sjmallett#define CVMX_ILK_TXX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180014010078ull) + ((offset) & 1) * 16384) 692232809Sjmallett#endif 693232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 694232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_INT_EN(unsigned long offset) 695232809Sjmallett{ 696232809Sjmallett if (!( 697232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 698232809Sjmallett cvmx_warn("CVMX_ILK_TXX_INT_EN(%lu) is invalid on this chip\n", offset); 699232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010080ull) + ((offset) & 1) * 16384; 700232809Sjmallett} 701232809Sjmallett#else 702232809Sjmallett#define CVMX_ILK_TXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x0001180014010080ull) + ((offset) & 1) * 16384) 703232809Sjmallett#endif 704232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 705232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_MEM_CAL0(unsigned long offset) 706232809Sjmallett{ 707232809Sjmallett if (!( 708232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 709232809Sjmallett cvmx_warn("CVMX_ILK_TXX_MEM_CAL0(%lu) is invalid on this chip\n", offset); 710232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010060ull) + ((offset) & 1) * 16384; 711232809Sjmallett} 712232809Sjmallett#else 713232809Sjmallett#define CVMX_ILK_TXX_MEM_CAL0(offset) (CVMX_ADD_IO_SEG(0x0001180014010060ull) + ((offset) & 1) * 16384) 714232809Sjmallett#endif 715232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 716232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_MEM_CAL1(unsigned long offset) 717232809Sjmallett{ 718232809Sjmallett if (!( 719232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 720232809Sjmallett cvmx_warn("CVMX_ILK_TXX_MEM_CAL1(%lu) is invalid on this chip\n", offset); 721232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010068ull) + ((offset) & 1) * 16384; 722232809Sjmallett} 723232809Sjmallett#else 724232809Sjmallett#define CVMX_ILK_TXX_MEM_CAL1(offset) (CVMX_ADD_IO_SEG(0x0001180014010068ull) + ((offset) & 1) * 16384) 725232809Sjmallett#endif 726232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 727232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_MEM_PMAP(unsigned long offset) 728232809Sjmallett{ 729232809Sjmallett if (!( 730232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 731232809Sjmallett cvmx_warn("CVMX_ILK_TXX_MEM_PMAP(%lu) is invalid on this chip\n", offset); 732232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010018ull) + ((offset) & 1) * 16384; 733232809Sjmallett} 734232809Sjmallett#else 735232809Sjmallett#define CVMX_ILK_TXX_MEM_PMAP(offset) (CVMX_ADD_IO_SEG(0x0001180014010018ull) + ((offset) & 1) * 16384) 736232809Sjmallett#endif 737232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 738232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_MEM_STAT0(unsigned long offset) 739232809Sjmallett{ 740232809Sjmallett if (!( 741232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 742232809Sjmallett cvmx_warn("CVMX_ILK_TXX_MEM_STAT0(%lu) is invalid on this chip\n", offset); 743232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010030ull) + ((offset) & 1) * 16384; 744232809Sjmallett} 745232809Sjmallett#else 746232809Sjmallett#define CVMX_ILK_TXX_MEM_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014010030ull) + ((offset) & 1) * 16384) 747232809Sjmallett#endif 748232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 749232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_MEM_STAT1(unsigned long offset) 750232809Sjmallett{ 751232809Sjmallett if (!( 752232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 753232809Sjmallett cvmx_warn("CVMX_ILK_TXX_MEM_STAT1(%lu) is invalid on this chip\n", offset); 754232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010038ull) + ((offset) & 1) * 16384; 755232809Sjmallett} 756232809Sjmallett#else 757232809Sjmallett#define CVMX_ILK_TXX_MEM_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014010038ull) + ((offset) & 1) * 16384) 758232809Sjmallett#endif 759232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 760232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_PIPE(unsigned long offset) 761232809Sjmallett{ 762232809Sjmallett if (!( 763232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 764232809Sjmallett cvmx_warn("CVMX_ILK_TXX_PIPE(%lu) is invalid on this chip\n", offset); 765232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010088ull) + ((offset) & 1) * 16384; 766232809Sjmallett} 767232809Sjmallett#else 768232809Sjmallett#define CVMX_ILK_TXX_PIPE(offset) (CVMX_ADD_IO_SEG(0x0001180014010088ull) + ((offset) & 1) * 16384) 769232809Sjmallett#endif 770232809Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 771232809Sjmallettstatic inline uint64_t CVMX_ILK_TXX_RMATCH(unsigned long offset) 772232809Sjmallett{ 773232809Sjmallett if (!( 774232809Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))))) 775232809Sjmallett cvmx_warn("CVMX_ILK_TXX_RMATCH(%lu) is invalid on this chip\n", offset); 776232809Sjmallett return CVMX_ADD_IO_SEG(0x0001180014010040ull) + ((offset) & 1) * 16384; 777232809Sjmallett} 778232809Sjmallett#else 779232809Sjmallett#define CVMX_ILK_TXX_RMATCH(offset) (CVMX_ADD_IO_SEG(0x0001180014010040ull) + ((offset) & 1) * 16384) 780232809Sjmallett#endif 781232809Sjmallett 782232809Sjmallett/** 783232809Sjmallett * cvmx_ilk_bist_sum 784232809Sjmallett */ 785232809Sjmallettunion cvmx_ilk_bist_sum { 786232809Sjmallett uint64_t u64; 787232809Sjmallett struct cvmx_ilk_bist_sum_s { 788232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 789232809Sjmallett uint64_t reserved_58_63 : 6; 790232809Sjmallett uint64_t rxf_x2p1 : 1; /**< Bist status of rxf.x2p_fif_mem1 */ 791232809Sjmallett uint64_t rxf_x2p0 : 1; /**< Bist status of rxf.x2p_fif_mem0 */ 792232809Sjmallett uint64_t rxf_pmap : 1; /**< Bist status of rxf.rx_map_mem */ 793232809Sjmallett uint64_t rxf_mem2 : 1; /**< Bist status of rxf.rx_fif_mem2 */ 794232809Sjmallett uint64_t rxf_mem1 : 1; /**< Bist status of rxf.rx_fif_mem1 */ 795232809Sjmallett uint64_t rxf_mem0 : 1; /**< Bist status of rxf.rx_fif_mem0 */ 796232809Sjmallett uint64_t reserved_36_51 : 16; 797232809Sjmallett uint64_t rle7_dsk1 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem1 */ 798232809Sjmallett uint64_t rle7_dsk0 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem0 */ 799232809Sjmallett uint64_t rle6_dsk1 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem1 */ 800232809Sjmallett uint64_t rle6_dsk0 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem0 */ 801232809Sjmallett uint64_t rle5_dsk1 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem1 */ 802232809Sjmallett uint64_t rle5_dsk0 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem0 */ 803232809Sjmallett uint64_t rle4_dsk1 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem1 */ 804232809Sjmallett uint64_t rle4_dsk0 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem0 */ 805232809Sjmallett uint64_t rle3_dsk1 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem1 */ 806232809Sjmallett uint64_t rle3_dsk0 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem0 */ 807232809Sjmallett uint64_t rle2_dsk1 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem1 */ 808232809Sjmallett uint64_t rle2_dsk0 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem0 */ 809232809Sjmallett uint64_t rle1_dsk1 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem1 */ 810232809Sjmallett uint64_t rle1_dsk0 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem0 */ 811232809Sjmallett uint64_t rle0_dsk1 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem1 */ 812232809Sjmallett uint64_t rle0_dsk0 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem0 */ 813232809Sjmallett uint64_t reserved_19_19 : 1; 814232809Sjmallett uint64_t rlk1_stat1 : 1; /**< Bist status of rlk1.csr.stat_mem1 ***NOTE: Added in pass 2.0 */ 815232809Sjmallett uint64_t rlk1_fwc : 1; /**< Bist status of rlk1.fwc.cal_chan_ram */ 816232809Sjmallett uint64_t rlk1_stat : 1; /**< Bist status of rlk1.csr.stat_mem */ 817232809Sjmallett uint64_t reserved_15_15 : 1; 818232809Sjmallett uint64_t rlk0_stat1 : 1; /**< Bist status of rlk0.csr.stat_mem1 ***NOTE: Added in pass 2.0 */ 819232809Sjmallett uint64_t rlk0_fwc : 1; /**< Bist status of rlk0.fwc.cal_chan_ram */ 820232809Sjmallett uint64_t rlk0_stat : 1; /**< Bist status of rlk0.csr.stat_mem */ 821232809Sjmallett uint64_t tlk1_stat1 : 1; /**< Bist status of tlk1.csr.stat_mem1 */ 822232809Sjmallett uint64_t tlk1_fwc : 1; /**< Bist status of tlk1.fwc.cal_chan_ram */ 823232809Sjmallett uint64_t reserved_9_9 : 1; 824232809Sjmallett uint64_t tlk1_txf2 : 1; /**< Bist status of tlk1.txf.tx_map_mem */ 825232809Sjmallett uint64_t tlk1_txf1 : 1; /**< Bist status of tlk1.txf.tx_fif_mem1 */ 826232809Sjmallett uint64_t tlk1_txf0 : 1; /**< Bist status of tlk1.txf.tx_fif_mem0 */ 827232809Sjmallett uint64_t tlk0_stat1 : 1; /**< Bist status of tlk0.csr.stat_mem1 */ 828232809Sjmallett uint64_t tlk0_fwc : 1; /**< Bist status of tlk0.fwc.cal_chan_ram */ 829232809Sjmallett uint64_t reserved_3_3 : 1; 830232809Sjmallett uint64_t tlk0_txf2 : 1; /**< Bist status of tlk0.txf.tx_map_mem */ 831232809Sjmallett uint64_t tlk0_txf1 : 1; /**< Bist status of tlk0.txf.tx_fif_mem1 */ 832232809Sjmallett uint64_t tlk0_txf0 : 1; /**< Bist status of tlk0.txf.tx_fif_mem0 */ 833232809Sjmallett#else 834232809Sjmallett uint64_t tlk0_txf0 : 1; 835232809Sjmallett uint64_t tlk0_txf1 : 1; 836232809Sjmallett uint64_t tlk0_txf2 : 1; 837232809Sjmallett uint64_t reserved_3_3 : 1; 838232809Sjmallett uint64_t tlk0_fwc : 1; 839232809Sjmallett uint64_t tlk0_stat1 : 1; 840232809Sjmallett uint64_t tlk1_txf0 : 1; 841232809Sjmallett uint64_t tlk1_txf1 : 1; 842232809Sjmallett uint64_t tlk1_txf2 : 1; 843232809Sjmallett uint64_t reserved_9_9 : 1; 844232809Sjmallett uint64_t tlk1_fwc : 1; 845232809Sjmallett uint64_t tlk1_stat1 : 1; 846232809Sjmallett uint64_t rlk0_stat : 1; 847232809Sjmallett uint64_t rlk0_fwc : 1; 848232809Sjmallett uint64_t rlk0_stat1 : 1; 849232809Sjmallett uint64_t reserved_15_15 : 1; 850232809Sjmallett uint64_t rlk1_stat : 1; 851232809Sjmallett uint64_t rlk1_fwc : 1; 852232809Sjmallett uint64_t rlk1_stat1 : 1; 853232809Sjmallett uint64_t reserved_19_19 : 1; 854232809Sjmallett uint64_t rle0_dsk0 : 1; 855232809Sjmallett uint64_t rle0_dsk1 : 1; 856232809Sjmallett uint64_t rle1_dsk0 : 1; 857232809Sjmallett uint64_t rle1_dsk1 : 1; 858232809Sjmallett uint64_t rle2_dsk0 : 1; 859232809Sjmallett uint64_t rle2_dsk1 : 1; 860232809Sjmallett uint64_t rle3_dsk0 : 1; 861232809Sjmallett uint64_t rle3_dsk1 : 1; 862232809Sjmallett uint64_t rle4_dsk0 : 1; 863232809Sjmallett uint64_t rle4_dsk1 : 1; 864232809Sjmallett uint64_t rle5_dsk0 : 1; 865232809Sjmallett uint64_t rle5_dsk1 : 1; 866232809Sjmallett uint64_t rle6_dsk0 : 1; 867232809Sjmallett uint64_t rle6_dsk1 : 1; 868232809Sjmallett uint64_t rle7_dsk0 : 1; 869232809Sjmallett uint64_t rle7_dsk1 : 1; 870232809Sjmallett uint64_t reserved_36_51 : 16; 871232809Sjmallett uint64_t rxf_mem0 : 1; 872232809Sjmallett uint64_t rxf_mem1 : 1; 873232809Sjmallett uint64_t rxf_mem2 : 1; 874232809Sjmallett uint64_t rxf_pmap : 1; 875232809Sjmallett uint64_t rxf_x2p0 : 1; 876232809Sjmallett uint64_t rxf_x2p1 : 1; 877232809Sjmallett uint64_t reserved_58_63 : 6; 878232809Sjmallett#endif 879232809Sjmallett } s; 880232809Sjmallett struct cvmx_ilk_bist_sum_cn68xx { 881232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 882232809Sjmallett uint64_t reserved_58_63 : 6; 883232809Sjmallett uint64_t rxf_x2p1 : 1; /**< Bist status of rxf.x2p_fif_mem1 */ 884232809Sjmallett uint64_t rxf_x2p0 : 1; /**< Bist status of rxf.x2p_fif_mem0 */ 885232809Sjmallett uint64_t rxf_pmap : 1; /**< Bist status of rxf.rx_map_mem */ 886232809Sjmallett uint64_t rxf_mem2 : 1; /**< Bist status of rxf.rx_fif_mem2 */ 887232809Sjmallett uint64_t rxf_mem1 : 1; /**< Bist status of rxf.rx_fif_mem1 */ 888232809Sjmallett uint64_t rxf_mem0 : 1; /**< Bist status of rxf.rx_fif_mem0 */ 889232809Sjmallett uint64_t reserved_36_51 : 16; 890232809Sjmallett uint64_t rle7_dsk1 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem1 */ 891232809Sjmallett uint64_t rle7_dsk0 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem0 */ 892232809Sjmallett uint64_t rle6_dsk1 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem1 */ 893232809Sjmallett uint64_t rle6_dsk0 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem0 */ 894232809Sjmallett uint64_t rle5_dsk1 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem1 */ 895232809Sjmallett uint64_t rle5_dsk0 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem0 */ 896232809Sjmallett uint64_t rle4_dsk1 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem1 */ 897232809Sjmallett uint64_t rle4_dsk0 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem0 */ 898232809Sjmallett uint64_t rle3_dsk1 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem1 */ 899232809Sjmallett uint64_t rle3_dsk0 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem0 */ 900232809Sjmallett uint64_t rle2_dsk1 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem1 */ 901232809Sjmallett uint64_t rle2_dsk0 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem0 */ 902232809Sjmallett uint64_t rle1_dsk1 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem1 */ 903232809Sjmallett uint64_t rle1_dsk0 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem0 */ 904232809Sjmallett uint64_t rle0_dsk1 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem1 */ 905232809Sjmallett uint64_t rle0_dsk0 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem0 */ 906232809Sjmallett uint64_t reserved_19_19 : 1; 907232809Sjmallett uint64_t rlk1_stat1 : 1; /**< Bist status of rlk1.csr.stat_mem1 ***NOTE: Added in pass 2.0 */ 908232809Sjmallett uint64_t rlk1_fwc : 1; /**< Bist status of rlk1.fwc.cal_chan_ram */ 909232809Sjmallett uint64_t rlk1_stat : 1; /**< Bist status of rlk1.csr.stat_mem0 */ 910232809Sjmallett uint64_t reserved_15_15 : 1; 911232809Sjmallett uint64_t rlk0_stat1 : 1; /**< Bist status of rlk0.csr.stat_mem1 ***NOTE: Added in pass 2.0 */ 912232809Sjmallett uint64_t rlk0_fwc : 1; /**< Bist status of rlk0.fwc.cal_chan_ram */ 913232809Sjmallett uint64_t rlk0_stat : 1; /**< Bist status of rlk0.csr.stat_mem0 */ 914232809Sjmallett uint64_t tlk1_stat1 : 1; /**< Bist status of tlk1.csr.stat_mem1 */ 915232809Sjmallett uint64_t tlk1_fwc : 1; /**< Bist status of tlk1.fwc.cal_chan_ram */ 916232809Sjmallett uint64_t tlk1_stat0 : 1; /**< Bist status of tlk1.csr.stat_mem0 */ 917232809Sjmallett uint64_t tlk1_txf2 : 1; /**< Bist status of tlk1.txf.tx_map_mem */ 918232809Sjmallett uint64_t tlk1_txf1 : 1; /**< Bist status of tlk1.txf.tx_fif_mem1 */ 919232809Sjmallett uint64_t tlk1_txf0 : 1; /**< Bist status of tlk1.txf.tx_fif_mem0 */ 920232809Sjmallett uint64_t tlk0_stat1 : 1; /**< Bist status of tlk0.csr.stat_mem1 */ 921232809Sjmallett uint64_t tlk0_fwc : 1; /**< Bist status of tlk0.fwc.cal_chan_ram */ 922232809Sjmallett uint64_t tlk0_stat0 : 1; /**< Bist status of tlk0.csr.stat_mem0 */ 923232809Sjmallett uint64_t tlk0_txf2 : 1; /**< Bist status of tlk0.txf.tx_map_mem */ 924232809Sjmallett uint64_t tlk0_txf1 : 1; /**< Bist status of tlk0.txf.tx_fif_mem1 */ 925232809Sjmallett uint64_t tlk0_txf0 : 1; /**< Bist status of tlk0.txf.tx_fif_mem0 */ 926232809Sjmallett#else 927232809Sjmallett uint64_t tlk0_txf0 : 1; 928232809Sjmallett uint64_t tlk0_txf1 : 1; 929232809Sjmallett uint64_t tlk0_txf2 : 1; 930232809Sjmallett uint64_t tlk0_stat0 : 1; 931232809Sjmallett uint64_t tlk0_fwc : 1; 932232809Sjmallett uint64_t tlk0_stat1 : 1; 933232809Sjmallett uint64_t tlk1_txf0 : 1; 934232809Sjmallett uint64_t tlk1_txf1 : 1; 935232809Sjmallett uint64_t tlk1_txf2 : 1; 936232809Sjmallett uint64_t tlk1_stat0 : 1; 937232809Sjmallett uint64_t tlk1_fwc : 1; 938232809Sjmallett uint64_t tlk1_stat1 : 1; 939232809Sjmallett uint64_t rlk0_stat : 1; 940232809Sjmallett uint64_t rlk0_fwc : 1; 941232809Sjmallett uint64_t rlk0_stat1 : 1; 942232809Sjmallett uint64_t reserved_15_15 : 1; 943232809Sjmallett uint64_t rlk1_stat : 1; 944232809Sjmallett uint64_t rlk1_fwc : 1; 945232809Sjmallett uint64_t rlk1_stat1 : 1; 946232809Sjmallett uint64_t reserved_19_19 : 1; 947232809Sjmallett uint64_t rle0_dsk0 : 1; 948232809Sjmallett uint64_t rle0_dsk1 : 1; 949232809Sjmallett uint64_t rle1_dsk0 : 1; 950232809Sjmallett uint64_t rle1_dsk1 : 1; 951232809Sjmallett uint64_t rle2_dsk0 : 1; 952232809Sjmallett uint64_t rle2_dsk1 : 1; 953232809Sjmallett uint64_t rle3_dsk0 : 1; 954232809Sjmallett uint64_t rle3_dsk1 : 1; 955232809Sjmallett uint64_t rle4_dsk0 : 1; 956232809Sjmallett uint64_t rle4_dsk1 : 1; 957232809Sjmallett uint64_t rle5_dsk0 : 1; 958232809Sjmallett uint64_t rle5_dsk1 : 1; 959232809Sjmallett uint64_t rle6_dsk0 : 1; 960232809Sjmallett uint64_t rle6_dsk1 : 1; 961232809Sjmallett uint64_t rle7_dsk0 : 1; 962232809Sjmallett uint64_t rle7_dsk1 : 1; 963232809Sjmallett uint64_t reserved_36_51 : 16; 964232809Sjmallett uint64_t rxf_mem0 : 1; 965232809Sjmallett uint64_t rxf_mem1 : 1; 966232809Sjmallett uint64_t rxf_mem2 : 1; 967232809Sjmallett uint64_t rxf_pmap : 1; 968232809Sjmallett uint64_t rxf_x2p0 : 1; 969232809Sjmallett uint64_t rxf_x2p1 : 1; 970232809Sjmallett uint64_t reserved_58_63 : 6; 971232809Sjmallett#endif 972232809Sjmallett } cn68xx; 973232809Sjmallett struct cvmx_ilk_bist_sum_cn68xxp1 { 974232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 975232809Sjmallett uint64_t reserved_58_63 : 6; 976232809Sjmallett uint64_t rxf_x2p1 : 1; /**< Bist status of rxf.x2p_fif_mem1 */ 977232809Sjmallett uint64_t rxf_x2p0 : 1; /**< Bist status of rxf.x2p_fif_mem0 */ 978232809Sjmallett uint64_t rxf_pmap : 1; /**< Bist status of rxf.rx_map_mem */ 979232809Sjmallett uint64_t rxf_mem2 : 1; /**< Bist status of rxf.rx_fif_mem2 */ 980232809Sjmallett uint64_t rxf_mem1 : 1; /**< Bist status of rxf.rx_fif_mem1 */ 981232809Sjmallett uint64_t rxf_mem0 : 1; /**< Bist status of rxf.rx_fif_mem0 */ 982232809Sjmallett uint64_t reserved_36_51 : 16; 983232809Sjmallett uint64_t rle7_dsk1 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem1 */ 984232809Sjmallett uint64_t rle7_dsk0 : 1; /**< Bist status of lne.rle7.dsk.dsk_fif_mem0 */ 985232809Sjmallett uint64_t rle6_dsk1 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem1 */ 986232809Sjmallett uint64_t rle6_dsk0 : 1; /**< Bist status of lne.rle6.dsk.dsk_fif_mem0 */ 987232809Sjmallett uint64_t rle5_dsk1 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem1 */ 988232809Sjmallett uint64_t rle5_dsk0 : 1; /**< Bist status of lne.rle5.dsk.dsk_fif_mem0 */ 989232809Sjmallett uint64_t rle4_dsk1 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem1 */ 990232809Sjmallett uint64_t rle4_dsk0 : 1; /**< Bist status of lne.rle4.dsk.dsk_fif_mem0 */ 991232809Sjmallett uint64_t rle3_dsk1 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem1 */ 992232809Sjmallett uint64_t rle3_dsk0 : 1; /**< Bist status of lne.rle3.dsk.dsk_fif_mem0 */ 993232809Sjmallett uint64_t rle2_dsk1 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem1 */ 994232809Sjmallett uint64_t rle2_dsk0 : 1; /**< Bist status of lne.rle2.dsk.dsk_fif_mem0 */ 995232809Sjmallett uint64_t rle1_dsk1 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem1 */ 996232809Sjmallett uint64_t rle1_dsk0 : 1; /**< Bist status of lne.rle1.dsk.dsk_fif_mem0 */ 997232809Sjmallett uint64_t rle0_dsk1 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem1 */ 998232809Sjmallett uint64_t rle0_dsk0 : 1; /**< Bist status of lne.rle0.dsk.dsk_fif_mem0 */ 999232809Sjmallett uint64_t reserved_18_19 : 2; 1000232809Sjmallett uint64_t rlk1_fwc : 1; /**< Bist status of rlk1.fwc.cal_chan_ram */ 1001232809Sjmallett uint64_t rlk1_stat : 1; /**< Bist status of rlk1.csr.stat_mem */ 1002232809Sjmallett uint64_t reserved_14_15 : 2; 1003232809Sjmallett uint64_t rlk0_fwc : 1; /**< Bist status of rlk0.fwc.cal_chan_ram */ 1004232809Sjmallett uint64_t rlk0_stat : 1; /**< Bist status of rlk0.csr.stat_mem */ 1005232809Sjmallett uint64_t reserved_11_11 : 1; 1006232809Sjmallett uint64_t tlk1_fwc : 1; /**< Bist status of tlk1.fwc.cal_chan_ram */ 1007232809Sjmallett uint64_t tlk1_stat : 1; /**< Bist status of tlk1.csr.stat_mem */ 1008232809Sjmallett uint64_t tlk1_txf2 : 1; /**< Bist status of tlk1.txf.tx_map_mem */ 1009232809Sjmallett uint64_t tlk1_txf1 : 1; /**< Bist status of tlk1.txf.tx_fif_mem1 */ 1010232809Sjmallett uint64_t tlk1_txf0 : 1; /**< Bist status of tlk1.txf.tx_fif_mem0 */ 1011232809Sjmallett uint64_t reserved_5_5 : 1; 1012232809Sjmallett uint64_t tlk0_fwc : 1; /**< Bist status of tlk0.fwc.cal_chan_ram */ 1013232809Sjmallett uint64_t tlk0_stat : 1; /**< Bist status of tlk0.csr.stat_mem */ 1014232809Sjmallett uint64_t tlk0_txf2 : 1; /**< Bist status of tlk0.txf.tx_map_mem */ 1015232809Sjmallett uint64_t tlk0_txf1 : 1; /**< Bist status of tlk0.txf.tx_fif_mem1 */ 1016232809Sjmallett uint64_t tlk0_txf0 : 1; /**< Bist status of tlk0.txf.tx_fif_mem0 */ 1017232809Sjmallett#else 1018232809Sjmallett uint64_t tlk0_txf0 : 1; 1019232809Sjmallett uint64_t tlk0_txf1 : 1; 1020232809Sjmallett uint64_t tlk0_txf2 : 1; 1021232809Sjmallett uint64_t tlk0_stat : 1; 1022232809Sjmallett uint64_t tlk0_fwc : 1; 1023232809Sjmallett uint64_t reserved_5_5 : 1; 1024232809Sjmallett uint64_t tlk1_txf0 : 1; 1025232809Sjmallett uint64_t tlk1_txf1 : 1; 1026232809Sjmallett uint64_t tlk1_txf2 : 1; 1027232809Sjmallett uint64_t tlk1_stat : 1; 1028232809Sjmallett uint64_t tlk1_fwc : 1; 1029232809Sjmallett uint64_t reserved_11_11 : 1; 1030232809Sjmallett uint64_t rlk0_stat : 1; 1031232809Sjmallett uint64_t rlk0_fwc : 1; 1032232809Sjmallett uint64_t reserved_14_15 : 2; 1033232809Sjmallett uint64_t rlk1_stat : 1; 1034232809Sjmallett uint64_t rlk1_fwc : 1; 1035232809Sjmallett uint64_t reserved_18_19 : 2; 1036232809Sjmallett uint64_t rle0_dsk0 : 1; 1037232809Sjmallett uint64_t rle0_dsk1 : 1; 1038232809Sjmallett uint64_t rle1_dsk0 : 1; 1039232809Sjmallett uint64_t rle1_dsk1 : 1; 1040232809Sjmallett uint64_t rle2_dsk0 : 1; 1041232809Sjmallett uint64_t rle2_dsk1 : 1; 1042232809Sjmallett uint64_t rle3_dsk0 : 1; 1043232809Sjmallett uint64_t rle3_dsk1 : 1; 1044232809Sjmallett uint64_t rle4_dsk0 : 1; 1045232809Sjmallett uint64_t rle4_dsk1 : 1; 1046232809Sjmallett uint64_t rle5_dsk0 : 1; 1047232809Sjmallett uint64_t rle5_dsk1 : 1; 1048232809Sjmallett uint64_t rle6_dsk0 : 1; 1049232809Sjmallett uint64_t rle6_dsk1 : 1; 1050232809Sjmallett uint64_t rle7_dsk0 : 1; 1051232809Sjmallett uint64_t rle7_dsk1 : 1; 1052232809Sjmallett uint64_t reserved_36_51 : 16; 1053232809Sjmallett uint64_t rxf_mem0 : 1; 1054232809Sjmallett uint64_t rxf_mem1 : 1; 1055232809Sjmallett uint64_t rxf_mem2 : 1; 1056232809Sjmallett uint64_t rxf_pmap : 1; 1057232809Sjmallett uint64_t rxf_x2p0 : 1; 1058232809Sjmallett uint64_t rxf_x2p1 : 1; 1059232809Sjmallett uint64_t reserved_58_63 : 6; 1060232809Sjmallett#endif 1061232809Sjmallett } cn68xxp1; 1062232809Sjmallett}; 1063232809Sjmalletttypedef union cvmx_ilk_bist_sum cvmx_ilk_bist_sum_t; 1064232809Sjmallett 1065232809Sjmallett/** 1066232809Sjmallett * cvmx_ilk_gbl_cfg 1067232809Sjmallett */ 1068232809Sjmallettunion cvmx_ilk_gbl_cfg { 1069232809Sjmallett uint64_t u64; 1070232809Sjmallett struct cvmx_ilk_gbl_cfg_s { 1071232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1072232809Sjmallett uint64_t reserved_4_63 : 60; 1073232809Sjmallett uint64_t rid_rstdis : 1; /**< Disable automatic reassembly-id error recovery. For diagnostic 1074232809Sjmallett use only. 1075232809Sjmallett 1076232809Sjmallett ***NOTE: Added in pass 2.0 */ 1077232809Sjmallett uint64_t reset : 1; /**< Reset ILK. For diagnostic use only. 1078232809Sjmallett 1079232809Sjmallett ***NOTE: Added in pass 2.0 */ 1080232809Sjmallett uint64_t cclk_dis : 1; /**< Disable ILK conditional clocking. For diagnostic use only. */ 1081232809Sjmallett uint64_t rxf_xlink : 1; /**< Causes external loopback traffic to switch links. Enabling 1082232809Sjmallett this allow simultaneous use of external and internal loopback. */ 1083232809Sjmallett#else 1084232809Sjmallett uint64_t rxf_xlink : 1; 1085232809Sjmallett uint64_t cclk_dis : 1; 1086232809Sjmallett uint64_t reset : 1; 1087232809Sjmallett uint64_t rid_rstdis : 1; 1088232809Sjmallett uint64_t reserved_4_63 : 60; 1089232809Sjmallett#endif 1090232809Sjmallett } s; 1091232809Sjmallett struct cvmx_ilk_gbl_cfg_s cn68xx; 1092232809Sjmallett struct cvmx_ilk_gbl_cfg_cn68xxp1 { 1093232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1094232809Sjmallett uint64_t reserved_2_63 : 62; 1095232809Sjmallett uint64_t cclk_dis : 1; /**< Disable ILK conditional clocking. For diagnostic use only. */ 1096232809Sjmallett uint64_t rxf_xlink : 1; /**< Causes external loopback traffic to switch links. Enabling 1097232809Sjmallett this allow simultaneous use of external and internal loopback. */ 1098232809Sjmallett#else 1099232809Sjmallett uint64_t rxf_xlink : 1; 1100232809Sjmallett uint64_t cclk_dis : 1; 1101232809Sjmallett uint64_t reserved_2_63 : 62; 1102232809Sjmallett#endif 1103232809Sjmallett } cn68xxp1; 1104232809Sjmallett}; 1105232809Sjmalletttypedef union cvmx_ilk_gbl_cfg cvmx_ilk_gbl_cfg_t; 1106232809Sjmallett 1107232809Sjmallett/** 1108232809Sjmallett * cvmx_ilk_gbl_int 1109232809Sjmallett */ 1110232809Sjmallettunion cvmx_ilk_gbl_int { 1111232809Sjmallett uint64_t u64; 1112232809Sjmallett struct cvmx_ilk_gbl_int_s { 1113232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1114232809Sjmallett uint64_t reserved_5_63 : 59; 1115232809Sjmallett uint64_t rxf_push_full : 1; /**< RXF overflow */ 1116232809Sjmallett uint64_t rxf_pop_empty : 1; /**< RXF underflow */ 1117232809Sjmallett uint64_t rxf_ctl_perr : 1; /**< RXF parity error occurred on sideband control signals. Data 1118232809Sjmallett cycle will be dropped. */ 1119232809Sjmallett uint64_t rxf_lnk1_perr : 1; /**< RXF parity error occurred on RxLink1 packet data 1120232809Sjmallett Packet will be marked with error at eop */ 1121232809Sjmallett uint64_t rxf_lnk0_perr : 1; /**< RXF parity error occurred on RxLink0 packet data. Packet will 1122232809Sjmallett be marked with error at eop */ 1123232809Sjmallett#else 1124232809Sjmallett uint64_t rxf_lnk0_perr : 1; 1125232809Sjmallett uint64_t rxf_lnk1_perr : 1; 1126232809Sjmallett uint64_t rxf_ctl_perr : 1; 1127232809Sjmallett uint64_t rxf_pop_empty : 1; 1128232809Sjmallett uint64_t rxf_push_full : 1; 1129232809Sjmallett uint64_t reserved_5_63 : 59; 1130232809Sjmallett#endif 1131232809Sjmallett } s; 1132232809Sjmallett struct cvmx_ilk_gbl_int_s cn68xx; 1133232809Sjmallett struct cvmx_ilk_gbl_int_s cn68xxp1; 1134232809Sjmallett}; 1135232809Sjmalletttypedef union cvmx_ilk_gbl_int cvmx_ilk_gbl_int_t; 1136232809Sjmallett 1137232809Sjmallett/** 1138232809Sjmallett * cvmx_ilk_gbl_int_en 1139232809Sjmallett */ 1140232809Sjmallettunion cvmx_ilk_gbl_int_en { 1141232809Sjmallett uint64_t u64; 1142232809Sjmallett struct cvmx_ilk_gbl_int_en_s { 1143232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1144232809Sjmallett uint64_t reserved_5_63 : 59; 1145232809Sjmallett uint64_t rxf_push_full : 1; /**< RXF overflow */ 1146232809Sjmallett uint64_t rxf_pop_empty : 1; /**< RXF underflow */ 1147232809Sjmallett uint64_t rxf_ctl_perr : 1; /**< RXF parity error occurred on sideband control signals. Data 1148232809Sjmallett cycle will be dropped. */ 1149232809Sjmallett uint64_t rxf_lnk1_perr : 1; /**< RXF parity error occurred on RxLink1 packet data 1150232809Sjmallett Packet will be marked with error at eop */ 1151232809Sjmallett uint64_t rxf_lnk0_perr : 1; /**< RXF parity error occurred on RxLink0 packet data 1152232809Sjmallett Packet will be marked with error at eop */ 1153232809Sjmallett#else 1154232809Sjmallett uint64_t rxf_lnk0_perr : 1; 1155232809Sjmallett uint64_t rxf_lnk1_perr : 1; 1156232809Sjmallett uint64_t rxf_ctl_perr : 1; 1157232809Sjmallett uint64_t rxf_pop_empty : 1; 1158232809Sjmallett uint64_t rxf_push_full : 1; 1159232809Sjmallett uint64_t reserved_5_63 : 59; 1160232809Sjmallett#endif 1161232809Sjmallett } s; 1162232809Sjmallett struct cvmx_ilk_gbl_int_en_s cn68xx; 1163232809Sjmallett struct cvmx_ilk_gbl_int_en_s cn68xxp1; 1164232809Sjmallett}; 1165232809Sjmalletttypedef union cvmx_ilk_gbl_int_en cvmx_ilk_gbl_int_en_t; 1166232809Sjmallett 1167232809Sjmallett/** 1168232809Sjmallett * cvmx_ilk_int_sum 1169232809Sjmallett */ 1170232809Sjmallettunion cvmx_ilk_int_sum { 1171232809Sjmallett uint64_t u64; 1172232809Sjmallett struct cvmx_ilk_int_sum_s { 1173232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1174232809Sjmallett uint64_t reserved_13_63 : 51; 1175232809Sjmallett uint64_t rle7_int : 1; /**< RxLane7 interrupt status. See ILK_RX_LNE7_INT */ 1176232809Sjmallett uint64_t rle6_int : 1; /**< RxLane6 interrupt status. See ILK_RX_LNE6_INT */ 1177232809Sjmallett uint64_t rle5_int : 1; /**< RxLane5 interrupt status. See ILK_RX_LNE5_INT */ 1178232809Sjmallett uint64_t rle4_int : 1; /**< RxLane4 interrupt status. See ILK_RX_LNE4_INT */ 1179232809Sjmallett uint64_t rle3_int : 1; /**< RxLane3 interrupt status. See ILK_RX_LNE3_INT */ 1180232809Sjmallett uint64_t rle2_int : 1; /**< RxLane2 interrupt status. See ILK_RX_LNE2_INT */ 1181232809Sjmallett uint64_t rle1_int : 1; /**< RxLane1 interrupt status. See ILK_RX_LNE1_INT */ 1182232809Sjmallett uint64_t rle0_int : 1; /**< RxLane0 interrupt status. See ILK_RX_LNE0_INT */ 1183232809Sjmallett uint64_t rlk1_int : 1; /**< RxLink1 interrupt status. See ILK_RX1_INT */ 1184232809Sjmallett uint64_t rlk0_int : 1; /**< RxLink0 interrupt status. See ILK_RX0_INT */ 1185232809Sjmallett uint64_t tlk1_int : 1; /**< TxLink1 interrupt status. See ILK_TX1_INT */ 1186232809Sjmallett uint64_t tlk0_int : 1; /**< TxLink0 interrupt status. See ILK_TX0_INT */ 1187232809Sjmallett uint64_t gbl_int : 1; /**< Global interrupt status. See ILK_GBL_INT */ 1188232809Sjmallett#else 1189232809Sjmallett uint64_t gbl_int : 1; 1190232809Sjmallett uint64_t tlk0_int : 1; 1191232809Sjmallett uint64_t tlk1_int : 1; 1192232809Sjmallett uint64_t rlk0_int : 1; 1193232809Sjmallett uint64_t rlk1_int : 1; 1194232809Sjmallett uint64_t rle0_int : 1; 1195232809Sjmallett uint64_t rle1_int : 1; 1196232809Sjmallett uint64_t rle2_int : 1; 1197232809Sjmallett uint64_t rle3_int : 1; 1198232809Sjmallett uint64_t rle4_int : 1; 1199232809Sjmallett uint64_t rle5_int : 1; 1200232809Sjmallett uint64_t rle6_int : 1; 1201232809Sjmallett uint64_t rle7_int : 1; 1202232809Sjmallett uint64_t reserved_13_63 : 51; 1203232809Sjmallett#endif 1204232809Sjmallett } s; 1205232809Sjmallett struct cvmx_ilk_int_sum_s cn68xx; 1206232809Sjmallett struct cvmx_ilk_int_sum_s cn68xxp1; 1207232809Sjmallett}; 1208232809Sjmalletttypedef union cvmx_ilk_int_sum cvmx_ilk_int_sum_t; 1209232809Sjmallett 1210232809Sjmallett/** 1211232809Sjmallett * cvmx_ilk_lne_dbg 1212232809Sjmallett */ 1213232809Sjmallettunion cvmx_ilk_lne_dbg { 1214232809Sjmallett uint64_t u64; 1215232809Sjmallett struct cvmx_ilk_lne_dbg_s { 1216232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1217232809Sjmallett uint64_t reserved_60_63 : 4; 1218232809Sjmallett uint64_t tx_bad_crc32 : 1; /**< Send 1 diagnostic word with bad CRC32 to the selected lane. 1219232809Sjmallett Note: injects just once */ 1220232809Sjmallett uint64_t tx_bad_6467_cnt : 5; /**< Send N bad 64B/67B codewords on selected lane */ 1221232809Sjmallett uint64_t tx_bad_sync_cnt : 3; /**< Send N bad sync words on selected lane */ 1222232809Sjmallett uint64_t tx_bad_scram_cnt : 3; /**< Send N bad scram state on selected lane */ 1223232809Sjmallett uint64_t reserved_40_47 : 8; 1224232809Sjmallett uint64_t tx_bad_lane_sel : 8; /**< Select lane to apply error injection counts */ 1225232809Sjmallett uint64_t reserved_24_31 : 8; 1226232809Sjmallett uint64_t tx_dis_dispr : 8; /**< Per-lane disparity disable */ 1227232809Sjmallett uint64_t reserved_8_15 : 8; 1228232809Sjmallett uint64_t tx_dis_scram : 8; /**< Per-lane scrambler disable */ 1229232809Sjmallett#else 1230232809Sjmallett uint64_t tx_dis_scram : 8; 1231232809Sjmallett uint64_t reserved_8_15 : 8; 1232232809Sjmallett uint64_t tx_dis_dispr : 8; 1233232809Sjmallett uint64_t reserved_24_31 : 8; 1234232809Sjmallett uint64_t tx_bad_lane_sel : 8; 1235232809Sjmallett uint64_t reserved_40_47 : 8; 1236232809Sjmallett uint64_t tx_bad_scram_cnt : 3; 1237232809Sjmallett uint64_t tx_bad_sync_cnt : 3; 1238232809Sjmallett uint64_t tx_bad_6467_cnt : 5; 1239232809Sjmallett uint64_t tx_bad_crc32 : 1; 1240232809Sjmallett uint64_t reserved_60_63 : 4; 1241232809Sjmallett#endif 1242232809Sjmallett } s; 1243232809Sjmallett struct cvmx_ilk_lne_dbg_s cn68xx; 1244232809Sjmallett struct cvmx_ilk_lne_dbg_s cn68xxp1; 1245232809Sjmallett}; 1246232809Sjmalletttypedef union cvmx_ilk_lne_dbg cvmx_ilk_lne_dbg_t; 1247232809Sjmallett 1248232809Sjmallett/** 1249232809Sjmallett * cvmx_ilk_lne_sts_msg 1250232809Sjmallett */ 1251232809Sjmallettunion cvmx_ilk_lne_sts_msg { 1252232809Sjmallett uint64_t u64; 1253232809Sjmallett struct cvmx_ilk_lne_sts_msg_s { 1254232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1255232809Sjmallett uint64_t reserved_56_63 : 8; 1256232809Sjmallett uint64_t rx_lnk_stat : 8; /**< Link status received in the diagnostic word (per-lane) */ 1257232809Sjmallett uint64_t reserved_40_47 : 8; 1258232809Sjmallett uint64_t rx_lne_stat : 8; /**< Lane status received in the diagnostic word (per-lane) */ 1259232809Sjmallett uint64_t reserved_24_31 : 8; 1260232809Sjmallett uint64_t tx_lnk_stat : 8; /**< Link status transmitted in the diagnostic word (per-lane) */ 1261232809Sjmallett uint64_t reserved_8_15 : 8; 1262232809Sjmallett uint64_t tx_lne_stat : 8; /**< Lane status transmitted in the diagnostic word (per-lane) */ 1263232809Sjmallett#else 1264232809Sjmallett uint64_t tx_lne_stat : 8; 1265232809Sjmallett uint64_t reserved_8_15 : 8; 1266232809Sjmallett uint64_t tx_lnk_stat : 8; 1267232809Sjmallett uint64_t reserved_24_31 : 8; 1268232809Sjmallett uint64_t rx_lne_stat : 8; 1269232809Sjmallett uint64_t reserved_40_47 : 8; 1270232809Sjmallett uint64_t rx_lnk_stat : 8; 1271232809Sjmallett uint64_t reserved_56_63 : 8; 1272232809Sjmallett#endif 1273232809Sjmallett } s; 1274232809Sjmallett struct cvmx_ilk_lne_sts_msg_s cn68xx; 1275232809Sjmallett struct cvmx_ilk_lne_sts_msg_s cn68xxp1; 1276232809Sjmallett}; 1277232809Sjmalletttypedef union cvmx_ilk_lne_sts_msg cvmx_ilk_lne_sts_msg_t; 1278232809Sjmallett 1279232809Sjmallett/** 1280232809Sjmallett * cvmx_ilk_rx#_cfg0 1281232809Sjmallett */ 1282232809Sjmallettunion cvmx_ilk_rxx_cfg0 { 1283232809Sjmallett uint64_t u64; 1284232809Sjmallett struct cvmx_ilk_rxx_cfg0_s { 1285232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1286232809Sjmallett uint64_t ext_lpbk_fc : 1; /**< Enable Rx-Tx flowcontrol loopback (external) */ 1287232809Sjmallett uint64_t ext_lpbk : 1; /**< Enable Rx-Tx data loopback (external). Note that with differing 1288232809Sjmallett transmit & receive clocks, skip word are inserted/deleted */ 1289232809Sjmallett uint64_t reserved_60_61 : 2; 1290232809Sjmallett uint64_t lnk_stats_wrap : 1; /**< Upon overflow, a statistics counter should wrap instead of 1291232809Sjmallett saturating. 1292232809Sjmallett 1293232809Sjmallett ***NOTE: Added in pass 2.0 */ 1294232809Sjmallett uint64_t bcw_push : 1; /**< The 8 byte burst control word containing the SOP will be 1295232809Sjmallett prepended to the corresponding packet. 1296232809Sjmallett 1297232809Sjmallett ***NOTE: Added in pass 2.0 */ 1298232809Sjmallett uint64_t mproto_ign : 1; /**< When LA_MODE=1 and MPROTO_IGN=0, the multi-protocol bit of the 1299232809Sjmallett LA control word is used to determine if the burst is an LA or 1300232809Sjmallett non-LA burst. When LA_MODE=1 and MPROTO_IGN=1, all bursts 1301232809Sjmallett are treated LA. When LA_MODE=0, this field is ignored 1302232809Sjmallett 1303232809Sjmallett ***NOTE: Added in pass 2.0 */ 1304232809Sjmallett uint64_t ptrn_mode : 1; /**< Enable programmable test pattern mode */ 1305232809Sjmallett uint64_t lnk_stats_rdclr : 1; /**< CSR read to ILK_RXx_STAT* clears the counter after returning 1306232809Sjmallett its current value. */ 1307232809Sjmallett uint64_t lnk_stats_ena : 1; /**< Enable link statistics counters */ 1308232809Sjmallett uint64_t mltuse_fc_ena : 1; /**< Use multi-use field for calendar */ 1309232809Sjmallett uint64_t cal_ena : 1; /**< Enable Rx calendar. When the calendar table is disabled, all 1310232809Sjmallett port-pipes receive XON. */ 1311232809Sjmallett uint64_t mfrm_len : 13; /**< The quantity of data sent on each lane including one sync word, 1312232809Sjmallett scrambler state, diag word, zero or more skip words, and the 1313232809Sjmallett data payload. Must be large than ILK_RXX_CFG1[SKIP_CNT]+9. 1314232809Sjmallett Supported range:ILK_RXX_CFG1[SKIP_CNT]+9 < MFRM_LEN <= 4096) */ 1315232809Sjmallett uint64_t brst_shrt : 7; /**< Minimum interval between burst control words, as a multiple of 1316232809Sjmallett 8 bytes. Supported range from 8 bytes to 512 (ie. 0 < 1317232809Sjmallett BRST_SHRT <= 64) 1318232809Sjmallett This field affects the ILK_RX*_STAT4[BRST_SHRT_ERR_CNT] 1319232809Sjmallett counter. It does not affect correct operation of the link. */ 1320232809Sjmallett uint64_t lane_rev : 1; /**< Lane reversal. When enabled, lane de-striping is performed 1321232809Sjmallett from most significant lane enabled to least significant lane 1322232809Sjmallett enabled. LANE_ENA must be zero before changing LANE_REV. */ 1323232809Sjmallett uint64_t brst_max : 5; /**< Maximum size of a data burst, as a multiple of 64 byte blocks. 1324232809Sjmallett Supported range is from 64 bytes to 1024 bytes. (ie. 0 < 1325232809Sjmallett BRST_MAX <= 16) 1326232809Sjmallett This field affects the ILK_RX*_STAT2[BRST_NOT_FULL_CNT] and 1327232809Sjmallett ILK_RX*_STAT3[BRST_MAX_ERR_CNT] counters. It does not affect 1328232809Sjmallett correct operation of the link. */ 1329232809Sjmallett uint64_t reserved_25_25 : 1; 1330232809Sjmallett uint64_t cal_depth : 9; /**< Number of valid entries in the calendar. Supported range from 1331232809Sjmallett 1 to 288. */ 1332232809Sjmallett uint64_t reserved_8_15 : 8; 1333232809Sjmallett uint64_t lane_ena : 8; /**< Lane enable mask. Link is enabled if any lane is enabled. The 1334232809Sjmallett same lane should not be enabled in multiple ILK_RXx_CFG0. Each 1335232809Sjmallett bit of LANE_ENA maps to a RX lane (RLE) and a QLM lane. NOTE: 1336232809Sjmallett LANE_REV has no effect on this mapping. 1337232809Sjmallett 1338232809Sjmallett LANE_ENA[0] = RLE0 = QLM1 lane 0 1339232809Sjmallett LANE_ENA[1] = RLE1 = QLM1 lane 1 1340232809Sjmallett LANE_ENA[2] = RLE2 = QLM1 lane 2 1341232809Sjmallett LANE_ENA[3] = RLE3 = QLM1 lane 3 1342232809Sjmallett LANE_ENA[4] = RLE4 = QLM2 lane 0 1343232809Sjmallett LANE_ENA[5] = RLE5 = QLM2 lane 1 1344232809Sjmallett LANE_ENA[6] = RLE6 = QLM2 lane 2 1345232809Sjmallett LANE_ENA[7] = RLE7 = QLM2 lane 3 */ 1346232809Sjmallett#else 1347232809Sjmallett uint64_t lane_ena : 8; 1348232809Sjmallett uint64_t reserved_8_15 : 8; 1349232809Sjmallett uint64_t cal_depth : 9; 1350232809Sjmallett uint64_t reserved_25_25 : 1; 1351232809Sjmallett uint64_t brst_max : 5; 1352232809Sjmallett uint64_t lane_rev : 1; 1353232809Sjmallett uint64_t brst_shrt : 7; 1354232809Sjmallett uint64_t mfrm_len : 13; 1355232809Sjmallett uint64_t cal_ena : 1; 1356232809Sjmallett uint64_t mltuse_fc_ena : 1; 1357232809Sjmallett uint64_t lnk_stats_ena : 1; 1358232809Sjmallett uint64_t lnk_stats_rdclr : 1; 1359232809Sjmallett uint64_t ptrn_mode : 1; 1360232809Sjmallett uint64_t mproto_ign : 1; 1361232809Sjmallett uint64_t bcw_push : 1; 1362232809Sjmallett uint64_t lnk_stats_wrap : 1; 1363232809Sjmallett uint64_t reserved_60_61 : 2; 1364232809Sjmallett uint64_t ext_lpbk : 1; 1365232809Sjmallett uint64_t ext_lpbk_fc : 1; 1366232809Sjmallett#endif 1367232809Sjmallett } s; 1368232809Sjmallett struct cvmx_ilk_rxx_cfg0_s cn68xx; 1369232809Sjmallett struct cvmx_ilk_rxx_cfg0_cn68xxp1 { 1370232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1371232809Sjmallett uint64_t ext_lpbk_fc : 1; /**< Enable Rx-Tx flowcontrol loopback (external) */ 1372232809Sjmallett uint64_t ext_lpbk : 1; /**< Enable Rx-Tx data loopback (external). Note that with differing 1373232809Sjmallett transmit & receive clocks, skip word are inserted/deleted */ 1374232809Sjmallett uint64_t reserved_57_61 : 5; 1375232809Sjmallett uint64_t ptrn_mode : 1; /**< Enable programmable test pattern mode */ 1376232809Sjmallett uint64_t lnk_stats_rdclr : 1; /**< CSR read to ILK_RXx_STAT* clears the counter after returning 1377232809Sjmallett its current value. */ 1378232809Sjmallett uint64_t lnk_stats_ena : 1; /**< Enable link statistics counters */ 1379232809Sjmallett uint64_t mltuse_fc_ena : 1; /**< Use multi-use field for calendar */ 1380232809Sjmallett uint64_t cal_ena : 1; /**< Enable Rx calendar. When the calendar table is disabled, all 1381232809Sjmallett port-pipes receive XON. */ 1382232809Sjmallett uint64_t mfrm_len : 13; /**< The quantity of data sent on each lane including one sync word, 1383232809Sjmallett scrambler state, diag word, zero or more skip words, and the 1384232809Sjmallett data payload. Must be large than ILK_RXX_CFG1[SKIP_CNT]+9. 1385232809Sjmallett Supported range:ILK_RXX_CFG1[SKIP_CNT]+9 < MFRM_LEN <= 4096) */ 1386232809Sjmallett uint64_t brst_shrt : 7; /**< Minimum interval between burst control words, as a multiple of 1387232809Sjmallett 8 bytes. Supported range from 8 bytes to 512 (ie. 0 < 1388232809Sjmallett BRST_SHRT <= 64) 1389232809Sjmallett This field affects the ILK_RX*_STAT4[BRST_SHRT_ERR_CNT] 1390232809Sjmallett counter. It does not affect correct operation of the link. */ 1391232809Sjmallett uint64_t lane_rev : 1; /**< Lane reversal. When enabled, lane de-striping is performed 1392232809Sjmallett from most significant lane enabled to least significant lane 1393232809Sjmallett enabled. LANE_ENA must be zero before changing LANE_REV. */ 1394232809Sjmallett uint64_t brst_max : 5; /**< Maximum size of a data burst, as a multiple of 64 byte blocks. 1395232809Sjmallett Supported range is from 64 bytes to 1024 bytes. (ie. 0 < 1396232809Sjmallett BRST_MAX <= 16) 1397232809Sjmallett This field affects the ILK_RX*_STAT2[BRST_NOT_FULL_CNT] and 1398232809Sjmallett ILK_RX*_STAT3[BRST_MAX_ERR_CNT] counters. It does not affect 1399232809Sjmallett correct operation of the link. */ 1400232809Sjmallett uint64_t reserved_25_25 : 1; 1401232809Sjmallett uint64_t cal_depth : 9; /**< Number of valid entries in the calendar. Supported range from 1402232809Sjmallett 1 to 288. */ 1403232809Sjmallett uint64_t reserved_8_15 : 8; 1404232809Sjmallett uint64_t lane_ena : 8; /**< Lane enable mask. Link is enabled if any lane is enabled. The 1405232809Sjmallett same lane should not be enabled in multiple ILK_RXx_CFG0. Each 1406232809Sjmallett bit of LANE_ENA maps to a RX lane (RLE) and a QLM lane. NOTE: 1407232809Sjmallett LANE_REV has no effect on this mapping. 1408232809Sjmallett 1409232809Sjmallett LANE_ENA[0] = RLE0 = QLM1 lane 0 1410232809Sjmallett LANE_ENA[1] = RLE1 = QLM1 lane 1 1411232809Sjmallett LANE_ENA[2] = RLE2 = QLM1 lane 2 1412232809Sjmallett LANE_ENA[3] = RLE3 = QLM1 lane 3 1413232809Sjmallett LANE_ENA[4] = RLE4 = QLM2 lane 0 1414232809Sjmallett LANE_ENA[5] = RLE5 = QLM2 lane 1 1415232809Sjmallett LANE_ENA[6] = RLE6 = QLM2 lane 2 1416232809Sjmallett LANE_ENA[7] = RLE7 = QLM2 lane 3 */ 1417232809Sjmallett#else 1418232809Sjmallett uint64_t lane_ena : 8; 1419232809Sjmallett uint64_t reserved_8_15 : 8; 1420232809Sjmallett uint64_t cal_depth : 9; 1421232809Sjmallett uint64_t reserved_25_25 : 1; 1422232809Sjmallett uint64_t brst_max : 5; 1423232809Sjmallett uint64_t lane_rev : 1; 1424232809Sjmallett uint64_t brst_shrt : 7; 1425232809Sjmallett uint64_t mfrm_len : 13; 1426232809Sjmallett uint64_t cal_ena : 1; 1427232809Sjmallett uint64_t mltuse_fc_ena : 1; 1428232809Sjmallett uint64_t lnk_stats_ena : 1; 1429232809Sjmallett uint64_t lnk_stats_rdclr : 1; 1430232809Sjmallett uint64_t ptrn_mode : 1; 1431232809Sjmallett uint64_t reserved_57_61 : 5; 1432232809Sjmallett uint64_t ext_lpbk : 1; 1433232809Sjmallett uint64_t ext_lpbk_fc : 1; 1434232809Sjmallett#endif 1435232809Sjmallett } cn68xxp1; 1436232809Sjmallett}; 1437232809Sjmalletttypedef union cvmx_ilk_rxx_cfg0 cvmx_ilk_rxx_cfg0_t; 1438232809Sjmallett 1439232809Sjmallett/** 1440232809Sjmallett * cvmx_ilk_rx#_cfg1 1441232809Sjmallett */ 1442232809Sjmallettunion cvmx_ilk_rxx_cfg1 { 1443232809Sjmallett uint64_t u64; 1444232809Sjmallett struct cvmx_ilk_rxx_cfg1_s { 1445232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1446232809Sjmallett uint64_t reserved_62_63 : 2; 1447232809Sjmallett uint64_t rx_fifo_cnt : 12; /**< Number of 64-bit words currently consumed by this link in the 1448232809Sjmallett RX fifo. */ 1449232809Sjmallett uint64_t reserved_48_49 : 2; 1450232809Sjmallett uint64_t rx_fifo_hwm : 12; /**< Number of 64-bit words consumed by this link before switch 1451232809Sjmallett transmitted link flow control status from XON to XOFF. 1452232809Sjmallett 1453232809Sjmallett XON = RX_FIFO_CNT < RX_FIFO_HWM 1454232809Sjmallett XOFF = RX_FIFO_CNT >= RX_FIFO_HWM. */ 1455232809Sjmallett uint64_t reserved_34_35 : 2; 1456232809Sjmallett uint64_t rx_fifo_max : 12; /**< Maximum number of 64-bit words consumed by this link in the RX 1457232809Sjmallett fifo. The sum of all links should be equal to 2048 (16KB) */ 1458232809Sjmallett uint64_t pkt_flush : 1; /**< Packet receive flush. Writing PKT_FLUSH=1 will cause all open 1459232809Sjmallett packets to be error-out, just as though the link went down. */ 1460232809Sjmallett uint64_t pkt_ena : 1; /**< Packet receive enable. When PKT_ENA=0, any received SOP causes 1461232809Sjmallett the entire packet to be dropped. */ 1462232809Sjmallett uint64_t la_mode : 1; /**< 0 = Interlaken 1463232809Sjmallett 1 = Interlaken Look-Aside */ 1464232809Sjmallett uint64_t tx_link_fc : 1; /**< Link flow control status transmitted by the Tx-Link 1465232809Sjmallett XON when RX_FIFO_CNT <= RX_FIFO_HWM and lane alignment is done */ 1466232809Sjmallett uint64_t rx_link_fc : 1; /**< Link flow control status received in burst/idle control words. 1467232809Sjmallett XOFF will cause Tx-Link to stop transmitting on all channels. */ 1468232809Sjmallett uint64_t rx_align_ena : 1; /**< Enable the lane alignment. This should only be done after all 1469232809Sjmallett enabled lanes have achieved word boundary lock and scrambler 1470232809Sjmallett synchronization. Note: Hardware will clear this when any 1471232809Sjmallett participating lane loses either word boundary lock or scrambler 1472232809Sjmallett synchronization */ 1473232809Sjmallett uint64_t reserved_8_15 : 8; 1474232809Sjmallett uint64_t rx_bdry_lock_ena : 8; /**< Enable word boundary lock. While disabled, received data is 1475232809Sjmallett tossed. Once enabled, received data is searched for legal 1476232809Sjmallett 2bit patterns. Automatically cleared for disabled lanes. */ 1477232809Sjmallett#else 1478232809Sjmallett uint64_t rx_bdry_lock_ena : 8; 1479232809Sjmallett uint64_t reserved_8_15 : 8; 1480232809Sjmallett uint64_t rx_align_ena : 1; 1481232809Sjmallett uint64_t rx_link_fc : 1; 1482232809Sjmallett uint64_t tx_link_fc : 1; 1483232809Sjmallett uint64_t la_mode : 1; 1484232809Sjmallett uint64_t pkt_ena : 1; 1485232809Sjmallett uint64_t pkt_flush : 1; 1486232809Sjmallett uint64_t rx_fifo_max : 12; 1487232809Sjmallett uint64_t reserved_34_35 : 2; 1488232809Sjmallett uint64_t rx_fifo_hwm : 12; 1489232809Sjmallett uint64_t reserved_48_49 : 2; 1490232809Sjmallett uint64_t rx_fifo_cnt : 12; 1491232809Sjmallett uint64_t reserved_62_63 : 2; 1492232809Sjmallett#endif 1493232809Sjmallett } s; 1494232809Sjmallett struct cvmx_ilk_rxx_cfg1_s cn68xx; 1495232809Sjmallett struct cvmx_ilk_rxx_cfg1_s cn68xxp1; 1496232809Sjmallett}; 1497232809Sjmalletttypedef union cvmx_ilk_rxx_cfg1 cvmx_ilk_rxx_cfg1_t; 1498232809Sjmallett 1499232809Sjmallett/** 1500232809Sjmallett * cvmx_ilk_rx#_flow_ctl0 1501232809Sjmallett */ 1502232809Sjmallettunion cvmx_ilk_rxx_flow_ctl0 { 1503232809Sjmallett uint64_t u64; 1504232809Sjmallett struct cvmx_ilk_rxx_flow_ctl0_s { 1505232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1506232809Sjmallett uint64_t status : 64; /**< Flow control status for port-pipes 63-0, where a 1 indicates 1507232809Sjmallett the presence of backpressure (ie. XOFF) and 0 indicates the 1508232809Sjmallett absence of backpressure (ie. XON) */ 1509232809Sjmallett#else 1510232809Sjmallett uint64_t status : 64; 1511232809Sjmallett#endif 1512232809Sjmallett } s; 1513232809Sjmallett struct cvmx_ilk_rxx_flow_ctl0_s cn68xx; 1514232809Sjmallett struct cvmx_ilk_rxx_flow_ctl0_s cn68xxp1; 1515232809Sjmallett}; 1516232809Sjmalletttypedef union cvmx_ilk_rxx_flow_ctl0 cvmx_ilk_rxx_flow_ctl0_t; 1517232809Sjmallett 1518232809Sjmallett/** 1519232809Sjmallett * cvmx_ilk_rx#_flow_ctl1 1520232809Sjmallett */ 1521232809Sjmallettunion cvmx_ilk_rxx_flow_ctl1 { 1522232809Sjmallett uint64_t u64; 1523232809Sjmallett struct cvmx_ilk_rxx_flow_ctl1_s { 1524232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1525232809Sjmallett uint64_t status : 64; /**< Flow control status for port-pipes 127-64, where a 1 indicates 1526232809Sjmallett the presence of backpressure (ie. XOFF) and 0 indicates the 1527232809Sjmallett absence of backpressure (ie. XON) */ 1528232809Sjmallett#else 1529232809Sjmallett uint64_t status : 64; 1530232809Sjmallett#endif 1531232809Sjmallett } s; 1532232809Sjmallett struct cvmx_ilk_rxx_flow_ctl1_s cn68xx; 1533232809Sjmallett struct cvmx_ilk_rxx_flow_ctl1_s cn68xxp1; 1534232809Sjmallett}; 1535232809Sjmalletttypedef union cvmx_ilk_rxx_flow_ctl1 cvmx_ilk_rxx_flow_ctl1_t; 1536232809Sjmallett 1537232809Sjmallett/** 1538232809Sjmallett * cvmx_ilk_rx#_idx_cal 1539232809Sjmallett */ 1540232809Sjmallettunion cvmx_ilk_rxx_idx_cal { 1541232809Sjmallett uint64_t u64; 1542232809Sjmallett struct cvmx_ilk_rxx_idx_cal_s { 1543232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1544232809Sjmallett uint64_t reserved_14_63 : 50; 1545232809Sjmallett uint64_t inc : 6; /**< Increment to add to current index for next index. NOTE: 1546232809Sjmallett Increment performed after access to ILK_RXx_MEM_CAL1 */ 1547232809Sjmallett uint64_t reserved_6_7 : 2; 1548232809Sjmallett uint64_t index : 6; /**< Specify the group of 8 entries accessed by the next CSR 1549232809Sjmallett read/write to calendar table memory. Software must never write 1550232809Sjmallett IDX >= 36 */ 1551232809Sjmallett#else 1552232809Sjmallett uint64_t index : 6; 1553232809Sjmallett uint64_t reserved_6_7 : 2; 1554232809Sjmallett uint64_t inc : 6; 1555232809Sjmallett uint64_t reserved_14_63 : 50; 1556232809Sjmallett#endif 1557232809Sjmallett } s; 1558232809Sjmallett struct cvmx_ilk_rxx_idx_cal_s cn68xx; 1559232809Sjmallett struct cvmx_ilk_rxx_idx_cal_s cn68xxp1; 1560232809Sjmallett}; 1561232809Sjmalletttypedef union cvmx_ilk_rxx_idx_cal cvmx_ilk_rxx_idx_cal_t; 1562232809Sjmallett 1563232809Sjmallett/** 1564232809Sjmallett * cvmx_ilk_rx#_idx_stat0 1565232809Sjmallett */ 1566232809Sjmallettunion cvmx_ilk_rxx_idx_stat0 { 1567232809Sjmallett uint64_t u64; 1568232809Sjmallett struct cvmx_ilk_rxx_idx_stat0_s { 1569232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1570232809Sjmallett uint64_t reserved_32_63 : 32; 1571232809Sjmallett uint64_t clr : 1; /**< CSR read to ILK_RXx_MEM_STAT0 clears the selected counter after 1572232809Sjmallett returning its current value. */ 1573232809Sjmallett uint64_t reserved_24_30 : 7; 1574232809Sjmallett uint64_t inc : 8; /**< Increment to add to current index for next index */ 1575232809Sjmallett uint64_t reserved_8_15 : 8; 1576232809Sjmallett uint64_t index : 8; /**< Specify the channel accessed during the next CSR read to the 1577232809Sjmallett ILK_RXx_MEM_STAT0 */ 1578232809Sjmallett#else 1579232809Sjmallett uint64_t index : 8; 1580232809Sjmallett uint64_t reserved_8_15 : 8; 1581232809Sjmallett uint64_t inc : 8; 1582232809Sjmallett uint64_t reserved_24_30 : 7; 1583232809Sjmallett uint64_t clr : 1; 1584232809Sjmallett uint64_t reserved_32_63 : 32; 1585232809Sjmallett#endif 1586232809Sjmallett } s; 1587232809Sjmallett struct cvmx_ilk_rxx_idx_stat0_s cn68xx; 1588232809Sjmallett struct cvmx_ilk_rxx_idx_stat0_s cn68xxp1; 1589232809Sjmallett}; 1590232809Sjmalletttypedef union cvmx_ilk_rxx_idx_stat0 cvmx_ilk_rxx_idx_stat0_t; 1591232809Sjmallett 1592232809Sjmallett/** 1593232809Sjmallett * cvmx_ilk_rx#_idx_stat1 1594232809Sjmallett */ 1595232809Sjmallettunion cvmx_ilk_rxx_idx_stat1 { 1596232809Sjmallett uint64_t u64; 1597232809Sjmallett struct cvmx_ilk_rxx_idx_stat1_s { 1598232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1599232809Sjmallett uint64_t reserved_32_63 : 32; 1600232809Sjmallett uint64_t clr : 1; /**< CSR read to ILK_RXx_MEM_STAT1 clears the selected counter after 1601232809Sjmallett returning its current value. */ 1602232809Sjmallett uint64_t reserved_24_30 : 7; 1603232809Sjmallett uint64_t inc : 8; /**< Increment to add to current index for next index */ 1604232809Sjmallett uint64_t reserved_8_15 : 8; 1605232809Sjmallett uint64_t index : 8; /**< Specify the channel accessed during the next CSR read to the 1606232809Sjmallett ILK_RXx_MEM_STAT1 */ 1607232809Sjmallett#else 1608232809Sjmallett uint64_t index : 8; 1609232809Sjmallett uint64_t reserved_8_15 : 8; 1610232809Sjmallett uint64_t inc : 8; 1611232809Sjmallett uint64_t reserved_24_30 : 7; 1612232809Sjmallett uint64_t clr : 1; 1613232809Sjmallett uint64_t reserved_32_63 : 32; 1614232809Sjmallett#endif 1615232809Sjmallett } s; 1616232809Sjmallett struct cvmx_ilk_rxx_idx_stat1_s cn68xx; 1617232809Sjmallett struct cvmx_ilk_rxx_idx_stat1_s cn68xxp1; 1618232809Sjmallett}; 1619232809Sjmalletttypedef union cvmx_ilk_rxx_idx_stat1 cvmx_ilk_rxx_idx_stat1_t; 1620232809Sjmallett 1621232809Sjmallett/** 1622232809Sjmallett * cvmx_ilk_rx#_int 1623232809Sjmallett */ 1624232809Sjmallettunion cvmx_ilk_rxx_int { 1625232809Sjmallett uint64_t u64; 1626232809Sjmallett struct cvmx_ilk_rxx_int_s { 1627232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1628232809Sjmallett uint64_t reserved_9_63 : 55; 1629232809Sjmallett uint64_t pkt_drop_sop : 1; /**< Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX, 1630232809Sjmallett lack of reassembly-ids or because ILK_RXX_CFG1[PKT_ENA]=0 | $RW 1631232809Sjmallett because ILK_RXX_CFG1[PKT_ENA]=0 1632232809Sjmallett 1633232809Sjmallett ***NOTE: Added in pass 2.0 */ 1634232809Sjmallett uint64_t pkt_drop_rid : 1; /**< Entire packet dropped due to the lack of reassembly-ids or 1635232809Sjmallett because ILK_RXX_CFG1[PKT_ENA]=0 */ 1636232809Sjmallett uint64_t pkt_drop_rxf : 1; /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */ 1637232809Sjmallett uint64_t lane_bad_word : 1; /**< A lane encountered either a bad 64B/67B codeword or an unknown 1638232809Sjmallett control word type. */ 1639232809Sjmallett uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */ 1640232809Sjmallett uint64_t lane_align_done : 1; /**< Lane alignment successful */ 1641232809Sjmallett uint64_t word_sync_done : 1; /**< All enabled lanes have achieved word boundary lock and 1642232809Sjmallett scrambler synchronization. Lane alignment may now be enabled. */ 1643232809Sjmallett uint64_t crc24_err : 1; /**< Burst CRC24 error. All open packets will be receive an error. */ 1644232809Sjmallett uint64_t lane_align_fail : 1; /**< Lane Alignment fails (4 tries). Hardware will repeat lane 1645232809Sjmallett alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA] 1646232809Sjmallett is cleared. */ 1647232809Sjmallett#else 1648232809Sjmallett uint64_t lane_align_fail : 1; 1649232809Sjmallett uint64_t crc24_err : 1; 1650232809Sjmallett uint64_t word_sync_done : 1; 1651232809Sjmallett uint64_t lane_align_done : 1; 1652232809Sjmallett uint64_t stat_cnt_ovfl : 1; 1653232809Sjmallett uint64_t lane_bad_word : 1; 1654232809Sjmallett uint64_t pkt_drop_rxf : 1; 1655232809Sjmallett uint64_t pkt_drop_rid : 1; 1656232809Sjmallett uint64_t pkt_drop_sop : 1; 1657232809Sjmallett uint64_t reserved_9_63 : 55; 1658232809Sjmallett#endif 1659232809Sjmallett } s; 1660232809Sjmallett struct cvmx_ilk_rxx_int_s cn68xx; 1661232809Sjmallett struct cvmx_ilk_rxx_int_cn68xxp1 { 1662232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1663232809Sjmallett uint64_t reserved_8_63 : 56; 1664232809Sjmallett uint64_t pkt_drop_rid : 1; /**< Entire packet dropped due to the lack of reassembly-ids or 1665232809Sjmallett because ILK_RXX_CFG1[PKT_ENA]=0 */ 1666232809Sjmallett uint64_t pkt_drop_rxf : 1; /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */ 1667232809Sjmallett uint64_t lane_bad_word : 1; /**< A lane encountered either a bad 64B/67B codeword or an unknown 1668232809Sjmallett control word type. */ 1669232809Sjmallett uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */ 1670232809Sjmallett uint64_t lane_align_done : 1; /**< Lane alignment successful */ 1671232809Sjmallett uint64_t word_sync_done : 1; /**< All enabled lanes have achieved word boundary lock and 1672232809Sjmallett scrambler synchronization. Lane alignment may now be enabled. */ 1673232809Sjmallett uint64_t crc24_err : 1; /**< Burst CRC24 error. All open packets will be receive an error. */ 1674232809Sjmallett uint64_t lane_align_fail : 1; /**< Lane Alignment fails (4 tries). Hardware will repeat lane 1675232809Sjmallett alignment until is succeeds or until ILK_RXx_CFG1[RX_ALIGN_ENA] 1676232809Sjmallett is cleared. */ 1677232809Sjmallett#else 1678232809Sjmallett uint64_t lane_align_fail : 1; 1679232809Sjmallett uint64_t crc24_err : 1; 1680232809Sjmallett uint64_t word_sync_done : 1; 1681232809Sjmallett uint64_t lane_align_done : 1; 1682232809Sjmallett uint64_t stat_cnt_ovfl : 1; 1683232809Sjmallett uint64_t lane_bad_word : 1; 1684232809Sjmallett uint64_t pkt_drop_rxf : 1; 1685232809Sjmallett uint64_t pkt_drop_rid : 1; 1686232809Sjmallett uint64_t reserved_8_63 : 56; 1687232809Sjmallett#endif 1688232809Sjmallett } cn68xxp1; 1689232809Sjmallett}; 1690232809Sjmalletttypedef union cvmx_ilk_rxx_int cvmx_ilk_rxx_int_t; 1691232809Sjmallett 1692232809Sjmallett/** 1693232809Sjmallett * cvmx_ilk_rx#_int_en 1694232809Sjmallett */ 1695232809Sjmallettunion cvmx_ilk_rxx_int_en { 1696232809Sjmallett uint64_t u64; 1697232809Sjmallett struct cvmx_ilk_rxx_int_en_s { 1698232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1699232809Sjmallett uint64_t reserved_9_63 : 55; 1700232809Sjmallett uint64_t pkt_drop_sop : 1; /**< Entire packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX, 1701232809Sjmallett lack of reassembly-ids or because ILK_RXX_CFG1[PKT_ENA]=0 | $PRW 1702232809Sjmallett because ILK_RXX_CFG1[PKT_ENA]=0 1703232809Sjmallett 1704232809Sjmallett ***NOTE: Added in pass 2.0 */ 1705232809Sjmallett uint64_t pkt_drop_rid : 1; /**< Entire packet dropped due to the lack of reassembly-ids or 1706232809Sjmallett because ILK_RXX_CFG1[PKT_ENA]=0 */ 1707232809Sjmallett uint64_t pkt_drop_rxf : 1; /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */ 1708232809Sjmallett uint64_t lane_bad_word : 1; /**< A lane encountered either a bad 64B/67B codeword or an unknown 1709232809Sjmallett control word type. */ 1710232809Sjmallett uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */ 1711232809Sjmallett uint64_t lane_align_done : 1; /**< Lane alignment successful */ 1712232809Sjmallett uint64_t word_sync_done : 1; /**< All enabled lanes have achieved word boundary lock and 1713232809Sjmallett scrambler synchronization. Lane alignment may now be enabled. */ 1714232809Sjmallett uint64_t crc24_err : 1; /**< Burst CRC24 error. All open packets will be receive an error. */ 1715232809Sjmallett uint64_t lane_align_fail : 1; /**< Lane Alignment fails (4 tries) */ 1716232809Sjmallett#else 1717232809Sjmallett uint64_t lane_align_fail : 1; 1718232809Sjmallett uint64_t crc24_err : 1; 1719232809Sjmallett uint64_t word_sync_done : 1; 1720232809Sjmallett uint64_t lane_align_done : 1; 1721232809Sjmallett uint64_t stat_cnt_ovfl : 1; 1722232809Sjmallett uint64_t lane_bad_word : 1; 1723232809Sjmallett uint64_t pkt_drop_rxf : 1; 1724232809Sjmallett uint64_t pkt_drop_rid : 1; 1725232809Sjmallett uint64_t pkt_drop_sop : 1; 1726232809Sjmallett uint64_t reserved_9_63 : 55; 1727232809Sjmallett#endif 1728232809Sjmallett } s; 1729232809Sjmallett struct cvmx_ilk_rxx_int_en_s cn68xx; 1730232809Sjmallett struct cvmx_ilk_rxx_int_en_cn68xxp1 { 1731232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1732232809Sjmallett uint64_t reserved_8_63 : 56; 1733232809Sjmallett uint64_t pkt_drop_rid : 1; /**< Entire packet dropped due to the lack of reassembly-ids or 1734232809Sjmallett because ILK_RXX_CFG1[PKT_ENA]=0 */ 1735232809Sjmallett uint64_t pkt_drop_rxf : 1; /**< Some/all of a packet dropped due to RX_FIFO_CNT == RX_FIFO_MAX */ 1736232809Sjmallett uint64_t lane_bad_word : 1; /**< A lane encountered either a bad 64B/67B codeword or an unknown 1737232809Sjmallett control word type. */ 1738232809Sjmallett uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */ 1739232809Sjmallett uint64_t lane_align_done : 1; /**< Lane alignment successful */ 1740232809Sjmallett uint64_t word_sync_done : 1; /**< All enabled lanes have achieved word boundary lock and 1741232809Sjmallett scrambler synchronization. Lane alignment may now be enabled. */ 1742232809Sjmallett uint64_t crc24_err : 1; /**< Burst CRC24 error. All open packets will be receive an error. */ 1743232809Sjmallett uint64_t lane_align_fail : 1; /**< Lane Alignment fails (4 tries) */ 1744232809Sjmallett#else 1745232809Sjmallett uint64_t lane_align_fail : 1; 1746232809Sjmallett uint64_t crc24_err : 1; 1747232809Sjmallett uint64_t word_sync_done : 1; 1748232809Sjmallett uint64_t lane_align_done : 1; 1749232809Sjmallett uint64_t stat_cnt_ovfl : 1; 1750232809Sjmallett uint64_t lane_bad_word : 1; 1751232809Sjmallett uint64_t pkt_drop_rxf : 1; 1752232809Sjmallett uint64_t pkt_drop_rid : 1; 1753232809Sjmallett uint64_t reserved_8_63 : 56; 1754232809Sjmallett#endif 1755232809Sjmallett } cn68xxp1; 1756232809Sjmallett}; 1757232809Sjmalletttypedef union cvmx_ilk_rxx_int_en cvmx_ilk_rxx_int_en_t; 1758232809Sjmallett 1759232809Sjmallett/** 1760232809Sjmallett * cvmx_ilk_rx#_jabber 1761232809Sjmallett */ 1762232809Sjmallettunion cvmx_ilk_rxx_jabber { 1763232809Sjmallett uint64_t u64; 1764232809Sjmallett struct cvmx_ilk_rxx_jabber_s { 1765232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1766232809Sjmallett uint64_t reserved_16_63 : 48; 1767232809Sjmallett uint64_t cnt : 16; /**< Byte count for jabber check. Failing packets will be 1768232809Sjmallett truncated to CNT bytes. 1769232809Sjmallett 1770232809Sjmallett NOTE: Hardware tracks the size of up to two concurrent packet 1771232809Sjmallett per link. If using segment mode with more than 2 channels, 1772232809Sjmallett some large packets may not be flagged or truncated. 1773232809Sjmallett 1774232809Sjmallett NOTE: CNT must be 8-byte aligned such that CNT[2:0] == 0 */ 1775232809Sjmallett#else 1776232809Sjmallett uint64_t cnt : 16; 1777232809Sjmallett uint64_t reserved_16_63 : 48; 1778232809Sjmallett#endif 1779232809Sjmallett } s; 1780232809Sjmallett struct cvmx_ilk_rxx_jabber_s cn68xx; 1781232809Sjmallett struct cvmx_ilk_rxx_jabber_s cn68xxp1; 1782232809Sjmallett}; 1783232809Sjmalletttypedef union cvmx_ilk_rxx_jabber cvmx_ilk_rxx_jabber_t; 1784232809Sjmallett 1785232809Sjmallett/** 1786232809Sjmallett * cvmx_ilk_rx#_mem_cal0 1787232809Sjmallett * 1788232809Sjmallett * Notes: 1789232809Sjmallett * Software must program the calendar table prior to enabling the 1790232809Sjmallett * link. 1791232809Sjmallett * 1792232809Sjmallett * Software must always write ILK_RXx_MEM_CAL0 then ILK_RXx_MEM_CAL1. 1793232809Sjmallett * Software must never write them in reverse order or write one without 1794232809Sjmallett * writing the other. 1795232809Sjmallett * 1796232809Sjmallett * A given calendar table entry has no effect on PKO pipe 1797232809Sjmallett * backpressure when either: 1798232809Sjmallett * - ENTRY_CTLx=Link (1), or 1799232809Sjmallett * - ENTRY_CTLx=XON (3) and PORT_PIPEx is outside the range of ILK_TXx_PIPE[BASE/NUMP]. 1800232809Sjmallett * 1801232809Sjmallett * Within the 8 calendar table entries of one IDX value, if more 1802232809Sjmallett * than one affects the same PKO pipe, XOFF always wins over XON, 1803232809Sjmallett * regardless of the calendar table order. 1804232809Sjmallett * 1805232809Sjmallett * Software must always read ILK_RXx_MEM_CAL0 then ILK_RXx_MEM_CAL1. Software 1806232809Sjmallett * must never read them in reverse order or read one without reading the 1807232809Sjmallett * other. 1808232809Sjmallett */ 1809232809Sjmallettunion cvmx_ilk_rxx_mem_cal0 { 1810232809Sjmallett uint64_t u64; 1811232809Sjmallett struct cvmx_ilk_rxx_mem_cal0_s { 1812232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1813232809Sjmallett uint64_t reserved_36_63 : 28; 1814232809Sjmallett uint64_t entry_ctl3 : 2; /**< XON/XOFF destination for entry (IDX*8)+3 1815232809Sjmallett 1816232809Sjmallett - 0: PKO port-pipe Apply backpressure received from the 1817232809Sjmallett remote tranmitter to the PKO pipe selected 1818232809Sjmallett by PORT_PIPE3. 1819232809Sjmallett 1820232809Sjmallett - 1: Link Apply the backpressure received from the 1821232809Sjmallett remote transmitter to link backpressure. 1822232809Sjmallett PORT_PIPE3 is unused. 1823232809Sjmallett 1824232809Sjmallett - 2: XOFF Apply XOFF to the PKO pipe selected by 1825232809Sjmallett PORT_PIPE3. 1826232809Sjmallett 1827232809Sjmallett - 3: XON Apply XON to the PKO pipe selected by 1828232809Sjmallett PORT_PIPE3. The calendar table entry is 1829232809Sjmallett effectively unused if PORT_PIPE3 is out of 1830232809Sjmallett range of ILK_TXx_PIPE[BASE/NUMP]. */ 1831232809Sjmallett uint64_t port_pipe3 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+3 1832232809Sjmallett 1833232809Sjmallett PORT_PIPE3 must reside in the range of ILK_TXx_PIPE[BASE/NUMP] 1834232809Sjmallett when ENTRY_CTL3 is "XOFF" (2) or "PKO port-pipe" (0). */ 1835232809Sjmallett uint64_t entry_ctl2 : 2; /**< XON/XOFF destination for entry (IDX*8)+2 1836232809Sjmallett 1837232809Sjmallett - 0: PKO port-pipe Apply backpressure received from the 1838232809Sjmallett remote tranmitter to the PKO pipe selected 1839232809Sjmallett by PORT_PIPE2. 1840232809Sjmallett 1841232809Sjmallett - 1: Link Apply the backpressure received from the 1842232809Sjmallett remote transmitter to link backpressure. 1843232809Sjmallett PORT_PIPE2 is unused. 1844232809Sjmallett 1845232809Sjmallett - 2: XOFF Apply XOFF to the PKO pipe selected by 1846232809Sjmallett PORT_PIPE2. 1847232809Sjmallett 1848232809Sjmallett - 3: XON Apply XON to the PKO pipe selected by 1849232809Sjmallett PORT_PIPE2. The calendar table entry is 1850232809Sjmallett effectively unused if PORT_PIPE2 is out of 1851232809Sjmallett range of ILK_TXx_PIPE[BASE/NUMP]. */ 1852232809Sjmallett uint64_t port_pipe2 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+2 1853232809Sjmallett 1854232809Sjmallett PORT_PIPE2 must reside in the range of ILK_TXx_PIPE[BASE/NUMP] 1855232809Sjmallett when ENTRY_CTL2 is "XOFF" (2) or "PKO port-pipe" (0). */ 1856232809Sjmallett uint64_t entry_ctl1 : 2; /**< XON/XOFF destination for entry (IDX*8)+1 1857232809Sjmallett 1858232809Sjmallett - 0: PKO port-pipe Apply backpressure received from the 1859232809Sjmallett remote tranmitter to the PKO pipe selected 1860232809Sjmallett by PORT_PIPE1. 1861232809Sjmallett 1862232809Sjmallett - 1: Link Apply the backpressure received from the 1863232809Sjmallett remote transmitter to link backpressure. 1864232809Sjmallett PORT_PIPE1 is unused. 1865232809Sjmallett 1866232809Sjmallett - 2: XOFF Apply XOFF to the PKO pipe selected by 1867232809Sjmallett PORT_PIPE1. 1868232809Sjmallett 1869232809Sjmallett - 3: XON Apply XON to the PKO pipe selected by 1870232809Sjmallett PORT_PIPE1. The calendar table entry is 1871232809Sjmallett effectively unused if PORT_PIPE1 is out of 1872232809Sjmallett range of ILK_TXx_PIPE[BASE/NUMP]. */ 1873232809Sjmallett uint64_t port_pipe1 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+1 1874232809Sjmallett 1875232809Sjmallett PORT_PIPE1 must reside in the range of ILK_TXx_PIPE[BASE/NUMP] 1876232809Sjmallett when ENTRY_CTL1 is "XOFF" (2) or "PKO port-pipe" (0). */ 1877232809Sjmallett uint64_t entry_ctl0 : 2; /**< XON/XOFF destination for entry (IDX*8)+0 1878232809Sjmallett 1879232809Sjmallett - 0: PKO port-pipe Apply backpressure received from the 1880232809Sjmallett remote tranmitter to the PKO pipe selected 1881232809Sjmallett by PORT_PIPE0. 1882232809Sjmallett 1883232809Sjmallett - 1: Link Apply the backpressure received from the 1884232809Sjmallett remote transmitter to link backpressure. 1885232809Sjmallett PORT_PIPE0 is unused. 1886232809Sjmallett 1887232809Sjmallett - 2: XOFF Apply XOFF to the PKO pipe selected by 1888232809Sjmallett PORT_PIPE0. 1889232809Sjmallett 1890232809Sjmallett - 3: XON Apply XON to the PKO pipe selected by 1891232809Sjmallett PORT_PIPE0. The calendar table entry is 1892232809Sjmallett effectively unused if PORT_PIPEx is out of 1893232809Sjmallett range of ILK_TXx_PIPE[BASE/NUMP]. */ 1894232809Sjmallett uint64_t port_pipe0 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+0 1895232809Sjmallett 1896232809Sjmallett PORT_PIPE0 must reside in the range of ILK_TXx_PIPE[BASE/NUMP] 1897232809Sjmallett when ENTRY_CTL0 is "XOFF" (2) or "PKO port-pipe" (0). */ 1898232809Sjmallett#else 1899232809Sjmallett uint64_t port_pipe0 : 7; 1900232809Sjmallett uint64_t entry_ctl0 : 2; 1901232809Sjmallett uint64_t port_pipe1 : 7; 1902232809Sjmallett uint64_t entry_ctl1 : 2; 1903232809Sjmallett uint64_t port_pipe2 : 7; 1904232809Sjmallett uint64_t entry_ctl2 : 2; 1905232809Sjmallett uint64_t port_pipe3 : 7; 1906232809Sjmallett uint64_t entry_ctl3 : 2; 1907232809Sjmallett uint64_t reserved_36_63 : 28; 1908232809Sjmallett#endif 1909232809Sjmallett } s; 1910232809Sjmallett struct cvmx_ilk_rxx_mem_cal0_s cn68xx; 1911232809Sjmallett struct cvmx_ilk_rxx_mem_cal0_s cn68xxp1; 1912232809Sjmallett}; 1913232809Sjmalletttypedef union cvmx_ilk_rxx_mem_cal0 cvmx_ilk_rxx_mem_cal0_t; 1914232809Sjmallett 1915232809Sjmallett/** 1916232809Sjmallett * cvmx_ilk_rx#_mem_cal1 1917232809Sjmallett * 1918232809Sjmallett * Notes: 1919232809Sjmallett * Software must program the calendar table prior to enabling the 1920232809Sjmallett * link. 1921232809Sjmallett * 1922232809Sjmallett * Software must always write ILK_RXx_MEM_CAL0 then ILK_RXx_MEM_CAL1. 1923232809Sjmallett * Software must never write them in reverse order or write one without 1924232809Sjmallett * writing the other. 1925232809Sjmallett * 1926232809Sjmallett * A given calendar table entry has no effect on PKO pipe 1927232809Sjmallett * backpressure when either: 1928232809Sjmallett * - ENTRY_CTLx=Link (1), or 1929232809Sjmallett * - ENTRY_CTLx=XON (3) and PORT_PIPEx is outside the range of ILK_TXx_PIPE[BASE/NUMP]. 1930232809Sjmallett * 1931232809Sjmallett * Within the 8 calendar table entries of one IDX value, if more 1932232809Sjmallett * than one affects the same PKO pipe, XOFF always wins over XON, 1933232809Sjmallett * regardless of the calendar table order. 1934232809Sjmallett * 1935232809Sjmallett * Software must always read ILK_RXx_MEM_CAL0 then ILK_Rx_MEM_CAL1. Software 1936232809Sjmallett * must never read them in reverse order or read one without reading the 1937232809Sjmallett * other. 1938232809Sjmallett */ 1939232809Sjmallettunion cvmx_ilk_rxx_mem_cal1 { 1940232809Sjmallett uint64_t u64; 1941232809Sjmallett struct cvmx_ilk_rxx_mem_cal1_s { 1942232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1943232809Sjmallett uint64_t reserved_36_63 : 28; 1944232809Sjmallett uint64_t entry_ctl7 : 2; /**< XON/XOFF destination for entry (IDX*8)+7 1945232809Sjmallett 1946232809Sjmallett - 0: PKO port-pipe Apply backpressure received from the 1947232809Sjmallett remote tranmitter to the PKO pipe selected 1948232809Sjmallett by PORT_PIPE7. 1949232809Sjmallett 1950232809Sjmallett - 1: Link Apply the backpressure received from the 1951232809Sjmallett remote transmitter to link backpressure. 1952232809Sjmallett PORT_PIPE7 is unused. 1953232809Sjmallett 1954232809Sjmallett - 2: XOFF Apply XOFF to the PKO pipe selected by 1955232809Sjmallett PORT_PIPE7. 1956232809Sjmallett 1957232809Sjmallett - 3: XON Apply XON to the PKO pipe selected by 1958232809Sjmallett PORT_PIPE7. The calendar table entry is 1959232809Sjmallett effectively unused if PORT_PIPE3 is out of 1960232809Sjmallett range of ILK_TXx_PIPE[BASE/NUMP]. */ 1961232809Sjmallett uint64_t port_pipe7 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+7 1962232809Sjmallett 1963232809Sjmallett PORT_PIPE7 must reside in the range of ILK_TXx_PIPE[BASE/NUMP] 1964232809Sjmallett when ENTRY_CTL7 is "XOFF" (2) or "PKO port-pipe" (0). */ 1965232809Sjmallett uint64_t entry_ctl6 : 2; /**< XON/XOFF destination for entry (IDX*8)+6 1966232809Sjmallett 1967232809Sjmallett - 0: PKO port-pipe Apply backpressure received from the 1968232809Sjmallett remote tranmitter to the PKO pipe selected 1969232809Sjmallett by PORT_PIPE6. 1970232809Sjmallett 1971232809Sjmallett - 1: Link Apply the backpressure received from the 1972232809Sjmallett remote transmitter to link backpressure. 1973232809Sjmallett PORT_PIPE6 is unused. 1974232809Sjmallett 1975232809Sjmallett - 2: XOFF Apply XOFF to the PKO pipe selected by 1976232809Sjmallett PORT_PIPE6. 1977232809Sjmallett 1978232809Sjmallett - 3: XON Apply XON to the PKO pipe selected by 1979232809Sjmallett PORT_PIPE6. The calendar table entry is 1980232809Sjmallett effectively unused if PORT_PIPE6 is out of 1981232809Sjmallett range of ILK_TXx_PIPE[BASE/NUMP]. */ 1982232809Sjmallett uint64_t port_pipe6 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+6 1983232809Sjmallett 1984232809Sjmallett PORT_PIPE6 must reside in the range of ILK_TXx_PIPE[BASE/NUMP] 1985232809Sjmallett when ENTRY_CTL6 is "XOFF" (2) or "PKO port-pipe" (0). */ 1986232809Sjmallett uint64_t entry_ctl5 : 2; /**< XON/XOFF destination for entry (IDX*8)+5 1987232809Sjmallett 1988232809Sjmallett - 0: PKO port-pipe Apply backpressure received from the 1989232809Sjmallett remote tranmitter to the PKO pipe selected 1990232809Sjmallett by PORT_PIPE5. 1991232809Sjmallett 1992232809Sjmallett - 1: Link Apply the backpressure received from the 1993232809Sjmallett remote transmitter to link backpressure. 1994232809Sjmallett PORT_PIPE5 is unused. 1995232809Sjmallett 1996232809Sjmallett - 2: XOFF Apply XOFF to the PKO pipe selected by 1997232809Sjmallett PORT_PIPE5. 1998232809Sjmallett 1999232809Sjmallett - 3: XON Apply XON to the PKO pipe selected by 2000232809Sjmallett PORT_PIPE5. The calendar table entry is 2001232809Sjmallett effectively unused if PORT_PIPE5 is out of 2002232809Sjmallett range of ILK_TXx_PIPE[BASE/NUMP]. */ 2003232809Sjmallett uint64_t port_pipe5 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+5 2004232809Sjmallett 2005232809Sjmallett PORT_PIPE5 must reside in the range of ILK_TXx_PIPE[BASE/NUMP] 2006232809Sjmallett when ENTRY_CTL5 is "XOFF" (2) or "PKO port-pipe" (0). */ 2007232809Sjmallett uint64_t entry_ctl4 : 2; /**< XON/XOFF destination for entry (IDX*8)+4 2008232809Sjmallett 2009232809Sjmallett - 0: PKO port-pipe Apply backpressure received from the 2010232809Sjmallett remote tranmitter to the PKO pipe selected 2011232809Sjmallett by PORT_PIPE4. 2012232809Sjmallett 2013232809Sjmallett - 1: Link Apply the backpressure received from the 2014232809Sjmallett remote transmitter to link backpressure. 2015232809Sjmallett PORT_PIPE4 is unused. 2016232809Sjmallett 2017232809Sjmallett - 2: XOFF Apply XOFF to the PKO pipe selected by 2018232809Sjmallett PORT_PIPE4. 2019232809Sjmallett 2020232809Sjmallett - 3: XON Apply XON to the PKO pipe selected by 2021232809Sjmallett PORT_PIPE4. The calendar table entry is 2022232809Sjmallett effectively unused if PORT_PIPE4 is out of 2023232809Sjmallett range of ILK_TXx_PIPE[BASE/NUMP]. */ 2024232809Sjmallett uint64_t port_pipe4 : 7; /**< Select PKO port-pipe for calendar table entry (IDX*8)+4 2025232809Sjmallett 2026232809Sjmallett PORT_PIPE4 must reside in the range of ILK_TXx_PIPE[BASE/NUMP] 2027232809Sjmallett when ENTRY_CTL4 is "XOFF" (2) or "PKO port-pipe" (0). */ 2028232809Sjmallett#else 2029232809Sjmallett uint64_t port_pipe4 : 7; 2030232809Sjmallett uint64_t entry_ctl4 : 2; 2031232809Sjmallett uint64_t port_pipe5 : 7; 2032232809Sjmallett uint64_t entry_ctl5 : 2; 2033232809Sjmallett uint64_t port_pipe6 : 7; 2034232809Sjmallett uint64_t entry_ctl6 : 2; 2035232809Sjmallett uint64_t port_pipe7 : 7; 2036232809Sjmallett uint64_t entry_ctl7 : 2; 2037232809Sjmallett uint64_t reserved_36_63 : 28; 2038232809Sjmallett#endif 2039232809Sjmallett } s; 2040232809Sjmallett struct cvmx_ilk_rxx_mem_cal1_s cn68xx; 2041232809Sjmallett struct cvmx_ilk_rxx_mem_cal1_s cn68xxp1; 2042232809Sjmallett}; 2043232809Sjmalletttypedef union cvmx_ilk_rxx_mem_cal1 cvmx_ilk_rxx_mem_cal1_t; 2044232809Sjmallett 2045232809Sjmallett/** 2046232809Sjmallett * cvmx_ilk_rx#_mem_stat0 2047232809Sjmallett */ 2048232809Sjmallettunion cvmx_ilk_rxx_mem_stat0 { 2049232809Sjmallett uint64_t u64; 2050232809Sjmallett struct cvmx_ilk_rxx_mem_stat0_s { 2051232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2052232809Sjmallett uint64_t reserved_28_63 : 36; 2053232809Sjmallett uint64_t rx_pkt : 28; /**< Number of packets received (256M) 2054232809Sjmallett Channel selected by ILK_RXx_IDX_STAT0[IDX]. Saturates. 2055232809Sjmallett Interrupt on saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2056232809Sjmallett#else 2057232809Sjmallett uint64_t rx_pkt : 28; 2058232809Sjmallett uint64_t reserved_28_63 : 36; 2059232809Sjmallett#endif 2060232809Sjmallett } s; 2061232809Sjmallett struct cvmx_ilk_rxx_mem_stat0_s cn68xx; 2062232809Sjmallett struct cvmx_ilk_rxx_mem_stat0_s cn68xxp1; 2063232809Sjmallett}; 2064232809Sjmalletttypedef union cvmx_ilk_rxx_mem_stat0 cvmx_ilk_rxx_mem_stat0_t; 2065232809Sjmallett 2066232809Sjmallett/** 2067232809Sjmallett * cvmx_ilk_rx#_mem_stat1 2068232809Sjmallett */ 2069232809Sjmallettunion cvmx_ilk_rxx_mem_stat1 { 2070232809Sjmallett uint64_t u64; 2071232809Sjmallett struct cvmx_ilk_rxx_mem_stat1_s { 2072232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2073232809Sjmallett uint64_t reserved_36_63 : 28; 2074232809Sjmallett uint64_t rx_bytes : 36; /**< Number of bytes received (64GB) 2075232809Sjmallett Channel selected by ILK_RXx_IDX_STAT1[IDX]. Saturates. 2076232809Sjmallett Interrupt on saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2077232809Sjmallett#else 2078232809Sjmallett uint64_t rx_bytes : 36; 2079232809Sjmallett uint64_t reserved_36_63 : 28; 2080232809Sjmallett#endif 2081232809Sjmallett } s; 2082232809Sjmallett struct cvmx_ilk_rxx_mem_stat1_s cn68xx; 2083232809Sjmallett struct cvmx_ilk_rxx_mem_stat1_s cn68xxp1; 2084232809Sjmallett}; 2085232809Sjmalletttypedef union cvmx_ilk_rxx_mem_stat1 cvmx_ilk_rxx_mem_stat1_t; 2086232809Sjmallett 2087232809Sjmallett/** 2088232809Sjmallett * cvmx_ilk_rx#_rid 2089232809Sjmallett */ 2090232809Sjmallettunion cvmx_ilk_rxx_rid { 2091232809Sjmallett uint64_t u64; 2092232809Sjmallett struct cvmx_ilk_rxx_rid_s { 2093232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2094232809Sjmallett uint64_t reserved_6_63 : 58; 2095232809Sjmallett uint64_t max_cnt : 6; /**< Maximum number of reassembly-ids allowed for a given link. If 2096232809Sjmallett an SOP arrives and the link has already allocated at least 2097232809Sjmallett MAX_CNT reassembly-ids, the packet will be dropped. 2098232809Sjmallett 2099232809Sjmallett Note: An an SOP allocates a reassembly-ids. 2100232809Sjmallett Note: An an EOP frees a reassembly-ids. 2101232809Sjmallett 2102232809Sjmallett ***NOTE: Added in pass 2.0 */ 2103232809Sjmallett#else 2104232809Sjmallett uint64_t max_cnt : 6; 2105232809Sjmallett uint64_t reserved_6_63 : 58; 2106232809Sjmallett#endif 2107232809Sjmallett } s; 2108232809Sjmallett struct cvmx_ilk_rxx_rid_s cn68xx; 2109232809Sjmallett}; 2110232809Sjmalletttypedef union cvmx_ilk_rxx_rid cvmx_ilk_rxx_rid_t; 2111232809Sjmallett 2112232809Sjmallett/** 2113232809Sjmallett * cvmx_ilk_rx#_stat0 2114232809Sjmallett */ 2115232809Sjmallettunion cvmx_ilk_rxx_stat0 { 2116232809Sjmallett uint64_t u64; 2117232809Sjmallett struct cvmx_ilk_rxx_stat0_s { 2118232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2119232809Sjmallett uint64_t reserved_33_63 : 31; 2120232809Sjmallett uint64_t crc24_match_cnt : 33; /**< Number of CRC24 matches received. Saturates. Interrupt on 2121232809Sjmallett saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2122232809Sjmallett#else 2123232809Sjmallett uint64_t crc24_match_cnt : 33; 2124232809Sjmallett uint64_t reserved_33_63 : 31; 2125232809Sjmallett#endif 2126232809Sjmallett } s; 2127232809Sjmallett struct cvmx_ilk_rxx_stat0_s cn68xx; 2128232809Sjmallett struct cvmx_ilk_rxx_stat0_cn68xxp1 { 2129232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2130232809Sjmallett uint64_t reserved_27_63 : 37; 2131232809Sjmallett uint64_t crc24_match_cnt : 27; /**< Number of CRC24 matches received. Saturates. Interrupt on 2132232809Sjmallett saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2133232809Sjmallett#else 2134232809Sjmallett uint64_t crc24_match_cnt : 27; 2135232809Sjmallett uint64_t reserved_27_63 : 37; 2136232809Sjmallett#endif 2137232809Sjmallett } cn68xxp1; 2138232809Sjmallett}; 2139232809Sjmalletttypedef union cvmx_ilk_rxx_stat0 cvmx_ilk_rxx_stat0_t; 2140232809Sjmallett 2141232809Sjmallett/** 2142232809Sjmallett * cvmx_ilk_rx#_stat1 2143232809Sjmallett */ 2144232809Sjmallettunion cvmx_ilk_rxx_stat1 { 2145232809Sjmallett uint64_t u64; 2146232809Sjmallett struct cvmx_ilk_rxx_stat1_s { 2147232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2148232809Sjmallett uint64_t reserved_18_63 : 46; 2149232809Sjmallett uint64_t crc24_err_cnt : 18; /**< Number of bursts with a detected CRC error. Saturates. 2150232809Sjmallett Interrupt on saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2151232809Sjmallett#else 2152232809Sjmallett uint64_t crc24_err_cnt : 18; 2153232809Sjmallett uint64_t reserved_18_63 : 46; 2154232809Sjmallett#endif 2155232809Sjmallett } s; 2156232809Sjmallett struct cvmx_ilk_rxx_stat1_s cn68xx; 2157232809Sjmallett struct cvmx_ilk_rxx_stat1_s cn68xxp1; 2158232809Sjmallett}; 2159232809Sjmalletttypedef union cvmx_ilk_rxx_stat1 cvmx_ilk_rxx_stat1_t; 2160232809Sjmallett 2161232809Sjmallett/** 2162232809Sjmallett * cvmx_ilk_rx#_stat2 2163232809Sjmallett */ 2164232809Sjmallettunion cvmx_ilk_rxx_stat2 { 2165232809Sjmallett uint64_t u64; 2166232809Sjmallett struct cvmx_ilk_rxx_stat2_s { 2167232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2168232809Sjmallett uint64_t reserved_48_63 : 16; 2169232809Sjmallett uint64_t brst_not_full_cnt : 16; /**< Number of bursts received which terminated without an eop and 2170232809Sjmallett contained fewer than BurstMax words. Saturates. Interrupt on 2171232809Sjmallett saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2172232809Sjmallett uint64_t reserved_28_31 : 4; 2173232809Sjmallett uint64_t brst_cnt : 28; /**< Number of bursts correctly received. (ie. good CRC24, not in 2174232809Sjmallett violation of BurstMax or BurstShort) */ 2175232809Sjmallett#else 2176232809Sjmallett uint64_t brst_cnt : 28; 2177232809Sjmallett uint64_t reserved_28_31 : 4; 2178232809Sjmallett uint64_t brst_not_full_cnt : 16; 2179232809Sjmallett uint64_t reserved_48_63 : 16; 2180232809Sjmallett#endif 2181232809Sjmallett } s; 2182232809Sjmallett struct cvmx_ilk_rxx_stat2_s cn68xx; 2183232809Sjmallett struct cvmx_ilk_rxx_stat2_cn68xxp1 { 2184232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2185232809Sjmallett uint64_t reserved_48_63 : 16; 2186232809Sjmallett uint64_t brst_not_full_cnt : 16; /**< Number of bursts received which terminated without an eop and 2187232809Sjmallett contained fewer than BurstMax words. Saturates. Interrupt on 2188232809Sjmallett saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2189232809Sjmallett uint64_t reserved_16_31 : 16; 2190232809Sjmallett uint64_t brst_cnt : 16; /**< Number of bursts correctly received. (ie. good CRC24, not in 2191232809Sjmallett violation of BurstMax or BurstShort) */ 2192232809Sjmallett#else 2193232809Sjmallett uint64_t brst_cnt : 16; 2194232809Sjmallett uint64_t reserved_16_31 : 16; 2195232809Sjmallett uint64_t brst_not_full_cnt : 16; 2196232809Sjmallett uint64_t reserved_48_63 : 16; 2197232809Sjmallett#endif 2198232809Sjmallett } cn68xxp1; 2199232809Sjmallett}; 2200232809Sjmalletttypedef union cvmx_ilk_rxx_stat2 cvmx_ilk_rxx_stat2_t; 2201232809Sjmallett 2202232809Sjmallett/** 2203232809Sjmallett * cvmx_ilk_rx#_stat3 2204232809Sjmallett */ 2205232809Sjmallettunion cvmx_ilk_rxx_stat3 { 2206232809Sjmallett uint64_t u64; 2207232809Sjmallett struct cvmx_ilk_rxx_stat3_s { 2208232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2209232809Sjmallett uint64_t reserved_16_63 : 48; 2210232809Sjmallett uint64_t brst_max_err_cnt : 16; /**< Number of bursts received longer than the BurstMax parameter */ 2211232809Sjmallett#else 2212232809Sjmallett uint64_t brst_max_err_cnt : 16; 2213232809Sjmallett uint64_t reserved_16_63 : 48; 2214232809Sjmallett#endif 2215232809Sjmallett } s; 2216232809Sjmallett struct cvmx_ilk_rxx_stat3_s cn68xx; 2217232809Sjmallett struct cvmx_ilk_rxx_stat3_s cn68xxp1; 2218232809Sjmallett}; 2219232809Sjmalletttypedef union cvmx_ilk_rxx_stat3 cvmx_ilk_rxx_stat3_t; 2220232809Sjmallett 2221232809Sjmallett/** 2222232809Sjmallett * cvmx_ilk_rx#_stat4 2223232809Sjmallett */ 2224232809Sjmallettunion cvmx_ilk_rxx_stat4 { 2225232809Sjmallett uint64_t u64; 2226232809Sjmallett struct cvmx_ilk_rxx_stat4_s { 2227232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2228232809Sjmallett uint64_t reserved_16_63 : 48; 2229232809Sjmallett uint64_t brst_shrt_err_cnt : 16; /**< Number of bursts received that violate the BurstShort 2230232809Sjmallett parameter. Saturates. Interrupt on saturation if 2231232809Sjmallett ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2232232809Sjmallett#else 2233232809Sjmallett uint64_t brst_shrt_err_cnt : 16; 2234232809Sjmallett uint64_t reserved_16_63 : 48; 2235232809Sjmallett#endif 2236232809Sjmallett } s; 2237232809Sjmallett struct cvmx_ilk_rxx_stat4_s cn68xx; 2238232809Sjmallett struct cvmx_ilk_rxx_stat4_s cn68xxp1; 2239232809Sjmallett}; 2240232809Sjmalletttypedef union cvmx_ilk_rxx_stat4 cvmx_ilk_rxx_stat4_t; 2241232809Sjmallett 2242232809Sjmallett/** 2243232809Sjmallett * cvmx_ilk_rx#_stat5 2244232809Sjmallett */ 2245232809Sjmallettunion cvmx_ilk_rxx_stat5 { 2246232809Sjmallett uint64_t u64; 2247232809Sjmallett struct cvmx_ilk_rxx_stat5_s { 2248232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2249232809Sjmallett uint64_t reserved_23_63 : 41; 2250232809Sjmallett uint64_t align_cnt : 23; /**< Number of alignment sequences received (ie. those that do not 2251232809Sjmallett violate the current alignment). Saturates. Interrupt on 2252232809Sjmallett saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2253232809Sjmallett#else 2254232809Sjmallett uint64_t align_cnt : 23; 2255232809Sjmallett uint64_t reserved_23_63 : 41; 2256232809Sjmallett#endif 2257232809Sjmallett } s; 2258232809Sjmallett struct cvmx_ilk_rxx_stat5_s cn68xx; 2259232809Sjmallett struct cvmx_ilk_rxx_stat5_cn68xxp1 { 2260232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2261232809Sjmallett uint64_t reserved_16_63 : 48; 2262232809Sjmallett uint64_t align_cnt : 16; /**< Number of alignment sequences received (ie. those that do not 2263232809Sjmallett violate the current alignment). Saturates. Interrupt on 2264232809Sjmallett saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2265232809Sjmallett#else 2266232809Sjmallett uint64_t align_cnt : 16; 2267232809Sjmallett uint64_t reserved_16_63 : 48; 2268232809Sjmallett#endif 2269232809Sjmallett } cn68xxp1; 2270232809Sjmallett}; 2271232809Sjmalletttypedef union cvmx_ilk_rxx_stat5 cvmx_ilk_rxx_stat5_t; 2272232809Sjmallett 2273232809Sjmallett/** 2274232809Sjmallett * cvmx_ilk_rx#_stat6 2275232809Sjmallett */ 2276232809Sjmallettunion cvmx_ilk_rxx_stat6 { 2277232809Sjmallett uint64_t u64; 2278232809Sjmallett struct cvmx_ilk_rxx_stat6_s { 2279232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2280232809Sjmallett uint64_t reserved_16_63 : 48; 2281232809Sjmallett uint64_t align_err_cnt : 16; /**< Number of alignment sequences received in error (ie. those that 2282232809Sjmallett violate the current alignment). Saturates. Interrupt on 2283232809Sjmallett saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2284232809Sjmallett#else 2285232809Sjmallett uint64_t align_err_cnt : 16; 2286232809Sjmallett uint64_t reserved_16_63 : 48; 2287232809Sjmallett#endif 2288232809Sjmallett } s; 2289232809Sjmallett struct cvmx_ilk_rxx_stat6_s cn68xx; 2290232809Sjmallett struct cvmx_ilk_rxx_stat6_s cn68xxp1; 2291232809Sjmallett}; 2292232809Sjmalletttypedef union cvmx_ilk_rxx_stat6 cvmx_ilk_rxx_stat6_t; 2293232809Sjmallett 2294232809Sjmallett/** 2295232809Sjmallett * cvmx_ilk_rx#_stat7 2296232809Sjmallett */ 2297232809Sjmallettunion cvmx_ilk_rxx_stat7 { 2298232809Sjmallett uint64_t u64; 2299232809Sjmallett struct cvmx_ilk_rxx_stat7_s { 2300232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2301232809Sjmallett uint64_t reserved_16_63 : 48; 2302232809Sjmallett uint64_t bad_64b67b_cnt : 16; /**< Number of bad 64B/67B codewords. Saturates. Interrupt on 2303232809Sjmallett saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2304232809Sjmallett#else 2305232809Sjmallett uint64_t bad_64b67b_cnt : 16; 2306232809Sjmallett uint64_t reserved_16_63 : 48; 2307232809Sjmallett#endif 2308232809Sjmallett } s; 2309232809Sjmallett struct cvmx_ilk_rxx_stat7_s cn68xx; 2310232809Sjmallett struct cvmx_ilk_rxx_stat7_s cn68xxp1; 2311232809Sjmallett}; 2312232809Sjmalletttypedef union cvmx_ilk_rxx_stat7 cvmx_ilk_rxx_stat7_t; 2313232809Sjmallett 2314232809Sjmallett/** 2315232809Sjmallett * cvmx_ilk_rx#_stat8 2316232809Sjmallett */ 2317232809Sjmallettunion cvmx_ilk_rxx_stat8 { 2318232809Sjmallett uint64_t u64; 2319232809Sjmallett struct cvmx_ilk_rxx_stat8_s { 2320232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2321232809Sjmallett uint64_t reserved_32_63 : 32; 2322232809Sjmallett uint64_t pkt_drop_rid_cnt : 16; /**< Number of packets dropped due to the lack of reassembly-ids or 2323232809Sjmallett because ILK_RXX_CFG1[PKT_ENA]=0. Saturates. Interrupt on 2324232809Sjmallett saturation if ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2325232809Sjmallett uint64_t pkt_drop_rxf_cnt : 16; /**< Number of packets dropped due to RX_FIFO_CNT >= RX_FIFO_MAX. 2326232809Sjmallett Saturates. Interrupt on saturation if 2327232809Sjmallett ILK_RXX_INT_EN[STAT_CNT_OVFL]=1. */ 2328232809Sjmallett#else 2329232809Sjmallett uint64_t pkt_drop_rxf_cnt : 16; 2330232809Sjmallett uint64_t pkt_drop_rid_cnt : 16; 2331232809Sjmallett uint64_t reserved_32_63 : 32; 2332232809Sjmallett#endif 2333232809Sjmallett } s; 2334232809Sjmallett struct cvmx_ilk_rxx_stat8_s cn68xx; 2335232809Sjmallett struct cvmx_ilk_rxx_stat8_s cn68xxp1; 2336232809Sjmallett}; 2337232809Sjmalletttypedef union cvmx_ilk_rxx_stat8 cvmx_ilk_rxx_stat8_t; 2338232809Sjmallett 2339232809Sjmallett/** 2340232809Sjmallett * cvmx_ilk_rx#_stat9 2341232809Sjmallett */ 2342232809Sjmallettunion cvmx_ilk_rxx_stat9 { 2343232809Sjmallett uint64_t u64; 2344232809Sjmallett struct cvmx_ilk_rxx_stat9_s { 2345232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2346232809Sjmallett uint64_t reserved_0_63 : 64; 2347232809Sjmallett#else 2348232809Sjmallett uint64_t reserved_0_63 : 64; 2349232809Sjmallett#endif 2350232809Sjmallett } s; 2351232809Sjmallett struct cvmx_ilk_rxx_stat9_s cn68xx; 2352232809Sjmallett struct cvmx_ilk_rxx_stat9_s cn68xxp1; 2353232809Sjmallett}; 2354232809Sjmalletttypedef union cvmx_ilk_rxx_stat9 cvmx_ilk_rxx_stat9_t; 2355232809Sjmallett 2356232809Sjmallett/** 2357232809Sjmallett * cvmx_ilk_rx_lne#_cfg 2358232809Sjmallett */ 2359232809Sjmallettunion cvmx_ilk_rx_lnex_cfg { 2360232809Sjmallett uint64_t u64; 2361232809Sjmallett struct cvmx_ilk_rx_lnex_cfg_s { 2362232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2363232809Sjmallett uint64_t reserved_9_63 : 55; 2364232809Sjmallett uint64_t rx_dis_psh_skip : 1; /**< When RX_DIS_PSH_SKIP=0, skip words are de-stripped. 2365232809Sjmallett When RX_DIS_PSH_SKIP=1, skip words are discarded in the lane 2366232809Sjmallett logic. 2367232809Sjmallett 2368232809Sjmallett If the lane is in internal loopback mode, RX_DIS_PSH_SKIP 2369232809Sjmallett is ignored and skip words are always discarded in the lane 2370232809Sjmallett logic. 2371232809Sjmallett 2372232809Sjmallett ***NOTE: Added in pass 2.0 */ 2373232809Sjmallett uint64_t reserved_6_7 : 2; 2374232809Sjmallett uint64_t rx_scrm_sync : 1; /**< Rx scrambler synchronization status 2375232809Sjmallett 2376232809Sjmallett ***NOTE: Added in pass 2.0 */ 2377232809Sjmallett uint64_t rx_bdry_sync : 1; /**< Rx word boundary sync status */ 2378232809Sjmallett uint64_t rx_dis_ukwn : 1; /**< Disable normal response to unknown words. They are still 2379232809Sjmallett logged but do not cause an error to all open channels */ 2380232809Sjmallett uint64_t rx_dis_scram : 1; /**< Disable lane scrambler (debug) */ 2381232809Sjmallett uint64_t stat_rdclr : 1; /**< CSR read to ILK_RX_LNEx_STAT* clears the selected counter after 2382232809Sjmallett returning its current value. */ 2383232809Sjmallett uint64_t stat_ena : 1; /**< Enable RX lane statistics counters */ 2384232809Sjmallett#else 2385232809Sjmallett uint64_t stat_ena : 1; 2386232809Sjmallett uint64_t stat_rdclr : 1; 2387232809Sjmallett uint64_t rx_dis_scram : 1; 2388232809Sjmallett uint64_t rx_dis_ukwn : 1; 2389232809Sjmallett uint64_t rx_bdry_sync : 1; 2390232809Sjmallett uint64_t rx_scrm_sync : 1; 2391232809Sjmallett uint64_t reserved_6_7 : 2; 2392232809Sjmallett uint64_t rx_dis_psh_skip : 1; 2393232809Sjmallett uint64_t reserved_9_63 : 55; 2394232809Sjmallett#endif 2395232809Sjmallett } s; 2396232809Sjmallett struct cvmx_ilk_rx_lnex_cfg_s cn68xx; 2397232809Sjmallett struct cvmx_ilk_rx_lnex_cfg_cn68xxp1 { 2398232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2399232809Sjmallett uint64_t reserved_5_63 : 59; 2400232809Sjmallett uint64_t rx_bdry_sync : 1; /**< Rx word boundary sync status */ 2401232809Sjmallett uint64_t rx_dis_ukwn : 1; /**< Disable normal response to unknown words. They are still 2402232809Sjmallett logged but do not cause an error to all open channels */ 2403232809Sjmallett uint64_t rx_dis_scram : 1; /**< Disable lane scrambler (debug) */ 2404232809Sjmallett uint64_t stat_rdclr : 1; /**< CSR read to ILK_RX_LNEx_STAT* clears the selected counter after 2405232809Sjmallett returning its current value. */ 2406232809Sjmallett uint64_t stat_ena : 1; /**< Enable RX lane statistics counters */ 2407232809Sjmallett#else 2408232809Sjmallett uint64_t stat_ena : 1; 2409232809Sjmallett uint64_t stat_rdclr : 1; 2410232809Sjmallett uint64_t rx_dis_scram : 1; 2411232809Sjmallett uint64_t rx_dis_ukwn : 1; 2412232809Sjmallett uint64_t rx_bdry_sync : 1; 2413232809Sjmallett uint64_t reserved_5_63 : 59; 2414232809Sjmallett#endif 2415232809Sjmallett } cn68xxp1; 2416232809Sjmallett}; 2417232809Sjmalletttypedef union cvmx_ilk_rx_lnex_cfg cvmx_ilk_rx_lnex_cfg_t; 2418232809Sjmallett 2419232809Sjmallett/** 2420232809Sjmallett * cvmx_ilk_rx_lne#_int 2421232809Sjmallett */ 2422232809Sjmallettunion cvmx_ilk_rx_lnex_int { 2423232809Sjmallett uint64_t u64; 2424232809Sjmallett struct cvmx_ilk_rx_lnex_int_s { 2425232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2426232809Sjmallett uint64_t reserved_9_63 : 55; 2427232809Sjmallett uint64_t bad_64b67b : 1; /**< Bad 64B/67B codeword encountered. Once the bad word reaches 2428232809Sjmallett the burst control unit (as deonted by 2429232809Sjmallett ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open 2430232809Sjmallett packets will receive an error. */ 2431232809Sjmallett uint64_t stat_cnt_ovfl : 1; /**< Rx lane statistic counter overflow */ 2432232809Sjmallett uint64_t stat_msg : 1; /**< Status bits for the link or a lane transitioned from a '1' 2433232809Sjmallett (healthy) to a '0' (problem) */ 2434232809Sjmallett uint64_t dskew_fifo_ovfl : 1; /**< Rx deskew fifo overflow occurred. */ 2435232809Sjmallett uint64_t scrm_sync_loss : 1; /**< 4 consecutive bad sync words or 3 consecutive scramble state 2436232809Sjmallett mismatches */ 2437232809Sjmallett uint64_t ukwn_cntl_word : 1; /**< Unknown framing control word. Block type does not match any of 2438232809Sjmallett (SYNC,SCRAM,SKIP,DIAG) */ 2439232809Sjmallett uint64_t crc32_err : 1; /**< Diagnostic CRC32 errors */ 2440232809Sjmallett uint64_t bdry_sync_loss : 1; /**< Rx logic loses word boundary sync (16 tries). Hardware will 2441232809Sjmallett automatically attempt to regain word boundary sync */ 2442232809Sjmallett uint64_t serdes_lock_loss : 1; /**< Rx SERDES loses lock */ 2443232809Sjmallett#else 2444232809Sjmallett uint64_t serdes_lock_loss : 1; 2445232809Sjmallett uint64_t bdry_sync_loss : 1; 2446232809Sjmallett uint64_t crc32_err : 1; 2447232809Sjmallett uint64_t ukwn_cntl_word : 1; 2448232809Sjmallett uint64_t scrm_sync_loss : 1; 2449232809Sjmallett uint64_t dskew_fifo_ovfl : 1; 2450232809Sjmallett uint64_t stat_msg : 1; 2451232809Sjmallett uint64_t stat_cnt_ovfl : 1; 2452232809Sjmallett uint64_t bad_64b67b : 1; 2453232809Sjmallett uint64_t reserved_9_63 : 55; 2454232809Sjmallett#endif 2455232809Sjmallett } s; 2456232809Sjmallett struct cvmx_ilk_rx_lnex_int_s cn68xx; 2457232809Sjmallett struct cvmx_ilk_rx_lnex_int_s cn68xxp1; 2458232809Sjmallett}; 2459232809Sjmalletttypedef union cvmx_ilk_rx_lnex_int cvmx_ilk_rx_lnex_int_t; 2460232809Sjmallett 2461232809Sjmallett/** 2462232809Sjmallett * cvmx_ilk_rx_lne#_int_en 2463232809Sjmallett */ 2464232809Sjmallettunion cvmx_ilk_rx_lnex_int_en { 2465232809Sjmallett uint64_t u64; 2466232809Sjmallett struct cvmx_ilk_rx_lnex_int_en_s { 2467232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2468232809Sjmallett uint64_t reserved_9_63 : 55; 2469232809Sjmallett uint64_t bad_64b67b : 1; /**< Bad 64B/67B codeword encountered. Once the bad word reaches 2470232809Sjmallett the burst control unit (as deonted by 2471232809Sjmallett ILK_RXx_INT[LANE_BAD_WORD]) it will be tossed and all open 2472232809Sjmallett packets will receive an error. */ 2473232809Sjmallett uint64_t stat_cnt_ovfl : 1; /**< Rx lane statistic counter overflow */ 2474232809Sjmallett uint64_t stat_msg : 1; /**< Status bits for the link or a lane transitioned from a '1' 2475232809Sjmallett (healthy) to a '0' (problem) */ 2476232809Sjmallett uint64_t dskew_fifo_ovfl : 1; /**< Rx deskew fifo overflow occurred. */ 2477232809Sjmallett uint64_t scrm_sync_loss : 1; /**< 4 consecutive bad sync words or 3 consecutive scramble state 2478232809Sjmallett mismatches */ 2479232809Sjmallett uint64_t ukwn_cntl_word : 1; /**< Unknown framing control word. Block type does not match any of 2480232809Sjmallett (SYNC,SCRAM,SKIP,DIAG) */ 2481232809Sjmallett uint64_t crc32_err : 1; /**< Diagnostic CRC32 error */ 2482232809Sjmallett uint64_t bdry_sync_loss : 1; /**< Rx logic loses word boundary sync (16 tries). Hardware will 2483232809Sjmallett automatically attempt to regain word boundary sync */ 2484232809Sjmallett uint64_t serdes_lock_loss : 1; /**< Rx SERDES loses lock */ 2485232809Sjmallett#else 2486232809Sjmallett uint64_t serdes_lock_loss : 1; 2487232809Sjmallett uint64_t bdry_sync_loss : 1; 2488232809Sjmallett uint64_t crc32_err : 1; 2489232809Sjmallett uint64_t ukwn_cntl_word : 1; 2490232809Sjmallett uint64_t scrm_sync_loss : 1; 2491232809Sjmallett uint64_t dskew_fifo_ovfl : 1; 2492232809Sjmallett uint64_t stat_msg : 1; 2493232809Sjmallett uint64_t stat_cnt_ovfl : 1; 2494232809Sjmallett uint64_t bad_64b67b : 1; 2495232809Sjmallett uint64_t reserved_9_63 : 55; 2496232809Sjmallett#endif 2497232809Sjmallett } s; 2498232809Sjmallett struct cvmx_ilk_rx_lnex_int_en_s cn68xx; 2499232809Sjmallett struct cvmx_ilk_rx_lnex_int_en_s cn68xxp1; 2500232809Sjmallett}; 2501232809Sjmalletttypedef union cvmx_ilk_rx_lnex_int_en cvmx_ilk_rx_lnex_int_en_t; 2502232809Sjmallett 2503232809Sjmallett/** 2504232809Sjmallett * cvmx_ilk_rx_lne#_stat0 2505232809Sjmallett */ 2506232809Sjmallettunion cvmx_ilk_rx_lnex_stat0 { 2507232809Sjmallett uint64_t u64; 2508232809Sjmallett struct cvmx_ilk_rx_lnex_stat0_s { 2509232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2510232809Sjmallett uint64_t reserved_18_63 : 46; 2511232809Sjmallett uint64_t ser_lock_loss_cnt : 18; /**< Number of times the lane lost clock-data-recovery. 2512232809Sjmallett Saturates. Interrupt on saturation if 2513232809Sjmallett ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2514232809Sjmallett#else 2515232809Sjmallett uint64_t ser_lock_loss_cnt : 18; 2516232809Sjmallett uint64_t reserved_18_63 : 46; 2517232809Sjmallett#endif 2518232809Sjmallett } s; 2519232809Sjmallett struct cvmx_ilk_rx_lnex_stat0_s cn68xx; 2520232809Sjmallett struct cvmx_ilk_rx_lnex_stat0_s cn68xxp1; 2521232809Sjmallett}; 2522232809Sjmalletttypedef union cvmx_ilk_rx_lnex_stat0 cvmx_ilk_rx_lnex_stat0_t; 2523232809Sjmallett 2524232809Sjmallett/** 2525232809Sjmallett * cvmx_ilk_rx_lne#_stat1 2526232809Sjmallett */ 2527232809Sjmallettunion cvmx_ilk_rx_lnex_stat1 { 2528232809Sjmallett uint64_t u64; 2529232809Sjmallett struct cvmx_ilk_rx_lnex_stat1_s { 2530232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2531232809Sjmallett uint64_t reserved_18_63 : 46; 2532232809Sjmallett uint64_t bdry_sync_loss_cnt : 18; /**< Number of times a lane lost word boundary synchronization. 2533232809Sjmallett Saturates. Interrupt on saturation if 2534232809Sjmallett ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2535232809Sjmallett#else 2536232809Sjmallett uint64_t bdry_sync_loss_cnt : 18; 2537232809Sjmallett uint64_t reserved_18_63 : 46; 2538232809Sjmallett#endif 2539232809Sjmallett } s; 2540232809Sjmallett struct cvmx_ilk_rx_lnex_stat1_s cn68xx; 2541232809Sjmallett struct cvmx_ilk_rx_lnex_stat1_s cn68xxp1; 2542232809Sjmallett}; 2543232809Sjmalletttypedef union cvmx_ilk_rx_lnex_stat1 cvmx_ilk_rx_lnex_stat1_t; 2544232809Sjmallett 2545232809Sjmallett/** 2546232809Sjmallett * cvmx_ilk_rx_lne#_stat2 2547232809Sjmallett */ 2548232809Sjmallettunion cvmx_ilk_rx_lnex_stat2 { 2549232809Sjmallett uint64_t u64; 2550232809Sjmallett struct cvmx_ilk_rx_lnex_stat2_s { 2551232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2552232809Sjmallett uint64_t reserved_50_63 : 14; 2553232809Sjmallett uint64_t syncw_good_cnt : 18; /**< Number of good synchronization words. Saturates. Interrupt on 2554232809Sjmallett saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2555232809Sjmallett uint64_t reserved_18_31 : 14; 2556232809Sjmallett uint64_t syncw_bad_cnt : 18; /**< Number of bad synchronization words. Saturates. Interrupt on 2557232809Sjmallett saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2558232809Sjmallett#else 2559232809Sjmallett uint64_t syncw_bad_cnt : 18; 2560232809Sjmallett uint64_t reserved_18_31 : 14; 2561232809Sjmallett uint64_t syncw_good_cnt : 18; 2562232809Sjmallett uint64_t reserved_50_63 : 14; 2563232809Sjmallett#endif 2564232809Sjmallett } s; 2565232809Sjmallett struct cvmx_ilk_rx_lnex_stat2_s cn68xx; 2566232809Sjmallett struct cvmx_ilk_rx_lnex_stat2_s cn68xxp1; 2567232809Sjmallett}; 2568232809Sjmalletttypedef union cvmx_ilk_rx_lnex_stat2 cvmx_ilk_rx_lnex_stat2_t; 2569232809Sjmallett 2570232809Sjmallett/** 2571232809Sjmallett * cvmx_ilk_rx_lne#_stat3 2572232809Sjmallett */ 2573232809Sjmallettunion cvmx_ilk_rx_lnex_stat3 { 2574232809Sjmallett uint64_t u64; 2575232809Sjmallett struct cvmx_ilk_rx_lnex_stat3_s { 2576232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2577232809Sjmallett uint64_t reserved_18_63 : 46; 2578232809Sjmallett uint64_t bad_64b67b_cnt : 18; /**< Number of bad 64B/67B words, meaning bit 65 or 64 has been 2579232809Sjmallett corrupted. Saturates. Interrupt on saturation if 2580232809Sjmallett ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2581232809Sjmallett#else 2582232809Sjmallett uint64_t bad_64b67b_cnt : 18; 2583232809Sjmallett uint64_t reserved_18_63 : 46; 2584232809Sjmallett#endif 2585232809Sjmallett } s; 2586232809Sjmallett struct cvmx_ilk_rx_lnex_stat3_s cn68xx; 2587232809Sjmallett struct cvmx_ilk_rx_lnex_stat3_s cn68xxp1; 2588232809Sjmallett}; 2589232809Sjmalletttypedef union cvmx_ilk_rx_lnex_stat3 cvmx_ilk_rx_lnex_stat3_t; 2590232809Sjmallett 2591232809Sjmallett/** 2592232809Sjmallett * cvmx_ilk_rx_lne#_stat4 2593232809Sjmallett */ 2594232809Sjmallettunion cvmx_ilk_rx_lnex_stat4 { 2595232809Sjmallett uint64_t u64; 2596232809Sjmallett struct cvmx_ilk_rx_lnex_stat4_s { 2597232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2598232809Sjmallett uint64_t reserved_59_63 : 5; 2599232809Sjmallett uint64_t cntl_word_cnt : 27; /**< Number of control words received. Saturates. Interrupt on 2600232809Sjmallett saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2601232809Sjmallett uint64_t reserved_27_31 : 5; 2602232809Sjmallett uint64_t data_word_cnt : 27; /**< Number of data words received. Saturates. Interrupt on 2603232809Sjmallett saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2604232809Sjmallett#else 2605232809Sjmallett uint64_t data_word_cnt : 27; 2606232809Sjmallett uint64_t reserved_27_31 : 5; 2607232809Sjmallett uint64_t cntl_word_cnt : 27; 2608232809Sjmallett uint64_t reserved_59_63 : 5; 2609232809Sjmallett#endif 2610232809Sjmallett } s; 2611232809Sjmallett struct cvmx_ilk_rx_lnex_stat4_s cn68xx; 2612232809Sjmallett struct cvmx_ilk_rx_lnex_stat4_s cn68xxp1; 2613232809Sjmallett}; 2614232809Sjmalletttypedef union cvmx_ilk_rx_lnex_stat4 cvmx_ilk_rx_lnex_stat4_t; 2615232809Sjmallett 2616232809Sjmallett/** 2617232809Sjmallett * cvmx_ilk_rx_lne#_stat5 2618232809Sjmallett */ 2619232809Sjmallettunion cvmx_ilk_rx_lnex_stat5 { 2620232809Sjmallett uint64_t u64; 2621232809Sjmallett struct cvmx_ilk_rx_lnex_stat5_s { 2622232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2623232809Sjmallett uint64_t reserved_18_63 : 46; 2624232809Sjmallett uint64_t unkwn_word_cnt : 18; /**< Number of unknown control words. Saturates. Interrupt on 2625232809Sjmallett saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2626232809Sjmallett#else 2627232809Sjmallett uint64_t unkwn_word_cnt : 18; 2628232809Sjmallett uint64_t reserved_18_63 : 46; 2629232809Sjmallett#endif 2630232809Sjmallett } s; 2631232809Sjmallett struct cvmx_ilk_rx_lnex_stat5_s cn68xx; 2632232809Sjmallett struct cvmx_ilk_rx_lnex_stat5_s cn68xxp1; 2633232809Sjmallett}; 2634232809Sjmalletttypedef union cvmx_ilk_rx_lnex_stat5 cvmx_ilk_rx_lnex_stat5_t; 2635232809Sjmallett 2636232809Sjmallett/** 2637232809Sjmallett * cvmx_ilk_rx_lne#_stat6 2638232809Sjmallett */ 2639232809Sjmallettunion cvmx_ilk_rx_lnex_stat6 { 2640232809Sjmallett uint64_t u64; 2641232809Sjmallett struct cvmx_ilk_rx_lnex_stat6_s { 2642232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2643232809Sjmallett uint64_t reserved_18_63 : 46; 2644232809Sjmallett uint64_t scrm_sync_loss_cnt : 18; /**< Number of times scrambler synchronization was lost (due to 2645232809Sjmallett either 4 consecutive bad sync words or 3 consecutive scrambler 2646232809Sjmallett state mismatches). Saturates. Interrupt on saturation if 2647232809Sjmallett ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2648232809Sjmallett#else 2649232809Sjmallett uint64_t scrm_sync_loss_cnt : 18; 2650232809Sjmallett uint64_t reserved_18_63 : 46; 2651232809Sjmallett#endif 2652232809Sjmallett } s; 2653232809Sjmallett struct cvmx_ilk_rx_lnex_stat6_s cn68xx; 2654232809Sjmallett struct cvmx_ilk_rx_lnex_stat6_s cn68xxp1; 2655232809Sjmallett}; 2656232809Sjmalletttypedef union cvmx_ilk_rx_lnex_stat6 cvmx_ilk_rx_lnex_stat6_t; 2657232809Sjmallett 2658232809Sjmallett/** 2659232809Sjmallett * cvmx_ilk_rx_lne#_stat7 2660232809Sjmallett */ 2661232809Sjmallettunion cvmx_ilk_rx_lnex_stat7 { 2662232809Sjmallett uint64_t u64; 2663232809Sjmallett struct cvmx_ilk_rx_lnex_stat7_s { 2664232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2665232809Sjmallett uint64_t reserved_18_63 : 46; 2666232809Sjmallett uint64_t scrm_match_cnt : 18; /**< Number of scrambler state matches received. Saturates. 2667232809Sjmallett Interrupt on saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2668232809Sjmallett#else 2669232809Sjmallett uint64_t scrm_match_cnt : 18; 2670232809Sjmallett uint64_t reserved_18_63 : 46; 2671232809Sjmallett#endif 2672232809Sjmallett } s; 2673232809Sjmallett struct cvmx_ilk_rx_lnex_stat7_s cn68xx; 2674232809Sjmallett struct cvmx_ilk_rx_lnex_stat7_s cn68xxp1; 2675232809Sjmallett}; 2676232809Sjmalletttypedef union cvmx_ilk_rx_lnex_stat7 cvmx_ilk_rx_lnex_stat7_t; 2677232809Sjmallett 2678232809Sjmallett/** 2679232809Sjmallett * cvmx_ilk_rx_lne#_stat8 2680232809Sjmallett */ 2681232809Sjmallettunion cvmx_ilk_rx_lnex_stat8 { 2682232809Sjmallett uint64_t u64; 2683232809Sjmallett struct cvmx_ilk_rx_lnex_stat8_s { 2684232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2685232809Sjmallett uint64_t reserved_18_63 : 46; 2686232809Sjmallett uint64_t skipw_good_cnt : 18; /**< Number of good skip words. Saturates. Interrupt on saturation 2687232809Sjmallett if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2688232809Sjmallett#else 2689232809Sjmallett uint64_t skipw_good_cnt : 18; 2690232809Sjmallett uint64_t reserved_18_63 : 46; 2691232809Sjmallett#endif 2692232809Sjmallett } s; 2693232809Sjmallett struct cvmx_ilk_rx_lnex_stat8_s cn68xx; 2694232809Sjmallett struct cvmx_ilk_rx_lnex_stat8_s cn68xxp1; 2695232809Sjmallett}; 2696232809Sjmalletttypedef union cvmx_ilk_rx_lnex_stat8 cvmx_ilk_rx_lnex_stat8_t; 2697232809Sjmallett 2698232809Sjmallett/** 2699232809Sjmallett * cvmx_ilk_rx_lne#_stat9 2700232809Sjmallett */ 2701232809Sjmallettunion cvmx_ilk_rx_lnex_stat9 { 2702232809Sjmallett uint64_t u64; 2703232809Sjmallett struct cvmx_ilk_rx_lnex_stat9_s { 2704232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2705232809Sjmallett uint64_t reserved_50_63 : 14; 2706232809Sjmallett uint64_t crc32_err_cnt : 18; /**< Number of errors in the lane CRC. Saturates. Interrupt on 2707232809Sjmallett saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2708232809Sjmallett uint64_t reserved_27_31 : 5; 2709232809Sjmallett uint64_t crc32_match_cnt : 27; /**< Number of CRC32 matches received. Saturates. Interrupt on 2710232809Sjmallett saturation if ILK_RX_LNEX_INT_EN[STAT_CNT_OVFL]=1 */ 2711232809Sjmallett#else 2712232809Sjmallett uint64_t crc32_match_cnt : 27; 2713232809Sjmallett uint64_t reserved_27_31 : 5; 2714232809Sjmallett uint64_t crc32_err_cnt : 18; 2715232809Sjmallett uint64_t reserved_50_63 : 14; 2716232809Sjmallett#endif 2717232809Sjmallett } s; 2718232809Sjmallett struct cvmx_ilk_rx_lnex_stat9_s cn68xx; 2719232809Sjmallett struct cvmx_ilk_rx_lnex_stat9_s cn68xxp1; 2720232809Sjmallett}; 2721232809Sjmalletttypedef union cvmx_ilk_rx_lnex_stat9 cvmx_ilk_rx_lnex_stat9_t; 2722232809Sjmallett 2723232809Sjmallett/** 2724232809Sjmallett * cvmx_ilk_rxf_idx_pmap 2725232809Sjmallett */ 2726232809Sjmallettunion cvmx_ilk_rxf_idx_pmap { 2727232809Sjmallett uint64_t u64; 2728232809Sjmallett struct cvmx_ilk_rxf_idx_pmap_s { 2729232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2730232809Sjmallett uint64_t reserved_25_63 : 39; 2731232809Sjmallett uint64_t inc : 9; /**< Increment to add to current index for next index. */ 2732232809Sjmallett uint64_t reserved_9_15 : 7; 2733232809Sjmallett uint64_t index : 9; /**< Specify the link/channel accessed by the next CSR read/write to 2734232809Sjmallett port map memory. IDX[8]=link, IDX[7:0]=channel */ 2735232809Sjmallett#else 2736232809Sjmallett uint64_t index : 9; 2737232809Sjmallett uint64_t reserved_9_15 : 7; 2738232809Sjmallett uint64_t inc : 9; 2739232809Sjmallett uint64_t reserved_25_63 : 39; 2740232809Sjmallett#endif 2741232809Sjmallett } s; 2742232809Sjmallett struct cvmx_ilk_rxf_idx_pmap_s cn68xx; 2743232809Sjmallett struct cvmx_ilk_rxf_idx_pmap_s cn68xxp1; 2744232809Sjmallett}; 2745232809Sjmalletttypedef union cvmx_ilk_rxf_idx_pmap cvmx_ilk_rxf_idx_pmap_t; 2746232809Sjmallett 2747232809Sjmallett/** 2748232809Sjmallett * cvmx_ilk_rxf_mem_pmap 2749232809Sjmallett */ 2750232809Sjmallettunion cvmx_ilk_rxf_mem_pmap { 2751232809Sjmallett uint64_t u64; 2752232809Sjmallett struct cvmx_ilk_rxf_mem_pmap_s { 2753232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2754232809Sjmallett uint64_t reserved_6_63 : 58; 2755232809Sjmallett uint64_t port_kind : 6; /**< Specify the port-kind for the link/channel selected by 2756232809Sjmallett ILK_IDX_PMAP[IDX] */ 2757232809Sjmallett#else 2758232809Sjmallett uint64_t port_kind : 6; 2759232809Sjmallett uint64_t reserved_6_63 : 58; 2760232809Sjmallett#endif 2761232809Sjmallett } s; 2762232809Sjmallett struct cvmx_ilk_rxf_mem_pmap_s cn68xx; 2763232809Sjmallett struct cvmx_ilk_rxf_mem_pmap_s cn68xxp1; 2764232809Sjmallett}; 2765232809Sjmalletttypedef union cvmx_ilk_rxf_mem_pmap cvmx_ilk_rxf_mem_pmap_t; 2766232809Sjmallett 2767232809Sjmallett/** 2768232809Sjmallett * cvmx_ilk_ser_cfg 2769232809Sjmallett */ 2770232809Sjmallettunion cvmx_ilk_ser_cfg { 2771232809Sjmallett uint64_t u64; 2772232809Sjmallett struct cvmx_ilk_ser_cfg_s { 2773232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2774232809Sjmallett uint64_t reserved_57_63 : 7; 2775232809Sjmallett uint64_t ser_rxpol_auto : 1; /**< Serdes lane receive polarity auto detection mode */ 2776232809Sjmallett uint64_t reserved_48_55 : 8; 2777232809Sjmallett uint64_t ser_rxpol : 8; /**< Serdes lane receive polarity 2778232809Sjmallett - 0: rx without inversion 2779232809Sjmallett - 1: rx with inversion */ 2780232809Sjmallett uint64_t reserved_32_39 : 8; 2781232809Sjmallett uint64_t ser_txpol : 8; /**< Serdes lane transmit polarity 2782232809Sjmallett - 0: tx without inversion 2783232809Sjmallett - 1: tx with inversion */ 2784232809Sjmallett uint64_t reserved_16_23 : 8; 2785232809Sjmallett uint64_t ser_reset_n : 8; /**< Serdes lane reset */ 2786232809Sjmallett uint64_t reserved_6_7 : 2; 2787232809Sjmallett uint64_t ser_pwrup : 2; /**< Serdes modules (QLM) power up. */ 2788232809Sjmallett uint64_t reserved_2_3 : 2; 2789232809Sjmallett uint64_t ser_haul : 2; /**< Serdes module (QLM) haul mode */ 2790232809Sjmallett#else 2791232809Sjmallett uint64_t ser_haul : 2; 2792232809Sjmallett uint64_t reserved_2_3 : 2; 2793232809Sjmallett uint64_t ser_pwrup : 2; 2794232809Sjmallett uint64_t reserved_6_7 : 2; 2795232809Sjmallett uint64_t ser_reset_n : 8; 2796232809Sjmallett uint64_t reserved_16_23 : 8; 2797232809Sjmallett uint64_t ser_txpol : 8; 2798232809Sjmallett uint64_t reserved_32_39 : 8; 2799232809Sjmallett uint64_t ser_rxpol : 8; 2800232809Sjmallett uint64_t reserved_48_55 : 8; 2801232809Sjmallett uint64_t ser_rxpol_auto : 1; 2802232809Sjmallett uint64_t reserved_57_63 : 7; 2803232809Sjmallett#endif 2804232809Sjmallett } s; 2805232809Sjmallett struct cvmx_ilk_ser_cfg_s cn68xx; 2806232809Sjmallett struct cvmx_ilk_ser_cfg_s cn68xxp1; 2807232809Sjmallett}; 2808232809Sjmalletttypedef union cvmx_ilk_ser_cfg cvmx_ilk_ser_cfg_t; 2809232809Sjmallett 2810232809Sjmallett/** 2811232809Sjmallett * cvmx_ilk_tx#_cfg0 2812232809Sjmallett */ 2813232809Sjmallettunion cvmx_ilk_txx_cfg0 { 2814232809Sjmallett uint64_t u64; 2815232809Sjmallett struct cvmx_ilk_txx_cfg0_s { 2816232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2817232809Sjmallett uint64_t ext_lpbk_fc : 1; /**< Enable Rx-Tx flowcontrol loopback (external) */ 2818232809Sjmallett uint64_t ext_lpbk : 1; /**< Enable Rx-Tx data loopback (external). Note that with differing 2819232809Sjmallett transmit & receive clocks, skip word are inserted/deleted */ 2820232809Sjmallett uint64_t int_lpbk : 1; /**< Enable Tx-Rx loopback (internal) */ 2821232809Sjmallett uint64_t reserved_57_60 : 4; 2822232809Sjmallett uint64_t ptrn_mode : 1; /**< Enable programmable test pattern mode. This mode allows 2823232809Sjmallett software to send a packet containing a programmable pattern. 2824232809Sjmallett While in this mode, the scramblers and disparity inversion will 2825232809Sjmallett be disabled. In addition, no framing layer control words will 2826232809Sjmallett be transmitted (ie. no SYNC, scrambler state, skip, or 2827232809Sjmallett diagnostic words will be transmitted). 2828232809Sjmallett 2829232809Sjmallett NOTE: Software must first write ILK_TXX_CFG0[LANE_ENA]=0 before 2830232809Sjmallett enabling/disabling this mode. */ 2831232809Sjmallett uint64_t reserved_55_55 : 1; 2832232809Sjmallett uint64_t lnk_stats_ena : 1; /**< Enable link statistics counters */ 2833232809Sjmallett uint64_t mltuse_fc_ena : 1; /**< When set, the multi-use field of control words will contain 2834232809Sjmallett flow control status. Otherwise, the multi-use field will 2835232809Sjmallett contain ILK_TXX_CFG1[TX_MLTUSE] */ 2836232809Sjmallett uint64_t cal_ena : 1; /**< Enable Tx calendar, else default calendar used: 2837232809Sjmallett First control word: 2838232809Sjmallett Entry 0 = link 2839232809Sjmallett Entry 1 = backpressue id 0 2840232809Sjmallett Entry 2 = backpressue id 1 2841232809Sjmallett ...etc. 2842232809Sjmallett Second control word: 2843232809Sjmallett Entry 15 = link 2844232809Sjmallett Entry 16 = backpressue id 15 2845232809Sjmallett Entry 17 = backpressue id 16 2846232809Sjmallett ...etc. 2847232809Sjmallett This continues until the status for all 64 backpressue ids gets 2848232809Sjmallett transmitted (ie. 0-68 calendar table entries). The remaining 3 2849232809Sjmallett calendar table entries (ie. 69-71) will always transmit XOFF. 2850232809Sjmallett 2851232809Sjmallett To disable backpressure completely, enable the calendar table 2852232809Sjmallett and program each calendar table entry to transmit XON */ 2853232809Sjmallett uint64_t mfrm_len : 13; /**< The quantity of data sent on each lane including one sync word, 2854232809Sjmallett scrambler state, diag word, zero or more skip words, and the 2855232809Sjmallett data payload. Must be large than ILK_TXX_CFG1[SKIP_CNT]+9. 2856232809Sjmallett Supported range:ILK_TXX_CFG1[SKIP_CNT]+9 < MFRM_LEN <= 4096) */ 2857232809Sjmallett uint64_t brst_shrt : 7; /**< Minimum interval between burst control words, as a multiple of 2858232809Sjmallett 8 bytes. Supported range from 8 bytes to 512 (ie. 0 < 2859232809Sjmallett BRST_SHRT <= 64) */ 2860232809Sjmallett uint64_t lane_rev : 1; /**< Lane reversal. When enabled, lane striping is performed from 2861232809Sjmallett most significant lane enabled to least significant lane 2862232809Sjmallett enabled. LANE_ENA must be zero before changing LANE_REV. */ 2863232809Sjmallett uint64_t brst_max : 5; /**< Maximum size of a data burst, as a multiple of 64 byte blocks. 2864232809Sjmallett Supported range is from 64 bytes to 1024 bytes. (ie. 0 < 2865232809Sjmallett BRST_MAX <= 16) */ 2866232809Sjmallett uint64_t reserved_25_25 : 1; 2867232809Sjmallett uint64_t cal_depth : 9; /**< Number of valid entries in the calendar. CAL_DEPTH[2:0] must 2868232809Sjmallett be zero. Supported range from 8 to 288. If CAL_ENA is 0, 2869232809Sjmallett this field has no effect and the calendar depth is 72 entries. */ 2870232809Sjmallett uint64_t reserved_8_15 : 8; 2871232809Sjmallett uint64_t lane_ena : 8; /**< Lane enable mask. Link is enabled if any lane is enabled. The 2872232809Sjmallett same lane should not be enabled in multiple ILK_TXx_CFG0. Each 2873232809Sjmallett bit of LANE_ENA maps to a TX lane (TLE) and a QLM lane. NOTE: 2874232809Sjmallett LANE_REV has no effect on this mapping. 2875232809Sjmallett 2876232809Sjmallett LANE_ENA[0] = TLE0 = QLM1 lane 0 2877232809Sjmallett LANE_ENA[1] = TLE1 = QLM1 lane 1 2878232809Sjmallett LANE_ENA[2] = TLE2 = QLM1 lane 2 2879232809Sjmallett LANE_ENA[3] = TLE3 = QLM1 lane 3 2880232809Sjmallett LANE_ENA[4] = TLE4 = QLM2 lane 0 2881232809Sjmallett LANE_ENA[5] = TLE5 = QLM2 lane 1 2882232809Sjmallett LANE_ENA[6] = TLE6 = QLM2 lane 2 2883232809Sjmallett LANE_ENA[7] = TLE7 = QLM2 lane 3 */ 2884232809Sjmallett#else 2885232809Sjmallett uint64_t lane_ena : 8; 2886232809Sjmallett uint64_t reserved_8_15 : 8; 2887232809Sjmallett uint64_t cal_depth : 9; 2888232809Sjmallett uint64_t reserved_25_25 : 1; 2889232809Sjmallett uint64_t brst_max : 5; 2890232809Sjmallett uint64_t lane_rev : 1; 2891232809Sjmallett uint64_t brst_shrt : 7; 2892232809Sjmallett uint64_t mfrm_len : 13; 2893232809Sjmallett uint64_t cal_ena : 1; 2894232809Sjmallett uint64_t mltuse_fc_ena : 1; 2895232809Sjmallett uint64_t lnk_stats_ena : 1; 2896232809Sjmallett uint64_t reserved_55_55 : 1; 2897232809Sjmallett uint64_t ptrn_mode : 1; 2898232809Sjmallett uint64_t reserved_57_60 : 4; 2899232809Sjmallett uint64_t int_lpbk : 1; 2900232809Sjmallett uint64_t ext_lpbk : 1; 2901232809Sjmallett uint64_t ext_lpbk_fc : 1; 2902232809Sjmallett#endif 2903232809Sjmallett } s; 2904232809Sjmallett struct cvmx_ilk_txx_cfg0_s cn68xx; 2905232809Sjmallett struct cvmx_ilk_txx_cfg0_s cn68xxp1; 2906232809Sjmallett}; 2907232809Sjmalletttypedef union cvmx_ilk_txx_cfg0 cvmx_ilk_txx_cfg0_t; 2908232809Sjmallett 2909232809Sjmallett/** 2910232809Sjmallett * cvmx_ilk_tx#_cfg1 2911232809Sjmallett */ 2912232809Sjmallettunion cvmx_ilk_txx_cfg1 { 2913232809Sjmallett uint64_t u64; 2914232809Sjmallett struct cvmx_ilk_txx_cfg1_s { 2915232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2916232809Sjmallett uint64_t reserved_33_63 : 31; 2917232809Sjmallett uint64_t pkt_busy : 1; /**< Tx-Link is transmitting data. */ 2918232809Sjmallett uint64_t pipe_crd_dis : 1; /**< Disable pipe credits. Should be set when PKO is configure to 2919232809Sjmallett ignore pipe credits. */ 2920232809Sjmallett uint64_t ptp_delay : 5; /**< Timestamp commit delay. Must not be zero. */ 2921232809Sjmallett uint64_t skip_cnt : 4; /**< Number of skip words to insert after the scrambler state */ 2922232809Sjmallett uint64_t pkt_flush : 1; /**< Packet transmit flush. While PKT_FLUSH=1, the TxFifo will 2923232809Sjmallett continuously drain; all data will be dropped. Software should 2924232809Sjmallett first write PKT_ENA=0 and wait packet transmission to stop. */ 2925232809Sjmallett uint64_t pkt_ena : 1; /**< Packet transmit enable. When PKT_ENA=0, the Tx-Link will stop 2926232809Sjmallett transmitting packets, as per RX_LINK_FC_PKT */ 2927232809Sjmallett uint64_t la_mode : 1; /**< 0 = Interlaken 2928232809Sjmallett 1 = Interlaken Look-Aside */ 2929232809Sjmallett uint64_t tx_link_fc : 1; /**< Link flow control status transmitted by the Tx-Link 2930232809Sjmallett XON when RX_FIFO_CNT <= RX_FIFO_HWM and lane alignment is done */ 2931232809Sjmallett uint64_t rx_link_fc : 1; /**< Link flow control status received in burst/idle control words. 2932232809Sjmallett When RX_LINK_FC_IGN=0, XOFF will cause Tx-Link to stop 2933232809Sjmallett transmitting on all channels. */ 2934232809Sjmallett uint64_t reserved_12_16 : 5; 2935232809Sjmallett uint64_t tx_link_fc_jam : 1; /**< All flow control transmitted in burst/idle control words will 2936232809Sjmallett be XOFF whenever TX_LINK_FC is XOFF. Enable this to allow 2937232809Sjmallett link XOFF to automatically XOFF all channels. */ 2938232809Sjmallett uint64_t rx_link_fc_pkt : 1; /**< Link flow control received in burst/idle control words causes 2939232809Sjmallett Tx-Link to stop transmitting at the end of a packet instead of 2940232809Sjmallett the end of a burst */ 2941232809Sjmallett uint64_t rx_link_fc_ign : 1; /**< Ignore the link flow control status received in burst/idle 2942232809Sjmallett control words */ 2943232809Sjmallett uint64_t rmatch : 1; /**< Enable rate matching circuitry */ 2944232809Sjmallett uint64_t tx_mltuse : 8; /**< Multiple Use bits used when ILKx_TX_CFG[LA_MODE=0] and 2945232809Sjmallett ILKx_TX_CFG[MLTUSE_FC_ENA] is zero */ 2946232809Sjmallett#else 2947232809Sjmallett uint64_t tx_mltuse : 8; 2948232809Sjmallett uint64_t rmatch : 1; 2949232809Sjmallett uint64_t rx_link_fc_ign : 1; 2950232809Sjmallett uint64_t rx_link_fc_pkt : 1; 2951232809Sjmallett uint64_t tx_link_fc_jam : 1; 2952232809Sjmallett uint64_t reserved_12_16 : 5; 2953232809Sjmallett uint64_t rx_link_fc : 1; 2954232809Sjmallett uint64_t tx_link_fc : 1; 2955232809Sjmallett uint64_t la_mode : 1; 2956232809Sjmallett uint64_t pkt_ena : 1; 2957232809Sjmallett uint64_t pkt_flush : 1; 2958232809Sjmallett uint64_t skip_cnt : 4; 2959232809Sjmallett uint64_t ptp_delay : 5; 2960232809Sjmallett uint64_t pipe_crd_dis : 1; 2961232809Sjmallett uint64_t pkt_busy : 1; 2962232809Sjmallett uint64_t reserved_33_63 : 31; 2963232809Sjmallett#endif 2964232809Sjmallett } s; 2965232809Sjmallett struct cvmx_ilk_txx_cfg1_s cn68xx; 2966232809Sjmallett struct cvmx_ilk_txx_cfg1_cn68xxp1 { 2967232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2968232809Sjmallett uint64_t reserved_32_63 : 32; 2969232809Sjmallett uint64_t pipe_crd_dis : 1; /**< Disable pipe credits. Should be set when PKO is configure to 2970232809Sjmallett ignore pipe credits. */ 2971232809Sjmallett uint64_t ptp_delay : 5; /**< Timestamp commit delay. Must not be zero. */ 2972232809Sjmallett uint64_t skip_cnt : 4; /**< Number of skip words to insert after the scrambler state */ 2973232809Sjmallett uint64_t pkt_flush : 1; /**< Packet transmit flush. While PKT_FLUSH=1, the TxFifo will 2974232809Sjmallett continuously drain; all data will be dropped. Software should 2975232809Sjmallett first write PKT_ENA=0 and wait packet transmission to stop. */ 2976232809Sjmallett uint64_t pkt_ena : 1; /**< Packet transmit enable. When PKT_ENA=0, the Tx-Link will stop 2977232809Sjmallett transmitting packets, as per RX_LINK_FC_PKT */ 2978232809Sjmallett uint64_t la_mode : 1; /**< 0 = Interlaken 2979232809Sjmallett 1 = Interlaken Look-Aside */ 2980232809Sjmallett uint64_t tx_link_fc : 1; /**< Link flow control status transmitted by the Tx-Link 2981232809Sjmallett XON when RX_FIFO_CNT <= RX_FIFO_HWM and lane alignment is done */ 2982232809Sjmallett uint64_t rx_link_fc : 1; /**< Link flow control status received in burst/idle control words. 2983232809Sjmallett When RX_LINK_FC_IGN=0, XOFF will cause Tx-Link to stop 2984232809Sjmallett transmitting on all channels. */ 2985232809Sjmallett uint64_t reserved_12_16 : 5; 2986232809Sjmallett uint64_t tx_link_fc_jam : 1; /**< All flow control transmitted in burst/idle control words will 2987232809Sjmallett be XOFF whenever TX_LINK_FC is XOFF. Enable this to allow 2988232809Sjmallett link XOFF to automatically XOFF all channels. */ 2989232809Sjmallett uint64_t rx_link_fc_pkt : 1; /**< Link flow control received in burst/idle control words causes 2990232809Sjmallett Tx-Link to stop transmitting at the end of a packet instead of 2991232809Sjmallett the end of a burst */ 2992232809Sjmallett uint64_t rx_link_fc_ign : 1; /**< Ignore the link flow control status received in burst/idle 2993232809Sjmallett control words */ 2994232809Sjmallett uint64_t rmatch : 1; /**< Enable rate matching circuitry */ 2995232809Sjmallett uint64_t tx_mltuse : 8; /**< Multiple Use bits used when ILKx_TX_CFG[LA_MODE=0] and 2996232809Sjmallett ILKx_TX_CFG[MLTUSE_FC_ENA] is zero */ 2997232809Sjmallett#else 2998232809Sjmallett uint64_t tx_mltuse : 8; 2999232809Sjmallett uint64_t rmatch : 1; 3000232809Sjmallett uint64_t rx_link_fc_ign : 1; 3001232809Sjmallett uint64_t rx_link_fc_pkt : 1; 3002232809Sjmallett uint64_t tx_link_fc_jam : 1; 3003232809Sjmallett uint64_t reserved_12_16 : 5; 3004232809Sjmallett uint64_t rx_link_fc : 1; 3005232809Sjmallett uint64_t tx_link_fc : 1; 3006232809Sjmallett uint64_t la_mode : 1; 3007232809Sjmallett uint64_t pkt_ena : 1; 3008232809Sjmallett uint64_t pkt_flush : 1; 3009232809Sjmallett uint64_t skip_cnt : 4; 3010232809Sjmallett uint64_t ptp_delay : 5; 3011232809Sjmallett uint64_t pipe_crd_dis : 1; 3012232809Sjmallett uint64_t reserved_32_63 : 32; 3013232809Sjmallett#endif 3014232809Sjmallett } cn68xxp1; 3015232809Sjmallett}; 3016232809Sjmalletttypedef union cvmx_ilk_txx_cfg1 cvmx_ilk_txx_cfg1_t; 3017232809Sjmallett 3018232809Sjmallett/** 3019232809Sjmallett * cvmx_ilk_tx#_dbg 3020232809Sjmallett */ 3021232809Sjmallettunion cvmx_ilk_txx_dbg { 3022232809Sjmallett uint64_t u64; 3023232809Sjmallett struct cvmx_ilk_txx_dbg_s { 3024232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3025232809Sjmallett uint64_t reserved_3_63 : 61; 3026232809Sjmallett uint64_t tx_bad_crc24 : 1; /**< Send a control word with bad CRC24. Hardware will clear this 3027232809Sjmallett field once the injection is performed. */ 3028232809Sjmallett uint64_t tx_bad_ctlw2 : 1; /**< Send a control word without the control bit set */ 3029232809Sjmallett uint64_t tx_bad_ctlw1 : 1; /**< Send a data word with the control bit set */ 3030232809Sjmallett#else 3031232809Sjmallett uint64_t tx_bad_ctlw1 : 1; 3032232809Sjmallett uint64_t tx_bad_ctlw2 : 1; 3033232809Sjmallett uint64_t tx_bad_crc24 : 1; 3034232809Sjmallett uint64_t reserved_3_63 : 61; 3035232809Sjmallett#endif 3036232809Sjmallett } s; 3037232809Sjmallett struct cvmx_ilk_txx_dbg_s cn68xx; 3038232809Sjmallett struct cvmx_ilk_txx_dbg_s cn68xxp1; 3039232809Sjmallett}; 3040232809Sjmalletttypedef union cvmx_ilk_txx_dbg cvmx_ilk_txx_dbg_t; 3041232809Sjmallett 3042232809Sjmallett/** 3043232809Sjmallett * cvmx_ilk_tx#_flow_ctl0 3044232809Sjmallett */ 3045232809Sjmallettunion cvmx_ilk_txx_flow_ctl0 { 3046232809Sjmallett uint64_t u64; 3047232809Sjmallett struct cvmx_ilk_txx_flow_ctl0_s { 3048232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3049232809Sjmallett uint64_t status : 64; /**< IPD flow control status for backpressue id 63-0, where a 0 3050232809Sjmallett indicates the presence of backpressure (ie. XOFF) and 1 3051232809Sjmallett indicates the absence of backpressure (ie. XON) */ 3052232809Sjmallett#else 3053232809Sjmallett uint64_t status : 64; 3054232809Sjmallett#endif 3055232809Sjmallett } s; 3056232809Sjmallett struct cvmx_ilk_txx_flow_ctl0_s cn68xx; 3057232809Sjmallett struct cvmx_ilk_txx_flow_ctl0_s cn68xxp1; 3058232809Sjmallett}; 3059232809Sjmalletttypedef union cvmx_ilk_txx_flow_ctl0 cvmx_ilk_txx_flow_ctl0_t; 3060232809Sjmallett 3061232809Sjmallett/** 3062232809Sjmallett * cvmx_ilk_tx#_flow_ctl1 3063232809Sjmallett * 3064232809Sjmallett * Notes: 3065232809Sjmallett * Do not publish. 3066232809Sjmallett * 3067232809Sjmallett */ 3068232809Sjmallettunion cvmx_ilk_txx_flow_ctl1 { 3069232809Sjmallett uint64_t u64; 3070232809Sjmallett struct cvmx_ilk_txx_flow_ctl1_s { 3071232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3072232809Sjmallett uint64_t reserved_0_63 : 64; 3073232809Sjmallett#else 3074232809Sjmallett uint64_t reserved_0_63 : 64; 3075232809Sjmallett#endif 3076232809Sjmallett } s; 3077232809Sjmallett struct cvmx_ilk_txx_flow_ctl1_s cn68xx; 3078232809Sjmallett struct cvmx_ilk_txx_flow_ctl1_s cn68xxp1; 3079232809Sjmallett}; 3080232809Sjmalletttypedef union cvmx_ilk_txx_flow_ctl1 cvmx_ilk_txx_flow_ctl1_t; 3081232809Sjmallett 3082232809Sjmallett/** 3083232809Sjmallett * cvmx_ilk_tx#_idx_cal 3084232809Sjmallett */ 3085232809Sjmallettunion cvmx_ilk_txx_idx_cal { 3086232809Sjmallett uint64_t u64; 3087232809Sjmallett struct cvmx_ilk_txx_idx_cal_s { 3088232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3089232809Sjmallett uint64_t reserved_14_63 : 50; 3090232809Sjmallett uint64_t inc : 6; /**< Increment to add to current index for next index. NOTE: 3091232809Sjmallett Increment only performed after *MEM_CAL1 access (ie. not 3092232809Sjmallett *MEM_CAL0) */ 3093232809Sjmallett uint64_t reserved_6_7 : 2; 3094232809Sjmallett uint64_t index : 6; /**< Specify the group of 8 entries accessed by the next CSR 3095232809Sjmallett read/write to calendar table memory. Software must ensure IDX 3096232809Sjmallett is <36 whenever writing to *MEM_CAL1 */ 3097232809Sjmallett#else 3098232809Sjmallett uint64_t index : 6; 3099232809Sjmallett uint64_t reserved_6_7 : 2; 3100232809Sjmallett uint64_t inc : 6; 3101232809Sjmallett uint64_t reserved_14_63 : 50; 3102232809Sjmallett#endif 3103232809Sjmallett } s; 3104232809Sjmallett struct cvmx_ilk_txx_idx_cal_s cn68xx; 3105232809Sjmallett struct cvmx_ilk_txx_idx_cal_s cn68xxp1; 3106232809Sjmallett}; 3107232809Sjmalletttypedef union cvmx_ilk_txx_idx_cal cvmx_ilk_txx_idx_cal_t; 3108232809Sjmallett 3109232809Sjmallett/** 3110232809Sjmallett * cvmx_ilk_tx#_idx_pmap 3111232809Sjmallett */ 3112232809Sjmallettunion cvmx_ilk_txx_idx_pmap { 3113232809Sjmallett uint64_t u64; 3114232809Sjmallett struct cvmx_ilk_txx_idx_pmap_s { 3115232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3116232809Sjmallett uint64_t reserved_23_63 : 41; 3117232809Sjmallett uint64_t inc : 7; /**< Increment to add to current index for next index. */ 3118232809Sjmallett uint64_t reserved_7_15 : 9; 3119232809Sjmallett uint64_t index : 7; /**< Specify the port-pipe accessed by the next CSR read/write to 3120232809Sjmallett ILK_TXx_MEM_PMAP. Note that IDX=n is always port-pipe n, 3121232809Sjmallett regardless of ILK_TXx_PIPE[BASE] */ 3122232809Sjmallett#else 3123232809Sjmallett uint64_t index : 7; 3124232809Sjmallett uint64_t reserved_7_15 : 9; 3125232809Sjmallett uint64_t inc : 7; 3126232809Sjmallett uint64_t reserved_23_63 : 41; 3127232809Sjmallett#endif 3128232809Sjmallett } s; 3129232809Sjmallett struct cvmx_ilk_txx_idx_pmap_s cn68xx; 3130232809Sjmallett struct cvmx_ilk_txx_idx_pmap_s cn68xxp1; 3131232809Sjmallett}; 3132232809Sjmalletttypedef union cvmx_ilk_txx_idx_pmap cvmx_ilk_txx_idx_pmap_t; 3133232809Sjmallett 3134232809Sjmallett/** 3135232809Sjmallett * cvmx_ilk_tx#_idx_stat0 3136232809Sjmallett */ 3137232809Sjmallettunion cvmx_ilk_txx_idx_stat0 { 3138232809Sjmallett uint64_t u64; 3139232809Sjmallett struct cvmx_ilk_txx_idx_stat0_s { 3140232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3141232809Sjmallett uint64_t reserved_32_63 : 32; 3142232809Sjmallett uint64_t clr : 1; /**< CSR read to ILK_TXx_MEM_STAT0 clears the selected counter after 3143232809Sjmallett returning its current value. */ 3144232809Sjmallett uint64_t reserved_24_30 : 7; 3145232809Sjmallett uint64_t inc : 8; /**< Increment to add to current index for next index */ 3146232809Sjmallett uint64_t reserved_8_15 : 8; 3147232809Sjmallett uint64_t index : 8; /**< Specify the channel accessed during the next CSR read to the 3148232809Sjmallett ILK_TXx_MEM_STAT0 */ 3149232809Sjmallett#else 3150232809Sjmallett uint64_t index : 8; 3151232809Sjmallett uint64_t reserved_8_15 : 8; 3152232809Sjmallett uint64_t inc : 8; 3153232809Sjmallett uint64_t reserved_24_30 : 7; 3154232809Sjmallett uint64_t clr : 1; 3155232809Sjmallett uint64_t reserved_32_63 : 32; 3156232809Sjmallett#endif 3157232809Sjmallett } s; 3158232809Sjmallett struct cvmx_ilk_txx_idx_stat0_s cn68xx; 3159232809Sjmallett struct cvmx_ilk_txx_idx_stat0_s cn68xxp1; 3160232809Sjmallett}; 3161232809Sjmalletttypedef union cvmx_ilk_txx_idx_stat0 cvmx_ilk_txx_idx_stat0_t; 3162232809Sjmallett 3163232809Sjmallett/** 3164232809Sjmallett * cvmx_ilk_tx#_idx_stat1 3165232809Sjmallett */ 3166232809Sjmallettunion cvmx_ilk_txx_idx_stat1 { 3167232809Sjmallett uint64_t u64; 3168232809Sjmallett struct cvmx_ilk_txx_idx_stat1_s { 3169232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3170232809Sjmallett uint64_t reserved_32_63 : 32; 3171232809Sjmallett uint64_t clr : 1; /**< CSR read to ILK_TXx_MEM_STAT1 clears the selected counter after 3172232809Sjmallett returning its current value. */ 3173232809Sjmallett uint64_t reserved_24_30 : 7; 3174232809Sjmallett uint64_t inc : 8; /**< Increment to add to current index for next index */ 3175232809Sjmallett uint64_t reserved_8_15 : 8; 3176232809Sjmallett uint64_t index : 8; /**< Specify the channel accessed during the next CSR read to the 3177232809Sjmallett ILK_TXx_MEM_STAT1 */ 3178232809Sjmallett#else 3179232809Sjmallett uint64_t index : 8; 3180232809Sjmallett uint64_t reserved_8_15 : 8; 3181232809Sjmallett uint64_t inc : 8; 3182232809Sjmallett uint64_t reserved_24_30 : 7; 3183232809Sjmallett uint64_t clr : 1; 3184232809Sjmallett uint64_t reserved_32_63 : 32; 3185232809Sjmallett#endif 3186232809Sjmallett } s; 3187232809Sjmallett struct cvmx_ilk_txx_idx_stat1_s cn68xx; 3188232809Sjmallett struct cvmx_ilk_txx_idx_stat1_s cn68xxp1; 3189232809Sjmallett}; 3190232809Sjmalletttypedef union cvmx_ilk_txx_idx_stat1 cvmx_ilk_txx_idx_stat1_t; 3191232809Sjmallett 3192232809Sjmallett/** 3193232809Sjmallett * cvmx_ilk_tx#_int 3194232809Sjmallett */ 3195232809Sjmallettunion cvmx_ilk_txx_int { 3196232809Sjmallett uint64_t u64; 3197232809Sjmallett struct cvmx_ilk_txx_int_s { 3198232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3199232809Sjmallett uint64_t reserved_4_63 : 60; 3200232809Sjmallett uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */ 3201232809Sjmallett uint64_t bad_pipe : 1; /**< Received a PKO port-pipe out of the range specified by 3202232809Sjmallett ILK_TXX_PIPE */ 3203232809Sjmallett uint64_t bad_seq : 1; /**< Received sequence is not SOP followed by 0 or more data cycles 3204232809Sjmallett followed by EOP. PKO config assigned multiple engines to the 3205232809Sjmallett same ILK Tx Link. */ 3206232809Sjmallett uint64_t txf_err : 1; /**< TX fifo parity error occurred. At EOP time, EOP_Format will 3207232809Sjmallett reflect the error. */ 3208232809Sjmallett#else 3209232809Sjmallett uint64_t txf_err : 1; 3210232809Sjmallett uint64_t bad_seq : 1; 3211232809Sjmallett uint64_t bad_pipe : 1; 3212232809Sjmallett uint64_t stat_cnt_ovfl : 1; 3213232809Sjmallett uint64_t reserved_4_63 : 60; 3214232809Sjmallett#endif 3215232809Sjmallett } s; 3216232809Sjmallett struct cvmx_ilk_txx_int_s cn68xx; 3217232809Sjmallett struct cvmx_ilk_txx_int_s cn68xxp1; 3218232809Sjmallett}; 3219232809Sjmalletttypedef union cvmx_ilk_txx_int cvmx_ilk_txx_int_t; 3220232809Sjmallett 3221232809Sjmallett/** 3222232809Sjmallett * cvmx_ilk_tx#_int_en 3223232809Sjmallett */ 3224232809Sjmallettunion cvmx_ilk_txx_int_en { 3225232809Sjmallett uint64_t u64; 3226232809Sjmallett struct cvmx_ilk_txx_int_en_s { 3227232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3228232809Sjmallett uint64_t reserved_4_63 : 60; 3229232809Sjmallett uint64_t stat_cnt_ovfl : 1; /**< Statistics counter overflow */ 3230232809Sjmallett uint64_t bad_pipe : 1; /**< Received a PKO port-pipe out of the range specified by 3231232809Sjmallett ILK_TXX_PIPE. */ 3232232809Sjmallett uint64_t bad_seq : 1; /**< Received sequence is not SOP followed by 0 or more data cycles 3233232809Sjmallett followed by EOP. PKO config assigned multiple engines to the 3234232809Sjmallett same ILK Tx Link. */ 3235232809Sjmallett uint64_t txf_err : 1; /**< TX fifo parity error occurred. At EOP time, EOP_Format will 3236232809Sjmallett reflect the error. */ 3237232809Sjmallett#else 3238232809Sjmallett uint64_t txf_err : 1; 3239232809Sjmallett uint64_t bad_seq : 1; 3240232809Sjmallett uint64_t bad_pipe : 1; 3241232809Sjmallett uint64_t stat_cnt_ovfl : 1; 3242232809Sjmallett uint64_t reserved_4_63 : 60; 3243232809Sjmallett#endif 3244232809Sjmallett } s; 3245232809Sjmallett struct cvmx_ilk_txx_int_en_s cn68xx; 3246232809Sjmallett struct cvmx_ilk_txx_int_en_s cn68xxp1; 3247232809Sjmallett}; 3248232809Sjmalletttypedef union cvmx_ilk_txx_int_en cvmx_ilk_txx_int_en_t; 3249232809Sjmallett 3250232809Sjmallett/** 3251232809Sjmallett * cvmx_ilk_tx#_mem_cal0 3252232809Sjmallett * 3253232809Sjmallett * Notes: 3254232809Sjmallett * Software must always read ILK_TXx_MEM_CAL0 then ILK_TXx_MEM_CAL1. Software 3255232809Sjmallett * must never read them in reverse order or read one without reading the 3256232809Sjmallett * other. 3257232809Sjmallett * 3258232809Sjmallett * Software must always write ILK_TXx_MEM_CAL0 then ILK_TXx_MEM_CAL1. 3259232809Sjmallett * Software must never write them in reverse order or write one without 3260232809Sjmallett * writing the other. 3261232809Sjmallett */ 3262232809Sjmallettunion cvmx_ilk_txx_mem_cal0 { 3263232809Sjmallett uint64_t u64; 3264232809Sjmallett struct cvmx_ilk_txx_mem_cal0_s { 3265232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3266232809Sjmallett uint64_t reserved_36_63 : 28; 3267232809Sjmallett uint64_t entry_ctl3 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+3 3268232809Sjmallett - 0: IPD backpressue id 3269232809Sjmallett - 1: Link 3270232809Sjmallett - 2: XOFF 3271232809Sjmallett - 3: XON */ 3272232809Sjmallett uint64_t reserved_33_33 : 1; 3273232809Sjmallett uint64_t bpid3 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+3 3274232809Sjmallett (unused if ENTRY_CTL3 != 0) */ 3275232809Sjmallett uint64_t entry_ctl2 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+2 3276232809Sjmallett - 0: IPD backpressue id 3277232809Sjmallett - 1: Link 3278232809Sjmallett - 2: XOFF 3279232809Sjmallett - 3: XON */ 3280232809Sjmallett uint64_t reserved_24_24 : 1; 3281232809Sjmallett uint64_t bpid2 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+2 3282232809Sjmallett (unused if ENTRY_CTL2 != 0) */ 3283232809Sjmallett uint64_t entry_ctl1 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+1 3284232809Sjmallett - 0: IPD backpressue id 3285232809Sjmallett - 1: Link 3286232809Sjmallett - 2: XOFF 3287232809Sjmallett - 3: XON */ 3288232809Sjmallett uint64_t reserved_15_15 : 1; 3289232809Sjmallett uint64_t bpid1 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+1 3290232809Sjmallett (unused if ENTRY_CTL1 != 0) */ 3291232809Sjmallett uint64_t entry_ctl0 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+0 3292232809Sjmallett - 0: IPD backpressue id 3293232809Sjmallett - 1: Link 3294232809Sjmallett - 2: XOFF 3295232809Sjmallett - 3: XON */ 3296232809Sjmallett uint64_t reserved_6_6 : 1; 3297232809Sjmallett uint64_t bpid0 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+0 3298232809Sjmallett (unused if ENTRY_CTL0 != 0) */ 3299232809Sjmallett#else 3300232809Sjmallett uint64_t bpid0 : 6; 3301232809Sjmallett uint64_t reserved_6_6 : 1; 3302232809Sjmallett uint64_t entry_ctl0 : 2; 3303232809Sjmallett uint64_t bpid1 : 6; 3304232809Sjmallett uint64_t reserved_15_15 : 1; 3305232809Sjmallett uint64_t entry_ctl1 : 2; 3306232809Sjmallett uint64_t bpid2 : 6; 3307232809Sjmallett uint64_t reserved_24_24 : 1; 3308232809Sjmallett uint64_t entry_ctl2 : 2; 3309232809Sjmallett uint64_t bpid3 : 6; 3310232809Sjmallett uint64_t reserved_33_33 : 1; 3311232809Sjmallett uint64_t entry_ctl3 : 2; 3312232809Sjmallett uint64_t reserved_36_63 : 28; 3313232809Sjmallett#endif 3314232809Sjmallett } s; 3315232809Sjmallett struct cvmx_ilk_txx_mem_cal0_s cn68xx; 3316232809Sjmallett struct cvmx_ilk_txx_mem_cal0_s cn68xxp1; 3317232809Sjmallett}; 3318232809Sjmalletttypedef union cvmx_ilk_txx_mem_cal0 cvmx_ilk_txx_mem_cal0_t; 3319232809Sjmallett 3320232809Sjmallett/** 3321232809Sjmallett * cvmx_ilk_tx#_mem_cal1 3322232809Sjmallett * 3323232809Sjmallett * Notes: 3324232809Sjmallett * Software must always read ILK_TXx_MEM_CAL0 then ILK_TXx_MEM_CAL1. Software 3325232809Sjmallett * must never read them in reverse order or read one without reading the 3326232809Sjmallett * other. 3327232809Sjmallett * 3328232809Sjmallett * Software must always write ILK_TXx_MEM_CAL0 then ILK_TXx_MEM_CAL1. 3329232809Sjmallett * Software must never write them in reverse order or write one without 3330232809Sjmallett * writing the other. 3331232809Sjmallett */ 3332232809Sjmallettunion cvmx_ilk_txx_mem_cal1 { 3333232809Sjmallett uint64_t u64; 3334232809Sjmallett struct cvmx_ilk_txx_mem_cal1_s { 3335232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3336232809Sjmallett uint64_t reserved_36_63 : 28; 3337232809Sjmallett uint64_t entry_ctl7 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+7 3338232809Sjmallett - 0: IPD backpressue id 3339232809Sjmallett - 1: Link 3340232809Sjmallett - 2: XOFF 3341232809Sjmallett - 3: XON */ 3342232809Sjmallett uint64_t reserved_33_33 : 1; 3343232809Sjmallett uint64_t bpid7 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+7 3344232809Sjmallett (unused if ENTRY_CTL7 != 0) */ 3345232809Sjmallett uint64_t entry_ctl6 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+6 3346232809Sjmallett - 0: IPD backpressue id 3347232809Sjmallett - 1: Link 3348232809Sjmallett - 2: XOFF 3349232809Sjmallett - 3: XON */ 3350232809Sjmallett uint64_t reserved_24_24 : 1; 3351232809Sjmallett uint64_t bpid6 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+6 3352232809Sjmallett (unused if ENTRY_CTL6 != 0) */ 3353232809Sjmallett uint64_t entry_ctl5 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+5 3354232809Sjmallett - 0: IPD backpressue id 3355232809Sjmallett - 1: Link 3356232809Sjmallett - 2: XOFF 3357232809Sjmallett - 3: XON */ 3358232809Sjmallett uint64_t reserved_15_15 : 1; 3359232809Sjmallett uint64_t bpid5 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+5 3360232809Sjmallett (unused if ENTRY_CTL5 != 0) */ 3361232809Sjmallett uint64_t entry_ctl4 : 2; /**< Select source of XON/XOFF for entry (IDX*8)+4 3362232809Sjmallett - 0: IPD backpressue id 3363232809Sjmallett - 1: Link 3364232809Sjmallett - 2: XOFF 3365232809Sjmallett - 3: XON */ 3366232809Sjmallett uint64_t reserved_6_6 : 1; 3367232809Sjmallett uint64_t bpid4 : 6; /**< Select IPD backpressue id for calendar table entry (IDX*8)+4 3368232809Sjmallett (unused if ENTRY_CTL4 != 0) */ 3369232809Sjmallett#else 3370232809Sjmallett uint64_t bpid4 : 6; 3371232809Sjmallett uint64_t reserved_6_6 : 1; 3372232809Sjmallett uint64_t entry_ctl4 : 2; 3373232809Sjmallett uint64_t bpid5 : 6; 3374232809Sjmallett uint64_t reserved_15_15 : 1; 3375232809Sjmallett uint64_t entry_ctl5 : 2; 3376232809Sjmallett uint64_t bpid6 : 6; 3377232809Sjmallett uint64_t reserved_24_24 : 1; 3378232809Sjmallett uint64_t entry_ctl6 : 2; 3379232809Sjmallett uint64_t bpid7 : 6; 3380232809Sjmallett uint64_t reserved_33_33 : 1; 3381232809Sjmallett uint64_t entry_ctl7 : 2; 3382232809Sjmallett uint64_t reserved_36_63 : 28; 3383232809Sjmallett#endif 3384232809Sjmallett } s; 3385232809Sjmallett struct cvmx_ilk_txx_mem_cal1_s cn68xx; 3386232809Sjmallett struct cvmx_ilk_txx_mem_cal1_s cn68xxp1; 3387232809Sjmallett}; 3388232809Sjmalletttypedef union cvmx_ilk_txx_mem_cal1 cvmx_ilk_txx_mem_cal1_t; 3389232809Sjmallett 3390232809Sjmallett/** 3391232809Sjmallett * cvmx_ilk_tx#_mem_pmap 3392232809Sjmallett */ 3393232809Sjmallettunion cvmx_ilk_txx_mem_pmap { 3394232809Sjmallett uint64_t u64; 3395232809Sjmallett struct cvmx_ilk_txx_mem_pmap_s { 3396232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3397232809Sjmallett uint64_t reserved_17_63 : 47; 3398232809Sjmallett uint64_t remap : 1; /**< Dynamically select channel using bits[39:32] of an 8-byte 3399232809Sjmallett header prepended to any packet transmitted on the port-pipe 3400232809Sjmallett selected by ILK_TXx_IDX_PMAP[IDX]. 3401232809Sjmallett 3402232809Sjmallett ***NOTE: Added in pass 2.0 */ 3403232809Sjmallett uint64_t reserved_8_15 : 8; 3404232809Sjmallett uint64_t channel : 8; /**< Specify the channel for the port-pipe selected by 3405232809Sjmallett ILK_TXx_IDX_PMAP[IDX] */ 3406232809Sjmallett#else 3407232809Sjmallett uint64_t channel : 8; 3408232809Sjmallett uint64_t reserved_8_15 : 8; 3409232809Sjmallett uint64_t remap : 1; 3410232809Sjmallett uint64_t reserved_17_63 : 47; 3411232809Sjmallett#endif 3412232809Sjmallett } s; 3413232809Sjmallett struct cvmx_ilk_txx_mem_pmap_s cn68xx; 3414232809Sjmallett struct cvmx_ilk_txx_mem_pmap_cn68xxp1 { 3415232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3416232809Sjmallett uint64_t reserved_8_63 : 56; 3417232809Sjmallett uint64_t channel : 8; /**< Specify the channel for the port-pipe selected by 3418232809Sjmallett ILK_TXx_IDX_PMAP[IDX] */ 3419232809Sjmallett#else 3420232809Sjmallett uint64_t channel : 8; 3421232809Sjmallett uint64_t reserved_8_63 : 56; 3422232809Sjmallett#endif 3423232809Sjmallett } cn68xxp1; 3424232809Sjmallett}; 3425232809Sjmalletttypedef union cvmx_ilk_txx_mem_pmap cvmx_ilk_txx_mem_pmap_t; 3426232809Sjmallett 3427232809Sjmallett/** 3428232809Sjmallett * cvmx_ilk_tx#_mem_stat0 3429232809Sjmallett */ 3430232809Sjmallettunion cvmx_ilk_txx_mem_stat0 { 3431232809Sjmallett uint64_t u64; 3432232809Sjmallett struct cvmx_ilk_txx_mem_stat0_s { 3433232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3434232809Sjmallett uint64_t reserved_28_63 : 36; 3435232809Sjmallett uint64_t tx_pkt : 28; /**< Number of packets transmitted per channel (256M) 3436232809Sjmallett Channel selected by ILK_TXx_IDX_STAT0[IDX]. Interrupt on 3437232809Sjmallett saturation if ILK_TXX_INT_EN[STAT_CNT_OVFL]=1. */ 3438232809Sjmallett#else 3439232809Sjmallett uint64_t tx_pkt : 28; 3440232809Sjmallett uint64_t reserved_28_63 : 36; 3441232809Sjmallett#endif 3442232809Sjmallett } s; 3443232809Sjmallett struct cvmx_ilk_txx_mem_stat0_s cn68xx; 3444232809Sjmallett struct cvmx_ilk_txx_mem_stat0_s cn68xxp1; 3445232809Sjmallett}; 3446232809Sjmalletttypedef union cvmx_ilk_txx_mem_stat0 cvmx_ilk_txx_mem_stat0_t; 3447232809Sjmallett 3448232809Sjmallett/** 3449232809Sjmallett * cvmx_ilk_tx#_mem_stat1 3450232809Sjmallett */ 3451232809Sjmallettunion cvmx_ilk_txx_mem_stat1 { 3452232809Sjmallett uint64_t u64; 3453232809Sjmallett struct cvmx_ilk_txx_mem_stat1_s { 3454232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3455232809Sjmallett uint64_t reserved_36_63 : 28; 3456232809Sjmallett uint64_t tx_bytes : 36; /**< Number of bytes transmitted per channel (64GB) Channel selected 3457232809Sjmallett by ILK_TXx_IDX_STAT1[IDX]. Saturates. Interrupt on 3458232809Sjmallett saturation if ILK_TXX_INT_EN[STAT_CNT_OVFL]=1. */ 3459232809Sjmallett#else 3460232809Sjmallett uint64_t tx_bytes : 36; 3461232809Sjmallett uint64_t reserved_36_63 : 28; 3462232809Sjmallett#endif 3463232809Sjmallett } s; 3464232809Sjmallett struct cvmx_ilk_txx_mem_stat1_s cn68xx; 3465232809Sjmallett struct cvmx_ilk_txx_mem_stat1_s cn68xxp1; 3466232809Sjmallett}; 3467232809Sjmalletttypedef union cvmx_ilk_txx_mem_stat1 cvmx_ilk_txx_mem_stat1_t; 3468232809Sjmallett 3469232809Sjmallett/** 3470232809Sjmallett * cvmx_ilk_tx#_pipe 3471232809Sjmallett */ 3472232809Sjmallettunion cvmx_ilk_txx_pipe { 3473232809Sjmallett uint64_t u64; 3474232809Sjmallett struct cvmx_ilk_txx_pipe_s { 3475232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3476232809Sjmallett uint64_t reserved_24_63 : 40; 3477232809Sjmallett uint64_t nump : 8; /**< Number of pipes assigned to this Tx Link */ 3478232809Sjmallett uint64_t reserved_7_15 : 9; 3479232809Sjmallett uint64_t base : 7; /**< When NUMP is non-zero, indicates the base pipe number this 3480232809Sjmallett Tx link will accept. This Tx will accept PKO packets from 3481232809Sjmallett pipes in the range of: BASE .. (BASE+(NUMP-1)) 3482232809Sjmallett 3483232809Sjmallett BASE and NUMP must be constrained such that 3484232809Sjmallett 1) BASE+(NUMP-1) < 127 3485232809Sjmallett 2) Each used PKO pipe must map to exactly 3486232809Sjmallett one port|channel 3487232809Sjmallett 3) The pipe ranges must be consistent with 3488232809Sjmallett the PKO configuration. */ 3489232809Sjmallett#else 3490232809Sjmallett uint64_t base : 7; 3491232809Sjmallett uint64_t reserved_7_15 : 9; 3492232809Sjmallett uint64_t nump : 8; 3493232809Sjmallett uint64_t reserved_24_63 : 40; 3494232809Sjmallett#endif 3495232809Sjmallett } s; 3496232809Sjmallett struct cvmx_ilk_txx_pipe_s cn68xx; 3497232809Sjmallett struct cvmx_ilk_txx_pipe_s cn68xxp1; 3498232809Sjmallett}; 3499232809Sjmalletttypedef union cvmx_ilk_txx_pipe cvmx_ilk_txx_pipe_t; 3500232809Sjmallett 3501232809Sjmallett/** 3502232809Sjmallett * cvmx_ilk_tx#_rmatch 3503232809Sjmallett */ 3504232809Sjmallettunion cvmx_ilk_txx_rmatch { 3505232809Sjmallett uint64_t u64; 3506232809Sjmallett struct cvmx_ilk_txx_rmatch_s { 3507232809Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3508232809Sjmallett uint64_t reserved_50_63 : 14; 3509232809Sjmallett uint64_t grnlrty : 2; /**< Granularity of a token, where 1 token equal (1<<GRNLRTY) bytes. */ 3510232809Sjmallett uint64_t brst_limit : 16; /**< Size of token bucket, also the maximum quantity of data that 3511232809Sjmallett may be burst across the interface before invoking rate limiting 3512232809Sjmallett logic. */ 3513232809Sjmallett uint64_t time_limit : 16; /**< Number of cycles per time interval. (Must be >= 4) */ 3514232809Sjmallett uint64_t rate_limit : 16; /**< Number of tokens added to the bucket when the interval timer 3515232809Sjmallett expires. */ 3516232809Sjmallett#else 3517232809Sjmallett uint64_t rate_limit : 16; 3518232809Sjmallett uint64_t time_limit : 16; 3519232809Sjmallett uint64_t brst_limit : 16; 3520232809Sjmallett uint64_t grnlrty : 2; 3521232809Sjmallett uint64_t reserved_50_63 : 14; 3522232809Sjmallett#endif 3523232809Sjmallett } s; 3524232809Sjmallett struct cvmx_ilk_txx_rmatch_s cn68xx; 3525232809Sjmallett struct cvmx_ilk_txx_rmatch_s cn68xxp1; 3526232809Sjmallett}; 3527232809Sjmalletttypedef union cvmx_ilk_txx_rmatch cvmx_ilk_txx_rmatch_t; 3528232809Sjmallett 3529232809Sjmallett#endif 3530