1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-gpio-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon gpio. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_GPIO_DEFS_H__ 53232812Sjmallett#define __CVMX_GPIO_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) || 61215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 62215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) || 63215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) || 64215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) || 65215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 66232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) || 67232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) || 68232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) || 69232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 15))) || 70232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15))))) 71215976Sjmallett cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8; 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_GPIO_BOOT_ENA CVMX_GPIO_BOOT_ENA_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_GPIO_BOOT_ENA_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))) 82215976Sjmallett cvmx_warn("CVMX_GPIO_BOOT_ENA not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008A8ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallettstatic inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset) 90215976Sjmallett{ 91215976Sjmallett if (!( 92215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 93215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) || 94232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) || 95232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) || 96232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) || 97232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) || 98232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3))))) 99215976Sjmallett cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset); 100215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8; 101215976Sjmallett} 102215976Sjmallett#else 103215976Sjmallett#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8) 104215976Sjmallett#endif 105215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 106215976Sjmallettstatic inline uint64_t CVMX_GPIO_CLK_QLMX(unsigned long offset) 107215976Sjmallett{ 108215976Sjmallett if (!( 109232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) || 110232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) || 111232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) || 112232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) || 113232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1))))) 114215976Sjmallett cvmx_warn("CVMX_GPIO_CLK_QLMX(%lu) is invalid on this chip\n", offset); 115215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8; 116215976Sjmallett} 117215976Sjmallett#else 118215976Sjmallett#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8) 119215976Sjmallett#endif 120215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 121215976Sjmallett#define CVMX_GPIO_DBG_ENA CVMX_GPIO_DBG_ENA_FUNC() 122215976Sjmallettstatic inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void) 123215976Sjmallett{ 124215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))) 125215976Sjmallett cvmx_warn("CVMX_GPIO_DBG_ENA not supported on this chip\n"); 126215976Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008A0ull); 127215976Sjmallett} 128215976Sjmallett#else 129215976Sjmallett#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) 130215976Sjmallett#endif 131215976Sjmallett#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull)) 132232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133232812Sjmallett#define CVMX_GPIO_MULTI_CAST CVMX_GPIO_MULTI_CAST_FUNC() 134232812Sjmallettstatic inline uint64_t CVMX_GPIO_MULTI_CAST_FUNC(void) 135232812Sjmallett{ 136232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 137232812Sjmallett cvmx_warn("CVMX_GPIO_MULTI_CAST not supported on this chip\n"); 138232812Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008B0ull); 139232812Sjmallett} 140232812Sjmallett#else 141232812Sjmallett#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull)) 142232812Sjmallett#endif 143232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144232812Sjmallett#define CVMX_GPIO_PIN_ENA CVMX_GPIO_PIN_ENA_FUNC() 145232812Sjmallettstatic inline uint64_t CVMX_GPIO_PIN_ENA_FUNC(void) 146232812Sjmallett{ 147232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN66XX))) 148232812Sjmallett cvmx_warn("CVMX_GPIO_PIN_ENA not supported on this chip\n"); 149232812Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008B8ull); 150232812Sjmallett} 151232812Sjmallett#else 152232812Sjmallett#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull)) 153232812Sjmallett#endif 154215976Sjmallett#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull)) 155232812Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 156232812Sjmallett#define CVMX_GPIO_TIM_CTL CVMX_GPIO_TIM_CTL_FUNC() 157232812Sjmallettstatic inline uint64_t CVMX_GPIO_TIM_CTL_FUNC(void) 158232812Sjmallett{ 159232812Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 160232812Sjmallett cvmx_warn("CVMX_GPIO_TIM_CTL not supported on this chip\n"); 161232812Sjmallett return CVMX_ADD_IO_SEG(0x00010700000008A0ull); 162232812Sjmallett} 163232812Sjmallett#else 164232812Sjmallett#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull)) 165232812Sjmallett#endif 166215976Sjmallett#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull)) 167215976Sjmallett#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull)) 168215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 169215976Sjmallettstatic inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset) 170215976Sjmallett{ 171215976Sjmallett if (!( 172215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) || 173215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) || 174232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23)))) || 175232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 16) && (offset <= 19)))) || 176232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 16) && (offset <= 19)))) || 177232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 16) && (offset <= 19)))))) 178215976Sjmallett cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset); 179215976Sjmallett return CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16; 180215976Sjmallett} 181215976Sjmallett#else 182215976Sjmallett#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16) 183215976Sjmallett#endif 184215976Sjmallett 185215976Sjmallett/** 186215976Sjmallett * cvmx_gpio_bit_cfg# 187232812Sjmallett * 188232812Sjmallett * Notes: 189232812Sjmallett * Only first 16 GPIO pins can introduce interrupts, GPIO_XBIT_CFG16(17,18,19)[INT_EN] and [INT_TYPE] 190232812Sjmallett * will not be used, read out always zero. 191215976Sjmallett */ 192232812Sjmallettunion cvmx_gpio_bit_cfgx { 193215976Sjmallett uint64_t u64; 194232812Sjmallett struct cvmx_gpio_bit_cfgx_s { 195232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 196215976Sjmallett uint64_t reserved_17_63 : 47; 197215976Sjmallett uint64_t synce_sel : 2; /**< Selects the QLM clock output 198215976Sjmallett x0=Normal GPIO output 199232812Sjmallett 01=GPIO QLM clock selected by CSR GPIO_CLK_QLM0 200232812Sjmallett 11=GPIO QLM clock selected by CSR GPIO_CLK_QLM1 */ 201215976Sjmallett uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */ 202215976Sjmallett uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */ 203215976Sjmallett uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */ 204215976Sjmallett uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */ 205215976Sjmallett uint64_t int_type : 1; /**< Type of interrupt 206215976Sjmallett 0 = level (default) 207215976Sjmallett 1 = rising edge */ 208215976Sjmallett uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */ 209215976Sjmallett uint64_t rx_xor : 1; /**< Invert the GPIO pin */ 210215976Sjmallett uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */ 211215976Sjmallett#else 212215976Sjmallett uint64_t tx_oe : 1; 213215976Sjmallett uint64_t rx_xor : 1; 214215976Sjmallett uint64_t int_en : 1; 215215976Sjmallett uint64_t int_type : 1; 216215976Sjmallett uint64_t fil_cnt : 4; 217215976Sjmallett uint64_t fil_sel : 4; 218215976Sjmallett uint64_t clk_sel : 2; 219215976Sjmallett uint64_t clk_gen : 1; 220215976Sjmallett uint64_t synce_sel : 2; 221215976Sjmallett uint64_t reserved_17_63 : 47; 222215976Sjmallett#endif 223215976Sjmallett } s; 224232812Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx { 225232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 226215976Sjmallett uint64_t reserved_12_63 : 52; 227215976Sjmallett uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */ 228215976Sjmallett uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */ 229215976Sjmallett uint64_t int_type : 1; /**< Type of interrupt 230215976Sjmallett 0 = level (default) 231215976Sjmallett 1 = rising edge */ 232215976Sjmallett uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */ 233215976Sjmallett uint64_t rx_xor : 1; /**< Invert the GPIO pin */ 234215976Sjmallett uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */ 235215976Sjmallett#else 236215976Sjmallett uint64_t tx_oe : 1; 237215976Sjmallett uint64_t rx_xor : 1; 238215976Sjmallett uint64_t int_en : 1; 239215976Sjmallett uint64_t int_type : 1; 240215976Sjmallett uint64_t fil_cnt : 4; 241215976Sjmallett uint64_t fil_sel : 4; 242215976Sjmallett uint64_t reserved_12_63 : 52; 243215976Sjmallett#endif 244215976Sjmallett } cn30xx; 245215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn31xx; 246215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; 247215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; 248215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; 249232812Sjmallett struct cvmx_gpio_bit_cfgx_cn52xx { 250232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 251215976Sjmallett uint64_t reserved_15_63 : 49; 252215976Sjmallett uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */ 253215976Sjmallett uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */ 254215976Sjmallett uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */ 255215976Sjmallett uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */ 256215976Sjmallett uint64_t int_type : 1; /**< Type of interrupt 257215976Sjmallett 0 = level (default) 258215976Sjmallett 1 = rising edge */ 259215976Sjmallett uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */ 260215976Sjmallett uint64_t rx_xor : 1; /**< Invert the GPIO pin */ 261215976Sjmallett uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */ 262215976Sjmallett#else 263215976Sjmallett uint64_t tx_oe : 1; 264215976Sjmallett uint64_t rx_xor : 1; 265215976Sjmallett uint64_t int_en : 1; 266215976Sjmallett uint64_t int_type : 1; 267215976Sjmallett uint64_t fil_cnt : 4; 268215976Sjmallett uint64_t fil_sel : 4; 269215976Sjmallett uint64_t clk_sel : 2; 270215976Sjmallett uint64_t clk_gen : 1; 271215976Sjmallett uint64_t reserved_15_63 : 49; 272215976Sjmallett#endif 273215976Sjmallett } cn52xx; 274215976Sjmallett struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1; 275215976Sjmallett struct cvmx_gpio_bit_cfgx_cn52xx cn56xx; 276215976Sjmallett struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1; 277215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; 278215976Sjmallett struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; 279232812Sjmallett struct cvmx_gpio_bit_cfgx_s cn61xx; 280215976Sjmallett struct cvmx_gpio_bit_cfgx_s cn63xx; 281215976Sjmallett struct cvmx_gpio_bit_cfgx_s cn63xxp1; 282232812Sjmallett struct cvmx_gpio_bit_cfgx_s cn66xx; 283232812Sjmallett struct cvmx_gpio_bit_cfgx_s cn68xx; 284232812Sjmallett struct cvmx_gpio_bit_cfgx_s cn68xxp1; 285232812Sjmallett struct cvmx_gpio_bit_cfgx_s cnf71xx; 286215976Sjmallett}; 287215976Sjmalletttypedef union cvmx_gpio_bit_cfgx cvmx_gpio_bit_cfgx_t; 288215976Sjmallett 289215976Sjmallett/** 290215976Sjmallett * cvmx_gpio_boot_ena 291215976Sjmallett */ 292232812Sjmallettunion cvmx_gpio_boot_ena { 293215976Sjmallett uint64_t u64; 294232812Sjmallett struct cvmx_gpio_boot_ena_s { 295232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 296215976Sjmallett uint64_t reserved_12_63 : 52; 297215976Sjmallett uint64_t boot_ena : 4; /**< Drive boot bus chip enables [7:4] on gpio [11:8] */ 298215976Sjmallett uint64_t reserved_0_7 : 8; 299215976Sjmallett#else 300215976Sjmallett uint64_t reserved_0_7 : 8; 301215976Sjmallett uint64_t boot_ena : 4; 302215976Sjmallett uint64_t reserved_12_63 : 52; 303215976Sjmallett#endif 304215976Sjmallett } s; 305215976Sjmallett struct cvmx_gpio_boot_ena_s cn30xx; 306215976Sjmallett struct cvmx_gpio_boot_ena_s cn31xx; 307215976Sjmallett struct cvmx_gpio_boot_ena_s cn50xx; 308215976Sjmallett}; 309215976Sjmalletttypedef union cvmx_gpio_boot_ena cvmx_gpio_boot_ena_t; 310215976Sjmallett 311215976Sjmallett/** 312215976Sjmallett * cvmx_gpio_clk_gen# 313215976Sjmallett */ 314232812Sjmallettunion cvmx_gpio_clk_genx { 315215976Sjmallett uint64_t u64; 316232812Sjmallett struct cvmx_gpio_clk_genx_s { 317232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 318215976Sjmallett uint64_t reserved_32_63 : 32; 319215976Sjmallett uint64_t n : 32; /**< Determines the frequency of the GPIO clk generator 320215976Sjmallett NOTE: Fgpio_clk = Feclk * N / 2^32 321215976Sjmallett N = (Fgpio_clk / Feclk) * 2^32 322215976Sjmallett NOTE: writing N == 0 stops the clock generator 323215976Sjmallett N should be <= 2^31-1. */ 324215976Sjmallett#else 325215976Sjmallett uint64_t n : 32; 326215976Sjmallett uint64_t reserved_32_63 : 32; 327215976Sjmallett#endif 328215976Sjmallett } s; 329215976Sjmallett struct cvmx_gpio_clk_genx_s cn52xx; 330215976Sjmallett struct cvmx_gpio_clk_genx_s cn52xxp1; 331215976Sjmallett struct cvmx_gpio_clk_genx_s cn56xx; 332215976Sjmallett struct cvmx_gpio_clk_genx_s cn56xxp1; 333232812Sjmallett struct cvmx_gpio_clk_genx_s cn61xx; 334215976Sjmallett struct cvmx_gpio_clk_genx_s cn63xx; 335215976Sjmallett struct cvmx_gpio_clk_genx_s cn63xxp1; 336232812Sjmallett struct cvmx_gpio_clk_genx_s cn66xx; 337232812Sjmallett struct cvmx_gpio_clk_genx_s cn68xx; 338232812Sjmallett struct cvmx_gpio_clk_genx_s cn68xxp1; 339232812Sjmallett struct cvmx_gpio_clk_genx_s cnf71xx; 340215976Sjmallett}; 341215976Sjmalletttypedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t; 342215976Sjmallett 343215976Sjmallett/** 344215976Sjmallett * cvmx_gpio_clk_qlm# 345215976Sjmallett * 346215976Sjmallett * Notes: 347232812Sjmallett * QLM0(A) and QLM1(B) can configured to source any of QLM0 or QLM2 as clock source. 348215976Sjmallett * Clock speed output for different modes ... 349215976Sjmallett * 350215976Sjmallett * Speed With Speed with 351215976Sjmallett * SERDES speed (Gbaud) DIV=0 (MHz) DIV=1 (MHz) 352215976Sjmallett * ********************************************************** 353215976Sjmallett * 1.25 62.5 31.25 354215976Sjmallett * 2.5 125 62.5 355215976Sjmallett * 3.125 156.25 78.125 356215976Sjmallett * 5.0 250 125 357215976Sjmallett * 6.25 312.5 156.25 358215976Sjmallett */ 359232812Sjmallettunion cvmx_gpio_clk_qlmx { 360215976Sjmallett uint64_t u64; 361232812Sjmallett struct cvmx_gpio_clk_qlmx_s { 362232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 363232812Sjmallett uint64_t reserved_11_63 : 53; 364232812Sjmallett uint64_t qlm_sel : 3; /**< Selects which DLM to select from 365232812Sjmallett x0 = select DLM0 as clock source 366232812Sjmallett x1 = Disabled */ 367232812Sjmallett uint64_t reserved_3_7 : 5; 368232812Sjmallett uint64_t div : 1; /**< Internal clock divider 369232812Sjmallett 0=DIV2 370232812Sjmallett 1=DIV4 */ 371232812Sjmallett uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLMx to use as 372232812Sjmallett the GPIO internal QLMx clock. The GPIO block can 373232812Sjmallett support upto two unique clocks to send out any 374232812Sjmallett GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL] 375232812Sjmallett The clock can either be a divided by 2 or divide 376232812Sjmallett by 4 of the selected RX lane clock. */ 377232812Sjmallett#else 378232812Sjmallett uint64_t lane_sel : 2; 379232812Sjmallett uint64_t div : 1; 380232812Sjmallett uint64_t reserved_3_7 : 5; 381232812Sjmallett uint64_t qlm_sel : 3; 382232812Sjmallett uint64_t reserved_11_63 : 53; 383232812Sjmallett#endif 384232812Sjmallett } s; 385232812Sjmallett struct cvmx_gpio_clk_qlmx_cn61xx { 386232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 387232812Sjmallett uint64_t reserved_10_63 : 54; 388232812Sjmallett uint64_t qlm_sel : 2; /**< Selects which QLM to select from 389232812Sjmallett 01 = select QLM0 as clock source 390232812Sjmallett 1x = select QLM2 as clock source 391232812Sjmallett 0 = Disabled */ 392232812Sjmallett uint64_t reserved_3_7 : 5; 393232812Sjmallett uint64_t div : 1; /**< Internal clock divider 394232812Sjmallett 0=DIV2 395232812Sjmallett 1=DIV4 */ 396232812Sjmallett uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLMx to use as 397232812Sjmallett the GPIO internal QLMx clock. The GPIO block can 398232812Sjmallett support upto two unique clocks to send out any 399232812Sjmallett GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL] 400232812Sjmallett The clock can either be a divided by 2 or divide 401232812Sjmallett by 4 of the selected RX lane clock. */ 402232812Sjmallett#else 403232812Sjmallett uint64_t lane_sel : 2; 404232812Sjmallett uint64_t div : 1; 405232812Sjmallett uint64_t reserved_3_7 : 5; 406232812Sjmallett uint64_t qlm_sel : 2; 407232812Sjmallett uint64_t reserved_10_63 : 54; 408232812Sjmallett#endif 409232812Sjmallett } cn61xx; 410232812Sjmallett struct cvmx_gpio_clk_qlmx_cn63xx { 411232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 412215976Sjmallett uint64_t reserved_3_63 : 61; 413215976Sjmallett uint64_t div : 1; /**< Internal clock divider 414215976Sjmallett 0=DIV2 415215976Sjmallett 1=DIV4 */ 416215976Sjmallett uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLM2 to use as 417215976Sjmallett the GPIO internal QLMx clock. The GPIO block can 418215976Sjmallett support upto two unique clocks to send out any 419215976Sjmallett GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL] 420215976Sjmallett The clock can either be a divided by 2 or divide 421215976Sjmallett by 4 of the selected RX lane clock. */ 422215976Sjmallett#else 423215976Sjmallett uint64_t lane_sel : 2; 424215976Sjmallett uint64_t div : 1; 425215976Sjmallett uint64_t reserved_3_63 : 61; 426215976Sjmallett#endif 427232812Sjmallett } cn63xx; 428232812Sjmallett struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1; 429232812Sjmallett struct cvmx_gpio_clk_qlmx_cn61xx cn66xx; 430232812Sjmallett struct cvmx_gpio_clk_qlmx_s cn68xx; 431232812Sjmallett struct cvmx_gpio_clk_qlmx_s cn68xxp1; 432232812Sjmallett struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx; 433215976Sjmallett}; 434215976Sjmalletttypedef union cvmx_gpio_clk_qlmx cvmx_gpio_clk_qlmx_t; 435215976Sjmallett 436215976Sjmallett/** 437215976Sjmallett * cvmx_gpio_dbg_ena 438215976Sjmallett */ 439232812Sjmallettunion cvmx_gpio_dbg_ena { 440215976Sjmallett uint64_t u64; 441232812Sjmallett struct cvmx_gpio_dbg_ena_s { 442232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 443215976Sjmallett uint64_t reserved_21_63 : 43; 444215976Sjmallett uint64_t dbg_ena : 21; /**< Enable the debug port to be driven on the gpio */ 445215976Sjmallett#else 446215976Sjmallett uint64_t dbg_ena : 21; 447215976Sjmallett uint64_t reserved_21_63 : 43; 448215976Sjmallett#endif 449215976Sjmallett } s; 450215976Sjmallett struct cvmx_gpio_dbg_ena_s cn30xx; 451215976Sjmallett struct cvmx_gpio_dbg_ena_s cn31xx; 452215976Sjmallett struct cvmx_gpio_dbg_ena_s cn50xx; 453215976Sjmallett}; 454215976Sjmalletttypedef union cvmx_gpio_dbg_ena cvmx_gpio_dbg_ena_t; 455215976Sjmallett 456215976Sjmallett/** 457215976Sjmallett * cvmx_gpio_int_clr 458232812Sjmallett * 459232812Sjmallett * Notes: 460232812Sjmallett * Only 16 out of 20 GPIOs support interrupt.GPIO_INT_CLR only apply to GPIO0-GPIO15. 461232812Sjmallett * 462215976Sjmallett */ 463232812Sjmallettunion cvmx_gpio_int_clr { 464215976Sjmallett uint64_t u64; 465232812Sjmallett struct cvmx_gpio_int_clr_s { 466232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 467215976Sjmallett uint64_t reserved_16_63 : 48; 468215976Sjmallett uint64_t type : 16; /**< Clear the interrupt rising edge detector */ 469215976Sjmallett#else 470215976Sjmallett uint64_t type : 16; 471215976Sjmallett uint64_t reserved_16_63 : 48; 472215976Sjmallett#endif 473215976Sjmallett } s; 474215976Sjmallett struct cvmx_gpio_int_clr_s cn30xx; 475215976Sjmallett struct cvmx_gpio_int_clr_s cn31xx; 476215976Sjmallett struct cvmx_gpio_int_clr_s cn38xx; 477215976Sjmallett struct cvmx_gpio_int_clr_s cn38xxp2; 478215976Sjmallett struct cvmx_gpio_int_clr_s cn50xx; 479215976Sjmallett struct cvmx_gpio_int_clr_s cn52xx; 480215976Sjmallett struct cvmx_gpio_int_clr_s cn52xxp1; 481215976Sjmallett struct cvmx_gpio_int_clr_s cn56xx; 482215976Sjmallett struct cvmx_gpio_int_clr_s cn56xxp1; 483215976Sjmallett struct cvmx_gpio_int_clr_s cn58xx; 484215976Sjmallett struct cvmx_gpio_int_clr_s cn58xxp1; 485232812Sjmallett struct cvmx_gpio_int_clr_s cn61xx; 486215976Sjmallett struct cvmx_gpio_int_clr_s cn63xx; 487215976Sjmallett struct cvmx_gpio_int_clr_s cn63xxp1; 488232812Sjmallett struct cvmx_gpio_int_clr_s cn66xx; 489232812Sjmallett struct cvmx_gpio_int_clr_s cn68xx; 490232812Sjmallett struct cvmx_gpio_int_clr_s cn68xxp1; 491232812Sjmallett struct cvmx_gpio_int_clr_s cnf71xx; 492215976Sjmallett}; 493215976Sjmalletttypedef union cvmx_gpio_int_clr cvmx_gpio_int_clr_t; 494215976Sjmallett 495215976Sjmallett/** 496232812Sjmallett * cvmx_gpio_multi_cast 497232812Sjmallett * 498232812Sjmallett * Notes: 499232812Sjmallett * GPIO<7:4> have the option of operating in GPIO Interrupt Multicast mode. In 500232812Sjmallett * this mode, the PP GPIO interrupts (CIU_INT<0-7>_SUM0/CIU_INT<0-3>_SUM4[GPIO<7:4>] values are 501232812Sjmallett * stored per cnMIPS core. 502232812Sjmallett * For GPIO<7:4> (x=4-7): 503232812Sjmallett * When GPIO_MULTI_CAST[EN] = 1: 504232812Sjmallett * When GPIO_BIT_CFGx[INT_EN]==1 & GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled): 505232812Sjmallett * * Reads to CIU_INT<0-7>_SUM0/<0-3>_SUM4[GPIO<x>] will return a unique interrupt state per 506232812Sjmallett * cnMIPS core. 507232812Sjmallett * * Reads to CIU_INT32/33_SUM0/4[GPIO<x>] will return the common GPIO<x> 508232812Sjmallett * interrupt state. 509232812Sjmallett * * Write of '1' to CIU_INT<0-7>_SUM0/<0-3>_SUM4[GPIO<x>] will clear the individual 510232812Sjmallett * interrupt associated with the cnMIPS core. 511232812Sjmallett * * Write of '1' to CIU_INT32/33_SUM0/4[GPIO<x>] will clear the common GPIO<x> 512232812Sjmallett * interrupt state. 513232812Sjmallett * * Write of '1' to GPIO_INT_CLR[TYPE<x>] will clear all 514232812Sjmallett * CIU_INT*_SUM0/4[GPIO<x>] state across all cnMIPS cores and common GPIO<x> interrupt states. 515232812Sjmallett * When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0, 516232812Sjmallett * * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<x>] 517232812Sjmallett * will have no effects. 518232812Sjmallett * When GPIO_MULTI_CAST[EN] = 0: 519232812Sjmallett * * Write of '1' to CIU_INT_SUM0/4[GPIO<x>] will have no effects, as this field is RO, 520232812Sjmallett * backward compatible with o63. 521232812Sjmallett * When GPIO_BIT_CFGx[INT_EN]==1 & GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled): 522232812Sjmallett * * Reads to CIU_INT*_SUM0/4[GPIO<x>] will return the common GPIO<X> interrupt state. 523232812Sjmallett * * Write of '1' to GPIO_INT_CLR[TYPE<x>] will clear all 524232812Sjmallett * CIU_INT*_SUM0/4[GPIO<x>] state across all cnMIPS cores and common GPIO<x> interrupt states. 525232812Sjmallett * When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0, 526232812Sjmallett * * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<x>] 527232812Sjmallett * will have no effects. 528232812Sjmallett * 529232812Sjmallett * GPIO<15:8> and GPIO<3:0> will never be in multicast mode as those don't have per cnMIPS capabilities. 530232812Sjmallett * For GPIO<y> (y=0-3,8-15): 531232812Sjmallett * When GPIO_BIT_CFGx[INT_EN]==1 & GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled): 532232812Sjmallett * * Reads to CIU_INT*_SUM0/4[GPIO<y>] will return the common GPIO<y> interrupt state. 533232812Sjmallett * * Write of '1' to GPIO_INT_CLR[TYPE<y>] will clear all CIU_INT*_SUM0/4[GPIO<y>] common GPIO<y> 534232812Sjmallett * interrupt states. 535232812Sjmallett * When GPIO_MULTI_CAST[EN] = 1: 536232812Sjmallett * * Write of '1' to CIU_INT*_SUM0/4[GPIO<y>] will clear the common GPIO<y> interrupt state. 537232812Sjmallett * When GPIO_MULTI_CAST[EN] = 0: 538232812Sjmallett * * Write of '1' to CIU_INT*_SUM0/4[GPIO<y>] has no effect, as this field is RO, 539232812Sjmallett * backward compatible to o63. 540232812Sjmallett * When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0, 541232812Sjmallett * * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<y>] 542232812Sjmallett * will have no effects. 543232812Sjmallett * 544232812Sjmallett * Whenever there is mode change, (GPIO_BIT_CFGx[INT_EN] or GPIO_BIT_CFGx[INT_TYPE] or GPIO_MULTI_CAST[EN]) 545232812Sjmallett * software needs to write to $GPIO_INT_CLR to clear up all pending/stale interrupts. 546232812Sjmallett */ 547232812Sjmallettunion cvmx_gpio_multi_cast { 548232812Sjmallett uint64_t u64; 549232812Sjmallett struct cvmx_gpio_multi_cast_s { 550232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 551232812Sjmallett uint64_t reserved_1_63 : 63; 552232812Sjmallett uint64_t en : 1; /**< Enable GPIO Interrupt Multicast mode 553232812Sjmallett When EN is set, GPIO<7:4> will function in 554232812Sjmallett multicast mode allowing these four GPIOs to 555232812Sjmallett interrupt multi-cores. 556232812Sjmallett Multicast functionality allows the GPIO to exist 557232812Sjmallett as per cnMIPS interrupts as opposed to a global 558232812Sjmallett interrupt. */ 559232812Sjmallett#else 560232812Sjmallett uint64_t en : 1; 561232812Sjmallett uint64_t reserved_1_63 : 63; 562232812Sjmallett#endif 563232812Sjmallett } s; 564232812Sjmallett struct cvmx_gpio_multi_cast_s cn61xx; 565232812Sjmallett struct cvmx_gpio_multi_cast_s cnf71xx; 566232812Sjmallett}; 567232812Sjmalletttypedef union cvmx_gpio_multi_cast cvmx_gpio_multi_cast_t; 568232812Sjmallett 569232812Sjmallett/** 570232812Sjmallett * cvmx_gpio_pin_ena 571232812Sjmallett * 572232812Sjmallett * Notes: 573232812Sjmallett * GPIO0-GPIO17 has dedicated pins. 574232812Sjmallett * GPIO18 share pin with UART (UART0_CTS_L/GPIO_18), GPIO18 enabled when $GPIO_PIN_ENA[ENA18]=1 575232812Sjmallett * GPIO19 share pin with UART (UART1_CTS_L/GPIO_19), GPIO18 enabled when $GPIO_PIN_ENA[ENA19]=1 576232812Sjmallett */ 577232812Sjmallettunion cvmx_gpio_pin_ena { 578232812Sjmallett uint64_t u64; 579232812Sjmallett struct cvmx_gpio_pin_ena_s { 580232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 581232812Sjmallett uint64_t reserved_20_63 : 44; 582232812Sjmallett uint64_t ena19 : 1; /**< If 0, UART1_CTS_L/GPIO_19 pin is UART pin 583232812Sjmallett If 1, UART1_CTS_L/GPIO_19 pin is GPIO19 pin */ 584232812Sjmallett uint64_t ena18 : 1; /**< If 0, UART0_CTS_L/GPIO_18 pin is UART pin 585232812Sjmallett If 1, UART0_CTS_L/GPIO_18 pin is GPIO18 pin */ 586232812Sjmallett uint64_t reserved_0_17 : 18; 587232812Sjmallett#else 588232812Sjmallett uint64_t reserved_0_17 : 18; 589232812Sjmallett uint64_t ena18 : 1; 590232812Sjmallett uint64_t ena19 : 1; 591232812Sjmallett uint64_t reserved_20_63 : 44; 592232812Sjmallett#endif 593232812Sjmallett } s; 594232812Sjmallett struct cvmx_gpio_pin_ena_s cn66xx; 595232812Sjmallett}; 596232812Sjmalletttypedef union cvmx_gpio_pin_ena cvmx_gpio_pin_ena_t; 597232812Sjmallett 598232812Sjmallett/** 599215976Sjmallett * cvmx_gpio_rx_dat 600215976Sjmallett */ 601232812Sjmallettunion cvmx_gpio_rx_dat { 602215976Sjmallett uint64_t u64; 603232812Sjmallett struct cvmx_gpio_rx_dat_s { 604232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 605215976Sjmallett uint64_t reserved_24_63 : 40; 606215976Sjmallett uint64_t dat : 24; /**< GPIO Read Data */ 607215976Sjmallett#else 608215976Sjmallett uint64_t dat : 24; 609215976Sjmallett uint64_t reserved_24_63 : 40; 610215976Sjmallett#endif 611215976Sjmallett } s; 612215976Sjmallett struct cvmx_gpio_rx_dat_s cn30xx; 613215976Sjmallett struct cvmx_gpio_rx_dat_s cn31xx; 614232812Sjmallett struct cvmx_gpio_rx_dat_cn38xx { 615232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 616215976Sjmallett uint64_t reserved_16_63 : 48; 617215976Sjmallett uint64_t dat : 16; /**< GPIO Read Data */ 618215976Sjmallett#else 619215976Sjmallett uint64_t dat : 16; 620215976Sjmallett uint64_t reserved_16_63 : 48; 621215976Sjmallett#endif 622215976Sjmallett } cn38xx; 623215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn38xxp2; 624215976Sjmallett struct cvmx_gpio_rx_dat_s cn50xx; 625215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn52xx; 626215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn52xxp1; 627215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn56xx; 628215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; 629215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn58xx; 630215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; 631232812Sjmallett struct cvmx_gpio_rx_dat_cn61xx { 632232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 633232812Sjmallett uint64_t reserved_20_63 : 44; 634232812Sjmallett uint64_t dat : 20; /**< GPIO Read Data */ 635232812Sjmallett#else 636232812Sjmallett uint64_t dat : 20; 637232812Sjmallett uint64_t reserved_20_63 : 44; 638232812Sjmallett#endif 639232812Sjmallett } cn61xx; 640215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn63xx; 641215976Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn63xxp1; 642232812Sjmallett struct cvmx_gpio_rx_dat_cn61xx cn66xx; 643232812Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn68xx; 644232812Sjmallett struct cvmx_gpio_rx_dat_cn38xx cn68xxp1; 645232812Sjmallett struct cvmx_gpio_rx_dat_cn61xx cnf71xx; 646215976Sjmallett}; 647215976Sjmalletttypedef union cvmx_gpio_rx_dat cvmx_gpio_rx_dat_t; 648215976Sjmallett 649215976Sjmallett/** 650232812Sjmallett * cvmx_gpio_tim_ctl 651232812Sjmallett */ 652232812Sjmallettunion cvmx_gpio_tim_ctl { 653232812Sjmallett uint64_t u64; 654232812Sjmallett struct cvmx_gpio_tim_ctl_s { 655232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 656232812Sjmallett uint64_t reserved_4_63 : 60; 657232812Sjmallett uint64_t sel : 4; /**< Selects the GPIO pin to route to TIM */ 658232812Sjmallett#else 659232812Sjmallett uint64_t sel : 4; 660232812Sjmallett uint64_t reserved_4_63 : 60; 661232812Sjmallett#endif 662232812Sjmallett } s; 663232812Sjmallett struct cvmx_gpio_tim_ctl_s cn68xx; 664232812Sjmallett struct cvmx_gpio_tim_ctl_s cn68xxp1; 665232812Sjmallett}; 666232812Sjmalletttypedef union cvmx_gpio_tim_ctl cvmx_gpio_tim_ctl_t; 667232812Sjmallett 668232812Sjmallett/** 669215976Sjmallett * cvmx_gpio_tx_clr 670215976Sjmallett */ 671232812Sjmallettunion cvmx_gpio_tx_clr { 672215976Sjmallett uint64_t u64; 673232812Sjmallett struct cvmx_gpio_tx_clr_s { 674232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 675215976Sjmallett uint64_t reserved_24_63 : 40; 676215976Sjmallett uint64_t clr : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set 677215976Sjmallett to '0'. When read, CLR returns the GPIO_TX_DAT 678215976Sjmallett storage. */ 679215976Sjmallett#else 680215976Sjmallett uint64_t clr : 24; 681215976Sjmallett uint64_t reserved_24_63 : 40; 682215976Sjmallett#endif 683215976Sjmallett } s; 684215976Sjmallett struct cvmx_gpio_tx_clr_s cn30xx; 685215976Sjmallett struct cvmx_gpio_tx_clr_s cn31xx; 686232812Sjmallett struct cvmx_gpio_tx_clr_cn38xx { 687232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 688215976Sjmallett uint64_t reserved_16_63 : 48; 689215976Sjmallett uint64_t clr : 16; /**< Bit mask to indicate which bits to drive to '0'. */ 690215976Sjmallett#else 691215976Sjmallett uint64_t clr : 16; 692215976Sjmallett uint64_t reserved_16_63 : 48; 693215976Sjmallett#endif 694215976Sjmallett } cn38xx; 695215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn38xxp2; 696215976Sjmallett struct cvmx_gpio_tx_clr_s cn50xx; 697215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn52xx; 698215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn52xxp1; 699215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn56xx; 700215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; 701215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn58xx; 702215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; 703232812Sjmallett struct cvmx_gpio_tx_clr_cn61xx { 704232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 705232812Sjmallett uint64_t reserved_20_63 : 44; 706232812Sjmallett uint64_t clr : 20; /**< Bit mask to indicate which GPIO_TX_DAT bits to set 707232812Sjmallett to '0'. When read, CLR returns the GPIO_TX_DAT 708232812Sjmallett storage. */ 709232812Sjmallett#else 710232812Sjmallett uint64_t clr : 20; 711232812Sjmallett uint64_t reserved_20_63 : 44; 712232812Sjmallett#endif 713232812Sjmallett } cn61xx; 714215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn63xx; 715215976Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn63xxp1; 716232812Sjmallett struct cvmx_gpio_tx_clr_cn61xx cn66xx; 717232812Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn68xx; 718232812Sjmallett struct cvmx_gpio_tx_clr_cn38xx cn68xxp1; 719232812Sjmallett struct cvmx_gpio_tx_clr_cn61xx cnf71xx; 720215976Sjmallett}; 721215976Sjmalletttypedef union cvmx_gpio_tx_clr cvmx_gpio_tx_clr_t; 722215976Sjmallett 723215976Sjmallett/** 724215976Sjmallett * cvmx_gpio_tx_set 725215976Sjmallett */ 726232812Sjmallettunion cvmx_gpio_tx_set { 727215976Sjmallett uint64_t u64; 728232812Sjmallett struct cvmx_gpio_tx_set_s { 729232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 730215976Sjmallett uint64_t reserved_24_63 : 40; 731215976Sjmallett uint64_t set : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set 732215976Sjmallett to '1'. When read, SET returns the GPIO_TX_DAT 733215976Sjmallett storage. */ 734215976Sjmallett#else 735215976Sjmallett uint64_t set : 24; 736215976Sjmallett uint64_t reserved_24_63 : 40; 737215976Sjmallett#endif 738215976Sjmallett } s; 739215976Sjmallett struct cvmx_gpio_tx_set_s cn30xx; 740215976Sjmallett struct cvmx_gpio_tx_set_s cn31xx; 741232812Sjmallett struct cvmx_gpio_tx_set_cn38xx { 742232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 743215976Sjmallett uint64_t reserved_16_63 : 48; 744215976Sjmallett uint64_t set : 16; /**< Bit mask to indicate which bits to drive to '1'. */ 745215976Sjmallett#else 746215976Sjmallett uint64_t set : 16; 747215976Sjmallett uint64_t reserved_16_63 : 48; 748215976Sjmallett#endif 749215976Sjmallett } cn38xx; 750215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn38xxp2; 751215976Sjmallett struct cvmx_gpio_tx_set_s cn50xx; 752215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn52xx; 753215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn52xxp1; 754215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn56xx; 755215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn56xxp1; 756215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn58xx; 757215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn58xxp1; 758232812Sjmallett struct cvmx_gpio_tx_set_cn61xx { 759232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 760232812Sjmallett uint64_t reserved_20_63 : 44; 761232812Sjmallett uint64_t set : 20; /**< Bit mask to indicate which GPIO_TX_DAT bits to set 762232812Sjmallett to '1'. When read, SET returns the GPIO_TX_DAT 763232812Sjmallett storage. */ 764232812Sjmallett#else 765232812Sjmallett uint64_t set : 20; 766232812Sjmallett uint64_t reserved_20_63 : 44; 767232812Sjmallett#endif 768232812Sjmallett } cn61xx; 769215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn63xx; 770215976Sjmallett struct cvmx_gpio_tx_set_cn38xx cn63xxp1; 771232812Sjmallett struct cvmx_gpio_tx_set_cn61xx cn66xx; 772232812Sjmallett struct cvmx_gpio_tx_set_cn38xx cn68xx; 773232812Sjmallett struct cvmx_gpio_tx_set_cn38xx cn68xxp1; 774232812Sjmallett struct cvmx_gpio_tx_set_cn61xx cnf71xx; 775215976Sjmallett}; 776215976Sjmalletttypedef union cvmx_gpio_tx_set cvmx_gpio_tx_set_t; 777215976Sjmallett 778215976Sjmallett/** 779215976Sjmallett * cvmx_gpio_xbit_cfg# 780232812Sjmallett * 781232812Sjmallett * Notes: 782232812Sjmallett * Only first 16 GPIO pins can introduce interrupts, GPIO_XBIT_CFG16(17,18,19)[INT_EN] and [INT_TYPE] 783232812Sjmallett * will not be used, read out always zero. 784215976Sjmallett */ 785232812Sjmallettunion cvmx_gpio_xbit_cfgx { 786215976Sjmallett uint64_t u64; 787232812Sjmallett struct cvmx_gpio_xbit_cfgx_s { 788232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 789232812Sjmallett uint64_t reserved_17_63 : 47; 790232812Sjmallett uint64_t synce_sel : 2; /**< Selects the QLM clock output 791232812Sjmallett x0=Normal GPIO output 792232812Sjmallett 01=GPIO QLM clock selected by CSR GPIO_CLK_QLM0 793232812Sjmallett 11=GPIO QLM clock selected by CSR GPIO_CLK_QLM1 */ 794232812Sjmallett uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */ 795232812Sjmallett uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */ 796232812Sjmallett uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */ 797232812Sjmallett uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */ 798232812Sjmallett uint64_t int_type : 1; /**< Type of interrupt 799232812Sjmallett 0 = level (default) 800232812Sjmallett 1 = rising edge */ 801232812Sjmallett uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */ 802232812Sjmallett uint64_t rx_xor : 1; /**< Invert the GPIO pin */ 803232812Sjmallett uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */ 804232812Sjmallett#else 805232812Sjmallett uint64_t tx_oe : 1; 806232812Sjmallett uint64_t rx_xor : 1; 807232812Sjmallett uint64_t int_en : 1; 808232812Sjmallett uint64_t int_type : 1; 809232812Sjmallett uint64_t fil_cnt : 4; 810232812Sjmallett uint64_t fil_sel : 4; 811232812Sjmallett uint64_t clk_sel : 2; 812232812Sjmallett uint64_t clk_gen : 1; 813232812Sjmallett uint64_t synce_sel : 2; 814232812Sjmallett uint64_t reserved_17_63 : 47; 815232812Sjmallett#endif 816232812Sjmallett } s; 817232812Sjmallett struct cvmx_gpio_xbit_cfgx_cn30xx { 818232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 819215976Sjmallett uint64_t reserved_12_63 : 52; 820215976Sjmallett uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */ 821215976Sjmallett uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */ 822215976Sjmallett uint64_t reserved_2_3 : 2; 823215976Sjmallett uint64_t rx_xor : 1; /**< Invert the GPIO pin */ 824215976Sjmallett uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */ 825215976Sjmallett#else 826215976Sjmallett uint64_t tx_oe : 1; 827215976Sjmallett uint64_t rx_xor : 1; 828215976Sjmallett uint64_t reserved_2_3 : 2; 829215976Sjmallett uint64_t fil_cnt : 4; 830215976Sjmallett uint64_t fil_sel : 4; 831215976Sjmallett uint64_t reserved_12_63 : 52; 832215976Sjmallett#endif 833232812Sjmallett } cn30xx; 834232812Sjmallett struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx; 835232812Sjmallett struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx; 836232812Sjmallett struct cvmx_gpio_xbit_cfgx_s cn61xx; 837232812Sjmallett struct cvmx_gpio_xbit_cfgx_s cn66xx; 838232812Sjmallett struct cvmx_gpio_xbit_cfgx_s cnf71xx; 839215976Sjmallett}; 840215976Sjmalletttypedef union cvmx_gpio_xbit_cfgx cvmx_gpio_xbit_cfgx_t; 841215976Sjmallett 842215976Sjmallett#endif 843