1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * 49210284Sjmallett * Interface to the PCI / PCIe DMA engines. These are only avialable 50210284Sjmallett * on chips with PCI / PCIe. 51210284Sjmallett * 52232812Sjmallett * <hr>$Revision: 70030 $<hr> 53210284Sjmallett */ 54210284Sjmallett 55210284Sjmallett#ifndef __CVMX_DMA_ENGINES_H__ 56210284Sjmallett#define __CVMX_DMA_ENGINES_H__ 57210284Sjmallett 58232812Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 59232812Sjmallett#include <asm/octeon/cvmx-dpi-defs.h> 60232812Sjmallett#else 61232812Sjmallett#include "cvmx-dpi-defs.h" 62232812Sjmallett#endif 63232812Sjmallett 64210284Sjmallett#ifdef __cplusplus 65210284Sjmallettextern "C" { 66210284Sjmallett#endif 67210284Sjmallett 68210284Sjmalletttypedef enum 69210284Sjmallett{ 70210284Sjmallett CVMX_DMA_ENGINE_TRANSFER_OUTBOUND = 0, /**< OUTBOUND (read from L2/DRAM, write into PCI / PCIe memory space) */ 71210284Sjmallett CVMX_DMA_ENGINE_TRANSFER_INBOUND = 1, /**< INBOUND (read from PCI / PCIe memory space, write into L2/DRAM) */ 72210284Sjmallett CVMX_DMA_ENGINE_TRANSFER_INTERNAL = 2, /**< INTERNAL-ONLY (read from L2/DRAM, write into L2/DRAM). Only available on chips with PCIe */ 73210284Sjmallett CVMX_DMA_ENGINE_TRANSFER_EXTERNAL = 3, /**< EXTERNAL-ONLY (read from PCIe memory space, write into PCIe memory space). Only available on chips with PCIe */ 74210284Sjmallett} cvmx_dma_engine_transfer_t; 75210284Sjmallett 76210284Sjmalletttypedef union 77210284Sjmallett{ 78210284Sjmallett uint64_t u64; 79210284Sjmallett struct 80210284Sjmallett { 81210284Sjmallett uint64_t reserved_60_63 : 4; /**< Must be zero */ 82210284Sjmallett uint64_t fport : 2; /**< First port. FPort indicates the physical PCIe port used for the 83210284Sjmallett PCIe memory space pointers in the FIRST POINTERS block in the 84210284Sjmallett EXTERNAL-ONLY case. Must be zero in the OUTBOUND, INBOUND and 85210284Sjmallett INTERNAL-ONLY cases. Must be zero on chips with PCI */ 86210284Sjmallett uint64_t lport : 2; /**< Last port. LPort indicates the physical PCIe port used for the 87210284Sjmallett PCIe memory space pointers in the LAST POINTERS block in the 88210284Sjmallett OUTBOUND, INBOUND, and EXTERNAL-ONLY cases. Must be zero in the 89210284Sjmallett INTERNAL-ONLY case. Must be zero on chips with PCI */ 90210284Sjmallett cvmx_dma_engine_transfer_t type : 2; /**< Type � A given PCI DMA transfer is either OUTBOUND (read from L2/DRAM, 91210284Sjmallett write into PCI / PCIe memory space), INBOUND (read from PCI / PCIe memory space, write 92210284Sjmallett into L2/DRAM), INTERNAL-ONLY (read from L2/DRAM, write into L2/DRAM), or 93210284Sjmallett EXTERNAL-ONLY (read from PCIe memory space, write into PCIe memory space). */ 94210284Sjmallett uint64_t wqp : 1; /**< Work-queue pointer. When WQP = 1, PTR (if non-zero) is a pointer to a 95210284Sjmallett work-queue entry that is submitted by the hardware after completing the DMA; 96210284Sjmallett when WQP = 0, PTR (if non-zero) is a pointer to a byte in local memory that 97210284Sjmallett is written to 0 by the hardware after completing the DMA. */ 98210284Sjmallett uint64_t c : 1; /**< C � Counter. 1 = use counter 1, 0 = use counter 0. 99210284Sjmallett The C bit selects between the two counters (NPEI_DMA_CNTS[DMA0,DMA1]) 100210284Sjmallett that can optionally be updated after an OUTBOUND or EXTERNAL-ONLY 101210284Sjmallett transfer, and also selects between the two forced-interrupt bits 102210284Sjmallett (NPEI_INT_SUMn[DMA0_FI, DMA1_FI]) that can optionally be set after an 103210284Sjmallett OUTBOUND or EXTERNAL-ONLY transfer. C must be zero for INBOUND or 104210284Sjmallett INTERNAL-ONLY transfers. */ 105210284Sjmallett uint64_t ca : 1; /**< CA � Counter add. 106210284Sjmallett When CA = 1, the hardware updates the selected counter after it completes the 107210284Sjmallett PCI DMA OUTBOUND or EXTERNAL-ONLY Instruction. 108210284Sjmallett - If C = 0, PCIE_DMA_CNT0 is updated 109210284Sjmallett - If C = 1, PCIE_DMA_CNT1 is updated. 110210284Sjmallett Note that this update may indirectly cause 111210284Sjmallett NPEI_INT_SUM[DCNT0,DCNT1,DTIME0,DTIME1] to become set (depending 112210284Sjmallett on the NPEI_DMA*_INT_LEVEL settings), so may cause interrupts to occur on a 113210284Sjmallett remote PCI host. 114210284Sjmallett - If NPEI_DMA_CONTROL[O_ADD1] = 1, the counter is updated by 1. 115210284Sjmallett - If NPEI_DMA_CONTROL[O_ADD1] = 0, the counter is updated by the total 116210284Sjmallett bytes in the transfer. 117210284Sjmallett When CA = 0, the hardware does not update any counters. 118210284Sjmallett For an INBOUND or INTERNAL-ONLY PCI DMA transfer, CA must never be 119210284Sjmallett set, and the hardware never adds to the counters. */ 120210284Sjmallett uint64_t fi : 1; /**< FI � Force interrupt. 121210284Sjmallett When FI is set for an OUTBOUND or EXTERNAL-ONLY transfer, the hardware 122210284Sjmallett sets a forced interrupt bit after it completes the PCI DMA Instruction. If C = 0, 123210284Sjmallett NPEI_INT_SUMn[DMA0_FI] is set, else NPEI_INT_SUMn[DMA1_FI] is set. For 124210284Sjmallett an INBOUND or INTERNAL-ONLY PCI DMA operation, FI must never be set, 125210284Sjmallett and the hardware never generates interrupts. */ 126210284Sjmallett uint64_t ii : 1; /**< II� Ignore the I bit (i.e. the I bit of the PCI DMA instruction local pointer). 127210284Sjmallett For OUTBOUND transfers when II = 1, ignore the I bit and the FL bit in the 128210284Sjmallett DMA HDR alone determines whether the hardware frees any/all of the local 129210284Sjmallett buffers in the FIRST POINTERS area: 130210284Sjmallett - when FL = 1, the hardware frees the local buffer when II=1. 131210284Sjmallett - when FL = 0, the hardware does not free the local buffer when II=1. 132210284Sjmallett For OUTBOUND transfers when II = 0, the I bit in the local pointer selects 133210284Sjmallett whether local buffers are freed on a pointer-by-pointer basis: 134210284Sjmallett - when (FL I) is true, the hardware frees the local buffer when II=0. 135210284Sjmallett For INBOUND, INTERNAL-ONLY, and EXTERNAL-ONLY PCI DMA transfers, 136210284Sjmallett II must never be set, and local buffers are never freed. */ 137210284Sjmallett uint64_t fl : 1; /**< FL � Free local buffer. 138210284Sjmallett When FL = 1, for an OUTBOUND operation, it indicates that the local buffers in 139210284Sjmallett the FIRST BUFFERS area should be freed. 140210284Sjmallett If II = 1, the FL bit alone indicates whether the local buffer should be freed: 141210284Sjmallett - when FL = 1, the hardware frees the local buffer when II=1. 142210284Sjmallett - when FL = 0, the hardware does not free the local buffer when II=1. 143210284Sjmallett If II = 0, the I bit in the local pointer (refer to Section 9.5.2) determines whether 144210284Sjmallett the local buffer is freed: 145210284Sjmallett - when (FL I) is true, the hardware frees the local buffer when II=0. 146210284Sjmallett For an INBOUND, INTERNAL-ONLY, or EXTERNAL-ONLY PCI DMA transfer, 147210284Sjmallett FL must never be set, and local buffers are never freed. */ 148210284Sjmallett uint64_t nlst : 4; /**< NLST � Number Last pointers. 149210284Sjmallett The number of pointers in the LAST POINTERS area. 150210284Sjmallett In the INBOUND, OUTBOUND, and EXTERNAL-ONLY cases, the LAST 151210284Sjmallett POINTERS area contains PCI components, and the number of 64-bit words 152210284Sjmallett required in the LAST POINTERS area is: 153210284Sjmallett - HDR.NLST + ((HDR.NLST + 3)/4) where the division removes the fraction. 154210284Sjmallett In the INTERNAL-ONLY case, the LAST POINTERS area contains local 155210284Sjmallett pointers, and the number of 64-bit words required in the LAST POINTERS area is: 156210284Sjmallett - HDR.NLST 157210284Sjmallett Note that the sum of the number of 64-bit words in the LAST POINTERS and 158210284Sjmallett FIRST POINTERS area must never exceed 31. */ 159210284Sjmallett uint64_t nfst : 4; /**< NFST � Number First pointers. 160210284Sjmallett The number of pointers in the FIRST POINTERS area. 161210284Sjmallett In the INBOUND, OUTBOUND, and INTERNAL-ONLY cases, the FIRST 162210284Sjmallett POINTERS area contains local pointers, and the number of 64-bit words required 163210284Sjmallett in the FIRST POINTERS area is: 164210284Sjmallett - HDR.NFST 165210284Sjmallett In the EXTERNAL-ONLY case, the FIRST POINTERS area contains PCI 166210284Sjmallett components, and the number of 64-bit words required in the FIRST POINTERS 167210284Sjmallett area is: 168210284Sjmallett - HDR.NFST + ((HDR.NFST + 3)/4) where the division removes the fraction. */ 169210284Sjmallett uint64_t addr : 40; /**< PTR � Pointer, either a work-queue-entry pointer (when WQP = 1) or a local 170210284Sjmallett memory pointer (WQP = 0). 171210284Sjmallett When WQP = 1 and PTR 0x0, the hardware inserts the work-queue entry 172210284Sjmallett indicated by PTR into a POW input queue after the PCI DMA operation is 173210284Sjmallett complete. (Section 5.4 describes the work queue entry requirements in this 174210284Sjmallett case.) When WQP = 1, PTR<2:0> must be 0x0. 175210284Sjmallett When WQP = 0 and PTR 0x0, the hardware writes the single byte in local 176210284Sjmallett memory indicated by PTR to 0x0 after the PCI DMA operation is complete. 177210284Sjmallett NPEI_DMA_CONTROL[B0_LEND] selects the endian-ness of PTR in this 178210284Sjmallett case. 179210284Sjmallett When PTR = 0x0, the hardware performs no operation after the PCI DMA 180210284Sjmallett operation is complete. */ 181210284Sjmallett } s; 182210284Sjmallett} cvmx_dma_engine_header_t; 183210284Sjmallett 184210284Sjmalletttypedef union 185210284Sjmallett{ 186210284Sjmallett uint64_t u64; 187210284Sjmallett struct 188210284Sjmallett { 189210284Sjmallett uint64_t i : 1; /**< I � Invert free. 190210284Sjmallett This bit gives the software the ability to free buffers independently for an 191210284Sjmallett OUTBOUND PCI DMA transfer. I is not used by the hardware when II is set. I 192210284Sjmallett must not be set, and buffers are never freed, for INBOUND, INTERNAL-ONLY, 193210284Sjmallett and EXTERNAL-ONLY PCI DMA transfers. */ 194210284Sjmallett uint64_t back : 4; /**< Back � Backup amount. 195210284Sjmallett Allows the start of a buffer that is to be freed during an OUTBOUND transfer to 196210284Sjmallett be different from the ptr value. Back specifies the amount to subtract from the 197210284Sjmallett pointer to reach the start when freeing a buffer. 198210284Sjmallett The address that is the start of the buffer being freed is: 199210284Sjmallett - Buffer start address = ((ptr >> 7) - Back) << 7. 200210284Sjmallett Back is only used by the hardware when the buffer corresponding to ptr is freed. 201210284Sjmallett Back must be 0x0, and buffers are never freed, for INBOUND, INTERNAL-ONLY, 202210284Sjmallett and EXTERNAL-ONLY PCI DMA transfers. */ 203210284Sjmallett uint64_t pool : 3; /**< Pool � Free pool. 204210284Sjmallett Specifies which pool (of the eight hardware-managed FPA free pools) receives the 205210284Sjmallett buffer associated with ptr when freed during an OUTBOUND transfer. 206210284Sjmallett Pool is only used when the buffer corresponding to ptr is freed. Pool must be 0x0, 207210284Sjmallett and buffers are never freed, for INBOUND, INTERNAL-ONLY, and EXTERNAL-ONLY 208210284Sjmallett PCI DMA transfers. */ 209210284Sjmallett uint64_t f : 1; /**< F � Full-block writes are allowed. 210210284Sjmallett When set, the hardware is permitted to write all the bytes in the cache blocks 211210284Sjmallett covered by ptr, ptr + Size - 1. This can improve memory system performance 212210284Sjmallett when the write misses in the L2 cache. 213210284Sjmallett F can only be set for local pointers that can be written to: 214210284Sjmallett - The local pointers in the FIRST POINTERS area that are write pointers for 215210284Sjmallett INBOUND transfers. 216210284Sjmallett - The local pointers in the LAST POINTERS area that are always write 217210284Sjmallett pointers (when present for INTERNAL-ONLY transfers). 218210284Sjmallett F must not be set for local pointers that are not written to: 219210284Sjmallett - The local pointers in the FIRST POINTERS area for OUTBOUND and 220210284Sjmallett INTERNAL-ONLY transfers. */ 221210284Sjmallett uint64_t a : 1; /**< A � Allocate L2. 222210284Sjmallett This is a hint to the hardware that the cache blocks should be allocated in the L2 223210284Sjmallett cache (if they were not already). */ 224210284Sjmallett uint64_t l : 1; /**< L � Little-endian. 225210284Sjmallett When L is set, the data at ptr is in little-endian format rather than big-endian. */ 226210284Sjmallett uint64_t size : 13; /**< Size � Size in bytes of the contiguous space specified by ptr. A Size value of 0 is 227210284Sjmallett illegal. Note that the sum of the sizes in the FIRST POINTERS area must always 228210284Sjmallett exactly equal the sum of the sizes/lengths in the LAST POINTERS area: 229210284Sjmallett - In the OUTBOUND and INBOUND cases, the HDR.NFST size fields in the 230210284Sjmallett local pointers in the FIRST POINTERS area must exactly equal the lengths 231210284Sjmallett of the HDR.NLST fragments in the PCI components in the LAST POINTERS 232210284Sjmallett area. 233210284Sjmallett - In the INTERNAL-ONLY case, the HDR.NFST size fields in the local 234210284Sjmallett pointers in the FIRST POINTERS area must equal the HDR.NLST size 235210284Sjmallett fields in the local pointers in the LAST POINTERS area. */ 236210284Sjmallett uint64_t reserved_36_39 : 4; /**< Must be zero */ 237210284Sjmallett uint64_t addr : 36; /**< L2/DRAM byte pointer. Points to where the packet data starts. 238210284Sjmallett Ptr can be any byte alignment. Note that ptr is interpreted as a big-endian byte 239210284Sjmallett pointer when L is clear, a little-endian byte pointer when L is set. */ 240210284Sjmallett } internal; 241210284Sjmallett struct 242210284Sjmallett { 243210284Sjmallett uint64_t len0 : 16; /**< Length of PCI / PCIe memory for address 0 */ 244210284Sjmallett uint64_t len1 : 16; /**< Length of PCI / PCIe memory for address 1 */ 245210284Sjmallett uint64_t len2 : 16; /**< Length of PCI / PCIe memory for address 2 */ 246210284Sjmallett uint64_t len3 : 16; /**< Length of PCI / PCIe memory for address 3 */ 247210284Sjmallett } pcie_length; 248210284Sjmallett} cvmx_dma_engine_buffer_t; 249210284Sjmallett 250210284Sjmallett/** 251210284Sjmallett * Initialize the DMA engines for use 252210284Sjmallett * 253210284Sjmallett * @return Zero on success, negative on failure 254210284Sjmallett */ 255210284Sjmallettint cvmx_dma_engine_initialize(void); 256210284Sjmallett 257210284Sjmallett/** 258210284Sjmallett * Shutdown all DMA engines. The engeines must be idle when this 259210284Sjmallett * function is called. 260210284Sjmallett * 261210284Sjmallett * @return Zero on success, negative on failure 262210284Sjmallett */ 263210284Sjmallettint cvmx_dma_engine_shutdown(void); 264210284Sjmallett 265210284Sjmallett/** 266210284Sjmallett * Return the number of DMA engimes supported by this chip 267210284Sjmallett * 268210284Sjmallett * @return Number of DMA engines 269210284Sjmallett */ 270210284Sjmallettint cvmx_dma_engine_get_num(void); 271210284Sjmallett 272210284Sjmallett/** 273232812Sjmallett * Submit a series of DMA command to the DMA engines. 274210284Sjmallett * 275215990Sjmallett * @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1) 276210284Sjmallett * @param header Command header 277210284Sjmallett * @param num_buffers 278210284Sjmallett * The number of data pointers 279232812Sjmallett * @param buffers Command data pointers 280210284Sjmallett * 281210284Sjmallett * @return Zero on success, negative on failure 282210284Sjmallett */ 283210284Sjmallettint cvmx_dma_engine_submit(int engine, cvmx_dma_engine_header_t header, int num_buffers, cvmx_dma_engine_buffer_t buffers[]); 284210284Sjmallett 285210284Sjmallett/** 286210284Sjmallett * Build the first and last pointers based on a DMA engine header 287210284Sjmallett * and submit them to the engine. The purpose of this function is 288210284Sjmallett * to simplify the building of DMA engine commands by automatically 289210284Sjmallett * converting a simple address and size into the apropriate internal 290210284Sjmallett * or PCI / PCIe address list. This function does not support gather lists, 291210284Sjmallett * so you will need to build your own lists in that case. 292210284Sjmallett * 293215990Sjmallett * @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1) 294210284Sjmallett * @param header DMA Command header. Note that the nfst and nlst fields do not 295210284Sjmallett * need to be filled in. All other fields must be set properly. 296210284Sjmallett * @param first_address 297210284Sjmallett * Address to use for the first pointers. In the case of INTERNAL, 298210284Sjmallett * INBOUND, and OUTBOUND this is an Octeon memory address. In the 299210284Sjmallett * case of EXTERNAL, this is the source PCI / PCIe address. 300210284Sjmallett * @param last_address 301210284Sjmallett * Address to use for the last pointers. In the case of EXTERNAL, 302210284Sjmallett * INBOUND, and OUTBOUND this is a PCI / PCIe address. In the 303210284Sjmallett * case of INTERNAL, this is the Octeon memory destination address. 304210284Sjmallett * @param size Size of the transfer to perform. 305210284Sjmallett * 306210284Sjmallett * @return Zero on success, negative on failure 307210284Sjmallett */ 308210284Sjmallettint cvmx_dma_engine_transfer(int engine, cvmx_dma_engine_header_t header, 309210284Sjmallett uint64_t first_address, uint64_t last_address, 310210284Sjmallett int size); 311210284Sjmallett 312210284Sjmallett/** 313210284Sjmallett * Simplified interface to the DMA engines to emulate memcpy() 314210284Sjmallett * 315215990Sjmallett * @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1) 316210284Sjmallett * @param dest Pointer to the destination memory. cvmx_ptr_to_phys() will be 317210284Sjmallett * used to turn this into a physical address. It cannot be a local 318210284Sjmallett * or CVMX_SHARED block. 319210284Sjmallett * @param source Pointer to the source memory. 320210284Sjmallett * cvmx_ptr_to_phys() will be used to turn this 321210284Sjmallett * into a physical address. It cannot be a local 322210284Sjmallett * or CVMX_SHARED block. 323210284Sjmallett * @param length Number of bytes to copy 324210284Sjmallett * 325210284Sjmallett * @return Zero on success, negative on failure 326210284Sjmallett */ 327210284Sjmallettstatic inline int cvmx_dma_engine_memcpy(int engine, void *dest, void *source, int length) 328210284Sjmallett{ 329210284Sjmallett cvmx_dma_engine_header_t header; 330210284Sjmallett header.u64 = 0; 331210284Sjmallett header.s.type = CVMX_DMA_ENGINE_TRANSFER_INTERNAL; 332210284Sjmallett return cvmx_dma_engine_transfer(engine, header, cvmx_ptr_to_phys(source), 333210284Sjmallett cvmx_ptr_to_phys(dest), length); 334210284Sjmallett} 335210284Sjmallett 336232812Sjmallett/** 337232812Sjmallett * Simplified interface to the DMA engines to emulate memcpy() 338232812Sjmallett * When dici_mode is enabled, send zero byte. 339232812Sjmallett * 340232812Sjmallett * @param engine Engine to submit to (0 to cvmx_dma_engine_get_num()-1) 341232812Sjmallett * @param dest Pointer to the destination memory. cvmx_ptr_to_phys() will be 342232812Sjmallett * used to turn this into a physical address. It cannot be a local 343232812Sjmallett * or CVMX_SHARED block. 344232812Sjmallett * @param source Pointer to the source memory. 345232812Sjmallett * cvmx_ptr_to_phys() will be used to turn this 346232812Sjmallett * into a physical address. It cannot be a local 347232812Sjmallett * or CVMX_SHARED block. 348232812Sjmallett * @param length Number of bytes to copy 349232812Sjmallett * @param core core number for zero byte write 350232812Sjmallett * 351232812Sjmallett * @return Zero on success, negative on failure 352232812Sjmallett */ 353232812Sjmallettstatic inline int cvmx_dma_engine_memcpy_zero_byte(int engine, void *dest, void *source, int length, int core) 354232812Sjmallett{ 355232812Sjmallett cvmx_dma_engine_header_t header; 356232812Sjmallett header.u64 = 0; 357232812Sjmallett header.s.type = CVMX_DMA_ENGINE_TRANSFER_INTERNAL; 358232812Sjmallett /* If dici_mode is set, DPI increments the DPI_DMA_PPn_CNT[CNT], where the 359232812Sjmallett value of core n is PTR<5:0>-1 when WQP=0 and PTR != 0 && PTR < 64. */ 360232812Sjmallett if (octeon_has_feature(OCTEON_FEATURE_DICI_MODE)) 361232812Sjmallett { 362232812Sjmallett cvmx_dpi_dma_control_t dma_control; 363232812Sjmallett dma_control.u64 = cvmx_read_csr(CVMX_DPI_DMA_CONTROL); 364232812Sjmallett if (dma_control.s.dici_mode) 365232812Sjmallett { 366232812Sjmallett header.s.wqp = 0; // local memory pointer 367232812Sjmallett header.s.addr = core + 1; 368232812Sjmallett } 369232812Sjmallett } 370232812Sjmallett return cvmx_dma_engine_transfer(engine, header, cvmx_ptr_to_phys(source), 371232812Sjmallett cvmx_ptr_to_phys(dest), length); 372232812Sjmallett} 373232812Sjmallett 374210284Sjmallett#ifdef __cplusplus 375210284Sjmallett} 376210284Sjmallett#endif 377210284Sjmallett 378210284Sjmallett#endif // __CVMX_CMD_QUEUE_H__ 379