1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * @file 43215976Sjmallett * 44215976Sjmallett * Interface to debug exception handler 45215976Sjmallett * 46215976Sjmallett * <hr>$Revision: $<hr> 47215976Sjmallett */ 48215976Sjmallett 49215976Sjmallett#ifndef __CVMX_DEBUG_H__ 50215976Sjmallett#define __CVMX_DEBUG_H__ 51215976Sjmallett 52215976Sjmallett#include "cvmx-core.h" 53215976Sjmallett#include "cvmx-spinlock.h" 54215976Sjmallett 55215976Sjmallett 56215976Sjmallett#define CVMX_DEBUG_MAX_REQUEST_SIZE 1024 + 34 /* Enough room for setting memory of 512 bytes. */ 57215976Sjmallett#define CVMX_DEBUG_MAX_RESPONSE_SIZE 1024 + 5 58215976Sjmallett 59215976Sjmallett#define CVMX_DEBUG_GLOBALS_BLOCK_NAME "cvmx-debug-globals" 60215976Sjmallett#define CVMX_DEBUG_GLOBALS_VERSION 3 61215976Sjmallett 62215976Sjmallett#ifdef __cplusplus 63215976Sjmallettextern "C" { 64215976Sjmallett#endif 65215976Sjmallett 66215976Sjmallettvoid cvmx_debug_init(void); 67215976Sjmallettvoid cvmx_debug_finish(void); 68215976Sjmallettvoid cvmx_debug_trigger_exception(void); 69215976Sjmallett 70232812Sjmallett#ifdef CVMX_BUILD_FOR_TOOLCHAIN 71215976Sjmallettextern int __octeon_debug_booted; 72215976Sjmallett 73215976Sjmallettstatic inline int cvmx_debug_booted(void) 74215976Sjmallett{ 75215976Sjmallett return __octeon_debug_booted; 76215976Sjmallett} 77215976Sjmallett 78215976Sjmallett#else 79215976Sjmallett 80215976Sjmallettstatic inline int cvmx_debug_booted(void) 81215976Sjmallett{ 82215976Sjmallett return cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_DEBUG; 83215976Sjmallett} 84215976Sjmallett#endif 85215976Sjmallett 86215976Sjmallett/* There are 64 TLB entries in CN5XXX and 32 TLB entries in CN3XXX and 87215976Sjmallett 128 TLB entries in CN6XXX. */ 88215976Sjmallett#define CVMX_DEBUG_N_TLB_ENTRIES 128 89215976Sjmallett 90215976Sjmallett/* Maximium number of hardware breakpoints/watchpoints allowed */ 91215976Sjmallett#define CVMX_DEBUG_MAX_OCTEON_HW_BREAKPOINTS 4 92215976Sjmallett 93215976Sjmalletttypedef struct 94215976Sjmallett{ 95215976Sjmallett volatile uint64_t remote_controlled; 96215976Sjmallett uint64_t regs[32]; 97215976Sjmallett uint64_t lo; 98215976Sjmallett uint64_t hi; 99215976Sjmallett 100215976Sjmallett#define CVMX_DEBUG_BASIC_CONTEXT \ 101215976Sjmallett F(remote_controlled); \ 102215976Sjmallett { int i; \ 103215976Sjmallett for (i = 0; i < 32; i++) \ 104215976Sjmallett F(regs[i]); \ 105215976Sjmallett } \ 106215976Sjmallett F(lo); \ 107215976Sjmallett F(hi); 108215976Sjmallett 109215976Sjmallett struct { 110215976Sjmallett uint64_t index; 111215976Sjmallett uint64_t entrylo[2]; 112215976Sjmallett uint64_t entryhi; 113215976Sjmallett uint64_t pagemask; 114215976Sjmallett uint64_t status; 115215976Sjmallett uint64_t badvaddr; 116215976Sjmallett uint64_t cause; 117215976Sjmallett uint64_t depc; 118215976Sjmallett uint64_t desave; 119215976Sjmallett uint64_t debug; 120215976Sjmallett uint64_t multicoredebug; 121215976Sjmallett uint64_t perfval[2]; 122215976Sjmallett uint64_t perfctrl[2]; 123215976Sjmallett } cop0; 124215976Sjmallett 125215976Sjmallett#define CVMX_DEBUG_COP0_CONTEXT \ 126215976Sjmallett F(cop0.index); \ 127215976Sjmallett F(cop0.entrylo[0]); \ 128215976Sjmallett F(cop0.entrylo[1]); \ 129215976Sjmallett F(cop0.entryhi); \ 130215976Sjmallett F(cop0.pagemask); \ 131215976Sjmallett F(cop0.status); \ 132215976Sjmallett F(cop0.badvaddr); \ 133215976Sjmallett F(cop0.cause); \ 134215976Sjmallett F(cop0.depc); \ 135215976Sjmallett F(cop0.desave); \ 136215976Sjmallett F(cop0.debug); \ 137215976Sjmallett F(cop0.multicoredebug); \ 138215976Sjmallett F(cop0.perfval[0]); \ 139215976Sjmallett F(cop0.perfval[1]); \ 140215976Sjmallett F(cop0.perfctrl[0]); \ 141215976Sjmallett F(cop0.perfctrl[1]); 142215976Sjmallett 143215976Sjmallett struct 144215976Sjmallett { 145215976Sjmallett uint64_t status; 146215976Sjmallett uint64_t address[4]; 147215976Sjmallett uint64_t address_mask[4]; 148215976Sjmallett uint64_t asid[4]; 149215976Sjmallett uint64_t control[4]; 150215976Sjmallett } hw_ibp, hw_dbp; 151215976Sjmallett 152215976Sjmallett/* Hardware Instruction Break Point */ 153215976Sjmallett 154215976Sjmallett#define CVMX_DEBUG_HW_IBP_CONTEXT \ 155215976Sjmallett F(hw_ibp.status); \ 156215976Sjmallett F(hw_ibp.address[0]); \ 157215976Sjmallett F(hw_ibp.address[1]); \ 158215976Sjmallett F(hw_ibp.address[2]); \ 159215976Sjmallett F(hw_ibp.address[3]); \ 160215976Sjmallett F(hw_ibp.address_mask[0]); \ 161215976Sjmallett F(hw_ibp.address_mask[1]); \ 162215976Sjmallett F(hw_ibp.address_mask[2]); \ 163215976Sjmallett F(hw_ibp.address_mask[3]); \ 164215976Sjmallett F(hw_ibp.asid[0]); \ 165215976Sjmallett F(hw_ibp.asid[1]); \ 166215976Sjmallett F(hw_ibp.asid[2]); \ 167215976Sjmallett F(hw_ibp.asid[3]); \ 168215976Sjmallett F(hw_ibp.control[0]); \ 169215976Sjmallett F(hw_ibp.control[1]); \ 170215976Sjmallett F(hw_ibp.control[2]); \ 171215976Sjmallett F(hw_ibp.control[3]); 172215976Sjmallett 173215976Sjmallett/* Hardware Data Break Point */ 174215976Sjmallett#define CVMX_DEBUG_HW_DBP_CONTEXT \ 175215976Sjmallett F(hw_dbp.status); \ 176215976Sjmallett F(hw_dbp.address[0]); \ 177215976Sjmallett F(hw_dbp.address[1]); \ 178215976Sjmallett F(hw_dbp.address[2]); \ 179215976Sjmallett F(hw_dbp.address[3]); \ 180215976Sjmallett F(hw_dbp.address_mask[0]); \ 181215976Sjmallett F(hw_dbp.address_mask[1]); \ 182215976Sjmallett F(hw_dbp.address_mask[2]); \ 183215976Sjmallett F(hw_dbp.address_mask[3]); \ 184215976Sjmallett F(hw_dbp.asid[0]); \ 185215976Sjmallett F(hw_dbp.asid[1]); \ 186215976Sjmallett F(hw_dbp.asid[2]); \ 187215976Sjmallett F(hw_dbp.asid[3]); \ 188215976Sjmallett F(hw_dbp.control[0]); \ 189215976Sjmallett F(hw_dbp.control[1]); \ 190215976Sjmallett F(hw_dbp.control[2]); \ 191215976Sjmallett F(hw_dbp.control[3]); 192215976Sjmallett 193215976Sjmallett 194215976Sjmallett struct cvmx_debug_tlb_t 195215976Sjmallett { 196215976Sjmallett uint64_t entryhi; 197215976Sjmallett uint64_t pagemask; 198215976Sjmallett uint64_t entrylo[2]; 199215976Sjmallett uint64_t reserved; 200215976Sjmallett } tlbs[CVMX_DEBUG_N_TLB_ENTRIES]; 201215976Sjmallett 202215976Sjmallett#define CVMX_DEBUG_TLB_CONTEXT \ 203215976Sjmallett { int i; \ 204215976Sjmallett for (i = 0; i < CVMX_DEBUG_N_TLB_ENTRIES; i++) \ 205215976Sjmallett { \ 206215976Sjmallett F(tlbs[i].entryhi); \ 207215976Sjmallett F(tlbs[i].pagemask); \ 208215976Sjmallett F(tlbs[i].entrylo[0]); \ 209215976Sjmallett F(tlbs[i].entrylo[1]); \ 210215976Sjmallett } \ 211215976Sjmallett } 212215976Sjmallett 213215976Sjmallett} cvmx_debug_core_context_t; 214215976Sjmallett 215215976Sjmalletttypedef struct cvmx_debug_tlb_t cvmx_debug_tlb_t; 216215976Sjmallett 217215976Sjmallett 218215976Sjmallett 219215976Sjmalletttypedef enum cvmx_debug_comm_type_e 220215976Sjmallett{ 221215976Sjmallett COMM_UART, 222215976Sjmallett COMM_REMOTE, 223215976Sjmallett COMM_SIZE 224215976Sjmallett}cvmx_debug_comm_type_t; 225215976Sjmallett 226215976Sjmalletttypedef enum 227215976Sjmallett{ 228215976Sjmallett COMMAND_NOP = 0, /**< Core doesn't need to do anything. Just stay in exception handler */ 229215976Sjmallett COMMAND_STEP, /**< Core needs to perform a single instruction step */ 230215976Sjmallett COMMAND_CONTINUE /**< Core need to start running. Doesn't return until some debug event occurs */ 231215976Sjmallett} cvmx_debug_command_t; 232215976Sjmallett 233215976Sjmallett/* Every field in this struct has to be uint32_t. */ 234215976Sjmalletttypedef struct 235215976Sjmallett{ 236215976Sjmallett uint32_t known_cores; 237215976Sjmallett uint32_t step_isr; /**< True if we are going to step into ISR's. */ 238215976Sjmallett uint32_t focus_switch; /**< Focus can be switched. */ 239215976Sjmallett uint32_t core_finished; /**< True if a core has finished and not been processed yet. */ 240215976Sjmallett uint32_t command; /**< Command for all cores (cvmx_debug_command_t) */ 241215976Sjmallett uint32_t step_all; /**< True if step and continue should affect all cores. False, only the focus core is affected */ 242215976Sjmallett uint32_t focus_core; /**< Core currently under control of the debugger */ 243215976Sjmallett uint32_t active_cores; /**< Bitmask of cores that should stop on a breakpoint */ 244215976Sjmallett uint32_t handler_cores; /**< Bitmask of cores currently running the exception handler */ 245215976Sjmallett uint32_t ever_been_in_debug; /**< True if we have been ever been in the debugger stub at all. */ 246215976Sjmallett}__attribute__ ((aligned(sizeof(uint64_t)))) cvmx_debug_state_t; 247215976Sjmallett 248215976Sjmalletttypedef int cvmx_debug_state_t_should_fit_inside_a_cache_block[sizeof(cvmx_debug_state_t)+sizeof(cvmx_spinlock_t)+4*sizeof(uint64_t) > 128 ? -1 : 1]; 249215976Sjmallett 250215976Sjmalletttypedef struct cvmx_debug_globals_s 251215976Sjmallett{ 252215976Sjmallett uint64_t version; /* This is always the first element of this struct */ 253215976Sjmallett uint64_t comm_type; /* cvmx_debug_comm_type_t */ 254215976Sjmallett volatile uint64_t comm_changed; /* cvmx_debug_comm_type_t+1 when someone wants to change it. */ 255215976Sjmallett volatile uint64_t init_complete; 256215976Sjmallett uint32_t tlb_entries; 257215976Sjmallett uint32_t state[sizeof(cvmx_debug_state_t)/sizeof(uint32_t)]; 258215976Sjmallett cvmx_spinlock_t lock; 259215976Sjmallett 260232812Sjmallett volatile cvmx_debug_core_context_t contextes[CVMX_MAX_CORES]; 261215976Sjmallett} cvmx_debug_globals_t; 262215976Sjmallett 263215976Sjmalletttypedef union 264215976Sjmallett{ 265215976Sjmallett uint64_t u64; 266215976Sjmallett struct 267215976Sjmallett { 268215976Sjmallett uint64_t rsrvd:32; /**< Unused */ 269215976Sjmallett uint64_t dbd:1; /**< Indicates whether the last debug exception or 270215976Sjmallett exception in Debug Mode occurred in a branch or 271215976Sjmallett jump delay slot */ 272215976Sjmallett uint64_t dm:1; /**< Indicates that the processor is operating in Debug 273215976Sjmallett Mode: */ 274215976Sjmallett uint64_t nodcr:1; /**< Indicates whether the dseg segment is present */ 275215976Sjmallett uint64_t lsnm:1; /**< Controls access of loads/stores between the dseg 276215976Sjmallett segment and remaining memory when the dseg 277215976Sjmallett segment is present */ 278215976Sjmallett uint64_t doze:1; /**< Indicates that the processor was in a low-power mode 279215976Sjmallett when a debug exception occurred */ 280215976Sjmallett uint64_t halt:1; /**< Indicates that the internal processor system bus clock 281215976Sjmallett was stopped when the debug exception occurred */ 282215976Sjmallett uint64_t countdm:1; /**< Controls or indicates the Count register behavior in 283215976Sjmallett Debug Mode. Implementations can have fixed 284215976Sjmallett behavior, in which case this bit is read-only (R), or 285215976Sjmallett the implementation can allow this bit to control the 286215976Sjmallett behavior, in which case this bit is read/write (R/W). 287215976Sjmallett The reset value of this bit indicates the behavior after 288215976Sjmallett reset, and depends on the implementation. 289215976Sjmallett Encoding of the bit is: 290215976Sjmallett - 0 Count register stopped in Debug Mode Count register is running in Debug 291215976Sjmallett - 1 Mode 292215976Sjmallett This bit is read-only (R) and reads as zero if not implemented. */ 293215976Sjmallett uint64_t ibusep:1; /**< Indicates if a Bus Error exception is pending from an 294215976Sjmallett instruction fetch. Set when an instruction fetch bus 295215976Sjmallett error event occurs or a 1 is written to the bit by 296215976Sjmallett software. Cleared when a Bus Error exception on an 297215976Sjmallett instruction fetch is taken by the processor. If IBusEP 298215976Sjmallett is set when IEXI is cleared, a Bus Error exception on 299215976Sjmallett an instruction fetch is taken by the processor, and 300215976Sjmallett IBusEP is cleared. 301215976Sjmallett In Debug Mode, a Bus Error exception applies to a 302215976Sjmallett Debug Mode Bus Error exception. 303215976Sjmallett This bit is read-only (R) and reads as zero if not 304215976Sjmallett implemented. */ 305215976Sjmallett uint64_t mcheckp:1; /**< Indicates if a Machine Check exception is pending. 306215976Sjmallett Set when a machine check event occurs or a 1 is 307215976Sjmallett written to the bit by software. Cleared when a 308215976Sjmallett Machine Check exception is taken by the processor. 309215976Sjmallett If MCheckP is set when IEXI is cleared, a Machine 310215976Sjmallett Check exception is taken by the processor, and 311215976Sjmallett MCheckP is cleared. 312215976Sjmallett In Debug Mode, a Machine Check exception applies 313215976Sjmallett to a Debug Mode Machine Check exception. 314215976Sjmallett This bit is read-only (R) and reads as zero if not 315215976Sjmallett implemented. */ 316215976Sjmallett uint64_t cacheep:1; /**< Indicates if a Cache Error is pending. Set when a 317215976Sjmallett cache error event occurs or a 1 is written to the bit by 318215976Sjmallett software. Cleared when a Cache Error exception is 319215976Sjmallett taken by the processor. If CacheEP is set when IEXI 320215976Sjmallett is cleared, a Cache Error exception is taken by the 321215976Sjmallett processor, and CacheEP is cleared. 322215976Sjmallett In Debug Mode, a Cache Error exception applies to a 323215976Sjmallett Debug Mode Cache Error exception. 324215976Sjmallett This bit is read-only (R) and reads as zero if not 325215976Sjmallett implemented. */ 326215976Sjmallett uint64_t dbusep:1; /**< Indicates if a Data Access Bus Error exception is 327215976Sjmallett pending. Set when a data access bus error event 328215976Sjmallett occurs or a 1 is written to the bit by software. Cleared 329215976Sjmallett when a Bus Error exception on data access is taken by 330215976Sjmallett the processor. If DBusEP is set when IEXI is cleared, 331215976Sjmallett a Bus Error exception on data access is taken by the 332215976Sjmallett processor, and DBusEP is cleared. 333215976Sjmallett In Debug Mode, a Bus Error exception applies to a 334215976Sjmallett Debug Mode Bus Error exception. 335215976Sjmallett This bit is read-only (R) and reads as zero if not 336215976Sjmallett implemented. */ 337215976Sjmallett uint64_t iexi:1; /**< An Imprecise Error eXception Inhibit (IEXI) controls 338215976Sjmallett exceptions taken due to imprecise error indications. 339215976Sjmallett Set when the processor takes a debug exception or an 340215976Sjmallett exception in Debug Mode occurs. Cleared by 341215976Sjmallett execution of the DERET instruction. Otherwise 342215976Sjmallett modifiable by Debug Mode software. 343215976Sjmallett When IEXI is set, then the imprecise error exceptions 344215976Sjmallett from bus errors on instruction fetches or data 345215976Sjmallett accesses, cache errors, or machine checks are 346215976Sjmallett inhibited and deferred until the bit is cleared. 347215976Sjmallett This bit is read-only (R) and reads as zero if not 348215976Sjmallett implemented. */ 349215976Sjmallett uint64_t ddbsimpr:1; /**< Indicates that a Debug Data Break Store Imprecise 350215976Sjmallett exception due to a store was the cause of the debug 351215976Sjmallett exception, or that an imprecise data hardware break 352215976Sjmallett due to a store was indicated after another debug 353215976Sjmallett exception occurred. Cleared on exception in Debug 354215976Sjmallett Mode. 355215976Sjmallett - 0 No match of an imprecise data hardware breakpoint on store 356215976Sjmallett - 1 Match of imprecise data hardware breakpoint on store 357215976Sjmallett This bit is read-only (R) and reads as zero if not 358215976Sjmallett implemented. */ 359215976Sjmallett uint64_t ddblimpr:1; /**< Indicates that a Debug Data Break Load Imprecise 360215976Sjmallett exception due to a load was the cause of the debug 361215976Sjmallett exception, or that an imprecise data hardware break 362215976Sjmallett due to a load was indicated after another debug 363215976Sjmallett exception occurred. Cleared on exception in Debug 364215976Sjmallett Mode. 365215976Sjmallett - 0 No match of an imprecise data hardware breakpoint on load 366215976Sjmallett - 1 Match of imprecise data hardware breakpoint on load 367215976Sjmallett This bit is read-only (R) and reads as zero if not 368215976Sjmallett implemented. */ 369215976Sjmallett uint64_t ejtagver:3; /**< Provides the EJTAG version. 370215976Sjmallett - 0 Version 1 and 2.0 371215976Sjmallett - 1 Version 2.5 372215976Sjmallett - 2 Version 2.6 373215976Sjmallett - 3-7 Reserved */ 374215976Sjmallett uint64_t dexccode:5; /**< Indicates the cause of the latest exception in Debug 375215976Sjmallett Mode. 376215976Sjmallett The field is encoded as the ExcCode field in the 377215976Sjmallett Cause register for those exceptions that can occur in 378215976Sjmallett Debug Mode (the encoding is shown in MIPS32 and 379215976Sjmallett MIPS64 specifications), with addition of code 30 380215976Sjmallett with the mnemonic CacheErr for cache errors and the 381215976Sjmallett use of code 9 with mnemonic Bp for the SDBBP 382215976Sjmallett instruction. 383215976Sjmallett This value is undefined after a debug exception. */ 384215976Sjmallett uint64_t nosst:1; /**< Indicates whether the single-step feature controllable 385215976Sjmallett by the SSt bit is available in this implementation: 386215976Sjmallett - 0 Single-step feature available 387215976Sjmallett - 1 No single-step feature available 388215976Sjmallett A minimum number of hardware instruction 389215976Sjmallett breakpoints must be available if no single-step 390215976Sjmallett feature is implemented in hardware. Refer to Section 391215976Sjmallett 4.8.1 on page 69 for more information. */ 392215976Sjmallett uint64_t sst:1; /**< Controls whether single-step feature is enabled: 393215976Sjmallett - 0 No enable of single-step feature 394215976Sjmallett - 1 Single-step feature enabled 395215976Sjmallett This bit is read-only (R) and reads as zero if not 396215976Sjmallett implemented due to no single-step feature (NoSSt is 397215976Sjmallett 1). */ 398215976Sjmallett uint64_t rsrvd2:2; /**< Must be zero */ 399215976Sjmallett uint64_t dint:1; /**< Indicates that a Debug Interrupt exception occurred. 400215976Sjmallett Cleared on exception in Debug Mode. 401215976Sjmallett - 0 No Debug Interrupt exception 402215976Sjmallett - 1 Debug Interrupt exception 403215976Sjmallett This bit is read-only (R) and reads as zero if not 404215976Sjmallett implemented. */ 405215976Sjmallett uint64_t dib:1; /**< Indicates that a Debug Instruction Break exception 406215976Sjmallett occurred. Cleared on exception in Debug Mode. 407215976Sjmallett - 0 No Debug Instruction Break exception 408215976Sjmallett - 1 Debug Instruction Break exception 409215976Sjmallett This bit is read-only (R) and reads as zero if not 410215976Sjmallett implemented. */ 411215976Sjmallett uint64_t ddbs:1; /**< Indicates that a Debug Data Break Store exception 412215976Sjmallett occurred on a store due to a precise data hardware 413215976Sjmallett break. Cleared on exception in Debug Mode. 414215976Sjmallett - 0 No Debug Data Break Store Exception 415215976Sjmallett - 1 Debug Data Break Store Exception 416215976Sjmallett This bit is read-only (R) and reads as zero if not 417215976Sjmallett implemented. */ 418215976Sjmallett uint64_t ddbl:1; /**< Indicates that a Debug Data Break Load exception 419215976Sjmallett occurred on a load due to a precise data hardware 420215976Sjmallett break. Cleared on exception in Debug Mode. 421215976Sjmallett - 0 No Debug Data Break Store Exception 422215976Sjmallett - 1 Debug Data Break Store Exception 423215976Sjmallett This bit is read-only (R) and reads as zero if not 424215976Sjmallett implemented. */ 425215976Sjmallett uint64_t dbp:1; /**< Indicates that a Debug Breakpoint exception 426215976Sjmallett occurred. Cleared on exception in Debug Mode. 427215976Sjmallett - 0 No Debug Breakpoint exception 428215976Sjmallett - 1 Debug Breakpoint exception */ 429215976Sjmallett uint64_t dss:1; /**< Indicates that a Debug Single Step exception 430215976Sjmallett occurred. Cleared on exception in Debug Mode. 431215976Sjmallett - 0 No debug single-step exception 432215976Sjmallett - 1 Debug single-step exception 433215976Sjmallett This bit is read-only (R) and reads as zero if not 434215976Sjmallett implemented. */ 435215976Sjmallett } s; 436215976Sjmallett} cvmx_debug_register_t; 437215976Sjmallett 438215976Sjmallett 439215976Sjmalletttypedef struct 440215976Sjmallett{ 441215976Sjmallett void (*init)(void); 442215976Sjmallett void (*install_break_handler)(void); 443215976Sjmallett int needs_proxy; 444215976Sjmallett int (*getpacket)(char *, size_t); 445215976Sjmallett int (*putpacket)(char *); 446215976Sjmallett void (*wait_for_resume)(volatile cvmx_debug_core_context_t *, cvmx_debug_state_t); 447215976Sjmallett void (*change_core)(int, int); 448215976Sjmallett} cvmx_debug_comm_t; 449215976Sjmallett 450215976Sjmallett#ifdef __cplusplus 451215976Sjmallett} 452215976Sjmallett#endif 453215976Sjmallett 454215976Sjmallett#endif /* __CVMX_DEBUG_H__ */ 455