cvmx-core.h revision 302408
1191005Sdelphij/***********************license start*************** 231899Ssef * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 331899Ssef * reserved. 431899Ssef * 531899Ssef * 631899Ssef * Redistribution and use in source and binary forms, with or without 731899Ssef * modification, are permitted provided that the following conditions are 831899Ssef * met: 931899Ssef * 1031899Ssef * * Redistributions of source code must retain the above copyright 1131899Ssef * notice, this list of conditions and the following disclaimer. 1231899Ssef * 1331899Ssef * * Redistributions in binary form must reproduce the above 1431899Ssef * copyright notice, this list of conditions and the following 1531899Ssef * disclaimer in the documentation and/or other materials provided 1631899Ssef * with the distribution. 1731899Ssef 1831899Ssef * * Neither the name of Cavium Inc. nor the names of 1931899Ssef * its contributors may be used to endorse or promote products 2031899Ssef * derived from this software without specific prior written 2131899Ssef * permission. 2231899Ssef 2331899Ssef * This Software, including technical data, may be subject to U.S. export control 2431899Ssef * laws, including the U.S. Export Administration Act and its associated 2531899Ssef * regulations, and may be subject to export or import regulations in other 2631899Ssef * countries. 2731899Ssef 2831899Ssef * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 2931899Ssef * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 3031899Ssef * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 3131899Ssef * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32119852Scharnier * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33119852Scharnier * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 3432275Scharnier * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 3531899Ssef * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 3631567Ssef * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 3731567Ssef * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 3831567Ssef ***********************license end**************************************/ 3931567Ssef 4031567Ssef 4185301Sdes 42123916Scracauer 43104581Smike 44123916Scracauer 45168569Sdelphij 46191005Sdelphij/** 4785301Sdes * @file 48132306Salfred * 4932275Scharnier * Module to support operations on core such as TLB config, etc. 5032275Scharnier * 5132275Scharnier * <hr>$Revision: 70030 $<hr> 5232275Scharnier * 5331567Ssef */ 5431567Ssef 5531567Ssef 56101423Smdodd#ifndef __CVMX_CORE_H__ 5731579Speter#define __CVMX_CORE_H__ 5831567Ssef 59101282Smdodd#ifdef __cplusplus 6087703Smarkmextern "C" { 6131567Ssef#endif 62171645Smarcel 6331567Ssef/** 64144177Salfred * The types of performance counters supported per cpu 6532275Scharnier */ 6632275Scharniertypedef enum 67144177Salfred{ 68153963Sbrian CVMX_CORE_PERF_NONE = 0, /**< Turn off the performance counter */ 69153963Sbrian CVMX_CORE_PERF_CLK = 1, /**< Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) */ 70144177Salfred CVMX_CORE_PERF_ISSUE = 2, /**< Instructions issued but not retired */ 7131567Ssef CVMX_CORE_PERF_RET = 3, /**< Instructions retired */ 7231567Ssef CVMX_CORE_PERF_NISSUE = 4, /**< Cycles no issue */ 7338897Ssef CVMX_CORE_PERF_SISSUE = 5, /**< Cycles single issue */ 7438897Ssef CVMX_CORE_PERF_DISSUE = 6, /**< Cycles dual issue */ 7538897Ssef CVMX_CORE_PERF_IFI = 7, /**< Cycle ifetch issued (but not necessarily commit to pp_mem) */ 7638897Ssef CVMX_CORE_PERF_BR = 8, /**< Branches retired */ 7731567Ssef CVMX_CORE_PERF_BRMIS = 9, /**< Branch mispredicts */ 78144177Salfred CVMX_CORE_PERF_J = 10, /**< Jumps retired */ 79144177Salfred CVMX_CORE_PERF_JMIS = 11, /**< Jumps mispredicted */ 80144177Salfred CVMX_CORE_PERF_REPLAY = 12, /**< Mem Replays */ 8131567Ssef CVMX_CORE_PERF_IUNA = 13, /**< Cycles idle due to unaligned_replays */ 82130394Sdwmalone CVMX_CORE_PERF_TRAP = 14, /**< trap_6a signal */ 83144177Salfred CVMX_CORE_PERF_UULOAD = 16, /**< Unexpected unaligned loads (REPUN=1) */ 84179051Sjhb CVMX_CORE_PERF_UUSTORE = 17, /**< Unexpected unaligned store (REPUN=1) */ 85179051Sjhb CVMX_CORE_PERF_ULOAD = 18, /**< Unaligned loads (REPUN=1 or USEUN=1) */ 86130394Sdwmalone CVMX_CORE_PERF_USTORE = 19, /**< Unaligned store (REPUN=1 or USEUN=1) */ 8739908Ssef CVMX_CORE_PERF_EC = 20, /**< Exec clocks(must set CvmCtl[DISCE] for accurate timing) */ 88144177Salfred CVMX_CORE_PERF_MC = 21, /**< Mul clocks(must set CvmCtl[DISCE] for accurate timing) */ 89144177Salfred CVMX_CORE_PERF_CC = 22, /**< Crypto clocks(must set CvmCtl[DISCE] for accurate timing) */ 90144177Salfred CVMX_CORE_PERF_CSRC = 23, /**< Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) */ 91144177Salfred CVMX_CORE_PERF_CFETCH = 24, /**< Icache committed fetches (demand+prefetch) */ 9239908Ssef CVMX_CORE_PERF_CPREF = 25, /**< Icache committed prefetches */ 93106716Smarcel CVMX_CORE_PERF_ICA = 26, /**< Icache aliases */ 94144177Salfred CVMX_CORE_PERF_II = 27, /**< Icache invalidates */ 95106716Smarcel CVMX_CORE_PERF_IP = 28, /**< Icache parity error */ 96154047Sgrehan CVMX_CORE_PERF_CIMISS = 29, /**< Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) */ 97154047Sgrehan CVMX_CORE_PERF_WBUF = 32, /**< Number of write buffer entries created */ 98154047Sgrehan CVMX_CORE_PERF_WDAT = 33, /**< Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 99154047Sgrehan CVMX_CORE_PERF_WBUFLD = 34, /**< Number of write buffer entries forced out by loads */ 100101320Sjake CVMX_CORE_PERF_WBUFFL = 35, /**< Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */ 101144177Salfred CVMX_CORE_PERF_WBUFTR = 36, /**< Number of stores that found no available write buffer entries */ 102101320Sjake CVMX_CORE_PERF_BADD = 37, /**< Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 103188628Simp CVMX_CORE_PERF_BADDL2 = 38, /**< Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) */ 104188628Simp CVMX_CORE_PERF_BFILL = 39, /**< Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 105188628Simp CVMX_CORE_PERF_DDIDS = 40, /**< Number of Dstream DIDs created */ 106188628Simp CVMX_CORE_PERF_IDIDS = 41, /**< Number of Istream DIDs created */ 107188628Simp CVMX_CORE_PERF_DIDNA = 42, /**< Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */ 108144177Salfred CVMX_CORE_PERF_LDS = 43, /**< Number of load issues */ 10931567Ssef CVMX_CORE_PERF_LMLDS = 44, /**< Number of local memory load */ 11031567Ssef CVMX_CORE_PERF_IOLDS = 45, /**< Number of I/O load issues */ 11131567Ssef CVMX_CORE_PERF_DMLDS = 46, /**< Number of loads that were not prefetches and missed in the cache */ 11231567Ssef CVMX_CORE_PERF_STS = 48, /**< Number of store issues */ 113168569Sdelphij CVMX_CORE_PERF_LMSTS = 49, /**< Number of local memory store issues */ 11431567Ssef CVMX_CORE_PERF_IOSTS = 50, /**< Number of I/O store issues */ 11531567Ssef CVMX_CORE_PERF_IOBDMA = 51, /**< Number of IOBDMAs */ 11631567Ssef CVMX_CORE_PERF_DTLB = 53, /**< Number of dstream TLB refill, invalid, or modified exceptions */ 117144177Salfred CVMX_CORE_PERF_DTLBAD = 54, /**< Number of dstream TLB address errors */ 118144177Salfred CVMX_CORE_PERF_ITLB = 55, /**< Number of istream TLB refill, invalid, or address error exceptions */ 119144177Salfred CVMX_CORE_PERF_SYNC = 56, /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */ 120144177Salfred CVMX_CORE_PERF_SYNCIOB = 57, /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */ 121168569Sdelphij CVMX_CORE_PERF_SYNCW = 58, /**< Number of SYNCWs */ 122168569Sdelphij /* Added in CN63XX */ 123168569Sdelphij CVMX_CORE_PERF_ERETMIS = 64, /**< D/eret mispredicts */ 124168569Sdelphij CVMX_CORE_PERF_LIKMIS = 65, /**< Branch likely mispredicts */ 12531567Ssef CVMX_CORE_PERF_HAZTR = 66, /**< Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers */ 126168569Sdelphij CVMX_CORE_PERF_MAX /**< This not a counter, just a marker for the highest number */ 127168569Sdelphij} cvmx_core_perf_t; 128168569Sdelphij 129168569Sdelphij/** 130168569Sdelphij * Bit description of the COP0 counter control register 131168569Sdelphij */ 132168569Sdelphijtypedef union 13331567Ssef{ 134144177Salfred uint32_t u32; 135144177Salfred struct 136144177Salfred { 13731567Ssef#ifdef __BIG_ENDIAN_BITFIELD 138144177Salfred uint32_t m : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */ 139144177Salfred uint32_t w : 1; /**< Set to 1 indicating counters are 64 bit */ 140144177Salfred uint32_t reserved_11_29 :15; 141144177Salfred cvmx_core_perf_t event :10; /**< Selects the event to be counted by the corresponding Counter Register */ 142144177Salfred uint32_t ie : 1; /**< Interrupt Enable */ 143144177Salfred uint32_t u : 1; /**< Count in user mode */ 14431567Ssef uint32_t s : 1; /**< Count in supervisor mode */ 14531567Ssef uint32_t k : 1; /**< Count in kernel mode */ 146132306Salfred uint32_t ex : 1; /**< Count in exception context */ 147132306Salfred#else 148132306Salfred uint32_t ex : 1; 149132306Salfred uint32_t k : 1; 150132306Salfred uint32_t s : 1; 151132306Salfred uint32_t u : 1; 152132306Salfred uint32_t ie : 1; 153132306Salfred uint32_t event :10; 154132306Salfred uint32_t reserved_11_29 :15; 155132306Salfred uint32_t w : 1; 156132306Salfred uint32_t m : 1; 157132306Salfred#endif 158132306Salfred } s; 159132306Salfred} cvmx_core_perf_control_t; 160132306Salfred 161132306Salfredtypedef enum { 162132306Salfred CVMX_TLB_PAGEMASK_4K = 0x3 << 11, 16332275Scharnier CVMX_TLB_PAGEMASK_16K = 0xF << 11, 164144177Salfred CVMX_TLB_PAGEMASK_64K = 0x3F << 11, 165144177Salfred CVMX_TLB_PAGEMASK_256K = 0xFF << 11, 166144177Salfred CVMX_TLB_PAGEMASK_1M = 0x3FF << 11, 167144177Salfred CVMX_TLB_PAGEMASK_4M = 0xFFF << 11, 168191005Sdelphij CVMX_TLB_PAGEMASK_16M = 0x3FFF << 11, 169191005Sdelphij CVMX_TLB_PAGEMASK_64M = 0xFFFF << 11, 170144177Salfred CVMX_TLB_PAGEMASK_256M = 0x3FFFF << 11, 171144177Salfred} cvmx_tlb_pagemask_t; 172171055Sdelphij 173144178Salfred 174144177Salfredint cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask); 175144177Salfred 17631567Ssef 177144178Salfredint cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask); 178144178Salfredint cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask); 179144178Salfred 180144177Salfred/** 181144177Salfred * Return number of TLB entries. 182144177Salfred */ 183144177Salfredint cvmx_core_get_tlb_entries(void); 184144177Salfred#ifdef __cplusplus 185168569Sdelphij} 186144177Salfred#endif 187153963Sbrian 188168569Sdelphij#endif /* __CVMX_CORE_H__ */ 189168569Sdelphij