cvmx-core.h revision 210286
155714Skris/***********************license start*************** 255714Skris * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 355714Skris * reserved. 455714Skris * 555714Skris * 655714Skris * Redistribution and use in source and binary forms, with or without 755714Skris * modification, are permitted provided that the following conditions are 855714Skris * met: 9238405Sjkim * 1055714Skris * * Redistributions of source code must retain the above copyright 1155714Skris * notice, this list of conditions and the following disclaimer. 1259191Skris * 1355714Skris * * Redistributions in binary form must reproduce the above 14238405Sjkim * copyright notice, this list of conditions and the following 15160814Ssimon * disclaimer in the documentation and/or other materials provided 16238405Sjkim * with the distribution. 17160814Ssimon * 18160814Ssimon * * Neither the name of Cavium Networks nor the names of 19238405Sjkim * its contributors may be used to endorse or promote products 20160814Ssimon * derived from this software without specific prior written 21238405Sjkim * permission. 22160814Ssimon * 23238405Sjkim * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24194206Ssimon * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25238405Sjkim * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26238405Sjkim * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27238405Sjkim * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28238405Sjkim * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29238405Sjkim * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30238405Sjkim * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31238405Sjkim * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32238405Sjkim * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33238405Sjkim * 34238405Sjkim * 35238405Sjkim * For any questions regarding licensing please contact marketing@caviumnetworks.com 36238405Sjkim * 37238405Sjkim ***********************license end**************************************/ 38238405Sjkim 39238405Sjkim 40238405Sjkim 41238405Sjkim 42238405Sjkim 43238405Sjkim 44238405Sjkim/** 45238405Sjkim * @file 46238405Sjkim * 47238405Sjkim * Module to support operations on core such as TLB config, etc. 48238405Sjkim * 49194206Ssimon * <hr>$Revision: 41586 $<hr> 50194206Ssimon * 51142425Snectar */ 5255714Skris 53238405Sjkim 54238405Sjkim#ifndef __CVMX_CORE_H__ 55238405Sjkim#define __CVMX_CORE_H__ 56238405Sjkim 57238405Sjkim#ifdef __cplusplus 58238405Sjkimextern "C" { 5955714Skris#endif 6055714Skris 6155714Skris/** 62238405Sjkim * The types of performance counters supported per cpu 63238405Sjkim */ 64142425Snectartypedef enum 6555714Skris{ 6655714Skris CVMX_CORE_PERF_NONE = 0, /**< Turn off the performance counter */ 6755714Skris CVMX_CORE_PERF_CLK = 1, /**< Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) */ 6855714Skris CVMX_CORE_PERF_ISSUE = 2, /**< Instructions issued but not retired */ 6955714Skris CVMX_CORE_PERF_RET = 3, /**< Instructions retired */ 70160814Ssimon CVMX_CORE_PERF_NISSUE = 4, /**< Cycles no issue */ 71160814Ssimon CVMX_CORE_PERF_SISSUE = 5, /**< Cycles single issue */ 72109998Smarkm CVMX_CORE_PERF_DISSUE = 6, /**< Cycles dual issue */ 7355714Skris CVMX_CORE_PERF_IFI = 7, /**< Cycle ifetch issued (but not necessarily commit to pp_mem) */ 7455714Skris CVMX_CORE_PERF_BR = 8, /**< Branches retired */ 7555714Skris CVMX_CORE_PERF_BRMIS = 9, /**< Branch mispredicts */ 7655714Skris CVMX_CORE_PERF_J = 10, /**< Jumps retired */ 7755714Skris CVMX_CORE_PERF_JMIS = 11, /**< Jumps mispredicted */ 7855714Skris CVMX_CORE_PERF_REPLAY = 12, /**< Mem Replays */ 7955714Skris CVMX_CORE_PERF_IUNA = 13, /**< Cycles idle due to unaligned_replays */ 80109998Smarkm CVMX_CORE_PERF_TRAP = 14, /**< trap_6a signal */ 81160814Ssimon CVMX_CORE_PERF_UULOAD = 16, /**< Unexpected unaligned loads (REPUN=1) */ 82194206Ssimon CVMX_CORE_PERF_UUSTORE = 17, /**< Unexpected unaligned store (REPUN=1) */ 83160814Ssimon CVMX_CORE_PERF_ULOAD = 18, /**< Unaligned loads (REPUN=1 or USEUN=1) */ 84160814Ssimon CVMX_CORE_PERF_USTORE = 19, /**< Unaligned store (REPUN=1 or USEUN=1) */ 8555714Skris CVMX_CORE_PERF_EC = 20, /**< Exec clocks(must set CvmCtl[DISCE] for accurate timing) */ 86238405Sjkim CVMX_CORE_PERF_MC = 21, /**< Mul clocks(must set CvmCtl[DISCE] for accurate timing) */ 8755714Skris CVMX_CORE_PERF_CC = 22, /**< Crypto clocks(must set CvmCtl[DISCE] for accurate timing) */ 8855714Skris CVMX_CORE_PERF_CSRC = 23, /**< Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) */ 8955714Skris CVMX_CORE_PERF_CFETCH = 24, /**< Icache committed fetches (demand+prefetch) */ 90160814Ssimon CVMX_CORE_PERF_CPREF = 25, /**< Icache committed prefetches */ 9155714Skris CVMX_CORE_PERF_ICA = 26, /**< Icache aliases */ 9255714Skris CVMX_CORE_PERF_II = 27, /**< Icache invalidates */ 9355714Skris CVMX_CORE_PERF_IP = 28, /**< Icache parity error */ 9455714Skris CVMX_CORE_PERF_CIMISS = 29, /**< Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) */ 9555714Skris CVMX_CORE_PERF_WBUF = 32, /**< Number of write buffer entries created */ 9655714Skris CVMX_CORE_PERF_WDAT = 33, /**< Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 9755714Skris CVMX_CORE_PERF_WBUFLD = 34, /**< Number of write buffer entries forced out by loads */ 9855714Skris CVMX_CORE_PERF_WBUFFL = 35, /**< Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */ 9955714Skris CVMX_CORE_PERF_WBUFTR = 36, /**< Number of stores that found no available write buffer entries */ 10055714Skris CVMX_CORE_PERF_BADD = 37, /**< Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 10155714Skris CVMX_CORE_PERF_BADDL2 = 38, /**< Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) */ 10268651Skris CVMX_CORE_PERF_BFILL = 39, /**< Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 10368651Skris CVMX_CORE_PERF_DDIDS = 40, /**< Number of Dstream DIDs created */ 104109998Smarkm CVMX_CORE_PERF_IDIDS = 41, /**< Number of Istream DIDs created */ 105194206Ssimon CVMX_CORE_PERF_DIDNA = 42, /**< Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */ 10655714Skris CVMX_CORE_PERF_LDS = 43, /**< Number of load issues */ 10755714Skris CVMX_CORE_PERF_LMLDS = 44, /**< Number of local memory load */ 10855714Skris CVMX_CORE_PERF_IOLDS = 45, /**< Number of I/O load issues */ 10955714Skris CVMX_CORE_PERF_DMLDS = 46, /**< Number of loads that were not prefetches and missed in the cache */ 110109998Smarkm CVMX_CORE_PERF_STS = 48, /**< Number of store issues */ 111238405Sjkim CVMX_CORE_PERF_LMSTS = 49, /**< Number of local memory store issues */ 112109998Smarkm CVMX_CORE_PERF_IOSTS = 50, /**< Number of I/O store issues */ 113160814Ssimon CVMX_CORE_PERF_IOBDMA = 51, /**< Number of IOBDMAs */ 114160814Ssimon CVMX_CORE_PERF_DTLB = 53, /**< Number of dstream TLB refill, invalid, or modified exceptions */ 115111147Snectar CVMX_CORE_PERF_DTLBAD = 54, /**< Number of dstream TLB address errors */ 116111147Snectar CVMX_CORE_PERF_ITLB = 55, /**< Number of istream TLB refill, invalid, or address error exceptions */ 11755714Skris CVMX_CORE_PERF_SYNC = 56, /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */ 118160814Ssimon CVMX_CORE_PERF_SYNCIOB = 57, /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */ 119194206Ssimon CVMX_CORE_PERF_SYNCW = 58, /**< Number of SYNCWs */ 12059191Skris CVMX_CORE_PERF_MAX /**< This not a counter, just a marker for the highest number */ 12155714Skris} cvmx_core_perf_t; 12255714Skris 12355714Skris/** 12455714Skris * Bit description of the COP0 counter control register 12568651Skris */ 12655714Skristypedef union 12755714Skris{ 12855714Skris uint32_t u32; 12955714Skris struct 13055714Skris { 13155714Skris uint32_t m : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */ 13255714Skris uint32_t w : 1; /**< Set to 1 indicating coutners are 64 bit */ 13355714Skris uint32_t reserved_11_29 :19; 13455714Skris cvmx_core_perf_t event : 6; /**< Selects the event to be counted by the corresponding Counter Register */ 13555714Skris uint32_t ie : 1; /**< Count in interrupt context */ 13655714Skris uint32_t u : 1; /**< Count in user mode */ 13755714Skris uint32_t s : 1; /**< Count in supervisor mode */ 13855714Skris uint32_t k : 1; /**< Count in kernel mode */ 139109998Smarkm uint32_t ex : 1; /**< Count in exception context */ 14055714Skris } s; 14155714Skris} cvmx_core_perf_control_t; 14255714Skris 14355714Skristypedef enum { 144160814Ssimon CVMX_TLB_PAGEMASK_4K = 0x3 << 11, 145160814Ssimon CVMX_TLB_PAGEMASK_16K = 0xF << 11, 14655714Skris CVMX_TLB_PAGEMASK_64K = 0x3F << 11, 14755714Skris CVMX_TLB_PAGEMASK_256K = 0xFF << 11, 14855714Skris CVMX_TLB_PAGEMASK_1M = 0x3FF << 11, 14955714Skris CVMX_TLB_PAGEMASK_4M = 0xFFF << 11, 15055714Skris CVMX_TLB_PAGEMASK_16M = 0x3FFF << 11, 151109998Smarkm CVMX_TLB_PAGEMASK_64M = 0xFFFF << 11, 15255714Skris CVMX_TLB_PAGEMASK_256M = 0x3FFFF << 11, 15355714Skris} cvmx_tlb_pagemask_t; 15455714Skris 15555714Skris 15655714Skrisint cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask); 15755714Skris 158160814Ssimon 159160814Ssimonint cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask); 16055714Skrisint cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask); 16155714Skris 16255714Skris#ifdef __cplusplus 16355714Skris} 16455714Skris#endif 16555714Skris 16655714Skris#endif /* __CVMX_CORE_H__ */ 16755714Skris