1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44210284Sjmallett 45215990Sjmallett 46210284Sjmallett/** 47210284Sjmallett * @file 48210284Sjmallett * 49210284Sjmallett * Module to support operations on core such as TLB config, etc. 50210284Sjmallett * 51232812Sjmallett * <hr>$Revision: 70030 $<hr> 52210284Sjmallett * 53210284Sjmallett */ 54210284Sjmallett 55210284Sjmallett 56210284Sjmallett#ifndef __CVMX_CORE_H__ 57210284Sjmallett#define __CVMX_CORE_H__ 58210284Sjmallett 59210284Sjmallett#ifdef __cplusplus 60210284Sjmallettextern "C" { 61210284Sjmallett#endif 62210284Sjmallett 63210284Sjmallett/** 64210284Sjmallett * The types of performance counters supported per cpu 65210284Sjmallett */ 66210284Sjmalletttypedef enum 67210284Sjmallett{ 68210284Sjmallett CVMX_CORE_PERF_NONE = 0, /**< Turn off the performance counter */ 69210284Sjmallett CVMX_CORE_PERF_CLK = 1, /**< Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) */ 70210284Sjmallett CVMX_CORE_PERF_ISSUE = 2, /**< Instructions issued but not retired */ 71210284Sjmallett CVMX_CORE_PERF_RET = 3, /**< Instructions retired */ 72210284Sjmallett CVMX_CORE_PERF_NISSUE = 4, /**< Cycles no issue */ 73210284Sjmallett CVMX_CORE_PERF_SISSUE = 5, /**< Cycles single issue */ 74210284Sjmallett CVMX_CORE_PERF_DISSUE = 6, /**< Cycles dual issue */ 75210284Sjmallett CVMX_CORE_PERF_IFI = 7, /**< Cycle ifetch issued (but not necessarily commit to pp_mem) */ 76210284Sjmallett CVMX_CORE_PERF_BR = 8, /**< Branches retired */ 77210284Sjmallett CVMX_CORE_PERF_BRMIS = 9, /**< Branch mispredicts */ 78210284Sjmallett CVMX_CORE_PERF_J = 10, /**< Jumps retired */ 79210284Sjmallett CVMX_CORE_PERF_JMIS = 11, /**< Jumps mispredicted */ 80210284Sjmallett CVMX_CORE_PERF_REPLAY = 12, /**< Mem Replays */ 81210284Sjmallett CVMX_CORE_PERF_IUNA = 13, /**< Cycles idle due to unaligned_replays */ 82210284Sjmallett CVMX_CORE_PERF_TRAP = 14, /**< trap_6a signal */ 83210284Sjmallett CVMX_CORE_PERF_UULOAD = 16, /**< Unexpected unaligned loads (REPUN=1) */ 84210284Sjmallett CVMX_CORE_PERF_UUSTORE = 17, /**< Unexpected unaligned store (REPUN=1) */ 85210284Sjmallett CVMX_CORE_PERF_ULOAD = 18, /**< Unaligned loads (REPUN=1 or USEUN=1) */ 86210284Sjmallett CVMX_CORE_PERF_USTORE = 19, /**< Unaligned store (REPUN=1 or USEUN=1) */ 87210284Sjmallett CVMX_CORE_PERF_EC = 20, /**< Exec clocks(must set CvmCtl[DISCE] for accurate timing) */ 88210284Sjmallett CVMX_CORE_PERF_MC = 21, /**< Mul clocks(must set CvmCtl[DISCE] for accurate timing) */ 89210284Sjmallett CVMX_CORE_PERF_CC = 22, /**< Crypto clocks(must set CvmCtl[DISCE] for accurate timing) */ 90210284Sjmallett CVMX_CORE_PERF_CSRC = 23, /**< Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) */ 91210284Sjmallett CVMX_CORE_PERF_CFETCH = 24, /**< Icache committed fetches (demand+prefetch) */ 92210284Sjmallett CVMX_CORE_PERF_CPREF = 25, /**< Icache committed prefetches */ 93210284Sjmallett CVMX_CORE_PERF_ICA = 26, /**< Icache aliases */ 94210284Sjmallett CVMX_CORE_PERF_II = 27, /**< Icache invalidates */ 95210284Sjmallett CVMX_CORE_PERF_IP = 28, /**< Icache parity error */ 96210284Sjmallett CVMX_CORE_PERF_CIMISS = 29, /**< Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) */ 97210284Sjmallett CVMX_CORE_PERF_WBUF = 32, /**< Number of write buffer entries created */ 98210284Sjmallett CVMX_CORE_PERF_WDAT = 33, /**< Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 99210284Sjmallett CVMX_CORE_PERF_WBUFLD = 34, /**< Number of write buffer entries forced out by loads */ 100210284Sjmallett CVMX_CORE_PERF_WBUFFL = 35, /**< Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */ 101210284Sjmallett CVMX_CORE_PERF_WBUFTR = 36, /**< Number of stores that found no available write buffer entries */ 102210284Sjmallett CVMX_CORE_PERF_BADD = 37, /**< Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 103210284Sjmallett CVMX_CORE_PERF_BADDL2 = 38, /**< Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) */ 104210284Sjmallett CVMX_CORE_PERF_BFILL = 39, /**< Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) */ 105210284Sjmallett CVMX_CORE_PERF_DDIDS = 40, /**< Number of Dstream DIDs created */ 106210284Sjmallett CVMX_CORE_PERF_IDIDS = 41, /**< Number of Istream DIDs created */ 107210284Sjmallett CVMX_CORE_PERF_DIDNA = 42, /**< Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) */ 108210284Sjmallett CVMX_CORE_PERF_LDS = 43, /**< Number of load issues */ 109210284Sjmallett CVMX_CORE_PERF_LMLDS = 44, /**< Number of local memory load */ 110210284Sjmallett CVMX_CORE_PERF_IOLDS = 45, /**< Number of I/O load issues */ 111210284Sjmallett CVMX_CORE_PERF_DMLDS = 46, /**< Number of loads that were not prefetches and missed in the cache */ 112210284Sjmallett CVMX_CORE_PERF_STS = 48, /**< Number of store issues */ 113210284Sjmallett CVMX_CORE_PERF_LMSTS = 49, /**< Number of local memory store issues */ 114210284Sjmallett CVMX_CORE_PERF_IOSTS = 50, /**< Number of I/O store issues */ 115210284Sjmallett CVMX_CORE_PERF_IOBDMA = 51, /**< Number of IOBDMAs */ 116210284Sjmallett CVMX_CORE_PERF_DTLB = 53, /**< Number of dstream TLB refill, invalid, or modified exceptions */ 117210284Sjmallett CVMX_CORE_PERF_DTLBAD = 54, /**< Number of dstream TLB address errors */ 118210284Sjmallett CVMX_CORE_PERF_ITLB = 55, /**< Number of istream TLB refill, invalid, or address error exceptions */ 119210284Sjmallett CVMX_CORE_PERF_SYNC = 56, /**< Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */ 120210284Sjmallett CVMX_CORE_PERF_SYNCIOB = 57, /**< Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) */ 121210284Sjmallett CVMX_CORE_PERF_SYNCW = 58, /**< Number of SYNCWs */ 122215990Sjmallett /* Added in CN63XX */ 123215990Sjmallett CVMX_CORE_PERF_ERETMIS = 64, /**< D/eret mispredicts */ 124215990Sjmallett CVMX_CORE_PERF_LIKMIS = 65, /**< Branch likely mispredicts */ 125215990Sjmallett CVMX_CORE_PERF_HAZTR = 66, /**< Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers */ 126210284Sjmallett CVMX_CORE_PERF_MAX /**< This not a counter, just a marker for the highest number */ 127210284Sjmallett} cvmx_core_perf_t; 128210284Sjmallett 129210284Sjmallett/** 130210284Sjmallett * Bit description of the COP0 counter control register 131210284Sjmallett */ 132210284Sjmalletttypedef union 133210284Sjmallett{ 134210284Sjmallett uint32_t u32; 135210284Sjmallett struct 136210284Sjmallett { 137232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 138210284Sjmallett uint32_t m : 1; /**< Set to 1 for sel 0 and 0 for sel 2, indicating there are two performance counters */ 139232812Sjmallett uint32_t w : 1; /**< Set to 1 indicating counters are 64 bit */ 140215990Sjmallett uint32_t reserved_11_29 :15; 141215990Sjmallett cvmx_core_perf_t event :10; /**< Selects the event to be counted by the corresponding Counter Register */ 142232812Sjmallett uint32_t ie : 1; /**< Interrupt Enable */ 143210284Sjmallett uint32_t u : 1; /**< Count in user mode */ 144210284Sjmallett uint32_t s : 1; /**< Count in supervisor mode */ 145210284Sjmallett uint32_t k : 1; /**< Count in kernel mode */ 146210284Sjmallett uint32_t ex : 1; /**< Count in exception context */ 147215990Sjmallett#else 148215990Sjmallett uint32_t ex : 1; 149215990Sjmallett uint32_t k : 1; 150215990Sjmallett uint32_t s : 1; 151215990Sjmallett uint32_t u : 1; 152215990Sjmallett uint32_t ie : 1; 153215990Sjmallett uint32_t event :10; 154215990Sjmallett uint32_t reserved_11_29 :15; 155215990Sjmallett uint32_t w : 1; 156215990Sjmallett uint32_t m : 1; 157215990Sjmallett#endif 158210284Sjmallett } s; 159210284Sjmallett} cvmx_core_perf_control_t; 160210284Sjmallett 161210284Sjmalletttypedef enum { 162210284Sjmallett CVMX_TLB_PAGEMASK_4K = 0x3 << 11, 163210284Sjmallett CVMX_TLB_PAGEMASK_16K = 0xF << 11, 164210284Sjmallett CVMX_TLB_PAGEMASK_64K = 0x3F << 11, 165210284Sjmallett CVMX_TLB_PAGEMASK_256K = 0xFF << 11, 166210284Sjmallett CVMX_TLB_PAGEMASK_1M = 0x3FF << 11, 167210284Sjmallett CVMX_TLB_PAGEMASK_4M = 0xFFF << 11, 168210284Sjmallett CVMX_TLB_PAGEMASK_16M = 0x3FFF << 11, 169210284Sjmallett CVMX_TLB_PAGEMASK_64M = 0xFFFF << 11, 170210284Sjmallett CVMX_TLB_PAGEMASK_256M = 0x3FFFF << 11, 171210284Sjmallett} cvmx_tlb_pagemask_t; 172210284Sjmallett 173210284Sjmallett 174210284Sjmallettint cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask); 175210284Sjmallett 176210284Sjmallett 177210284Sjmallettint cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask); 178210284Sjmallettint cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask); 179210284Sjmallett 180215990Sjmallett/** 181215990Sjmallett * Return number of TLB entries. 182215990Sjmallett */ 183215990Sjmallettint cvmx_core_get_tlb_entries(void); 184210284Sjmallett#ifdef __cplusplus 185210284Sjmallett} 186210284Sjmallett#endif 187210284Sjmallett 188210284Sjmallett#endif /* __CVMX_CORE_H__ */ 189