1/***********************license start***************
2 * Copyright (c) 2003-2010  Cavium Inc. (support@cavium.com). All rights
3 * reserved.
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 *   * Redistributions of source code must retain the above copyright
11 *     notice, this list of conditions and the following disclaimer.
12 *
13 *   * Redistributions in binary form must reproduce the above
14 *     copyright notice, this list of conditions and the following
15 *     disclaimer in the documentation and/or other materials provided
16 *     with the distribution.
17
18 *   * Neither the name of Cavium Inc. nor the names of
19 *     its contributors may be used to endorse or promote products
20 *     derived from this software without specific prior written
21 *     permission.
22
23 * This Software, including technical data, may be subject to U.S. export  control
24 * laws, including the U.S. Export Administration Act and its  associated
25 * regulations, and may be subject to export or import  regulations in other
26 * countries.
27
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
39
40
41
42
43
44
45
46/**
47 * @file
48 *
49 * Interface to Core, IO and DDR Clock.
50 *
51 * <hr>$Revision: 45089 $<hr>
52*/
53
54#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
55#include <linux/module.h>
56#include <asm/octeon/octeon.h>
57#include <asm/octeon/cvmx-clock.h>
58#include <asm/octeon/cvmx-npei-defs.h>
59#include <asm/octeon/cvmx-pexp-defs.h>
60#include <asm/octeon/cvmx-dbg-defs.h>
61#else
62#if !defined(__FreeBSD__) || !defined(_KERNEL)
63#include "executive-config.h"
64#endif
65#include "cvmx.h"
66#endif
67
68#ifndef CVMX_BUILD_FOR_UBOOT
69static uint64_t rate_eclk = 0;
70static uint64_t rate_sclk = 0;
71static uint64_t rate_dclk = 0;
72#endif
73
74/**
75 * Get clock rate based on the clock type.
76 *
77 * @param clock - Enumeration of the clock type.
78 * @return      - return the clock rate.
79 */
80uint64_t cvmx_clock_get_rate(cvmx_clock_t clock)
81{
82    const uint64_t REF_CLOCK = 50000000;
83
84#ifdef CVMX_BUILD_FOR_UBOOT
85    uint64_t rate_eclk = 0;
86    uint64_t rate_sclk = 0;
87    uint64_t rate_dclk = 0;
88#endif
89
90    if (cvmx_unlikely(!rate_eclk))
91    {
92	/* Note: The order of these checks is important.
93	** octeon_has_feature(OCTEON_FEATURE_PCIE) is true for both 6XXX
94	** and 52XX/56XX, so OCTEON_FEATURE_NPEI _must_ be checked first */
95        if (octeon_has_feature(OCTEON_FEATURE_NPEI))
96        {
97            cvmx_npei_dbg_data_t npei_dbg_data;
98            npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
99            rate_eclk =  REF_CLOCK * npei_dbg_data.s.c_mul;
100            rate_sclk = rate_eclk;
101        }
102        else if (octeon_has_feature(OCTEON_FEATURE_PCIE))
103        {
104            cvmx_mio_rst_boot_t mio_rst_boot;
105            mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
106            rate_eclk =  REF_CLOCK * mio_rst_boot.s.c_mul;
107            rate_sclk = REF_CLOCK * mio_rst_boot.s.pnr_mul;
108        }
109        else
110        {
111            cvmx_dbg_data_t dbg_data;
112            dbg_data.u64 = cvmx_read_csr(CVMX_DBG_DATA);
113            rate_eclk =  REF_CLOCK * dbg_data.s.c_mul;
114            rate_sclk = rate_eclk;
115        }
116    }
117
118    switch (clock)
119    {
120        case CVMX_CLOCK_SCLK:
121        case CVMX_CLOCK_TIM:
122        case CVMX_CLOCK_IPD:
123            return rate_sclk;
124
125        case CVMX_CLOCK_RCLK:
126        case CVMX_CLOCK_CORE:
127            return rate_eclk;
128
129        case CVMX_CLOCK_DDR:
130#if !defined(CVMX_BUILD_FOR_LINUX_HOST) && !defined(CVMX_BUILD_FOR_TOOLCHAIN)
131            if (cvmx_unlikely(!rate_dclk))
132                rate_dclk = cvmx_sysinfo_get()->dram_data_rate_hz;
133#endif
134            return rate_dclk;
135    }
136
137    cvmx_dprintf("cvmx_clock_get_rate: Unknown clock type\n");
138    return 0;
139}
140#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
141EXPORT_SYMBOL(cvmx_clock_get_rate);
142#endif
143