1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40215990Sjmallett 41210284Sjmallett/** 42210284Sjmallett * @file 43210284Sjmallett * Typedefs and defines for working with Octeon physical addresses. 44210284Sjmallett * 45210284Sjmallett * <hr>$Revision: 38306 $<hr> 46210284Sjmallett*/ 47210284Sjmallett#ifndef __CVMX_ADDRESS_H__ 48210284Sjmallett#define __CVMX_ADDRESS_H__ 49210284Sjmallett 50232812Sjmallett#ifndef CVMX_BUILD_FOR_LINUX_KERNEL 51232812Sjmallett#include "cvmx-abi.h" 52232812Sjmallett#endif 53232812Sjmallett 54210284Sjmallett#ifdef __cplusplus 55210284Sjmallettextern "C" { 56210284Sjmallett#endif 57210284Sjmallett 58210284Sjmalletttypedef enum { 59210284Sjmallett CVMX_MIPS_SPACE_XKSEG = 3LL, 60210284Sjmallett CVMX_MIPS_SPACE_XKPHYS = 2LL, 61210284Sjmallett CVMX_MIPS_SPACE_XSSEG = 1LL, 62210284Sjmallett CVMX_MIPS_SPACE_XUSEG = 0LL 63210284Sjmallett} cvmx_mips_space_t; 64210284Sjmallett 65210284Sjmalletttypedef enum { 66210284Sjmallett CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL, 67210284Sjmallett CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL, 68210284Sjmallett CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL, 69210284Sjmallett CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL 70210284Sjmallett} cvmx_mips_xkseg_space_t; 71210284Sjmallett 72215990Sjmallett /* decodes <14:13> of a kseg3 window address */ 73210284Sjmalletttypedef enum { 74210284Sjmallett CVMX_ADD_WIN_SCR = 0L, 75215990Sjmallett CVMX_ADD_WIN_DMA = 1L, /* see cvmx_add_win_dma_dec_t for further decode */ 76210284Sjmallett CVMX_ADD_WIN_UNUSED = 2L, 77210284Sjmallett CVMX_ADD_WIN_UNUSED2 = 3L 78210284Sjmallett} cvmx_add_win_dec_t; 79210284Sjmallett 80215990Sjmallett /* decode within DMA space */ 81210284Sjmalletttypedef enum { 82215990Sjmallett CVMX_ADD_WIN_DMA_ADD = 0L, /* add store data to the write buffer entry, allocating it if necessary */ 83215990Sjmallett CVMX_ADD_WIN_DMA_SENDMEM = 1L, /* send out the write buffer entry to DRAM */ 84215990Sjmallett /* store data must be normal DRAM memory space address in this case */ 85215990Sjmallett CVMX_ADD_WIN_DMA_SENDDMA = 2L, /* send out the write buffer entry as an IOBDMA command */ 86215990Sjmallett /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */ 87215990Sjmallett CVMX_ADD_WIN_DMA_SENDIO = 3L, /* send out the write buffer entry as an IO write */ 88215990Sjmallett /* store data must be normal IO space address in this case */ 89215990Sjmallett CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, /* send out a single-tick command on the NCB bus */ 90215990Sjmallett /* no write buffer data needed/used */ 91210284Sjmallett} cvmx_add_win_dma_dec_t; 92210284Sjmallett 93210284Sjmallett/** 94210284Sjmallett * Physical Address Decode 95210284Sjmallett * 96210284Sjmallett * Octeon-I HW never interprets this X (<39:36> reserved 97210284Sjmallett * for future expansion), software should set to 0. 98210284Sjmallett * 99210284Sjmallett * - 0x0 XXX0 0000 0000 to DRAM Cached 100210284Sjmallett * - 0x0 XXX0 0FFF FFFF 101210284Sjmallett * 102210284Sjmallett * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 103210284Sjmallett * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) 104210284Sjmallett * 105210284Sjmallett * - 0x0 XXX0 2000 0000 to DRAM Cached 106210284Sjmallett * - 0x0 XXXF FFFF FFFF 107210284Sjmallett * 108210284Sjmallett * - 0x1 00X0 0000 0000 to Boot Bus Uncached 109210284Sjmallett * - 0x1 00XF FFFF FFFF 110210284Sjmallett * 111210284Sjmallett * - 0x1 01X0 0000 0000 to Other NCB Uncached 112210284Sjmallett * - 0x1 FFXF FFFF FFFF devices 113210284Sjmallett * 114210284Sjmallett * Decode of all Octeon addresses 115210284Sjmallett */ 116210284Sjmalletttypedef union { 117210284Sjmallett 118210284Sjmallett uint64_t u64; 119210284Sjmallett 120210284Sjmallett struct { 121210284Sjmallett cvmx_mips_space_t R : 2; 122210284Sjmallett uint64_t offset :62; 123215990Sjmallett } sva; /* mapped or unmapped virtual address */ 124210284Sjmallett 125210284Sjmallett struct { 126210284Sjmallett uint64_t zeroes :33; 127210284Sjmallett uint64_t offset :31; 128215990Sjmallett } suseg; /* mapped USEG virtual addresses (typically) */ 129210284Sjmallett 130210284Sjmallett struct { 131210284Sjmallett uint64_t ones :33; 132210284Sjmallett cvmx_mips_xkseg_space_t sp : 2; 133210284Sjmallett uint64_t offset :29; 134215990Sjmallett } sxkseg; /* mapped or unmapped virtual address */ 135210284Sjmallett 136210284Sjmallett struct { 137215990Sjmallett cvmx_mips_space_t R : 2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ 138215990Sjmallett uint64_t cca : 3; /* ignored by octeon */ 139210284Sjmallett uint64_t mbz :10; 140215990Sjmallett uint64_t pa :49; /* physical address */ 141215990Sjmallett } sxkphys; /* physical address accessed through xkphys unmapped virtual address */ 142210284Sjmallett 143210284Sjmallett struct { 144210284Sjmallett uint64_t mbz :15; 145215990Sjmallett uint64_t is_io : 1; /* if set, the address is uncached and resides on MCB bus */ 146215990Sjmallett uint64_t did : 8; /* the hardware ignores this field when is_io==0, else device ID */ 147215990Sjmallett uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */ 148210284Sjmallett uint64_t offset :36; 149215990Sjmallett } sphys; /* physical address */ 150210284Sjmallett 151210284Sjmallett struct { 152215990Sjmallett uint64_t zeroes :24; /* techically, <47:40> are dont-cares */ 153215990Sjmallett uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */ 154210284Sjmallett uint64_t offset :36; 155215990Sjmallett } smem; /* physical mem address */ 156210284Sjmallett 157210284Sjmallett struct { 158210284Sjmallett uint64_t mem_region :2; 159210284Sjmallett uint64_t mbz :13; 160215990Sjmallett uint64_t is_io : 1; /* 1 in this case */ 161215990Sjmallett uint64_t did : 8; /* the hardware ignores this field when is_io==0, else device ID */ 162215990Sjmallett uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */ 163210284Sjmallett uint64_t offset :36; 164215990Sjmallett } sio; /* physical IO address */ 165210284Sjmallett 166210284Sjmallett struct { 167210284Sjmallett uint64_t ones : 49; 168215990Sjmallett cvmx_add_win_dec_t csrdec : 2; /* CVMX_ADD_WIN_SCR (0) in this case */ 169210284Sjmallett uint64_t addr : 13; 170215990Sjmallett } sscr; /* scratchpad virtual address - accessed through a window at the end of kseg3 */ 171210284Sjmallett 172215990Sjmallett /* there should only be stores to IOBDMA space, no loads */ 173210284Sjmallett struct { 174210284Sjmallett uint64_t ones : 49; 175215990Sjmallett cvmx_add_win_dec_t csrdec : 2; /* CVMX_ADD_WIN_DMA (1) in this case */ 176210284Sjmallett uint64_t unused2: 3; 177210284Sjmallett cvmx_add_win_dma_dec_t type : 3; 178210284Sjmallett uint64_t addr : 7; 179215990Sjmallett } sdma; /* IOBDMA virtual address - accessed through a window at the end of kseg3 */ 180210284Sjmallett 181210284Sjmallett struct { 182210284Sjmallett uint64_t didspace : 24; 183210284Sjmallett uint64_t unused : 40; 184210284Sjmallett } sfilldidspace; 185210284Sjmallett 186210284Sjmallett} cvmx_addr_t; 187210284Sjmallett 188210284Sjmallett/* These macros for used by 32 bit applications */ 189210284Sjmallett 190210284Sjmallett#define CVMX_MIPS32_SPACE_KSEG0 1l 191210284Sjmallett#define CVMX_ADD_SEG32(segment, add) (((int32_t)segment << 31) | (int32_t)(add)) 192210284Sjmallett 193210284Sjmallett/* Currently all IOs are performed using XKPHYS addressing. Linux uses the 194210284Sjmallett CvmMemCtl register to enable XKPHYS addressing to IO space from user mode. 195210284Sjmallett Future OSes may need to change the upper bits of IO addresses. The 196210284Sjmallett following define controls the upper two bits for all IO addresses generated 197210284Sjmallett by the simple executive library */ 198210284Sjmallett#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS 199210284Sjmallett 200210284Sjmallett/* These macros simplify the process of creating common IO addresses */ 201210284Sjmallett#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add)) 202210284Sjmallett#ifndef CVMX_ADD_IO_SEG 203210284Sjmallett#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) 204210284Sjmallett#endif 205210284Sjmallett#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did)) 206210284Sjmallett#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40) 207210284Sjmallett#define CVMX_FULL_DID(did,subdid) (((did) << 3) | (subdid)) 208210284Sjmallett 209210284Sjmallett 210215990Sjmallett /* from include/ncb_rsl_id.v */ 211215990Sjmallett#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */ 212210284Sjmallett#define CVMX_OCT_DID_GMX0 1ULL 213210284Sjmallett#define CVMX_OCT_DID_GMX1 2ULL 214210284Sjmallett#define CVMX_OCT_DID_PCI 3ULL 215210284Sjmallett#define CVMX_OCT_DID_KEY 4ULL 216210284Sjmallett#define CVMX_OCT_DID_FPA 5ULL 217210284Sjmallett#define CVMX_OCT_DID_DFA 6ULL 218210284Sjmallett#define CVMX_OCT_DID_ZIP 7ULL 219210284Sjmallett#define CVMX_OCT_DID_RNG 8ULL 220210284Sjmallett#define CVMX_OCT_DID_IPD 9ULL 221210284Sjmallett#define CVMX_OCT_DID_PKT 10ULL 222210284Sjmallett#define CVMX_OCT_DID_TIM 11ULL 223210284Sjmallett#define CVMX_OCT_DID_TAG 12ULL 224215990Sjmallett /* the rest are not on the IO bus */ 225210284Sjmallett#define CVMX_OCT_DID_L2C 16ULL 226210284Sjmallett#define CVMX_OCT_DID_LMC 17ULL 227210284Sjmallett#define CVMX_OCT_DID_SPX0 18ULL 228210284Sjmallett#define CVMX_OCT_DID_SPX1 19ULL 229210284Sjmallett#define CVMX_OCT_DID_PIP 20ULL 230210284Sjmallett#define CVMX_OCT_DID_ASX0 22ULL 231210284Sjmallett#define CVMX_OCT_DID_ASX1 23ULL 232210284Sjmallett#define CVMX_OCT_DID_IOB 30ULL 233210284Sjmallett 234210284Sjmallett#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT,2ULL) 235210284Sjmallett#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG,0ULL) 236210284Sjmallett#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG,1ULL) 237210284Sjmallett#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL) 238210284Sjmallett#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL) 239210284Sjmallett#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL) 240232812Sjmallett#define CVMX_OCT_DID_TAG_TAG5 CVMX_FULL_DID(CVMX_OCT_DID_TAG,5ULL) 241210284Sjmallett#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL) 242210284Sjmallett#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL) 243210284Sjmallett#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL) 244210284Sjmallett#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY,0ULL) 245210284Sjmallett#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI,6ULL) 246210284Sjmallett#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS,0ULL) 247210284Sjmallett#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI,0ULL) 248210284Sjmallett#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD,7ULL) 249210284Sjmallett#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA,7ULL) 250210284Sjmallett#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL) 251210284Sjmallett#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL) 252210284Sjmallett 253232812Sjmallett#ifndef CVMX_BUILD_FOR_LINUX_KERNEL 254232812Sjmallett#ifdef CVMX_ABI_N32 255232812Sjmallett#define UNMAPPED_PTR(x) ( (1U << 31) | x ) 256232812Sjmallett#else 257232812Sjmallett#define UNMAPPED_PTR(x) ( (1ULL << 63) | x ) 258232812Sjmallett#endif 259232812Sjmallett#endif 260232812Sjmallett 261210284Sjmallett#ifdef __cplusplus 262210284Sjmallett} 263210284Sjmallett#endif 264210284Sjmallett 265210284Sjmallett#endif /* __CVMX_ADDRESS_H__ */ 266210284Sjmallett 267