1296177Sjhibbits/****************************************************************************** 2296177Sjhibbits 3296177Sjhibbits � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. 4296177Sjhibbits All rights reserved. 5296177Sjhibbits 6296177Sjhibbits This is proprietary source code of Freescale Semiconductor Inc., 7296177Sjhibbits and its use is subject to the NetComm Device Drivers EULA. 8296177Sjhibbits The copyright notice above does not evidence any actual or intended 9296177Sjhibbits publication of such source code. 10296177Sjhibbits 11296177Sjhibbits ALTERNATIVELY, redistribution and use in source and binary forms, with 12296177Sjhibbits or without modification, are permitted provided that the following 13296177Sjhibbits conditions are met: 14296177Sjhibbits * Redistributions of source code must retain the above copyright 15296177Sjhibbits notice, this list of conditions and the following disclaimer. 16296177Sjhibbits * Redistributions in binary form must reproduce the above copyright 17296177Sjhibbits notice, this list of conditions and the following disclaimer in the 18296177Sjhibbits documentation and/or other materials provided with the distribution. 19296177Sjhibbits * Neither the name of Freescale Semiconductor nor the 20296177Sjhibbits names of its contributors may be used to endorse or promote products 21296177Sjhibbits derived from this software without specific prior written permission. 22296177Sjhibbits 23296177Sjhibbits THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24296177Sjhibbits EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25296177Sjhibbits WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26296177Sjhibbits DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27296177Sjhibbits DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28296177Sjhibbits (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29296177Sjhibbits LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30296177Sjhibbits ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31296177Sjhibbits (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32296177Sjhibbits SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33296177Sjhibbits * 34296177Sjhibbits 35296177Sjhibbits **************************************************************************/ 36296177Sjhibbits/****************************************************************************** 37296177Sjhibbits @File qman_private.h 38296177Sjhibbits 39296177Sjhibbits @Description QM private header 40296177Sjhibbits*//***************************************************************************/ 41296177Sjhibbits#ifndef __QMAN_PRIVATE_H 42296177Sjhibbits#define __QMAN_PRIVATE_H 43296177Sjhibbits 44296177Sjhibbits#include "fsl_qman.h" 45296177Sjhibbits 46296177Sjhibbits 47296177Sjhibbits#define __ERR_MODULE__ MODULE_QM 48296177Sjhibbits 49296177Sjhibbits#if defined(DEBUG) || !defined(DISABLE_ASSERTIONS) 50296177Sjhibbits/* Optionally compile-in assertion-checking */ 51296177Sjhibbits#define QM_CHECKING 52296177Sjhibbits#endif /* defined(DEBUG) || ... */ 53296177Sjhibbits 54296177Sjhibbits/* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers 55296177Sjhibbits * and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or 56296177Sjhibbits * execution reordering with respect to other code/instructions that manipulate 57296177Sjhibbits * the same cacheline. */ 58296177Sjhibbits#ifdef CORE_E500MC 59296177Sjhibbits 60296177Sjhibbits#if defined(_DIAB_TOOL) 61296177Sjhibbits#define hwsync() \ 62296177Sjhibbitsdo { \ 63296177Sjhibbits__asm__ __volatile__ ("sync"); \ 64296177Sjhibbits} while(0) 65296177Sjhibbits 66296177Sjhibbits#define lwsync() \ 67296177Sjhibbitsdo { \ 68296177Sjhibbits__asm__ __volatile__ ("lwsync"); \ 69296177Sjhibbits} while(0) 70296177Sjhibbits 71296177Sjhibbits__asm__ __volatile__ void dcbf (volatile void * addr) 72296177Sjhibbits{ 73296177Sjhibbits%reg addr 74296177Sjhibbits dcbf r0, addr 75296177Sjhibbits} 76296177Sjhibbits 77296177Sjhibbits__asm__ __volatile__ void dcbt_ro (volatile void * addr) 78296177Sjhibbits{ 79296177Sjhibbits%reg addr 80296177Sjhibbits dcbt r0, addr 81296177Sjhibbits} 82296177Sjhibbits 83296177Sjhibbits__asm__ __volatile__ void dcbt_rw (volatile void * addr) 84296177Sjhibbits{ 85296177Sjhibbits%reg addr 86296177Sjhibbits dcbtst r0, addr 87296177Sjhibbits} 88296177Sjhibbits 89296177Sjhibbits__asm__ __volatile__ void dcbzl (volatile void * addr) 90296177Sjhibbits{ 91296177Sjhibbits%reg addr 92296177Sjhibbits dcbzl r0, addr 93296177Sjhibbits} 94296177Sjhibbits 95296177Sjhibbits#define dcbz_64(p) \ 96296177Sjhibbits do { \ 97296177Sjhibbits dcbzl(p); \ 98296177Sjhibbits } while (0) 99296177Sjhibbits 100296177Sjhibbits#define dcbf_64(p) \ 101296177Sjhibbits do { \ 102296177Sjhibbits dcbf(p); \ 103296177Sjhibbits } while (0) 104296177Sjhibbits 105296177Sjhibbits/* Commonly used combo */ 106296177Sjhibbits#define dcbit_ro(p) \ 107296177Sjhibbits do { \ 108296177Sjhibbits dcbi(p); \ 109296177Sjhibbits dcbt_ro(p); \ 110296177Sjhibbits } while (0) 111296177Sjhibbits 112296177Sjhibbits#else /* GNU C */ 113296177Sjhibbits#define hwsync() \ 114296177Sjhibbits do { \ 115296177Sjhibbits __asm__ __volatile__ ("sync" : : : "memory"); \ 116296177Sjhibbits } while(0) 117296177Sjhibbits 118296177Sjhibbits#define lwsync() \ 119296177Sjhibbits do { \ 120296177Sjhibbits __asm__ __volatile__ ("lwsync" : : : "memory"); \ 121296177Sjhibbits } while(0) 122296177Sjhibbits 123296177Sjhibbits#define dcbf(addr) \ 124296177Sjhibbits do { \ 125296177Sjhibbits __asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \ 126296177Sjhibbits } while(0) 127296177Sjhibbits 128296177Sjhibbits#define dcbt_ro(addr) \ 129296177Sjhibbits do { \ 130296177Sjhibbits __asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \ 131296177Sjhibbits } while(0) 132296177Sjhibbits 133296177Sjhibbits#define dcbt_rw(addr) \ 134296177Sjhibbits do { \ 135296177Sjhibbits __asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \ 136296177Sjhibbits } while(0) 137296177Sjhibbits 138296177Sjhibbits#define dcbzl(p) \ 139296177Sjhibbits do { \ 140296177Sjhibbits __asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \ 141296177Sjhibbits } while(0) 142296177Sjhibbits 143296177Sjhibbits#define dcbz_64(p) \ 144296177Sjhibbits do { \ 145296177Sjhibbits dcbzl(p); \ 146296177Sjhibbits } while (0) 147296177Sjhibbits 148296177Sjhibbits#define dcbf_64(p) \ 149296177Sjhibbits do { \ 150296177Sjhibbits dcbf(p); \ 151296177Sjhibbits } while (0) 152296177Sjhibbits 153296177Sjhibbits/* Commonly used combo */ 154296177Sjhibbits#define dcbit_ro(p) \ 155296177Sjhibbits do { \ 156296177Sjhibbits dcbi(p); \ 157296177Sjhibbits dcbt_ro(p); \ 158296177Sjhibbits } while (0) 159296177Sjhibbits 160296177Sjhibbits#endif /* _DIAB_TOOL */ 161296177Sjhibbits 162296177Sjhibbits#else 163296177Sjhibbits#define hwsync CORE_MemoryBarrier 164296177Sjhibbits#define lwsync hwsync 165296177Sjhibbits 166296177Sjhibbits#define dcbf(p) \ 167296177Sjhibbits do { \ 168296177Sjhibbits __asm__ __volatile__ ("dcbf 0,%0" : : "r" (p)); \ 169296177Sjhibbits } while(0) 170296177Sjhibbits#define dcbt_ro(p) \ 171296177Sjhibbits do { \ 172296177Sjhibbits __asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \ 173296177Sjhibbits lwsync(); \ 174296177Sjhibbits } while(0) 175296177Sjhibbits#define dcbt_rw(p) \ 176296177Sjhibbits do { \ 177296177Sjhibbits __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \ 178296177Sjhibbits } while(0) 179296177Sjhibbits#define dcbz(p) \ 180296177Sjhibbits do { \ 181296177Sjhibbits __asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \ 182296177Sjhibbits } while (0) 183296177Sjhibbits#define dcbz_64(p) \ 184296177Sjhibbits do { \ 185296177Sjhibbits dcbz((uint32_t)p + 32); \ 186296177Sjhibbits dcbz(p); \ 187296177Sjhibbits } while (0) 188296177Sjhibbits#define dcbf_64(p) \ 189296177Sjhibbits do { \ 190296177Sjhibbits dcbf((uint32_t)p + 32); \ 191296177Sjhibbits dcbf(p); \ 192296177Sjhibbits } while (0) 193296177Sjhibbits/* Commonly used combo */ 194296177Sjhibbits#define dcbit_ro(p) \ 195296177Sjhibbits do { \ 196296177Sjhibbits dcbi(p); \ 197296177Sjhibbits dcbi((uint32_t)p + 32); \ 198296177Sjhibbits dcbt_ro(p); \ 199296177Sjhibbits dcbt_ro((uint32_t)p + 32); \ 200296177Sjhibbits } while (0) 201296177Sjhibbits 202296177Sjhibbits#endif /* CORE_E500MC */ 203296177Sjhibbits 204296177Sjhibbits#define dcbi(p) dcbf(p) 205296177Sjhibbits 206296177Sjhibbitsstruct qm_addr { 207296177Sjhibbits void *addr_ce; /* cache-enabled */ 208296177Sjhibbits void *addr_ci; /* cache-inhibited */ 209296177Sjhibbits}; 210296177Sjhibbits 211296177Sjhibbits/* EQCR state */ 212296177Sjhibbitsstruct qm_eqcr { 213296177Sjhibbits struct qm_eqcr_entry *ring, *cursor; 214296177Sjhibbits uint8_t ci, available, ithresh, vbit; 215296177Sjhibbits 216296177Sjhibbits#ifdef QM_CHECKING 217296177Sjhibbits uint32_t busy; 218296177Sjhibbits e_QmPortalProduceMode pmode; 219296177Sjhibbits e_QmPortalEqcrConsumeMode cmode; 220296177Sjhibbits#endif /* QM_CHECKING */ 221296177Sjhibbits}; 222296177Sjhibbits 223296177Sjhibbits/* DQRR state */ 224296177Sjhibbitsstruct qm_dqrr { 225296177Sjhibbits struct qm_dqrr_entry *ring, *cursor; 226296177Sjhibbits uint8_t pi, ci, fill, ithresh, vbit, flags; 227296177Sjhibbits 228296177Sjhibbits#ifdef QM_CHECKING 229296177Sjhibbits e_QmPortalDequeueMode dmode; 230296177Sjhibbits e_QmPortalProduceMode pmode; 231296177Sjhibbits e_QmPortalDqrrConsumeMode cmode; 232296177Sjhibbits#endif /* QM_CHECKING */ 233296177Sjhibbits}; 234296177Sjhibbits#define QM_DQRR_FLAG_RE 0x01 /* Stash ring entries */ 235296177Sjhibbits#define QM_DQRR_FLAG_SE 0x02 /* Stash data */ 236296177Sjhibbits 237296177Sjhibbits/* MR state */ 238296177Sjhibbitsstruct qm_mr { 239296177Sjhibbits struct qm_mr_entry *ring, *cursor; 240296177Sjhibbits uint8_t pi, ci, fill, ithresh, vbit; 241296177Sjhibbits 242296177Sjhibbits#ifdef QM_CHECKING 243296177Sjhibbits e_QmPortalProduceMode pmode; 244296177Sjhibbits e_QmPortalMrConsumeMode cmode; 245296177Sjhibbits#endif /* QM_CHECKING */ 246296177Sjhibbits}; 247296177Sjhibbits 248296177Sjhibbits/* MC state */ 249296177Sjhibbitsstruct qm_mc { 250296177Sjhibbits struct qm_mc_command *cr; 251296177Sjhibbits struct qm_mc_result *rr; 252296177Sjhibbits uint8_t rridx, vbit; 253296177Sjhibbits#ifdef QM_CHECKING 254296177Sjhibbits enum { 255296177Sjhibbits /* Can be _mc_start()ed */ 256296177Sjhibbits mc_idle, 257296177Sjhibbits /* Can be _mc_commit()ed or _mc_abort()ed */ 258296177Sjhibbits mc_user, 259296177Sjhibbits /* Can only be _mc_retry()ed */ 260296177Sjhibbits mc_hw 261296177Sjhibbits } state; 262296177Sjhibbits#endif /* QM_CHECKING */ 263296177Sjhibbits}; 264296177Sjhibbits 265296177Sjhibbits/********************/ 266296177Sjhibbits/* Portal structure */ 267296177Sjhibbits/********************/ 268296177Sjhibbits 269296177Sjhibbitsstruct qm_portal { 270296177Sjhibbits /* In the non-QM_CHECKING case, everything up to and 271296177Sjhibbits * including 'mc' fits in a cacheline (yay!). The 'config' part is setup-only, so isn't a 272296177Sjhibbits * cause for a concern. In other words, don't rearrange this structure 273296177Sjhibbits * on a whim, there be dragons ... */ 274296177Sjhibbits struct qm_addr addr; 275296177Sjhibbits struct qm_eqcr eqcr; 276296177Sjhibbits struct qm_dqrr dqrr; 277296177Sjhibbits struct qm_mr mr; 278296177Sjhibbits struct qm_mc mc; 279296177Sjhibbits struct qm_portal_config config; 280296177Sjhibbits t_Handle bind_lock; 281296177Sjhibbits /* Logical index (not cell-index) */ 282296177Sjhibbits int index; 283296177Sjhibbits}; 284296177Sjhibbits 285296177Sjhibbits#endif /* __QMAN_PRIVATE_H */ 286