1296177Sjhibbits/****************************************************************************** 2296177Sjhibbits 3296177Sjhibbits � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. 4296177Sjhibbits All rights reserved. 5296177Sjhibbits 6296177Sjhibbits This is proprietary source code of Freescale Semiconductor Inc., 7296177Sjhibbits and its use is subject to the NetComm Device Drivers EULA. 8296177Sjhibbits The copyright notice above does not evidence any actual or intended 9296177Sjhibbits publication of such source code. 10296177Sjhibbits 11296177Sjhibbits ALTERNATIVELY, redistribution and use in source and binary forms, with 12296177Sjhibbits or without modification, are permitted provided that the following 13296177Sjhibbits conditions are met: 14296177Sjhibbits * Redistributions of source code must retain the above copyright 15296177Sjhibbits notice, this list of conditions and the following disclaimer. 16296177Sjhibbits * Redistributions in binary form must reproduce the above copyright 17296177Sjhibbits notice, this list of conditions and the following disclaimer in the 18296177Sjhibbits documentation and/or other materials provided with the distribution. 19296177Sjhibbits * Neither the name of Freescale Semiconductor nor the 20296177Sjhibbits names of its contributors may be used to endorse or promote products 21296177Sjhibbits derived from this software without specific prior written permission. 22296177Sjhibbits 23296177Sjhibbits THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24296177Sjhibbits EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25296177Sjhibbits WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26296177Sjhibbits DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27296177Sjhibbits DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28296177Sjhibbits (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29296177Sjhibbits LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30296177Sjhibbits ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31296177Sjhibbits (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32296177Sjhibbits SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33296177Sjhibbits * 34296177Sjhibbits 35296177Sjhibbits **************************************************************************/ 36296177Sjhibbits/****************************************************************************** 37296177Sjhibbits @File qm.h 38296177Sjhibbits 39296177Sjhibbits @Description QM header 40296177Sjhibbits*//***************************************************************************/ 41296177Sjhibbits#ifndef __QM_H 42296177Sjhibbits#define __QM_H 43296177Sjhibbits 44296177Sjhibbits#include "std_ext.h" 45296177Sjhibbits#include "list_ext.h" 46296177Sjhibbits#include "qm_ext.h" 47296177Sjhibbits#include "qman_private.h" 48296177Sjhibbits#include "qm_ipc.h" 49296177Sjhibbits 50296177Sjhibbits 51296177Sjhibbits#define __ERR_MODULE__ MODULE_QM 52296177Sjhibbits 53296177Sjhibbits#define QM_NUM_OF_SWP 10 54296177Sjhibbits#define QM_NUM_OF_DCP 5 55296177Sjhibbits 56296177Sjhibbits#define CACHELINE_SIZE 64 57296177Sjhibbits#define QM_CONTEXTA_MAX_STASH_SIZE (3 * CACHELINE_SIZE) 58296177Sjhibbits 59296177Sjhibbits/**************************************************************************//** 60296177Sjhibbits @Description Exceptions 61296177Sjhibbits*//***************************************************************************/ 62296177Sjhibbits#define QM_EX_CORENET_INITIATOR_DATA 0x20000000 63296177Sjhibbits#define QM_EX_CORENET_TARGET_DATA 0x10000000 64296177Sjhibbits#define QM_EX_CORENET_INVALID_TARGET_TRANSACTION 0x08000000 65296177Sjhibbits#define QM_EX_PFDR_THRESHOLD 0x04000000 66296177Sjhibbits#define QM_EX_MULTI_ECC 0x02000000 67296177Sjhibbits#define QM_EX_SINGLE_ECC 0x01000000 68296177Sjhibbits#define QM_EX_PFDR_ENQUEUE_BLOCKED 0x00800000 69296177Sjhibbits#define QM_EX_INVALID_COMMAND 0x00010000 70296177Sjhibbits#define QM_EX_DEQUEUE_DCP 0x00000800 71296177Sjhibbits#define QM_EX_DEQUEUE_FQ 0x00000400 72296177Sjhibbits#define QM_EX_DEQUEUE_SOURCE 0x00000200 73296177Sjhibbits#define QM_EX_DEQUEUE_QUEUE 0x00000100 74296177Sjhibbits#define QM_EX_ENQUEUE_OVERFLOW 0x00000008 75296177Sjhibbits#define QM_EX_ENQUEUE_STATE 0x00000004 76296177Sjhibbits#define QM_EX_ENQUEUE_CHANNEL 0x00000002 77296177Sjhibbits#define QM_EX_ENQUEUE_QUEUE 0x00000001 78296177Sjhibbits 79296177Sjhibbits#define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \ 80296177Sjhibbits case e_QM_EX_CORENET_INITIATOR_DATA: \ 81296177Sjhibbits bitMask = QM_EX_CORENET_INITIATOR_DATA; break; \ 82296177Sjhibbits case e_QM_EX_CORENET_TARGET_DATA: \ 83296177Sjhibbits bitMask = QM_EX_CORENET_TARGET_DATA; break; \ 84296177Sjhibbits case e_QM_EX_CORENET_INVALID_TARGET_TRANSACTION: \ 85296177Sjhibbits bitMask = QM_EX_CORENET_INVALID_TARGET_TRANSACTION; break; \ 86296177Sjhibbits case e_QM_EX_PFDR_THRESHOLD: \ 87296177Sjhibbits bitMask = QM_EX_PFDR_THRESHOLD; break; \ 88296177Sjhibbits case e_QM_EX_PFDR_ENQUEUE_BLOCKED: \ 89296177Sjhibbits bitMask = QM_EX_PFDR_ENQUEUE_BLOCKED; break; \ 90296177Sjhibbits case e_QM_EX_SINGLE_ECC: \ 91296177Sjhibbits bitMask = QM_EX_SINGLE_ECC; break; \ 92296177Sjhibbits case e_QM_EX_MULTI_ECC: \ 93296177Sjhibbits bitMask = QM_EX_MULTI_ECC; break; \ 94296177Sjhibbits case e_QM_EX_INVALID_COMMAND: \ 95296177Sjhibbits bitMask = QM_EX_INVALID_COMMAND; break; \ 96296177Sjhibbits case e_QM_EX_DEQUEUE_DCP: \ 97296177Sjhibbits bitMask = QM_EX_DEQUEUE_DCP; break; \ 98296177Sjhibbits case e_QM_EX_DEQUEUE_FQ: \ 99296177Sjhibbits bitMask = QM_EX_DEQUEUE_FQ; break; \ 100296177Sjhibbits case e_QM_EX_DEQUEUE_SOURCE: \ 101296177Sjhibbits bitMask = QM_EX_DEQUEUE_SOURCE; break; \ 102296177Sjhibbits case e_QM_EX_DEQUEUE_QUEUE: \ 103296177Sjhibbits bitMask = QM_EX_DEQUEUE_QUEUE; break; \ 104296177Sjhibbits case e_QM_EX_ENQUEUE_OVERFLOW: \ 105296177Sjhibbits bitMask = QM_EX_ENQUEUE_OVERFLOW; break; \ 106296177Sjhibbits case e_QM_EX_ENQUEUE_STATE: \ 107296177Sjhibbits bitMask = QM_EX_ENQUEUE_STATE; break; \ 108296177Sjhibbits case e_QM_EX_ENQUEUE_CHANNEL: \ 109296177Sjhibbits bitMask = QM_EX_ENQUEUE_CHANNEL; break; \ 110296177Sjhibbits case e_QM_EX_ENQUEUE_QUEUE: \ 111296177Sjhibbits bitMask = QM_EX_ENQUEUE_QUEUE; break; \ 112296177Sjhibbits default: bitMask = 0;break;} 113296177Sjhibbits 114296177Sjhibbits/**************************************************************************//** 115296177Sjhibbits @Description defaults 116296177Sjhibbits*//***************************************************************************/ 117296177Sjhibbits/* QM defaults */ 118296177Sjhibbits#define DEFAULT_exceptions ((uint32_t)(QM_EX_CORENET_INITIATOR_DATA | \ 119296177Sjhibbits QM_EX_CORENET_TARGET_DATA | \ 120296177Sjhibbits QM_EX_CORENET_INVALID_TARGET_TRANSACTION | \ 121296177Sjhibbits QM_EX_PFDR_THRESHOLD | \ 122296177Sjhibbits QM_EX_SINGLE_ECC | \ 123296177Sjhibbits QM_EX_MULTI_ECC | \ 124296177Sjhibbits QM_EX_PFDR_ENQUEUE_BLOCKED | \ 125296177Sjhibbits QM_EX_INVALID_COMMAND | \ 126296177Sjhibbits QM_EX_DEQUEUE_DCP | \ 127296177Sjhibbits QM_EX_DEQUEUE_FQ | \ 128296177Sjhibbits QM_EX_DEQUEUE_SOURCE | \ 129296177Sjhibbits QM_EX_DEQUEUE_QUEUE | \ 130296177Sjhibbits QM_EX_ENQUEUE_OVERFLOW | \ 131296177Sjhibbits QM_EX_ENQUEUE_STATE | \ 132296177Sjhibbits QM_EX_ENQUEUE_CHANNEL | \ 133296177Sjhibbits QM_EX_ENQUEUE_QUEUE )) 134296177Sjhibbits#define DEFAULT_rtFramesDepth 30000 135296177Sjhibbits#define DEFAULT_pfdrThreshold 0 136296177Sjhibbits#define DEFAULT_sfdrThreshold 0 137296177Sjhibbits#define DEFAULT_pfdrBaseConstant 64 138296177Sjhibbits/* Corenet initiator settings. Stash request queues are 4-deep to match cores' 139296177Sjhibbits ability to snart. Stash priority is 3, other priorities are 2. */ 140296177Sjhibbits#define DEFAULT_initiatorSrcciv 0 141296177Sjhibbits#define DEFAULT_initiatorSrqW 3 142296177Sjhibbits#define DEFAULT_initiatorRwW 2 143296177Sjhibbits#define DEFAULT_initiatorBmanW 2 144296177Sjhibbits 145296177Sjhibbits 146296177Sjhibbits/* QM-Portal defaults */ 147296177Sjhibbits#define DEFAULT_dequeueDcaMode FALSE 148296177Sjhibbits#define DEFAULT_dequeueUpToThreeFrames TRUE 149296177Sjhibbits#define DEFAULT_dequeueCommandType e_QM_PORTAL_PRIORITY_PRECEDENCE_INTRA_CLASS_SCHEDULING 150296177Sjhibbits#define DEFAULT_dequeueUserToken 0xab 151296177Sjhibbits#define DEFAULT_dequeueSpecifiedWq FALSE 152296177Sjhibbits#define DEFAULT_dequeueDedicatedChannel TRUE 153296177Sjhibbits#define DEFAULT_dequeuePoolChannelId 0 154296177Sjhibbits#define DEFAULT_dequeueWqId 0 155296177Sjhibbits#define DEFAULT_dequeueDedicatedChannelHasPrecedenceOverPoolChannels TRUE 156296177Sjhibbits#define DEFAULT_dqrrSize DQRR_MAXFILL 157296177Sjhibbits#define DEFAULT_pullMode FALSE 158296177Sjhibbits#define DEFAULT_portalExceptions ((uint32_t)(QM_PIRQ_EQCI | \ 159296177Sjhibbits QM_PIRQ_EQRI | \ 160296177Sjhibbits QM_PIRQ_DQRI | \ 161296177Sjhibbits QM_PIRQ_MRI | \ 162296177Sjhibbits QM_PIRQ_CSCI)) 163296177Sjhibbits 164296177Sjhibbits/**************************************************************************//** 165296177Sjhibbits @Description Memory Mapped Registers 166296177Sjhibbits*//***************************************************************************/ 167296177Sjhibbits 168296177Sjhibbits#if defined(__MWERKS__) && !defined(__GNUC__) 169296177Sjhibbits#pragma pack(push,1) 170296177Sjhibbits#endif /* defined(__MWERKS__) && ... */ 171296177Sjhibbits#define MEM_MAP_START 172296177Sjhibbits 173296177Sjhibbitstypedef _Packed struct 174296177Sjhibbits{ 175296177Sjhibbits /* QMan Software Portal Configuration Registers */ 176296177Sjhibbits _Packed struct { 177296177Sjhibbits volatile uint32_t lio_cfg; /**< QMan Software Portal LIO Configuration */ 178296177Sjhibbits volatile uint32_t io_cfg; /**< QMan Software Portal 0 IO Configuration */ 179296177Sjhibbits volatile uint8_t res1[4]; /**< reserved */ 180296177Sjhibbits volatile uint32_t dd_cfg; /**< Software Portal Dynamic Debug Configuration */ 181296177Sjhibbits } _PackedType swpConfRegs[QM_NUM_OF_SWP]; 182296177Sjhibbits volatile uint8_t res1[352]; /**< reserved */ 183296177Sjhibbits 184296177Sjhibbits /* Dynamic Debug (DD) Configuration Registers */ 185296177Sjhibbits volatile uint32_t qman_dd_cfg; /**< QMan Dynamic Debug (DD) Configuration */ 186296177Sjhibbits volatile uint8_t res2[12]; /**< reserved */ 187296177Sjhibbits volatile uint32_t qcsp_dd_ihrsr; /**< Software Portal DD Internal Halt Request Status */ 188296177Sjhibbits volatile uint32_t qcsp_dd_ihrfr; /**< Software Portal DD Internal Halt Request Force */ 189296177Sjhibbits volatile uint32_t qcsp_dd_hasr; /**< Software Portal DD Halt Acknowledge Status */ 190296177Sjhibbits volatile uint8_t res3[4]; /**< reserved */ 191296177Sjhibbits volatile uint32_t dcp_dd_ihrsr; /**< DCP DD Internal Halt Request Status */ 192296177Sjhibbits volatile uint32_t dcp_dd_ihrfr; /**< DCP DD Internal Halt Request Force */ 193296177Sjhibbits volatile uint32_t dcp_dd_hasr; /**< DCP DD Halt Acknowledge Status */ 194296177Sjhibbits volatile uint8_t res4[212]; /**< reserved */ 195296177Sjhibbits 196296177Sjhibbits /* Direct Connect Portal (DCP) Configuration Registers */ 197296177Sjhibbits _Packed struct { 198296177Sjhibbits volatile uint32_t cfg; /**< DCP Configuration */ 199296177Sjhibbits volatile uint32_t dd_cfg; /**< DCP Dynamic Debug Configuration */ 200296177Sjhibbits volatile uint32_t dlm_cfg; /**< DCP Dequeue Latency Monitor Configuration */ 201296177Sjhibbits volatile uint32_t dlm_avg; /**< DCP Dequeue Latency Monitor Average */ 202296177Sjhibbits } _PackedType dcpConfRegs[QM_NUM_OF_DCP]; 203296177Sjhibbits volatile uint8_t res5[176]; /**< reserved */ 204296177Sjhibbits 205296177Sjhibbits /* Packed Frame Descriptor Record (PFDR) Manager Query Registers */ 206296177Sjhibbits volatile uint32_t pfdr_fpc; /**< PFDR Free Pool Count */ 207296177Sjhibbits volatile uint32_t pfdr_fp_head; /**< PFDR Free Pool Head Pointer */ 208296177Sjhibbits volatile uint32_t pfdr_fp_tail; /**< PFDR Free Pool Tail Pointer */ 209296177Sjhibbits volatile uint8_t res6[4]; /**< reserved */ 210296177Sjhibbits volatile uint32_t pfdr_fp_lwit; /**< PFDR Free Pool Low Watermark Interrupt Threshold */ 211296177Sjhibbits volatile uint32_t pfdr_cfg; /**< PFDR Configuration */ 212296177Sjhibbits volatile uint8_t res7[232]; /**< reserved */ 213296177Sjhibbits 214296177Sjhibbits /* Single Frame Descriptor Record (SFDR) Manager Registers */ 215296177Sjhibbits volatile uint32_t sfdr_cfg; /**< SFDR Configuration */ 216296177Sjhibbits volatile uint32_t sfdr_in_use; /**< SFDR In Use Register */ 217296177Sjhibbits volatile uint8_t res8[248]; /**< reserved */ 218296177Sjhibbits 219296177Sjhibbits /* Work Queue Semaphore and Context Manager Registers */ 220296177Sjhibbits volatile uint32_t wq_cs_cfg[6]; /**< Work Queue Class Scheduler Configuration */ 221296177Sjhibbits volatile uint8_t res9[24]; /**< reserved */ 222296177Sjhibbits volatile uint32_t wq_def_enq_wqid; /**< Work Queue Default Enqueue WQID */ 223296177Sjhibbits volatile uint8_t res10[12]; /**< reserved */ 224296177Sjhibbits volatile uint32_t wq_sc_dd_cfg[5]; /**< WQ S/W Channel Dynamic Debug Config */ 225296177Sjhibbits volatile uint8_t res11[44]; /**< reserved */ 226296177Sjhibbits volatile uint32_t wq_pc_dd_cs_cfg[8]; /**< WQ Pool Channel Dynamic Debug Config */ 227296177Sjhibbits volatile uint8_t res12[32]; /**< reserved */ 228296177Sjhibbits volatile uint32_t wq_dc0_dd_cs_cfg[6]; /**< WQ DCP0 Chan. Dynamic Debug Config */ 229296177Sjhibbits volatile uint8_t res13[40]; /**< reserved */ 230296177Sjhibbits volatile uint32_t wq_dc1_dd_cs_cfg[6]; /**< WQ DCP1 Chan. Dynamic Debug Config */ 231296177Sjhibbits volatile uint8_t res14[40]; /**< reserved */ 232296177Sjhibbits volatile uint32_t wq_dc2_dd_cs_cfg; /**< WQ DCP2 Chan. Dynamic Debug Config */ 233296177Sjhibbits volatile uint8_t res15[60]; /**< reserved */ 234296177Sjhibbits volatile uint32_t wq_dc3_dd_cs_cfg; /**< WQ DCP3 Chan. Dynamic Debug Config */ 235296177Sjhibbits volatile uint8_t res16[124]; /**< reserved */ 236296177Sjhibbits 237296177Sjhibbits /* Congestion Manager (CM) Registers */ 238296177Sjhibbits volatile uint32_t cm_cfg; /**< CM Configuration Register */ 239296177Sjhibbits volatile uint8_t res17[508]; /**< reserved */ 240296177Sjhibbits 241296177Sjhibbits /* QMan Error Capture Registers */ 242296177Sjhibbits volatile uint32_t ecsr; /**< QMan Error Capture Status Register */ 243296177Sjhibbits volatile uint32_t ecir; /**< QMan Error Capture Information Register */ 244296177Sjhibbits volatile uint32_t eadr; /**< QMan Error Capture Address Register */ 245296177Sjhibbits volatile uint8_t res18[4]; /**< reserved */ 246296177Sjhibbits volatile uint32_t edata[16]; /**< QMan ECC Error Data Register */ 247296177Sjhibbits volatile uint8_t res19[32]; /**< reserved */ 248296177Sjhibbits volatile uint32_t sbet; /**< QMan Single Bit ECC Error Threshold Register */ 249296177Sjhibbits volatile uint8_t res20[12]; /**< reserved */ 250296177Sjhibbits volatile uint32_t sbec[7]; /**< QMan Single Bit ECC Error Count Register */ 251296177Sjhibbits volatile uint8_t res21[100]; /**< reserved */ 252296177Sjhibbits 253296177Sjhibbits /* QMan Initialization and Debug Control Registers */ 254296177Sjhibbits volatile uint32_t mcr; /**< QMan Management Command/Result Register */ 255296177Sjhibbits volatile uint32_t mcp0; /**< QMan Management Command Parameter 0 Register */ 256296177Sjhibbits volatile uint32_t mcp1; /**< QMan Management Command Parameter 1 Register */ 257296177Sjhibbits volatile uint8_t res22[20]; /**< reserved */ 258296177Sjhibbits volatile uint32_t mr[16]; /**< QMan Management Return Register */ 259296177Sjhibbits volatile uint8_t res23[148]; /**< reserved */ 260296177Sjhibbits volatile uint32_t idle_stat; /**< QMan Idle Status Register */ 261296177Sjhibbits 262296177Sjhibbits /* QMan ID/Revision Registers */ 263296177Sjhibbits volatile uint32_t ip_rev_1; /**< QMan IP Block Revision 1 register */ 264296177Sjhibbits volatile uint32_t ip_rev_2; /**< QMan IP Block Revision 2 register */ 265296177Sjhibbits 266296177Sjhibbits /* QMan Initiator Interface Memory Window Configuration Registers */ 267296177Sjhibbits volatile uint32_t fqd_bare; /**< FQD Extended Base Address Register */ 268296177Sjhibbits volatile uint32_t fqd_bar; /**< Frame Queue Descriptor (FQD) Base Address Register */ 269296177Sjhibbits volatile uint8_t res24[8]; /**< reserved */ 270296177Sjhibbits volatile uint32_t fqd_ar; /**< FQD Attributes Register */ 271296177Sjhibbits volatile uint8_t res25[12]; /**< reserved */ 272296177Sjhibbits volatile uint32_t pfdr_bare; /**< PFDR Extended Base Address Register */ 273296177Sjhibbits volatile uint32_t pfdr_bar; /**< Packed Frame Descriptor Record (PFDR) Base Addr */ 274296177Sjhibbits volatile uint8_t res26[8]; /**< reserved */ 275296177Sjhibbits volatile uint32_t pfdr_ar; /**< PFDR Attributes Register */ 276296177Sjhibbits volatile uint8_t res27[76]; /**< reserved */ 277296177Sjhibbits volatile uint32_t qcsp_bare; /**< QCSP Extended Base Address */ 278296177Sjhibbits volatile uint32_t qcsp_bar; /**< QMan Software Portal Base Address */ 279296177Sjhibbits volatile uint8_t res28[120]; /**< reserved */ 280296177Sjhibbits volatile uint32_t ci_sched_cfg; /**< Initiator Scheduling Configuration */ 281296177Sjhibbits volatile uint32_t srcidr; /**< QMan Source ID Register */ 282296177Sjhibbits volatile uint32_t liodnr; /**< QMan Logical I/O Device Number Register */ 283296177Sjhibbits volatile uint8_t res29[4]; /**< reserved */ 284296177Sjhibbits volatile uint32_t ci_rlm_cfg; /**< Initiator Read Latency Monitor Configuration */ 285296177Sjhibbits volatile uint32_t ci_rlm_avg; /**< Initiator Read Latency Monitor Average */ 286296177Sjhibbits volatile uint8_t res30[232]; /**< reserved */ 287296177Sjhibbits 288296177Sjhibbits /* QMan Interrupt and Error Registers */ 289296177Sjhibbits volatile uint32_t err_isr; /**< QMan Error Interrupt Status Register */ 290296177Sjhibbits volatile uint32_t err_ier; /**< QMan Error Interrupt Enable Register */ 291296177Sjhibbits volatile uint32_t err_isdr; /**< QMan Error Interrupt Status Disable Register */ 292296177Sjhibbits volatile uint32_t err_iir; /**< QMan Error Interrupt Inhibit Register */ 293296177Sjhibbits volatile uint8_t res31[4]; /**< reserved */ 294296177Sjhibbits volatile uint32_t err_her; /**< QMan Error Halt Enable Register */ 295296177Sjhibbits 296296177Sjhibbits} _PackedType t_QmRegs; 297296177Sjhibbits 298296177Sjhibbits#define MEM_MAP_END 299296177Sjhibbits#if defined(__MWERKS__) && !defined(__GNUC__) 300296177Sjhibbits#pragma pack(pop) 301296177Sjhibbits#endif /* defined(__MWERKS__) && ... */ 302296177Sjhibbits 303296177Sjhibbits 304296177Sjhibbits/**************************************************************************//** 305296177Sjhibbits @Description General defines 306296177Sjhibbits*//***************************************************************************/ 307296177Sjhibbits 308296177Sjhibbits#define MODULE_NAME_SIZE 30 309296177Sjhibbits 310296177Sjhibbits#define PORTALS_OFFSET_CE(portal) (0x4000 * portal) 311296177Sjhibbits#define PORTALS_OFFSET_CI(portal) (0x1000 * portal) 312296177Sjhibbits 313296177Sjhibbits#define PFDR_ENTRY_SIZE 64 /* 64 bytes */ 314296177Sjhibbits#define FQD_ENTRY_SIZE 64 /* 64 bytes */ 315296177Sjhibbits 316296177Sjhibbits/* Compilation constants */ 317296177Sjhibbits#define DQRR_MAXFILL 15 318296177Sjhibbits#define EQCR_THRESH 1 /* reread h/w CI when running out of space */ 319296177Sjhibbits 320296177Sjhibbits/**************************************************************************//** 321296177Sjhibbits @Description Register defines 322296177Sjhibbits*//***************************************************************************/ 323296177Sjhibbits 324296177Sjhibbits/* Assists for QMAN_MCR */ 325296177Sjhibbits#define MCR_INIT_PFDR 0x01000000 326296177Sjhibbits#define MCR_get_rslt(v) (uint8_t)((v) >> 24) 327296177Sjhibbits#define MCR_rslt_idle(r) (!rslt || (rslt >= 0xf0)) 328296177Sjhibbits#define MCR_rslt_ok(r) (rslt == 0xf0) 329296177Sjhibbits#define MCR_rslt_eaccess(r) (rslt == 0xf8) 330296177Sjhibbits#define MCR_rslt_inval(r) (rslt == 0xff) 331296177Sjhibbits 332296177Sjhibbits/* masks */ 333296177Sjhibbits#define REV1_MAJOR_MASK 0x0000FF00 334296177Sjhibbits#define REV1_MINOR_MASK 0x000000FF 335296177Sjhibbits 336296177Sjhibbits#define REV2_INTEG_MASK 0x00FF0000 337296177Sjhibbits#define REV2_ERR_MASK 0x0000FF00 338296177Sjhibbits#define REV2_CFG_MASK 0x000000FF 339296177Sjhibbits 340296177Sjhibbits#define AR_ENABLE 0x80000000 341296177Sjhibbits#define AR_PRIORITY 0x40000000 342296177Sjhibbits#define AR_STASH 0x20000000 343296177Sjhibbits#define AR_SIZE_MASK 0x0000003f 344296177Sjhibbits 345296177Sjhibbits#define ECIR_PORTAL_TYPE 0x20000000 346296177Sjhibbits#define ECIR_PORTAL_MASK 0x1f000000 347296177Sjhibbits#define ECIR_FQID_MASK 0x00ffffff 348296177Sjhibbits 349296177Sjhibbits#define CI_SCHED_CFG_EN 0x80000000 350296177Sjhibbits/* shifts */ 351296177Sjhibbits#define REV1_MAJOR_SHIFT 8 352296177Sjhibbits#define REV1_MINOR_SHIFT 0 353296177Sjhibbits 354296177Sjhibbits#define REV2_INTEG_SHIFT 16 355296177Sjhibbits#define REV2_ERR_SHIFT 8 356296177Sjhibbits#define REV2_CFG_SHIFT 0 357296177Sjhibbits 358296177Sjhibbits#define AR_SIZE_SHIFT 0 359296177Sjhibbits 360296177Sjhibbits#define ECIR_PORTAL_SHIFT 24 361296177Sjhibbits#define ECIR_FQID_SHIFT 0 362296177Sjhibbits 363296177Sjhibbits#define CI_SCHED_CFG_SRCCIV_SHIFT 24 364296177Sjhibbits#define CI_SCHED_CFG_SRQ_W_SHIFT 8 365296177Sjhibbits#define CI_SCHED_CFG_RW_W_SHIFT 4 366296177Sjhibbits#define CI_SCHED_CFG_BMAN_W_SHIFT 0 367296177Sjhibbits 368296177Sjhibbits 369296177Sjhibbits/********* CGR ******************************/ 370296177Sjhibbits#define QM_CGR_TARG_FIRST_SWPORTAL 0x80000000 371296177Sjhibbits#define QM_CGR_TARG_FIRST_DCPORTAL 0x00200000 372296177Sjhibbits#define QM_CGR_TARGET_SWP(portlaId) (QM_CGR_TARG_FIRST_SWPORTAL >> portlaId) 373296177Sjhibbits#define QM_CGR_TARGET_DCP(portlaId) (QM_CGR_TARG_FIRST_DCPORTAL >> portlaId) 374296177Sjhibbits 375296177Sjhibbits 376296177Sjhibbits#define QM_DCP_CFG_ED 0x00000100 377296177Sjhibbits/* 378296177Sjhibbits#define CGR_VALID 0x80 379296177Sjhibbits#define CGR_VERB_INIT 0x50 380296177Sjhibbits#define CGR_VERB_MODIFY 0x51 381296177Sjhibbits#define CGR_WRITE_ALL 0x07FF 382296177Sjhibbits#define CGR_WRITE_ENABLE_CSCN 0x0010 383296177Sjhibbits#define CGR_WRITE_ENABLE_GREEN_MODIFY 0x0380 384296177Sjhibbits#define CGR_WRITE_ENABLE_YELLOW_MODIFY 0x0240 385296177Sjhibbits#define CGR_WRITE_ENABLE_RED_MODIFY 0x0120 386296177Sjhibbits 387296177Sjhibbits 388296177Sjhibbits#define CGR_MODE_BYTE 0x00 389296177Sjhibbits#define CGR_MODE_FRAME 0x01 390296177Sjhibbits#define GCR_ENABLE_WRED 0x01 391296177Sjhibbits#define GCR_ENABLE_TD 0x01 392296177Sjhibbits#define GCR_ENABLE_CSCN 0x01 393296177Sjhibbits*/ 394296177Sjhibbits 395296177Sjhibbits 396296177Sjhibbits/* Lock/unlock frame queues, subject to the "UNLOCKED" flag. This is about 397296177Sjhibbits * inter-processor locking only. */ 398296177Sjhibbits#define FQLOCK(fq) \ 399296177Sjhibbits do { \ 400296177Sjhibbits if (fq->flags & QMAN_FQ_FLAG_LOCKED) \ 401296177Sjhibbits XX_LockSpinlock(&fq->fqlock); \ 402296177Sjhibbits } while(0) 403296177Sjhibbits#define FQUNLOCK(fq) \ 404296177Sjhibbits do { \ 405296177Sjhibbits if (fq->flags & QMAN_FQ_FLAG_LOCKED) \ 406296177Sjhibbits XX_UnlockSpinlock(&fq->fqlock); \ 407296177Sjhibbits } while(0) 408296177Sjhibbits 409296177Sjhibbits/* Lock/unlock portals, subject to "UNLOCKED" flag. This is about disabling 410296177Sjhibbits * interrupts/preemption and, if FLAG_UNLOCKED isn't defined, inter-processor 411296177Sjhibbits * locking as well. */ 412296177Sjhibbits#define NCSW_PLOCK(p) ((t_QmPortal*)(p))->irq_flags = XX_DisableAllIntr() 413296177Sjhibbits#define PUNLOCK(p) XX_RestoreAllIntr(((t_QmPortal*)(p))->irq_flags) 414296177Sjhibbits 415296177Sjhibbits 416296177Sjhibbitstypedef void (t_QmLoopDequeueRing)(t_Handle h_QmPortal); 417296177Sjhibbits 418296177Sjhibbits/* Follows WQ_CS_CFG0-5 */ 419296177Sjhibbitstypedef enum { 420296177Sjhibbits e_QM_WQ_SW_PORTALS = 0, 421296177Sjhibbits e_QM_WQ_POOLS, 422296177Sjhibbits e_QM_WQ_DCP0, 423296177Sjhibbits e_QM_WQ_DCP1, 424296177Sjhibbits e_QM_WQ_DCP2, 425296177Sjhibbits e_QM_WQ_DCP3 426296177Sjhibbits} e_QmWqClass; 427296177Sjhibbits 428296177Sjhibbitstypedef enum { 429296177Sjhibbits e_QM_PORTAL_NO_DEQUEUES = 0, 430296177Sjhibbits e_QM_PORTAL_PRIORITY_PRECEDENCE_INTRA_CLASS_SCHEDULING, 431296177Sjhibbits e_QM_PORTAL_ACTIVE_FQ_PRECEDENCE_INTRA_CLASS_SCHEDULING, 432296177Sjhibbits e_QM_PORTAL_ACTIVE_FQ_PRECEDENCE_OVERRIDE_INTRA_CLASS_SCHEDULING 433296177Sjhibbits} e_QmPortalDequeueCommandType; 434296177Sjhibbits 435296177Sjhibbitstypedef enum e_QmInterModuleCounters { 436296177Sjhibbits e_QM_IM_COUNTERS_SFDR_IN_USE = 0, 437296177Sjhibbits e_QM_IM_COUNTERS_PFDR_IN_USE, 438296177Sjhibbits e_QM_IM_COUNTERS_PFDR_FREE_POOL 439296177Sjhibbits} e_QmInterModuleCounters; 440296177Sjhibbits 441296177Sjhibbitstypedef struct t_QmInterModulePortalInitParams { 442296177Sjhibbits uint8_t portalId; 443296177Sjhibbits uint8_t stashDestQueue; 444296177Sjhibbits uint16_t liodn; 445296177Sjhibbits uint16_t dqrrLiodn; 446296177Sjhibbits uint16_t fdFqLiodn; 447296177Sjhibbits} t_QmInterModulePortalInitParams; 448296177Sjhibbits 449296177Sjhibbitstypedef struct t_QmCg { 450296177Sjhibbits t_Handle h_Qm; 451296177Sjhibbits t_Handle h_QmPortal; 452296177Sjhibbits t_QmExceptionsCallback *f_Exception; 453296177Sjhibbits t_Handle h_App; 454296177Sjhibbits uint8_t id; 455296177Sjhibbits} t_QmCg; 456296177Sjhibbits 457296177Sjhibbitstypedef struct { 458296177Sjhibbits uintptr_t swPortalsBaseAddress; /**< QM Software Portals Base Address (virtual) */ 459296177Sjhibbits uint32_t partFqidBase; 460296177Sjhibbits uint32_t partNumOfFqids; 461296177Sjhibbits uint32_t totalNumOfFqids; 462296177Sjhibbits uint32_t rtFramesDepth; 463296177Sjhibbits uint32_t fqdMemPartitionId; 464296177Sjhibbits uint32_t pfdrMemPartitionId; 465296177Sjhibbits uint32_t pfdrThreshold; 466296177Sjhibbits uint32_t sfdrThreshold; 467296177Sjhibbits uint32_t pfdrBaseConstant; 468296177Sjhibbits uint16_t liodn; 469296177Sjhibbits t_QmDcPortalParams dcPortalsParams[DPAA_MAX_NUM_OF_DC_PORTALS]; 470296177Sjhibbits} t_QmDriverParams; 471296177Sjhibbits 472296177Sjhibbitstypedef struct { 473296177Sjhibbits uint8_t guestId; 474296177Sjhibbits t_Handle h_RsrvFqidMm; 475296177Sjhibbits t_Handle h_FqidMm; 476296177Sjhibbits t_Handle h_Session; 477296177Sjhibbits char moduleName[MODULE_NAME_SIZE]; 478296177Sjhibbits t_Handle h_Portals[DPAA_MAX_NUM_OF_SW_PORTALS]; 479296177Sjhibbits t_QmRegs *p_QmRegs; 480296177Sjhibbits uint32_t *p_FqdBase; 481296177Sjhibbits uint32_t *p_PfdrBase; 482296177Sjhibbits uint32_t exceptions; 483296177Sjhibbits t_QmExceptionsCallback *f_Exception; 484296177Sjhibbits t_Handle h_App; 485296177Sjhibbits int errIrq; /**< error interrupt line; NO_IRQ if interrupts not used */ 486296177Sjhibbits uint32_t numOfPfdr; 487296177Sjhibbits uint16_t partNumOfCgs; 488296177Sjhibbits uint16_t partCgsBase; 489296177Sjhibbits uint8_t cgsUsed[QM_MAX_NUM_OF_CGS]; 490296177Sjhibbitst_Handle lock; 491296177Sjhibbits t_QmDriverParams *p_QmDriverParams; 492296177Sjhibbits} t_Qm; 493296177Sjhibbits 494296177Sjhibbitstypedef struct { 495296177Sjhibbits uint32_t hwExtStructsMemAttr; 496296177Sjhibbits uint8_t dqrrSize; 497296177Sjhibbits bool pullMode; 498296177Sjhibbits bool dequeueDcaMode; 499296177Sjhibbits bool dequeueUpToThreeFrames; 500296177Sjhibbits e_QmPortalDequeueCommandType commandType; 501296177Sjhibbits uint8_t userToken; 502296177Sjhibbits bool specifiedWq; 503296177Sjhibbits bool dedicatedChannel; 504296177Sjhibbits bool dedicatedChannelHasPrecedenceOverPoolChannels; 505296177Sjhibbits uint8_t poolChannels[QM_MAX_NUM_OF_POOL_CHANNELS]; 506296177Sjhibbits uint8_t poolChannelId; 507296177Sjhibbits uint8_t wqId; 508296177Sjhibbits uint16_t fdLiodnOffset; 509296177Sjhibbits uint8_t stashDestQueue; 510296177Sjhibbits uint8_t eqcr; 511296177Sjhibbits bool eqcrHighPri; 512296177Sjhibbits bool dqrr; 513296177Sjhibbits uint16_t dqrrLiodn; 514296177Sjhibbits bool dqrrHighPri; 515296177Sjhibbits bool fdFq; 516296177Sjhibbits uint16_t fdFqLiodn; 517296177Sjhibbits bool fdFqHighPri; 518296177Sjhibbits bool fdFqDrop; 519296177Sjhibbits} t_QmPortalDriverParams; 520296177Sjhibbits 521296177Sjhibbits/*typedef struct t_QmPortalCgs{ 522296177Sjhibbits uint32_t cgsMask[QM_MAX_NUM_OF_CGS/32]; 523296177Sjhibbits}t_QmPortalCgs; 524296177Sjhibbits*/ 525296177Sjhibbitstypedef struct t_QmPortal { 526296177Sjhibbits t_Handle h_Qm; 527296177Sjhibbits struct qm_portal *p_LowQmPortal; 528296177Sjhibbits uint32_t bits; /* PORTAL_BITS_*** - dynamic, strictly internal */ 529296177Sjhibbits t_Handle h_App; 530296177Sjhibbits t_QmLoopDequeueRing *f_LoopDequeueRingCB; 531296177Sjhibbits bool pullMode; 532296177Sjhibbits /* To avoid overloading the term "flags", we use these 2; */ 533296177Sjhibbits uint32_t options; /* QMAN_PORTAL_FLAG_*** - static, caller-provided */ 534296177Sjhibbits uint32_t irq_flags; 535296177Sjhibbits /* The wrap-around eq_[prod|cons] counters are used to support 536296177Sjhibbits * QMAN_ENQUEUE_FLAG_WAIT_SYNC. */ 537296177Sjhibbits uint32_t eqProd; 538296177Sjhibbits volatile int disable_count; 539296177Sjhibbits struct qman_cgrs cgrs[2]; /* 2-element array. cgrs[0] is mask, cgrs[1] is previous snapshot. */ 540296177Sjhibbits /* If we receive a DQRR or MR ring entry for a "null" FQ, ie. for which 541296177Sjhibbits * FQD::contextB is NULL rather than pointing to a FQ object, we use 542296177Sjhibbits * these handlers. (This is not considered a fast-path mechanism.) */ 543296177Sjhibbits t_Handle cgsHandles[QM_MAX_NUM_OF_CGS]; 544296177Sjhibbits struct qman_fq_cb *p_NullCB; 545296177Sjhibbits t_QmReceivedFrameCallback *f_DfltFrame; 546296177Sjhibbits t_QmRejectedFrameCallback *f_RejectedFrame; 547296177Sjhibbits t_QmPortalDriverParams *p_QmPortalDriverParams; 548296177Sjhibbits} t_QmPortal; 549296177Sjhibbits 550296177Sjhibbitsstruct qman_fq { 551296177Sjhibbits struct qman_fq_cb cb; 552296177Sjhibbits t_Handle h_App; 553296177Sjhibbits t_Handle h_QmFqr; 554296177Sjhibbits t_Handle fqlock; 555296177Sjhibbits uint32_t fqid; 556296177Sjhibbits uint32_t fqidOffset; 557296177Sjhibbits uint32_t flags; 558296177Sjhibbits /* s/w-visible states. Ie. tentatively scheduled + truly scheduled + 559296177Sjhibbits * active + held-active + held-suspended are just "sched". Things like 560296177Sjhibbits * 'retired' will not be assumed until it is complete (ie. 561296177Sjhibbits * QMAN_FQ_STATE_CHANGING is set until then, to indicate it's completing 562296177Sjhibbits * and to gate attempts to retry the retire command). Note, park 563296177Sjhibbits * commands do not set QMAN_FQ_STATE_CHANGING because it's technically 564296177Sjhibbits * impossible in the case of enqueue DCAs (which refer to DQRR ring 565296177Sjhibbits * index rather than the FQ that ring entry corresponds to), so repeated 566296177Sjhibbits * park commands are allowed (if you're silly enough to try) but won't 567296177Sjhibbits * change FQ state, and the resulting park notifications move FQs from 568296177Sjhibbits * 'sched' to 'parked'. */ 569296177Sjhibbits enum qman_fq_state state; 570296177Sjhibbits int cgr_groupid; 571296177Sjhibbits}; 572296177Sjhibbits 573296177Sjhibbitstypedef struct { 574296177Sjhibbits t_Handle h_Qm; 575296177Sjhibbits t_Handle h_QmPortal; 576296177Sjhibbits e_QmFQChannel channel; 577296177Sjhibbits uint8_t workQueue; 578296177Sjhibbits bool shadowMode; 579296177Sjhibbits uint32_t fqidBase; 580296177Sjhibbits uint32_t numOfFqids; 581296177Sjhibbits t_QmFqrDrainedCompletionCB *f_CompletionCB; 582296177Sjhibbits t_Handle h_App; 583296177Sjhibbits uint32_t numOfDrainedFqids; 584296177Sjhibbits bool *p_DrainedFqs; 585296177Sjhibbits struct qman_fq **p_Fqs; 586296177Sjhibbits} t_QmFqr; 587296177Sjhibbits 588296177Sjhibbits 589296177Sjhibbits/****************************************/ 590296177Sjhibbits/* Inter-Module functions */ 591296177Sjhibbits/****************************************/ 592296177Sjhibbitsuint32_t QmGetCounter(t_Handle h_Qm, e_QmInterModuleCounters counter); 593296177Sjhibbitst_Error QmGetRevision(t_Handle h_Qm, t_QmRevisionInfo *p_QmRevisionInfo); 594296177Sjhibbitst_Error QmGetSetPortalParams(t_Handle h_Qm, t_QmInterModulePortalInitParams *p_PortalParams); 595296177Sjhibbitst_Error QmFreeDcPortal(t_Handle h_Qm, e_DpaaDcPortal dcPortalId); 596296177Sjhibbitsuint32_t QmFqidGet(t_Qm *p_Qm, uint32_t size, uint32_t alignment, bool force, uint32_t base); 597296177Sjhibbitst_Error QmFqidPut(t_Qm *p_Qm, uint32_t base); 598296177Sjhibbitst_Error QmGetCgId(t_Handle h_Qm, uint8_t *p_CgId); 599296177Sjhibbitst_Error QmFreeCgId(t_Handle h_Qm, uint8_t cgId); 600296177Sjhibbits 601296177Sjhibbits 602296177Sjhibbitsstatic __inline__ void QmSetPortalHandle(t_Handle h_Qm, t_Handle h_Portal, e_DpaaSwPortal portalId) 603296177Sjhibbits{ 604296177Sjhibbits ASSERT_COND(!((t_Qm*)h_Qm)->h_Portals[portalId] || !h_Portal); 605296177Sjhibbits ((t_Qm*)h_Qm)->h_Portals[portalId] = h_Portal; 606296177Sjhibbits} 607296177Sjhibbits 608296177Sjhibbitsstatic __inline__ t_Handle QmGetPortalHandle(t_Handle h_Qm) 609296177Sjhibbits{ 610296177Sjhibbits t_Qm *p_Qm = (t_Qm*)h_Qm; 611296177Sjhibbits 612296177Sjhibbits ASSERT_COND(p_Qm); 613296177Sjhibbits return p_Qm->h_Portals[CORE_GetId()]; 614296177Sjhibbits} 615296177Sjhibbits 616296177Sjhibbitsstatic __inline__ uint32_t GenerateCgrThresh(uint64_t val, int roundup) 617296177Sjhibbits{ 618296177Sjhibbits uint32_t e = 0; /* co-efficient, exponent */ 619296177Sjhibbits uint32_t oddbit = 0; 620296177Sjhibbits while(val > 0xff) { 621296177Sjhibbits oddbit = (uint32_t)val & 1; 622296177Sjhibbits val >>= 1; 623296177Sjhibbits e++; 624296177Sjhibbits if(roundup && oddbit) 625296177Sjhibbits val++; 626296177Sjhibbits } 627296177Sjhibbits return (uint32_t)((val << 5) | e); 628296177Sjhibbits} 629296177Sjhibbits 630296177Sjhibbitsstatic __inline__ t_Error SetException(t_Qm *p_Qm, e_QmExceptions exception, bool enable) 631296177Sjhibbits{ 632296177Sjhibbits uint32_t bitMask = 0; 633296177Sjhibbits 634296177Sjhibbits ASSERT_COND(p_Qm); 635296177Sjhibbits 636296177Sjhibbits GET_EXCEPTION_FLAG(bitMask, exception); 637296177Sjhibbits if(bitMask) 638296177Sjhibbits { 639296177Sjhibbits if (enable) 640296177Sjhibbits p_Qm->exceptions |= bitMask; 641296177Sjhibbits else 642296177Sjhibbits p_Qm->exceptions &= ~bitMask; 643296177Sjhibbits } 644296177Sjhibbits else 645296177Sjhibbits RETURN_ERROR(MAJOR, E_INVALID_VALUE, ("Undefined exception")); 646296177Sjhibbits 647296177Sjhibbits return E_OK; 648296177Sjhibbits} 649296177Sjhibbits 650296177Sjhibbits 651296177Sjhibbits#endif /* __QM_H */ 652