1296177Sjhibbits/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. 2296177Sjhibbits * All rights reserved. 3296177Sjhibbits * 4296177Sjhibbits * Redistribution and use in source and binary forms, with or without 5296177Sjhibbits * modification, are permitted provided that the following conditions are met: 6296177Sjhibbits * * Redistributions of source code must retain the above copyright 7296177Sjhibbits * notice, this list of conditions and the following disclaimer. 8296177Sjhibbits * * Redistributions in binary form must reproduce the above copyright 9296177Sjhibbits * notice, this list of conditions and the following disclaimer in the 10296177Sjhibbits * documentation and/or other materials provided with the distribution. 11296177Sjhibbits * * Neither the name of Freescale Semiconductor nor the 12296177Sjhibbits * names of its contributors may be used to endorse or promote products 13296177Sjhibbits * derived from this software without specific prior written permission. 14296177Sjhibbits * 15296177Sjhibbits * 16296177Sjhibbits * ALTERNATIVELY, this software may be distributed under the terms of the 17296177Sjhibbits * GNU General Public License ("GPL") as published by the Free Software 18296177Sjhibbits * Foundation, either version 2 of that License or (at your option) any 19296177Sjhibbits * later version. 20296177Sjhibbits * 21296177Sjhibbits * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22296177Sjhibbits * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23296177Sjhibbits * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24296177Sjhibbits * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25296177Sjhibbits * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26296177Sjhibbits * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27296177Sjhibbits * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28296177Sjhibbits * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29296177Sjhibbits * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30296177Sjhibbits * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31296177Sjhibbits */ 32296177Sjhibbits 33296177Sjhibbits/****************************************************************************** 34296177Sjhibbits @File fm.h 35296177Sjhibbits 36296177Sjhibbits @Description FM internal structures and definitions. 37296177Sjhibbits*//***************************************************************************/ 38296177Sjhibbits#ifndef __FM_H 39296177Sjhibbits#define __FM_H 40296177Sjhibbits 41296177Sjhibbits#include "error_ext.h" 42296177Sjhibbits#include "std_ext.h" 43296177Sjhibbits#include "fm_ext.h" 44296177Sjhibbits#include "fm_ipc.h" 45296177Sjhibbits 46296177Sjhibbits 47296177Sjhibbits#define __ERR_MODULE__ MODULE_FM 48296177Sjhibbits 49296177Sjhibbits#define FM_MAX_NUM_OF_HW_PORT_IDS 64 50296177Sjhibbits#define FM_MAX_NUM_OF_GUESTS 100 51296177Sjhibbits 52296177Sjhibbits/**************************************************************************//** 53296177Sjhibbits @Description Exceptions 54296177Sjhibbits*//***************************************************************************/ 55296177Sjhibbits#define FM_EX_DMA_BUS_ERROR 0x80000000 /**< DMA bus error. */ 56296177Sjhibbits#define FM_EX_DMA_READ_ECC 0x40000000 57296177Sjhibbits#define FM_EX_DMA_SYSTEM_WRITE_ECC 0x20000000 58296177Sjhibbits#define FM_EX_DMA_FM_WRITE_ECC 0x10000000 59296177Sjhibbits#define FM_EX_FPM_STALL_ON_TASKS 0x08000000 /**< Stall of tasks on FPM */ 60296177Sjhibbits#define FM_EX_FPM_SINGLE_ECC 0x04000000 /**< Single ECC on FPM */ 61296177Sjhibbits#define FM_EX_FPM_DOUBLE_ECC 0x02000000 62296177Sjhibbits#define FM_EX_QMI_SINGLE_ECC 0x01000000 /**< Single ECC on FPM */ 63296177Sjhibbits#define FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 /**< Dequeu from default queue id */ 64296177Sjhibbits#define FM_EX_QMI_DOUBLE_ECC 0x00400000 65296177Sjhibbits#define FM_EX_BMI_LIST_RAM_ECC 0x00200000 66296177Sjhibbits#define FM_EX_BMI_PIPELINE_ECC 0x00100000 67296177Sjhibbits#define FM_EX_BMI_STATISTICS_RAM_ECC 0x00080000 68296177Sjhibbits#define FM_EX_IRAM_ECC 0x00040000 69296177Sjhibbits#define FM_EX_NURAM_ECC 0x00020000 70296177Sjhibbits#define FM_EX_BMI_DISPATCH_RAM_ECC 0x00010000 71296177Sjhibbits 72296177Sjhibbits#define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \ 73296177Sjhibbits case e_FM_EX_DMA_BUS_ERROR: \ 74296177Sjhibbits bitMask = FM_EX_DMA_BUS_ERROR; break; \ 75296177Sjhibbits case e_FM_EX_DMA_READ_ECC: \ 76296177Sjhibbits bitMask = FM_EX_DMA_READ_ECC; break; \ 77296177Sjhibbits case e_FM_EX_DMA_SYSTEM_WRITE_ECC: \ 78296177Sjhibbits bitMask = FM_EX_DMA_SYSTEM_WRITE_ECC; break; \ 79296177Sjhibbits case e_FM_EX_DMA_FM_WRITE_ECC: \ 80296177Sjhibbits bitMask = FM_EX_DMA_FM_WRITE_ECC; break; \ 81296177Sjhibbits case e_FM_EX_FPM_STALL_ON_TASKS: \ 82296177Sjhibbits bitMask = FM_EX_FPM_STALL_ON_TASKS; break; \ 83296177Sjhibbits case e_FM_EX_FPM_SINGLE_ECC: \ 84296177Sjhibbits bitMask = FM_EX_FPM_SINGLE_ECC; break; \ 85296177Sjhibbits case e_FM_EX_FPM_DOUBLE_ECC: \ 86296177Sjhibbits bitMask = FM_EX_FPM_DOUBLE_ECC; break; \ 87296177Sjhibbits case e_FM_EX_QMI_SINGLE_ECC: \ 88296177Sjhibbits bitMask = FM_EX_QMI_SINGLE_ECC; break; \ 89296177Sjhibbits case e_FM_EX_QMI_DOUBLE_ECC: \ 90296177Sjhibbits bitMask = FM_EX_QMI_DOUBLE_ECC; break; \ 91296177Sjhibbits case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: \ 92296177Sjhibbits bitMask = FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; break; \ 93296177Sjhibbits case e_FM_EX_BMI_LIST_RAM_ECC: \ 94296177Sjhibbits bitMask = FM_EX_BMI_LIST_RAM_ECC; break; \ 95296177Sjhibbits case e_FM_EX_BMI_PIPELINE_ECC: \ 96296177Sjhibbits bitMask = FM_EX_BMI_PIPELINE_ECC; break; \ 97296177Sjhibbits case e_FM_EX_BMI_STATISTICS_RAM_ECC: \ 98296177Sjhibbits bitMask = FM_EX_BMI_STATISTICS_RAM_ECC; break; \ 99296177Sjhibbits case e_FM_EX_BMI_DISPATCH_RAM_ECC: \ 100296177Sjhibbits bitMask = FM_EX_BMI_DISPATCH_RAM_ECC; break; \ 101296177Sjhibbits case e_FM_EX_IRAM_ECC: \ 102296177Sjhibbits bitMask = FM_EX_IRAM_ECC; break; \ 103296177Sjhibbits case e_FM_EX_MURAM_ECC: \ 104296177Sjhibbits bitMask = FM_EX_NURAM_ECC; break; \ 105296177Sjhibbits default: bitMask = 0;break;} 106296177Sjhibbits 107296177Sjhibbits/**************************************************************************//** 108296177Sjhibbits @Description defaults 109296177Sjhibbits*//***************************************************************************/ 110296177Sjhibbits#define DEFAULT_exceptions (FM_EX_DMA_BUS_ERROR |\ 111296177Sjhibbits FM_EX_DMA_READ_ECC |\ 112296177Sjhibbits FM_EX_DMA_SYSTEM_WRITE_ECC |\ 113296177Sjhibbits FM_EX_DMA_FM_WRITE_ECC |\ 114296177Sjhibbits FM_EX_FPM_STALL_ON_TASKS |\ 115296177Sjhibbits FM_EX_FPM_SINGLE_ECC |\ 116296177Sjhibbits FM_EX_FPM_DOUBLE_ECC |\ 117296177Sjhibbits FM_EX_QMI_SINGLE_ECC |\ 118296177Sjhibbits FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID|\ 119296177Sjhibbits FM_EX_QMI_DOUBLE_ECC |\ 120296177Sjhibbits FM_EX_BMI_LIST_RAM_ECC |\ 121296177Sjhibbits FM_EX_BMI_PIPELINE_ECC |\ 122296177Sjhibbits FM_EX_BMI_STATISTICS_RAM_ECC |\ 123296177Sjhibbits FM_EX_BMI_DISPATCH_RAM_ECC |\ 124296177Sjhibbits FM_EX_IRAM_ECC |\ 125296177Sjhibbits FM_EX_NURAM_ECC ) 126296177Sjhibbits#define DEFAULT_totalNumOfTasks (BMI_MAX_NUM_OF_TASKS*3/4) 127296177Sjhibbits#define DEFAULT_totalFifoSize (BMI_MAX_FIFO_SIZE*3/4) 128296177Sjhibbits#define DEFAULT_maxNumOfOpenDmas (BMI_MAX_NUM_OF_DMAS*3/4) 129296177Sjhibbits#define DEFAULT_eccEnable FALSE 130296177Sjhibbits#define DEFAULT_dispLimit 0 131296177Sjhibbits#define DEFAULT_prsDispTh 16 132296177Sjhibbits#define DEFAULT_plcrDispTh 16 133296177Sjhibbits#define DEFAULT_kgDispTh 16 134296177Sjhibbits#define DEFAULT_bmiDispTh 16 135296177Sjhibbits#define DEFAULT_qmiEnqDispTh 16 136296177Sjhibbits#define DEFAULT_qmiDeqDispTh 16 137296177Sjhibbits#define DEFAULT_fmCtl1DispTh 16 138296177Sjhibbits#define DEFAULT_fmCtl2DispTh 16 139296177Sjhibbits#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR 140296177Sjhibbits#ifdef FM_PEDANTIC_DMA 141296177Sjhibbits#define DEFAULT_aidOverride TRUE 142296177Sjhibbits#else 143296177Sjhibbits#define DEFAULT_aidOverride FALSE 144296177Sjhibbits#endif /* FM_PEDANTIC_DMA */ 145296177Sjhibbits#define DEFAULT_aidMode e_FM_DMA_AID_OUT_TNUM 146296177Sjhibbits#define DEFAULT_dmaStopOnBusError FALSE 147296177Sjhibbits#define DEFAULT_stopAtBusError FALSE 148296177Sjhibbits#define DEFAULT_axiDbgNumOfBeats 1 149296177Sjhibbits#define DEFAULT_dmaCamNumOfEntries 32 150296177Sjhibbits#define DEFAULT_dmaCommQLow ((DMA_THRESH_MAX_COMMQ+1)/2) 151296177Sjhibbits#define DEFAULT_dmaCommQHigh ((DMA_THRESH_MAX_COMMQ+1)*3/4) 152296177Sjhibbits#define DEFAULT_dmaReadIntBufLow ((DMA_THRESH_MAX_BUF+1)/2) 153296177Sjhibbits#define DEFAULT_dmaReadIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4) 154296177Sjhibbits#define DEFAULT_dmaWriteIntBufLow ((DMA_THRESH_MAX_BUF+1)/2) 155296177Sjhibbits#define DEFAULT_dmaWriteIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4) 156296177Sjhibbits#define DEFAULT_dmaSosEmergency 0 157296177Sjhibbits#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT 158296177Sjhibbits#define DEFAULT_catastrophicErr e_FM_CATASTROPHIC_ERR_STALL_PORT 159296177Sjhibbits#define DEFAULT_dmaErr e_FM_DMA_ERR_CATASTROPHIC 160296177Sjhibbits#define DEFAULT_resetOnInit FALSE 161296177Sjhibbits#define DEFAULT_haltOnExternalActivation FALSE /* do not change! if changed, must be disabled for rev1 ! */ 162296177Sjhibbits#define DEFAULT_haltOnUnrecoverableEccError FALSE /* do not change! if changed, must be disabled for rev1 ! */ 163296177Sjhibbits#define DEFAULT_externalEccRamsEnable FALSE 164296177Sjhibbits#define DEFAULT_VerifyUcode FALSE 165296177Sjhibbits#define DEFAULT_tnumAgingPeriod 0 166296177Sjhibbits#define DEFAULT_dmaWatchdog 0 /* disabled */ 167296177Sjhibbits#define DEFAULT_mtu 9600 168296177Sjhibbits 169296177Sjhibbits/**************************************************************************//** 170296177Sjhibbits @Description Modules registers offsets 171296177Sjhibbits*//***************************************************************************/ 172296177Sjhibbits#define FM_MM_MURAM 0x00000000 173296177Sjhibbits#define FM_MM_BMI 0x00080000 174296177Sjhibbits#define FM_MM_QMI 0x00080400 175296177Sjhibbits#define FM_MM_PRS 0x000c7000 176296177Sjhibbits#define FM_MM_KG 0x000C1000 177296177Sjhibbits#define FM_MM_DMA 0x000C2000 178296177Sjhibbits#define FM_MM_FPM 0x000C3000 179296177Sjhibbits#define FM_MM_PLCR 0x000C0000 180296177Sjhibbits#define FM_MM_IMEM 0x000C4000 181296177Sjhibbits 182296177Sjhibbits/**************************************************************************//** 183296177Sjhibbits @Description Interrupt Enable/Mask 184296177Sjhibbits*//***************************************************************************/ 185296177Sjhibbits 186296177Sjhibbits/**************************************************************************//** 187296177Sjhibbits @Description Memory Mapped Registers 188296177Sjhibbits*//***************************************************************************/ 189296177Sjhibbits 190296177Sjhibbits#if defined(__MWERKS__) && !defined(__GNUC__) 191296177Sjhibbits#pragma pack(push,1) 192296177Sjhibbits#endif /* defined(__MWERKS__) && ... */ 193296177Sjhibbits#define MEM_MAP_START 194296177Sjhibbits 195296177Sjhibbitstypedef _Packed struct 196296177Sjhibbits{ 197296177Sjhibbits volatile uint32_t fpmtnc; /**< FPM TNUM Control */ 198296177Sjhibbits volatile uint32_t fpmpr; /**< FPM Port_ID FmCtl Association */ 199296177Sjhibbits volatile uint32_t brkc; /**< FPM Breakpoint Control */ 200296177Sjhibbits volatile uint32_t fpmflc; /**< FPM Flush Control */ 201296177Sjhibbits volatile uint32_t fpmdis1; /**< FPM Dispatch Thresholds1 */ 202296177Sjhibbits volatile uint32_t fpmdis2; /**< FPM Dispatch Thresholds2 */ 203296177Sjhibbits volatile uint32_t fmepi; /**< FM Error Pending Interrupts */ 204296177Sjhibbits volatile uint32_t fmrie; /**< FM Error Interrupt Enable */ 205296177Sjhibbits volatile uint32_t fmfpfcev[4]; /**< FPM FMan-Controller Event 1-4 */ 206296177Sjhibbits volatile uint8_t res1[16]; /**< reserved */ 207296177Sjhibbits volatile uint32_t fmfpfcee[4]; /**< PM FMan-Controller Event 1-4 */ 208296177Sjhibbits volatile uint8_t res2[16]; /**< reserved */ 209296177Sjhibbits volatile uint32_t fpmtsc1; /**< FPM TimeStamp Control1 */ 210296177Sjhibbits volatile uint32_t fpmtsc2; /**< FPM TimeStamp Control2 */ 211296177Sjhibbits volatile uint32_t fpmtsp; /**< FPM Time Stamp */ 212296177Sjhibbits volatile uint32_t fpmtsf; /**< FPM Time Stamp Fraction */ 213296177Sjhibbits volatile uint32_t fmrcr; /**< FM Rams Control */ 214296177Sjhibbits volatile uint32_t fpmextc; /**< FPM External Requests Control */ 215296177Sjhibbits volatile uint32_t fpmext1; /**< FPM External Requests Config1 */ 216296177Sjhibbits volatile uint32_t fpmext2; /**< FPM External Requests Config2 */ 217296177Sjhibbits volatile uint32_t fpmdrd[16]; /**< FPM Data_Ram Data 0-15 */ 218296177Sjhibbits volatile uint32_t fpmdra; /**< FPM Data Ram Access */ 219296177Sjhibbits volatile uint32_t fm_ip_rev_1; /**< FM IP Block Revision 1 */ 220296177Sjhibbits volatile uint32_t fm_ip_rev_2; /**< FM IP Block Revision 2 */ 221296177Sjhibbits volatile uint32_t fmrstc; /**< FM Reset Command */ 222296177Sjhibbits volatile uint32_t fmcld; /**< FM Classifier Debug */ 223296177Sjhibbits volatile uint32_t fmnpi; /**< FM Normal Pending Interrupts */ 224296177Sjhibbits volatile uint32_t fmfp_exte; /**< FPM External Requests Enable */ 225296177Sjhibbits volatile uint32_t fpmem; /**< FPM Event & Mask */ 226296177Sjhibbits volatile uint32_t fpmcev[4]; /**< FPM CPU Event 1-4 */ 227296177Sjhibbits volatile uint8_t res4[16]; /**< reserved */ 228296177Sjhibbits volatile uint32_t fmfp_ps[0x40]; /**< FPM Port Status */ 229296177Sjhibbits volatile uint8_t reserved1[0x260]; 230296177Sjhibbits volatile uint32_t fpmts[128]; /**< 0x400: FPM Task Status */ 231296177Sjhibbits} _PackedType t_FmFpmRegs; 232296177Sjhibbits 233296177Sjhibbits#define NUM_OF_DBG_TRAPS 3 234296177Sjhibbits 235296177Sjhibbitstypedef _Packed struct 236296177Sjhibbits{ 237296177Sjhibbits volatile uint32_t fmbm_init; /**< BMI Initialization */ 238296177Sjhibbits volatile uint32_t fmbm_cfg1; /**< BMI Configuration 1 */ 239296177Sjhibbits volatile uint32_t fmbm_cfg2; /**< BMI Configuration 2 */ 240296177Sjhibbits volatile uint32_t reserved[5]; 241296177Sjhibbits volatile uint32_t fmbm_ievr; /**< Interrupt Event Register */ 242296177Sjhibbits volatile uint32_t fmbm_ier; /**< Interrupt Enable Register */ 243296177Sjhibbits volatile uint32_t fmbm_ifr; /**< Interrupt Force Register */ 244296177Sjhibbits volatile uint32_t reserved1[5]; 245296177Sjhibbits volatile uint32_t fmbm_arb[8]; /**< BMI Arbitration */ 246296177Sjhibbits volatile uint32_t reserved2[12]; 247296177Sjhibbits volatile uint32_t fmbm_dtc[NUM_OF_DBG_TRAPS]; /**< BMI Debug Trap Counter */ 248296177Sjhibbits volatile uint32_t reserved3; 249296177Sjhibbits volatile uint32_t fmbm_dcv[NUM_OF_DBG_TRAPS][4]; /**< BMI Debug Compare Value */ 250296177Sjhibbits volatile uint32_t fmbm_dcm[NUM_OF_DBG_TRAPS][4]; /**< BMI Debug Compare Mask */ 251296177Sjhibbits volatile uint32_t fmbm_gde; /**< BMI Global Debug Enable */ 252296177Sjhibbits volatile uint32_t fmbm_pp[63]; /**< BMI Port Parameters */ 253296177Sjhibbits volatile uint32_t reserved4; 254296177Sjhibbits volatile uint32_t fmbm_pfs[63]; /**< BMI Port FIFO Size */ 255296177Sjhibbits volatile uint32_t reserved5; 256296177Sjhibbits volatile uint32_t fmbm_ppid[63]; /**< Port Partition ID */ 257296177Sjhibbits} _PackedType t_FmBmiRegs; 258296177Sjhibbits 259296177Sjhibbitstypedef _Packed struct 260296177Sjhibbits{ 261296177Sjhibbits volatile uint32_t fmqm_gc; /**< General Configuration Register */ 262296177Sjhibbits volatile uint32_t Reserved0; 263296177Sjhibbits volatile uint32_t fmqm_eie; /**< Error Interrupt Event Register */ 264296177Sjhibbits volatile uint32_t fmqm_eien; /**< Error Interrupt Enable Register */ 265296177Sjhibbits volatile uint32_t fmqm_eif; /**< Error Interrupt Force Register */ 266296177Sjhibbits volatile uint32_t fmqm_ie; /**< Interrupt Event Register */ 267296177Sjhibbits volatile uint32_t fmqm_ien; /**< Interrupt Enable Register */ 268296177Sjhibbits volatile uint32_t fmqm_if; /**< Interrupt Force Register */ 269296177Sjhibbits volatile uint32_t fmqm_gs; /**< Global Status Register */ 270296177Sjhibbits volatile uint32_t fmqm_ts; /**< Task Status Register */ 271296177Sjhibbits volatile uint32_t fmqm_etfc; /**< Enqueue Total Frame Counter */ 272296177Sjhibbits volatile uint32_t fmqm_dtfc; /**< Dequeue Total Frame Counter */ 273296177Sjhibbits volatile uint32_t fmqm_dc0; /**< Dequeue Counter 0 */ 274296177Sjhibbits volatile uint32_t fmqm_dc1; /**< Dequeue Counter 1 */ 275296177Sjhibbits volatile uint32_t fmqm_dc2; /**< Dequeue Counter 2 */ 276296177Sjhibbits volatile uint32_t fmqm_dc3; /**< Dequeue Counter 3 */ 277296177Sjhibbits volatile uint32_t fmqm_dfdc; /**< Dequeue FQID from Default Counter */ 278296177Sjhibbits volatile uint32_t fmqm_dfcc; /**< Dequeue FQID from Context Counter */ 279296177Sjhibbits volatile uint32_t fmqm_dffc; /**< Dequeue FQID from FD Counter */ 280296177Sjhibbits volatile uint32_t fmqm_dcc; /**< Dequeue Confirm Counter */ 281296177Sjhibbits volatile uint32_t Reserved1a[7]; 282296177Sjhibbits volatile uint32_t fmqm_tapc; /**< Tnum Aging Period Control */ 283296177Sjhibbits volatile uint32_t fmqm_dmcvc; /**< Dequeue MAC Command Valid Counter */ 284296177Sjhibbits volatile uint32_t fmqm_difdcc; /**< Dequeue Invalid FD Command Counter */ 285296177Sjhibbits volatile uint32_t fmqm_da1v; /**< Dequeue A1 Valid Counter */ 286296177Sjhibbits volatile uint32_t Reserved1b; 287296177Sjhibbits volatile uint32_t fmqm_dtc; /**< 0x0080 Debug Trap Counter */ 288296177Sjhibbits volatile uint32_t fmqm_efddd; /**< 0x0084 Enqueue Frame Descriptor Dynamic Debug */ 289296177Sjhibbits volatile uint32_t Reserved3[2]; 290296177Sjhibbits _Packed struct { 291296177Sjhibbits volatile uint32_t fmqm_dtcfg1; /**< 0x0090 Debug Trap Configuration 1 Register */ 292296177Sjhibbits volatile uint32_t fmqm_dtval1; /**< Debug Trap Value 1 Register */ 293296177Sjhibbits volatile uint32_t fmqm_dtm1; /**< Debug Trap Mask 1 Register */ 294296177Sjhibbits volatile uint32_t fmqm_dtc1; /**< Debug Trap Counter 1 Register */ 295296177Sjhibbits volatile uint32_t fmqm_dtcfg2; /**< Debug Trap Configuration 2 Register */ 296296177Sjhibbits volatile uint32_t fmqm_dtval2; /**< Debug Trap Value 2 Register */ 297296177Sjhibbits volatile uint32_t fmqm_dtm2; /**< Debug Trap Mask 2 Register */ 298296177Sjhibbits volatile uint32_t Reserved1; 299296177Sjhibbits } _PackedType dbgTraps[NUM_OF_DBG_TRAPS]; 300296177Sjhibbits} _PackedType t_FmQmiRegs; 301296177Sjhibbits 302296177Sjhibbitstypedef _Packed struct 303296177Sjhibbits{ 304296177Sjhibbits volatile uint32_t fmdmsr; /**< FM DMA status register 0x04 */ 305296177Sjhibbits volatile uint32_t fmdmmr; /**< FM DMA mode register 0x08 */ 306296177Sjhibbits volatile uint32_t fmdmtr; /**< FM DMA bus threshold register 0x0c */ 307296177Sjhibbits volatile uint32_t fmdmhy; /**< FM DMA bus hysteresis register 0x10 */ 308296177Sjhibbits volatile uint32_t fmdmsetr; /**< FM DMA SOS emergency Threshold Register 0x14 */ 309296177Sjhibbits volatile uint32_t fmdmtah; /**< FM DMA transfer bus address high register 0x18 */ 310296177Sjhibbits volatile uint32_t fmdmtal; /**< FM DMA transfer bus address low register 0x1C */ 311296177Sjhibbits volatile uint32_t fmdmtcid; /**< FM DMA transfer bus communication ID register 0x20 */ 312296177Sjhibbits volatile uint32_t fmdmra; /**< FM DMA bus internal ram address register 0x24 */ 313296177Sjhibbits volatile uint32_t fmdmrd; /**< FM DMA bus internal ram data register 0x28 */ 314296177Sjhibbits volatile uint32_t fmdmwcr; /**< FM DMA CAM watchdog counter value 0x2C */ 315296177Sjhibbits volatile uint32_t fmdmebcr; /**< FM DMA CAM base in MURAM register 0x30 */ 316296177Sjhibbits volatile uint32_t fmdmccqdr; /**< FM DMA CAM and CMD Queue Debug register 0x34 */ 317296177Sjhibbits volatile uint32_t fmdmccqvr1; /**< FM DMA CAM and CMD Queue Value register #1 0x38 */ 318296177Sjhibbits volatile uint32_t fmdmccqvr2; /**< FM DMA CAM and CMD Queue Value register #2 0x3C */ 319296177Sjhibbits volatile uint32_t fmdmcqvr3; /**< FM DMA CMD Queue Value register #3 0x40 */ 320296177Sjhibbits volatile uint32_t fmdmcqvr4; /**< FM DMA CMD Queue Value register #4 0x44 */ 321296177Sjhibbits volatile uint32_t fmdmcqvr5; /**< FM DMA CMD Queue Value register #5 0x48 */ 322296177Sjhibbits volatile uint32_t fmdmsefrc; /**< FM DMA Semaphore Entry Full Reject Counter 0x50 */ 323296177Sjhibbits volatile uint32_t fmdmsqfrc; /**< FM DMA Semaphore Queue Full Reject Counter 0x54 */ 324296177Sjhibbits volatile uint32_t fmdmssrc; /**< FM DMA Semaphore SYNC Reject Counter 0x54 */ 325296177Sjhibbits volatile uint32_t fmdmdcr; /**< FM DMA Debug Counter */ 326296177Sjhibbits volatile uint32_t fmdmemsr; /**< FM DMA Emrgency Smoother Register */ 327296177Sjhibbits volatile uint32_t reserved; 328296177Sjhibbits volatile uint32_t fmdmplr[FM_SIZE_OF_LIODN_TABLE/2]; 329296177Sjhibbits /**< FM DMA PID-LIODN # register */ 330296177Sjhibbits} _PackedType t_FmDmaRegs; 331296177Sjhibbits 332296177Sjhibbitstypedef _Packed struct 333296177Sjhibbits{ 334296177Sjhibbits volatile uint32_t iadd; /**< FM IRAM instruction address register */ 335296177Sjhibbits volatile uint32_t idata; /**< FM IRAM instruction data register */ 336296177Sjhibbits volatile uint32_t itcfg; /**< FM IRAM timing config register */ 337296177Sjhibbits volatile uint32_t iready; /**< FM IRAM ready register */ 338296177Sjhibbits volatile uint8_t res[0x80000-0x10]; 339296177Sjhibbits} _PackedType t_FMIramRegs; 340296177Sjhibbits 341296177Sjhibbits#define MEM_MAP_END 342296177Sjhibbits#if defined(__MWERKS__) && !defined(__GNUC__) 343296177Sjhibbits#pragma pack(pop) 344296177Sjhibbits#endif /* defined(__MWERKS__) && ... */ 345296177Sjhibbits 346296177Sjhibbits 347296177Sjhibbits/**************************************************************************//** 348296177Sjhibbits @Description General defines 349296177Sjhibbits*//***************************************************************************/ 350296177Sjhibbits 351296177Sjhibbits#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL 352296177Sjhibbits#define FM_UCODE_DEBUG_INSTRUCTION 0x6ffff805UL 353296177Sjhibbits 354296177Sjhibbits 355296177Sjhibbits/**************************************************************************//** 356296177Sjhibbits @Description DMA definitions 357296177Sjhibbits*//***************************************************************************/ 358296177Sjhibbits 359296177Sjhibbits/* masks */ 360296177Sjhibbits#define DMA_MODE_AID_OR 0x20000000 361296177Sjhibbits#define DMA_MODE_SBER 0x10000000 362296177Sjhibbits#define DMA_MODE_BER 0x00200000 363296177Sjhibbits#define DMA_MODE_ECC 0x00000020 364296177Sjhibbits#define DMA_MODE_PRIVILEGE_PROT 0x00001000 365296177Sjhibbits#define DMA_MODE_SECURE_PROT 0x00000800 366296177Sjhibbits#define DMA_MODE_EMERGENCY_READ 0x00080000 367296177Sjhibbits#define DMA_MODE_EMERGENCY_WRITE 0x00040000 368296177Sjhibbits 369296177Sjhibbits#define DMA_TRANSFER_PORTID_MASK 0xFF000000 370296177Sjhibbits#define DMA_TRANSFER_TNUM_MASK 0x00FF0000 371296177Sjhibbits#define DMA_TRANSFER_LIODN_MASK 0x00000FFF 372296177Sjhibbits 373296177Sjhibbits#define DMA_HIGH_LIODN_MASK 0x0FFF0000 374296177Sjhibbits#define DMA_LOW_LIODN_MASK 0x00000FFF 375296177Sjhibbits 376296177Sjhibbits#define DMA_STATUS_CMD_QUEUE_NOT_EMPTY 0x10000000 377296177Sjhibbits#define DMA_STATUS_BUS_ERR 0x08000000 378296177Sjhibbits#define DMA_STATUS_READ_ECC 0x04000000 379296177Sjhibbits#define DMA_STATUS_SYSTEM_WRITE_ECC 0x02000000 380296177Sjhibbits#define DMA_STATUS_FM_WRITE_ECC 0x01000000 381296177Sjhibbits#define DMA_STATUS_SYSTEM_DPEXT_ECC 0x00800000 382296177Sjhibbits#define DMA_STATUS_FM_DPEXT_ECC 0x00400000 383296177Sjhibbits#define DMA_STATUS_SYSTEM_DPDAT_ECC 0x00200000 384296177Sjhibbits#define DMA_STATUS_FM_DPDAT_ECC 0x00100000 385296177Sjhibbits#define DMA_STATUS_FM_SPDAT_ECC 0x00080000 386296177Sjhibbits 387296177Sjhibbits#define FM_LIODN_BASE_MASK 0x00000FFF 388296177Sjhibbits 389296177Sjhibbits/* shifts */ 390296177Sjhibbits#define DMA_MODE_CACHE_OR_SHIFT 30 391296177Sjhibbits#define DMA_MODE_BUS_PRI_SHIFT 16 392296177Sjhibbits#define DMA_MODE_AXI_DBG_SHIFT 24 393296177Sjhibbits#define DMA_MODE_CEN_SHIFT 13 394296177Sjhibbits#define DMA_MODE_BUS_PROT_SHIFT 10 395296177Sjhibbits#define DMA_MODE_DBG_SHIFT 7 396296177Sjhibbits#define DMA_MODE_EMERGENCY_LEVEL_SHIFT 6 397296177Sjhibbits#define DMA_MODE_AID_MODE_SHIFT 4 398296177Sjhibbits#define DMA_MODE_MAX_AXI_DBG_NUM_OF_BEATS 16 399296177Sjhibbits#define DMA_MODE_MAX_CAM_NUM_OF_ENTRIES 32 400296177Sjhibbits 401296177Sjhibbits#define DMA_THRESH_COMMQ_SHIFT 24 402296177Sjhibbits#define DMA_THRESH_READ_INT_BUF_SHIFT 16 403296177Sjhibbits 404296177Sjhibbits#define DMA_LIODN_SHIFT 16 405296177Sjhibbits 406296177Sjhibbits#define DMA_TRANSFER_PORTID_SHIFT 24 407296177Sjhibbits#define DMA_TRANSFER_TNUM_SHIFT 16 408296177Sjhibbits 409296177Sjhibbits/* sizes */ 410296177Sjhibbits#define DMA_MAX_WATCHDOG 0xffffffff 411296177Sjhibbits 412296177Sjhibbits/* others */ 413296177Sjhibbits#define DMA_CAM_SIZEOF_ENTRY 0x40 414296177Sjhibbits#define DMA_CAM_ALIGN 0x1000 415296177Sjhibbits#define DMA_CAM_UNITS 8 416296177Sjhibbits 417296177Sjhibbits 418296177Sjhibbits/**************************************************************************//** 419296177Sjhibbits @Description FPM defines 420296177Sjhibbits*//***************************************************************************/ 421296177Sjhibbits 422296177Sjhibbits/* masks */ 423296177Sjhibbits#define FPM_EV_MASK_DOUBLE_ECC 0x80000000 424296177Sjhibbits#define FPM_EV_MASK_STALL 0x40000000 425296177Sjhibbits#define FPM_EV_MASK_SINGLE_ECC 0x20000000 426296177Sjhibbits#define FPM_EV_MASK_RELEASE_FM 0x00010000 427296177Sjhibbits#define FPM_EV_MASK_DOUBLE_ECC_EN 0x00008000 428296177Sjhibbits#define FPM_EV_MASK_STALL_EN 0x00004000 429296177Sjhibbits#define FPM_EV_MASK_SINGLE_ECC_EN 0x00002000 430296177Sjhibbits#define FPM_EV_MASK_EXTERNAL_HALT 0x00000008 431296177Sjhibbits#define FPM_EV_MASK_ECC_ERR_HALT 0x00000004 432296177Sjhibbits 433296177Sjhibbits#define FPM_RAM_CTL_RAMS_ECC_EN 0x80000000 434296177Sjhibbits#define FPM_RAM_CTL_IRAM_ECC_EN 0x40000000 435296177Sjhibbits#define FPM_RAM_CTL_MURAM_ECC 0x00008000 436296177Sjhibbits#define FPM_RAM_CTL_IRAM_ECC 0x00004000 437296177Sjhibbits#define FPM_RAM_CTL_MURAM_TEST_ECC 0x20000000 438296177Sjhibbits#define FPM_RAM_CTL_IRAM_TEST_ECC 0x10000000 439296177Sjhibbits#define FPM_RAM_CTL_RAMS_ECC_EN_SRC_SEL 0x08000000 440296177Sjhibbits 441296177Sjhibbits#define FPM_IRAM_ECC_ERR_EX_EN 0x00020000 442296177Sjhibbits#define FPM_MURAM_ECC_ERR_EX_EN 0x00040000 443296177Sjhibbits 444296177Sjhibbits#define FPM_REV1_MAJOR_MASK 0x0000FF00 445296177Sjhibbits#define FPM_REV1_MINOR_MASK 0x000000FF 446296177Sjhibbits 447296177Sjhibbits#define FPM_REV2_INTEG_MASK 0x00FF0000 448296177Sjhibbits#define FPM_REV2_ERR_MASK 0x0000FF00 449296177Sjhibbits#define FPM_REV2_CFG_MASK 0x000000FF 450296177Sjhibbits 451296177Sjhibbits#define FPM_TS_FRACTION_MASK 0x0000FFFF 452296177Sjhibbits#define FPM_TS_CTL_EN 0x80000000 453296177Sjhibbits 454296177Sjhibbits#define FPM_PORT_FM_CTL1 0x00000001 455296177Sjhibbits#define FPM_PORT_FM_CTL2 0x00000002 456296177Sjhibbits#define FPM_PRC_REALSE_STALLED 0x00800000 457296177Sjhibbits 458296177Sjhibbits#define FPM_PS_STALLED 0x00800000 459296177Sjhibbits#define FPM_PS_FM_CTL1_SEL 0x80000000 460296177Sjhibbits#define FPM_PS_FM_CTL2_SEL 0x40000000 461296177Sjhibbits#define FPM_PS_FM_CTL_SEL_MASK (FPM_PS_FM_CTL1_SEL | FPM_PS_FM_CTL2_SEL) 462296177Sjhibbits 463296177Sjhibbits#define FPM_RSTC_FM_RESET 0x80000000 464296177Sjhibbits#define FPM_RSTC_10G0_RESET 0x04000000 465296177Sjhibbits#define FPM_RSTC_1G0_RESET 0x40000000 466296177Sjhibbits#define FPM_RSTC_1G1_RESET 0x20000000 467296177Sjhibbits#define FPM_RSTC_1G2_RESET 0x10000000 468296177Sjhibbits#define FPM_RSTC_1G3_RESET 0x08000000 469296177Sjhibbits#define FPM_RSTC_1G4_RESET 0x02000000 470296177Sjhibbits 471296177Sjhibbits 472296177Sjhibbits/* shifts */ 473296177Sjhibbits#define FPM_DISP_LIMIT_SHIFT 24 474296177Sjhibbits 475296177Sjhibbits#define FPM_THR1_PRS_SHIFT 24 476296177Sjhibbits#define FPM_THR1_KG_SHIFT 16 477296177Sjhibbits#define FPM_THR1_PLCR_SHIFT 8 478296177Sjhibbits#define FPM_THR1_BMI_SHIFT 0 479296177Sjhibbits 480296177Sjhibbits#define FPM_THR2_QMI_ENQ_SHIFT 24 481296177Sjhibbits#define FPM_THR2_QMI_DEQ_SHIFT 0 482296177Sjhibbits#define FPM_THR2_FM_CTL1_SHIFT 16 483296177Sjhibbits#define FPM_THR2_FM_CTL2_SHIFT 8 484296177Sjhibbits 485296177Sjhibbits#define FPM_EV_MASK_CAT_ERR_SHIFT 1 486296177Sjhibbits#define FPM_EV_MASK_DMA_ERR_SHIFT 0 487296177Sjhibbits 488296177Sjhibbits#define FPM_REV1_MAJOR_SHIFT 8 489296177Sjhibbits#define FPM_REV1_MINOR_SHIFT 0 490296177Sjhibbits 491296177Sjhibbits#define FPM_REV2_INTEG_SHIFT 16 492296177Sjhibbits#define FPM_REV2_ERR_SHIFT 8 493296177Sjhibbits#define FPM_REV2_CFG_SHIFT 0 494296177Sjhibbits 495296177Sjhibbits#define FPM_TS_INT_SHIFT 16 496296177Sjhibbits 497296177Sjhibbits#define FPM_PORT_FM_CTL_PORTID_SHIFT 24 498296177Sjhibbits 499296177Sjhibbits#define FPM_PS_FM_CTL_SEL_SHIFT 30 500296177Sjhibbits#define FPM_PRC_ORA_FM_CTL_SEL_SHIFT 16 501296177Sjhibbits 502296177Sjhibbits/* Interrupts defines */ 503296177Sjhibbits#define FPM_EVENT_FM_CTL_0 0x00008000 504296177Sjhibbits#define FPM_EVENT_FM_CTL 0x0000FF00 505296177Sjhibbits#define FPM_EVENT_FM_CTL_BRK 0x00000080 506296177Sjhibbits 507296177Sjhibbits/* others */ 508296177Sjhibbits#define FPM_MAX_DISP_LIMIT 31 509296177Sjhibbits 510296177Sjhibbits/**************************************************************************//** 511296177Sjhibbits @Description BMI defines 512296177Sjhibbits*//***************************************************************************/ 513296177Sjhibbits/* masks */ 514296177Sjhibbits#define BMI_INIT_START 0x80000000 515296177Sjhibbits#define BMI_ERR_INTR_EN_PIPELINE_ECC 0x80000000 516296177Sjhibbits#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000 517296177Sjhibbits#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000 518296177Sjhibbits#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000 519296177Sjhibbits#define BMI_NUM_OF_TASKS_MASK 0x3F000000 520296177Sjhibbits#define BMI_NUM_OF_EXTRA_TASKS_MASK 0x000F0000 521296177Sjhibbits#define BMI_NUM_OF_DMAS_MASK 0x00000F00 522296177Sjhibbits#define BMI_NUM_OF_EXTRA_DMAS_MASK 0x0000000F 523296177Sjhibbits#define BMI_FIFO_SIZE_MASK 0x000003FF 524296177Sjhibbits#define BMI_EXTRA_FIFO_SIZE_MASK 0x03FF0000 525296177Sjhibbits#define BMI_CFG2_DMAS_MASK 0x0000003F 526296177Sjhibbits 527296177Sjhibbits/* shifts */ 528296177Sjhibbits#define BMI_CFG2_TASKS_SHIFT 16 529296177Sjhibbits#define BMI_CFG2_DMAS_SHIFT 0 530296177Sjhibbits#define BMI_CFG1_FIFO_SIZE_SHIFT 16 531296177Sjhibbits#define BMI_FIFO_SIZE_SHIFT 0 532296177Sjhibbits#define BMI_EXTRA_FIFO_SIZE_SHIFT 16 533296177Sjhibbits#define BMI_NUM_OF_TASKS_SHIFT 24 534296177Sjhibbits#define BMI_EXTRA_NUM_OF_TASKS_SHIFT 16 535296177Sjhibbits#define BMI_NUM_OF_DMAS_SHIFT 8 536296177Sjhibbits#define BMI_EXTRA_NUM_OF_DMAS_SHIFT 0 537296177Sjhibbits 538296177Sjhibbits/* others */ 539296177Sjhibbits#define BMI_FIFO_ALIGN 0x100 540296177Sjhibbits 541296177Sjhibbits 542296177Sjhibbits/**************************************************************************//** 543296177Sjhibbits @Description QMI defines 544296177Sjhibbits*//***************************************************************************/ 545296177Sjhibbits/* masks */ 546296177Sjhibbits#define QMI_CFG_ENQ_EN 0x80000000 547296177Sjhibbits#define QMI_CFG_DEQ_EN 0x40000000 548296177Sjhibbits#define QMI_CFG_EN_COUNTERS 0x10000000 549296177Sjhibbits#define QMI_CFG_SOFT_RESET 0x01000000 550296177Sjhibbits#define QMI_CFG_DEQ_MASK 0x0000003F 551296177Sjhibbits#define QMI_CFG_ENQ_MASK 0x00003F00 552296177Sjhibbits 553296177Sjhibbits#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000 554296177Sjhibbits#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000 555296177Sjhibbits#define QMI_INTR_EN_SINGLE_ECC 0x80000000 556296177Sjhibbits 557296177Sjhibbits/* shifts */ 558296177Sjhibbits#define QMI_CFG_ENQ_SHIFT 8 559296177Sjhibbits#define QMI_TAPC_TAP 22 560296177Sjhibbits 561296177Sjhibbits 562296177Sjhibbits/**************************************************************************//** 563296177Sjhibbits @Description IRAM defines 564296177Sjhibbits*//***************************************************************************/ 565296177Sjhibbits/* masks */ 566296177Sjhibbits#define IRAM_IADD_AIE 0x80000000 567296177Sjhibbits#define IRAM_READY 0x80000000 568296177Sjhibbits 569296177Sjhibbitstypedef struct { 570296177Sjhibbits void (*f_Isr) (t_Handle h_Arg, uint32_t event); 571296177Sjhibbits t_Handle h_SrcHandle; 572296177Sjhibbits} t_FmanCtrlIntrSrc; 573296177Sjhibbits 574296177Sjhibbits 575296177Sjhibbitstypedef struct 576296177Sjhibbits{ 577296177Sjhibbits /* uint8_t numOfPartitions; */ 578296177Sjhibbits bool resetOnInit; 579296177Sjhibbits#ifdef FM_PARTITION_ARRAY 580296177Sjhibbits uint16_t liodnBasePerPort[FM_SIZE_OF_LIODN_TABLE]; 581296177Sjhibbits#endif 582296177Sjhibbits bool enCounters; 583296177Sjhibbits t_FmThresholds thresholds; 584296177Sjhibbits e_FmDmaCacheOverride dmaCacheOverride; 585296177Sjhibbits e_FmDmaAidMode dmaAidMode; 586296177Sjhibbits bool dmaAidOverride; 587296177Sjhibbits uint8_t dmaAxiDbgNumOfBeats; 588296177Sjhibbits uint8_t dmaCamNumOfEntries; 589296177Sjhibbits uint32_t dmaWatchdog; 590296177Sjhibbits t_FmDmaThresholds dmaCommQThresholds; 591296177Sjhibbits t_FmDmaThresholds dmaWriteBufThresholds; 592296177Sjhibbits t_FmDmaThresholds dmaReadBufThresholds; 593296177Sjhibbits uint32_t dmaSosEmergency; 594296177Sjhibbits e_FmDmaDbgCntMode dmaDbgCntMode; 595296177Sjhibbits bool dmaStopOnBusError; 596296177Sjhibbits bool dmaEnEmergency; 597296177Sjhibbits t_FmDmaEmergency dmaEmergency; 598296177Sjhibbits bool dmaEnEmergencySmoother; 599296177Sjhibbits uint32_t dmaEmergencySwitchCounter; 600296177Sjhibbits bool haltOnExternalActivation; 601296177Sjhibbits bool haltOnUnrecoverableEccError; 602296177Sjhibbits e_FmCatastrophicErr catastrophicErr; 603296177Sjhibbits e_FmDmaErr dmaErr; 604296177Sjhibbits bool enMuramTestMode; 605296177Sjhibbits bool enIramTestMode; 606296177Sjhibbits bool externalEccRamsEnable; 607296177Sjhibbits uint16_t tnumAgingPeriod; 608296177Sjhibbits t_FmPcdFirmwareParams firmware; 609296177Sjhibbits bool fwVerify; 610296177Sjhibbits} t_FmDriverParam; 611296177Sjhibbits 612296177Sjhibbitstypedef void (t_FmanCtrlIsr)( t_Handle h_Fm, uint32_t event); 613296177Sjhibbits 614296177Sjhibbitstypedef struct 615296177Sjhibbits{ 616296177Sjhibbits/***************************/ 617296177Sjhibbits/* Master/Guest parameters */ 618296177Sjhibbits/***************************/ 619296177Sjhibbits uint8_t fmId; 620296177Sjhibbits e_FmPortType portsTypes[FM_MAX_NUM_OF_HW_PORT_IDS]; 621296177Sjhibbits uint16_t fmClkFreq; 622296177Sjhibbits/**************************/ 623296177Sjhibbits/* Master Only parameters */ 624296177Sjhibbits/**************************/ 625296177Sjhibbits bool enabledTimeStamp; 626296177Sjhibbits uint8_t count1MicroBit; 627296177Sjhibbits uint8_t totalNumOfTasks; 628296177Sjhibbits uint32_t totalFifoSize; 629296177Sjhibbits uint8_t maxNumOfOpenDmas; 630296177Sjhibbits uint8_t accumulatedNumOfTasks; 631296177Sjhibbits uint32_t accumulatedFifoSize; 632296177Sjhibbits uint8_t accumulatedNumOfOpenDmas; 633296177Sjhibbits#ifdef FM_QMI_DEQ_OPTIONS_SUPPORT 634296177Sjhibbits uint8_t accumulatedNumOfDeqTnums; 635296177Sjhibbits#endif /* FM_QMI_DEQ_OPTIONS_SUPPORT */ 636296177Sjhibbits#ifdef FM_LOW_END_RESTRICTION 637296177Sjhibbits bool lowEndRestriction; 638296177Sjhibbits#endif /* FM_LOW_END_RESTRICTION */ 639296177Sjhibbits uint32_t exceptions; 640296177Sjhibbits int irq; 641296177Sjhibbits int errIrq; 642296177Sjhibbits bool ramsEccEnable; 643296177Sjhibbits bool explicitEnable; 644296177Sjhibbits bool internalCall; 645296177Sjhibbits uint8_t ramsEccOwners; 646296177Sjhibbits uint32_t extraFifoPoolSize; 647296177Sjhibbits uint8_t extraTasksPoolSize; 648296177Sjhibbits uint8_t extraOpenDmasPoolSize; 649296177Sjhibbits#if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS) 650296177Sjhibbits uint16_t macMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS]; 651296177Sjhibbits#endif /* defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS) */ 652296177Sjhibbits uint16_t macMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS]; 653296177Sjhibbits} t_FmStateStruct; 654296177Sjhibbits 655296177Sjhibbitstypedef struct 656296177Sjhibbits{ 657296177Sjhibbits/***************************/ 658296177Sjhibbits/* Master/Guest parameters */ 659296177Sjhibbits/***************************/ 660296177Sjhibbits/* locals for recovery */ 661296177Sjhibbits uintptr_t baseAddr; 662296177Sjhibbits 663296177Sjhibbits/* un-needed for recovery */ 664296177Sjhibbits t_Handle h_Pcd; 665296177Sjhibbits char fmModuleName[MODULE_NAME_SIZE]; 666296177Sjhibbits char fmIpcHandlerModuleName[FM_MAX_NUM_OF_GUESTS][MODULE_NAME_SIZE]; 667296177Sjhibbits t_Handle h_IpcSessions[FM_MAX_NUM_OF_GUESTS]; 668296177Sjhibbits t_FmIntrSrc intrMng[e_FM_EV_DUMMY_LAST]; /* FM exceptions user callback */ 669296177Sjhibbits uint8_t guestId; 670296177Sjhibbits/**************************/ 671296177Sjhibbits/* Master Only parameters */ 672296177Sjhibbits/**************************/ 673296177Sjhibbits/* locals for recovery */ 674296177Sjhibbits t_FmFpmRegs *p_FmFpmRegs; 675296177Sjhibbits t_FmBmiRegs *p_FmBmiRegs; 676296177Sjhibbits t_FmQmiRegs *p_FmQmiRegs; 677296177Sjhibbits t_FmDmaRegs *p_FmDmaRegs; 678296177Sjhibbits t_FmExceptionsCallback *f_Exception; 679296177Sjhibbits t_FmBusErrorCallback *f_BusError; 680296177Sjhibbits t_Handle h_App; /* Application handle */ 681296177Sjhibbits t_Handle h_Spinlock; 682296177Sjhibbits bool recoveryMode; 683296177Sjhibbits t_FmStateStruct *p_FmStateStruct; 684296177Sjhibbits 685296177Sjhibbits/* un-needed for recovery */ 686296177Sjhibbits t_FmDriverParam *p_FmDriverParam; 687296177Sjhibbits t_Handle h_FmMuram; 688296177Sjhibbits uint64_t fmMuramPhysBaseAddr; 689296177Sjhibbits bool independentMode; 690296177Sjhibbits bool hcPortInitialized; 691296177Sjhibbits uintptr_t camBaseAddr; /* save for freeing */ 692296177Sjhibbits uintptr_t resAddr; 693296177Sjhibbits uintptr_t fifoBaseAddr; /* save for freeing */ 694296177Sjhibbits t_FmanCtrlIntrSrc fmanCtrlIntr[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; /* FM exceptions user callback */ 695296177Sjhibbits bool usedEventRegs[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; 696296177Sjhibbits} t_Fm; 697296177Sjhibbits 698296177Sjhibbits 699296177Sjhibbits#endif /* __FM_H */ 700