1296177Sjhibbits/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. 2296177Sjhibbits * All rights reserved. 3296177Sjhibbits * 4296177Sjhibbits * Redistribution and use in source and binary forms, with or without 5296177Sjhibbits * modification, are permitted provided that the following conditions are met: 6296177Sjhibbits * * Redistributions of source code must retain the above copyright 7296177Sjhibbits * notice, this list of conditions and the following disclaimer. 8296177Sjhibbits * * Redistributions in binary form must reproduce the above copyright 9296177Sjhibbits * notice, this list of conditions and the following disclaimer in the 10296177Sjhibbits * documentation and/or other materials provided with the distribution. 11296177Sjhibbits * * Neither the name of Freescale Semiconductor nor the 12296177Sjhibbits * names of its contributors may be used to endorse or promote products 13296177Sjhibbits * derived from this software without specific prior written permission. 14296177Sjhibbits * 15296177Sjhibbits * 16296177Sjhibbits * ALTERNATIVELY, this software may be distributed under the terms of the 17296177Sjhibbits * GNU General Public License ("GPL") as published by the Free Software 18296177Sjhibbits * Foundation, either version 2 of that License or (at your option) any 19296177Sjhibbits * later version. 20296177Sjhibbits * 21296177Sjhibbits * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22296177Sjhibbits * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23296177Sjhibbits * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24296177Sjhibbits * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25296177Sjhibbits * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26296177Sjhibbits * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27296177Sjhibbits * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28296177Sjhibbits * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29296177Sjhibbits * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30296177Sjhibbits * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31296177Sjhibbits */ 32296177Sjhibbits 33296177Sjhibbits 34296177Sjhibbits#include "error_ext.h" 35296177Sjhibbits#include "std_ext.h" 36296177Sjhibbits#include "fm_mac.h" 37296177Sjhibbits#include "tgec.h" 38296177Sjhibbits#include "xx_ext.h" 39296177Sjhibbits 40296177Sjhibbits 41296177Sjhibbits/*****************************************************************************/ 42296177Sjhibbitst_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec, 43296177Sjhibbits uint8_t phyAddr, 44296177Sjhibbits uint8_t reg, 45296177Sjhibbits uint16_t data) 46296177Sjhibbits{ 47296177Sjhibbits t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; 48296177Sjhibbits t_TgecMiiAccessMemMap *p_MiiAccess; 49296177Sjhibbits 50296177Sjhibbits SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); 51296177Sjhibbits SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE); 52296177Sjhibbits 53296177Sjhibbits p_MiiAccess = p_Tgec->p_MiiMemMap; 54296177Sjhibbits 55296177Sjhibbits while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) 56296177Sjhibbits XX_UDelay (1); 57296177Sjhibbits 58296177Sjhibbits WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr); 59296177Sjhibbits 60296177Sjhibbits WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg); 61296177Sjhibbits 62296177Sjhibbits CORE_MemoryBarrier(); 63296177Sjhibbits 64296177Sjhibbits while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) 65296177Sjhibbits XX_UDelay (1); 66296177Sjhibbits 67296177Sjhibbits WRITE_UINT32(p_MiiAccess->mdio_data, data); 68296177Sjhibbits 69296177Sjhibbits CORE_MemoryBarrier(); 70296177Sjhibbits 71296177Sjhibbits while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY) 72296177Sjhibbits XX_UDelay (1); 73296177Sjhibbits 74296177Sjhibbits return E_OK; 75296177Sjhibbits} 76296177Sjhibbits 77296177Sjhibbits/*****************************************************************************/ 78296177Sjhibbitst_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec, 79296177Sjhibbits uint8_t phyAddr, 80296177Sjhibbits uint8_t reg, 81296177Sjhibbits uint16_t *p_Data) 82296177Sjhibbits{ 83296177Sjhibbits t_Tgec *p_Tgec = (t_Tgec *)h_Tgec; 84296177Sjhibbits t_TgecMiiAccessMemMap *p_MiiAccess; 85296177Sjhibbits uint32_t cfg_status; 86296177Sjhibbits 87296177Sjhibbits SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE); 88296177Sjhibbits SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE); 89296177Sjhibbits 90296177Sjhibbits p_MiiAccess = p_Tgec->p_MiiMemMap; 91296177Sjhibbits 92296177Sjhibbits while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) 93296177Sjhibbits XX_UDelay (1); 94296177Sjhibbits 95296177Sjhibbits WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr); 96296177Sjhibbits 97296177Sjhibbits WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg); 98296177Sjhibbits 99296177Sjhibbits CORE_MemoryBarrier(); 100296177Sjhibbits 101296177Sjhibbits while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY) 102296177Sjhibbits XX_UDelay (1); 103296177Sjhibbits 104296177Sjhibbits WRITE_UINT32(p_MiiAccess->mdio_command, (uint32_t)(phyAddr | MIIMCOM_READ_CYCLE)); 105296177Sjhibbits 106296177Sjhibbits CORE_MemoryBarrier(); 107296177Sjhibbits 108296177Sjhibbits while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY) 109296177Sjhibbits XX_UDelay (1); 110296177Sjhibbits 111296177Sjhibbits *p_Data = (uint16_t)GET_UINT32(p_MiiAccess->mdio_data); 112296177Sjhibbits 113296177Sjhibbits cfg_status = GET_UINT32(p_MiiAccess->mdio_cfg_status); 114296177Sjhibbits 115296177Sjhibbits if (cfg_status & MIIMIND_READ_ERROR) 116296177Sjhibbits RETURN_ERROR(MINOR, E_INVALID_VALUE, 117296177Sjhibbits ("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfg_status 0x%x", 118296177Sjhibbits ((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfg_status)); 119296177Sjhibbits 120296177Sjhibbits return E_OK; 121296177Sjhibbits} 122