1296177Sjhibbits/****************************************************************************** 2296177Sjhibbits 3296177Sjhibbits � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc. 4296177Sjhibbits All rights reserved. 5296177Sjhibbits 6296177Sjhibbits This is proprietary source code of Freescale Semiconductor Inc., 7296177Sjhibbits and its use is subject to the NetComm Device Drivers EULA. 8296177Sjhibbits The copyright notice above does not evidence any actual or intended 9296177Sjhibbits publication of such source code. 10296177Sjhibbits 11296177Sjhibbits ALTERNATIVELY, redistribution and use in source and binary forms, with 12296177Sjhibbits or without modification, are permitted provided that the following 13296177Sjhibbits conditions are met: 14296177Sjhibbits * Redistributions of source code must retain the above copyright 15296177Sjhibbits notice, this list of conditions and the following disclaimer. 16296177Sjhibbits * Redistributions in binary form must reproduce the above copyright 17296177Sjhibbits notice, this list of conditions and the following disclaimer in the 18296177Sjhibbits documentation and/or other materials provided with the distribution. 19296177Sjhibbits * Neither the name of Freescale Semiconductor nor the 20296177Sjhibbits names of its contributors may be used to endorse or promote products 21296177Sjhibbits derived from this software without specific prior written permission. 22296177Sjhibbits 23296177Sjhibbits THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24296177Sjhibbits EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25296177Sjhibbits WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26296177Sjhibbits DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27296177Sjhibbits DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28296177Sjhibbits (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29296177Sjhibbits LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30296177Sjhibbits ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31296177Sjhibbits (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32296177Sjhibbits SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33296177Sjhibbits * 34296177Sjhibbits 35296177Sjhibbits **************************************************************************/ 36296177Sjhibbits/****************************************************************************** 37296177Sjhibbits @File bman_private.h 38296177Sjhibbits 39296177Sjhibbits @Description BM header 40296177Sjhibbits*//***************************************************************************/ 41296177Sjhibbits#ifndef __BMAN_PRIV_H 42296177Sjhibbits#define __BMAN_PRIV_H 43296177Sjhibbits 44296177Sjhibbits#include "fsl_bman.h" 45296177Sjhibbits 46296177Sjhibbits#define __ERR_MODULE__ MODULE_BM 47296177Sjhibbits 48296177Sjhibbits#if defined(DEBUG) || !defined(DISABLE_ASSERTIONS) 49296177Sjhibbits/* Optionally compile-in assertion-checking */ 50296177Sjhibbits#define BM_CHECKING 51296177Sjhibbits#endif /* defined(DEBUG) || ... */ 52296177Sjhibbits 53296177Sjhibbits/* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers 54296177Sjhibbits * and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or 55296177Sjhibbits * execution reordering with respect to other code/instructions that manipulate 56296177Sjhibbits * the same cacheline. */ 57296177Sjhibbits#ifdef CORE_E500MC 58296177Sjhibbits 59296177Sjhibbits#if defined(_DIAB_TOOL) 60296177Sjhibbits#define hwsync() \ 61296177Sjhibbitsdo { \ 62296177Sjhibbits__asm__ __volatile__ ("sync"); \ 63296177Sjhibbits} while(0) 64296177Sjhibbits 65296177Sjhibbits#define lwsync() \ 66296177Sjhibbitsdo { \ 67296177Sjhibbits__asm__ __volatile__ ("lwsync"); \ 68296177Sjhibbits} while(0) 69296177Sjhibbits 70296177Sjhibbits__asm__ __volatile__ void dcbf (volatile void * addr) 71296177Sjhibbits{ 72296177Sjhibbits%reg addr 73296177Sjhibbits dcbf r0, addr 74296177Sjhibbits} 75296177Sjhibbits 76296177Sjhibbits__asm__ __volatile__ void dcbt_ro (volatile void * addr) 77296177Sjhibbits{ 78296177Sjhibbits%reg addr 79296177Sjhibbits dcbt r0, addr 80296177Sjhibbits} 81296177Sjhibbits 82296177Sjhibbits__asm__ __volatile__ void dcbt_rw (volatile void * addr) 83296177Sjhibbits{ 84296177Sjhibbits%reg addr 85296177Sjhibbits dcbtst r0, addr 86296177Sjhibbits} 87296177Sjhibbits 88296177Sjhibbits__asm__ __volatile__ void dcbzl (volatile void * addr) 89296177Sjhibbits{ 90296177Sjhibbits%reg addr 91296177Sjhibbits dcbzl r0, addr 92296177Sjhibbits} 93296177Sjhibbits 94296177Sjhibbits#define dcbz_64(p) \ 95296177Sjhibbits do { \ 96296177Sjhibbits dcbzl(p); \ 97296177Sjhibbits } while (0) 98296177Sjhibbits 99296177Sjhibbits#define dcbf_64(p) \ 100296177Sjhibbits do { \ 101296177Sjhibbits dcbf(p); \ 102296177Sjhibbits } while (0) 103296177Sjhibbits 104296177Sjhibbits/* Commonly used combo */ 105296177Sjhibbits#define dcbit_ro(p) \ 106296177Sjhibbits do { \ 107296177Sjhibbits dcbi(p); \ 108296177Sjhibbits dcbt_ro(p); \ 109296177Sjhibbits } while (0) 110296177Sjhibbits 111296177Sjhibbits#else /* GNU C */ 112296177Sjhibbits#define hwsync() \ 113296177Sjhibbits do { \ 114296177Sjhibbits __asm__ __volatile__ ("sync" : : : "memory"); \ 115296177Sjhibbits } while(0) 116296177Sjhibbits 117296177Sjhibbits#define lwsync() \ 118296177Sjhibbits do { \ 119296177Sjhibbits __asm__ __volatile__ ("lwsync" : : : "memory"); \ 120296177Sjhibbits } while(0) 121296177Sjhibbits 122296177Sjhibbits#define dcbf(addr) \ 123296177Sjhibbits do { \ 124296177Sjhibbits __asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \ 125296177Sjhibbits } while(0) 126296177Sjhibbits 127296177Sjhibbits#define dcbt_ro(addr) \ 128296177Sjhibbits do { \ 129296177Sjhibbits __asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \ 130296177Sjhibbits } while(0) 131296177Sjhibbits 132296177Sjhibbits#define dcbt_rw(addr) \ 133296177Sjhibbits do { \ 134296177Sjhibbits __asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \ 135296177Sjhibbits } while(0) 136296177Sjhibbits 137296177Sjhibbits#define dcbzl(p) \ 138296177Sjhibbits do { \ 139296177Sjhibbits __asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \ 140296177Sjhibbits } while(0) 141296177Sjhibbits 142296177Sjhibbits#define dcbz_64(p) \ 143296177Sjhibbits do { \ 144296177Sjhibbits dcbzl(p); \ 145296177Sjhibbits } while (0) 146296177Sjhibbits 147296177Sjhibbits#define dcbf_64(p) \ 148296177Sjhibbits do { \ 149296177Sjhibbits dcbf(p); \ 150296177Sjhibbits } while (0) 151296177Sjhibbits 152296177Sjhibbits/* Commonly used combo */ 153296177Sjhibbits#define dcbit_ro(p) \ 154296177Sjhibbits do { \ 155296177Sjhibbits dcbi(p); \ 156296177Sjhibbits dcbt_ro(p); \ 157296177Sjhibbits } while (0) 158296177Sjhibbits 159296177Sjhibbits#endif /* _DIAB_TOOL */ 160296177Sjhibbits 161296177Sjhibbits#else 162296177Sjhibbits#define hwsync CORE_MemoryBarrier 163296177Sjhibbits#define lwsync hwsync 164296177Sjhibbits 165296177Sjhibbits#define dcbf(p) \ 166296177Sjhibbits do { \ 167296177Sjhibbits __asm__ __volatile__ ("dcbf 0,%0" : : "r" (p)); \ 168296177Sjhibbits } while(0) 169296177Sjhibbits#define dcbt_ro(p) \ 170296177Sjhibbits do { \ 171296177Sjhibbits __asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \ 172296177Sjhibbits lwsync(); \ 173296177Sjhibbits } while(0) 174296177Sjhibbits#define dcbt_rw(p) \ 175296177Sjhibbits do { \ 176296177Sjhibbits __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \ 177296177Sjhibbits } while(0) 178296177Sjhibbits#define dcbz(p) \ 179296177Sjhibbits do { \ 180296177Sjhibbits __asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \ 181296177Sjhibbits } while (0) 182296177Sjhibbits#define dcbz_64(p) \ 183296177Sjhibbits do { \ 184296177Sjhibbits dcbz((uint32_t)p + 32); \ 185296177Sjhibbits dcbz(p); \ 186296177Sjhibbits } while (0) 187296177Sjhibbits#define dcbf_64(p) \ 188296177Sjhibbits do { \ 189296177Sjhibbits dcbf((uint32_t)p + 32); \ 190296177Sjhibbits dcbf(p); \ 191296177Sjhibbits } while (0) 192296177Sjhibbits/* Commonly used combo */ 193296177Sjhibbits#define dcbit_ro(p) \ 194296177Sjhibbits do { \ 195296177Sjhibbits dcbi(p); \ 196296177Sjhibbits dcbi((uint32_t)p + 32); \ 197296177Sjhibbits dcbt_ro(p); \ 198296177Sjhibbits dcbt_ro((uint32_t)p + 32); \ 199296177Sjhibbits } while (0) 200296177Sjhibbits 201296177Sjhibbits#endif /* CORE_E500MC */ 202296177Sjhibbits 203296177Sjhibbits#define dcbi(p) dcbf(p) 204296177Sjhibbits 205296177Sjhibbitsstruct bm_addr { 206296177Sjhibbits void *addr_ce; /* cache-enabled */ 207296177Sjhibbits void *addr_ci; /* cache-inhibited */ 208296177Sjhibbits}; 209296177Sjhibbits 210296177Sjhibbits/* RCR state */ 211296177Sjhibbitsstruct bm_rcr { 212296177Sjhibbits struct bm_rcr_entry *ring, *cursor; 213296177Sjhibbits uint8_t ci, available, ithresh, vbit; 214296177Sjhibbits#ifdef BM_CHECKING 215296177Sjhibbits uint32_t busy; 216296177Sjhibbits e_BmPortalProduceMode pmode; 217296177Sjhibbits e_BmPortalRcrConsumeMode cmode; 218296177Sjhibbits#endif /* BM_CHECKING */ 219296177Sjhibbits}; 220296177Sjhibbits 221296177Sjhibbits/* MC state */ 222296177Sjhibbitsstruct bm_mc { 223296177Sjhibbits struct bm_mc_command *cr; 224296177Sjhibbits struct bm_mc_result *rr; 225296177Sjhibbits uint8_t rridx, vbit; 226296177Sjhibbits#ifdef BM_CHECKING 227296177Sjhibbits enum { 228296177Sjhibbits /* Can only be _mc_start()ed */ 229296177Sjhibbits mc_idle, 230296177Sjhibbits /* Can only be _mc_commit()ed or _mc_abort()ed */ 231296177Sjhibbits mc_user, 232296177Sjhibbits /* Can only be _mc_retry()ed */ 233296177Sjhibbits mc_hw 234296177Sjhibbits } state; 235296177Sjhibbits#endif /* BM_CHECKING */ 236296177Sjhibbits}; 237296177Sjhibbits 238296177Sjhibbits/********************/ 239296177Sjhibbits/* Portal structure */ 240296177Sjhibbits/********************/ 241296177Sjhibbits 242296177Sjhibbitsstruct bm_portal { 243296177Sjhibbits struct bm_addr addr; 244296177Sjhibbits struct bm_rcr rcr; 245296177Sjhibbits struct bm_mc mc; 246296177Sjhibbits}; 247296177Sjhibbits 248296177Sjhibbits 249296177Sjhibbits#endif /* __BMAN_PRIV_H */ 250