ena_plat.h revision 361534
1/*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#ifndef ENA_PLAT_H_ 35#define ENA_PLAT_H_ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: stable/11/sys/contrib/ena-com/ena_plat.h 361534 2020-05-26 17:54:11Z mw $"); 39 40#include <sys/param.h> 41#include <sys/systm.h> 42 43#include <sys/bus.h> 44#include <sys/condvar.h> 45#include <sys/endian.h> 46#include <sys/kernel.h> 47#include <sys/kthread.h> 48#include <sys/malloc.h> 49#include <sys/mbuf.h> 50#include <sys/module.h> 51#include <sys/rman.h> 52#include <sys/proc.h> 53#include <sys/smp.h> 54#include <sys/socket.h> 55#include <sys/sockio.h> 56#include <sys/sysctl.h> 57#include <sys/taskqueue.h> 58#include <sys/eventhandler.h> 59#include <sys/types.h> 60#include <sys/timetc.h> 61#include <sys/cdefs.h> 62 63#include <machine/atomic.h> 64#include <machine/bus.h> 65#include <machine/in_cksum.h> 66#include <machine/pcpu.h> 67#include <machine/resource.h> 68#include <machine/_inttypes.h> 69 70#include <net/bpf.h> 71#include <net/ethernet.h> 72#include <net/if.h> 73#include <net/if_var.h> 74#include <net/if_arp.h> 75#include <net/if_dl.h> 76#include <net/if_media.h> 77 78#include <net/if_types.h> 79#include <net/if_vlan_var.h> 80 81#include <netinet/in_systm.h> 82#include <netinet/in.h> 83#include <netinet/if_ether.h> 84#include <netinet/ip.h> 85#include <netinet/ip6.h> 86#include <netinet/tcp.h> 87#include <netinet/tcp_lro.h> 88#include <netinet/udp.h> 89 90#include <dev/led/led.h> 91#include <dev/pci/pcivar.h> 92#include <dev/pci/pcireg.h> 93 94extern struct ena_bus_space ebs; 95 96/* Levels */ 97#define ENA_ALERT (1 << 0) /* Alerts are providing more error info. */ 98#define ENA_WARNING (1 << 1) /* Driver output is more error sensitive. */ 99#define ENA_INFO (1 << 2) /* Provides additional driver info. */ 100#define ENA_DBG (1 << 3) /* Driver output for debugging. */ 101/* Detailed info that will be printed with ENA_INFO or ENA_DEBUG flag. */ 102#define ENA_TXPTH (1 << 4) /* Allows TX path tracing. */ 103#define ENA_RXPTH (1 << 5) /* Allows RX path tracing. */ 104#define ENA_RSC (1 << 6) /* Goes with TXPTH or RXPTH, free/alloc res. */ 105#define ENA_IOQ (1 << 7) /* Detailed info about IO queues. */ 106#define ENA_ADMQ (1 << 8) /* Detailed info about admin queue. */ 107#define ENA_NETMAP (1 << 9) /* Detailed info about netmap. */ 108 109extern int ena_log_level; 110 111#define ena_trace_raw(level, fmt, args...) \ 112 do { \ 113 if (((level) & ena_log_level) != (level)) \ 114 break; \ 115 printf(fmt, ##args); \ 116 } while (0) 117 118#define ena_trace(level, fmt, args...) \ 119 ena_trace_raw(level, "%s() [TID:%d]: " \ 120 fmt, __func__, curthread->td_tid, ##args) 121 122 123#define ena_trc_dbg(format, arg...) ena_trace(ENA_DBG, format, ##arg) 124#define ena_trc_info(format, arg...) ena_trace(ENA_INFO, format, ##arg) 125#define ena_trc_warn(format, arg...) ena_trace(ENA_WARNING, format, ##arg) 126#define ena_trc_err(format, arg...) ena_trace(ENA_ALERT, format, ##arg) 127 128#define unlikely(x) __predict_false(!!(x)) 129#define likely(x) __predict_true(!!(x)) 130 131#define __iomem 132#define ____cacheline_aligned __aligned(CACHE_LINE_SIZE) 133 134#define MAX_ERRNO 4095 135#define IS_ERR_VALUE(x) unlikely((x) <= (unsigned long)MAX_ERRNO) 136 137#define ENA_ASSERT(cond, format, arg...) \ 138 do { \ 139 if (unlikely(!(cond))) { \ 140 ena_trc_err( \ 141 "Assert failed on %s:%s:%d:" format, \ 142 __FILE__, __func__, __LINE__, ##arg); \ 143 } \ 144 } while (0) 145 146#define ENA_WARN(cond, format, arg...) \ 147 do { \ 148 if (unlikely((cond))) { \ 149 ena_trc_warn(format, ##arg); \ 150 } \ 151 } while (0) 152 153static inline long IS_ERR(const void *ptr) 154{ 155 return IS_ERR_VALUE((unsigned long)ptr); 156} 157 158static inline void *ERR_PTR(long error) 159{ 160 return (void *)error; 161} 162 163static inline long PTR_ERR(const void *ptr) 164{ 165 return (long) ptr; 166} 167 168#define GENMASK(h, l) (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h)))) 169#define GENMASK_ULL(h, l) (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h)))) 170#define BIT(x) (1UL << (x)) 171 172#define ENA_ABORT() BUG() 173#define BUG() panic("ENA BUG") 174 175#define SZ_256 (256) 176#define SZ_4K (4096) 177 178#define ENA_COM_OK 0 179#define ENA_COM_FAULT EFAULT 180#define ENA_COM_INVAL EINVAL 181#define ENA_COM_NO_MEM ENOMEM 182#define ENA_COM_NO_SPACE ENOSPC 183#define ENA_COM_TRY_AGAIN -1 184#define ENA_COM_UNSUPPORTED EOPNOTSUPP 185#define ENA_COM_NO_DEVICE ENODEV 186#define ENA_COM_PERMISSION EPERM 187#define ENA_COM_TIMER_EXPIRED ETIMEDOUT 188 189#define ENA_MSLEEP(x) pause_sbt("ena", SBT_1MS * (x), SBT_1MS, 0) 190#define ENA_USLEEP(x) pause_sbt("ena", SBT_1US * (x), SBT_1US, 0) 191#define ENA_UDELAY(x) DELAY(x) 192#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \ 193 ((long)cputick2usec(cpu_ticks()) + (timeout_us)) 194#define ENA_TIME_EXPIRE(timeout) ((timeout) < cputick2usec(cpu_ticks())) 195#define ENA_MIGHT_SLEEP() 196 197#define min_t(type, _x, _y) ((type)(_x) < (type)(_y) ? (type)(_x) : (type)(_y)) 198#define max_t(type, _x, _y) ((type)(_x) > (type)(_y) ? (type)(_x) : (type)(_y)) 199 200#define ENA_MIN32(x,y) MIN(x, y) 201#define ENA_MIN16(x,y) MIN(x, y) 202#define ENA_MIN8(x,y) MIN(x, y) 203 204#define ENA_MAX32(x,y) MAX(x, y) 205#define ENA_MAX16(x,y) MAX(x, y) 206#define ENA_MAX8(x,y) MAX(x, y) 207 208/* Spinlock related methods */ 209#define ena_spinlock_t struct mtx 210#define ENA_SPINLOCK_INIT(spinlock) \ 211 mtx_init(&(spinlock), "ena_spin", NULL, MTX_SPIN) 212#define ENA_SPINLOCK_DESTROY(spinlock) \ 213 do { \ 214 if (mtx_initialized(&(spinlock))) \ 215 mtx_destroy(&(spinlock)); \ 216 } while (0) 217#define ENA_SPINLOCK_LOCK(spinlock, flags) \ 218 do { \ 219 (void)(flags); \ 220 mtx_lock_spin(&(spinlock)); \ 221 } while (0) 222#define ENA_SPINLOCK_UNLOCK(spinlock, flags) \ 223 do { \ 224 (void)(flags); \ 225 mtx_unlock_spin(&(spinlock)); \ 226 } while (0) 227 228 229/* Wait queue related methods */ 230#define ena_wait_event_t struct { struct cv wq; struct mtx mtx; } 231#define ENA_WAIT_EVENT_INIT(waitqueue) \ 232 do { \ 233 cv_init(&((waitqueue).wq), "cv"); \ 234 mtx_init(&((waitqueue).mtx), "wq", NULL, MTX_DEF); \ 235 } while (0) 236#define ENA_WAIT_EVENT_DESTROY(waitqueue) \ 237 do { \ 238 cv_destroy(&((waitqueue).wq)); \ 239 mtx_destroy(&((waitqueue).mtx)); \ 240 } while (0) 241#define ENA_WAIT_EVENT_CLEAR(waitqueue) \ 242 cv_init(&((waitqueue).wq), (waitqueue).wq.cv_description) 243#define ENA_WAIT_EVENT_WAIT(waitqueue, timeout_us) \ 244 do { \ 245 mtx_lock(&((waitqueue).mtx)); \ 246 cv_timedwait(&((waitqueue).wq), &((waitqueue).mtx), \ 247 timeout_us * hz / 1000 / 1000 ); \ 248 mtx_unlock(&((waitqueue).mtx)); \ 249 } while (0) 250#define ENA_WAIT_EVENT_SIGNAL(waitqueue) \ 251 do { \ 252 mtx_lock(&((waitqueue).mtx)); \ 253 cv_broadcast(&((waitqueue).wq)); \ 254 mtx_unlock(&((waitqueue).mtx)); \ 255 } while (0) 256 257#define dma_addr_t bus_addr_t 258#define u8 uint8_t 259#define u16 uint16_t 260#define u32 uint32_t 261#define u64 uint64_t 262 263typedef struct { 264 bus_addr_t paddr; 265 caddr_t vaddr; 266 bus_dma_tag_t tag; 267 bus_dmamap_t map; 268 bus_dma_segment_t seg; 269 int nseg; 270} ena_mem_handle_t; 271 272struct ena_bus { 273 bus_space_handle_t reg_bar_h; 274 bus_space_tag_t reg_bar_t; 275 bus_space_handle_t mem_bar_h; 276 bus_space_tag_t mem_bar_t; 277}; 278 279typedef uint32_t ena_atomic32_t; 280 281#define ENA_PRIu64 PRIu64 282 283typedef uint64_t ena_time_t; 284 285void ena_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nseg, 286 int error); 287int ena_dma_alloc(device_t dmadev, bus_size_t size, ena_mem_handle_t *dma, 288 int mapflags); 289 290static inline uint32_t 291ena_reg_read32(struct ena_bus *bus, bus_size_t offset) 292{ 293 uint32_t v = bus_space_read_4(bus->reg_bar_t, bus->reg_bar_h, offset); 294 rmb(); 295 return v; 296} 297 298#define ENA_MEMCPY_TO_DEVICE_64(dst, src, size) \ 299 do { \ 300 int count, i; \ 301 volatile uint64_t *to = (volatile uint64_t *)(dst); \ 302 const uint64_t *from = (const uint64_t *)(src); \ 303 count = (size) / 8; \ 304 \ 305 for (i = 0; i < count; i++, from++, to++) \ 306 *to = *from; \ 307 } while (0) 308 309#define ENA_MEM_ALLOC(dmadev, size) malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO) 310#define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) (virt = NULL) 311#define ENA_MEM_FREE(dmadev, ptr, size) \ 312 do { \ 313 (void)(size); \ 314 free(ptr, M_DEVBUF); \ 315 } while (0) 316#define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, handle, node, \ 317 dev_node) \ 318 do { \ 319 ((virt) = NULL); \ 320 (void)(dev_node); \ 321 } while (0) 322 323#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, dma) \ 324 do { \ 325 ena_dma_alloc((dmadev), (size), &(dma), 0); \ 326 (virt) = (void *)(dma).vaddr; \ 327 (phys) = (dma).paddr; \ 328 } while (0) 329 330#define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, dma) \ 331 do { \ 332 (void)size; \ 333 bus_dmamap_unload((dma).tag, (dma).map); \ 334 bus_dmamem_free((dma).tag, (virt), (dma).map); \ 335 bus_dma_tag_destroy((dma).tag); \ 336 (dma).tag = NULL; \ 337 (virt) = NULL; \ 338 } while (0) 339 340/* Register R/W methods */ 341#define ENA_REG_WRITE32(bus, value, offset) \ 342 do { \ 343 wmb(); \ 344 ENA_REG_WRITE32_RELAXED(bus, value, offset); \ 345 } while (0) 346 347#define ENA_REG_WRITE32_RELAXED(bus, value, offset) \ 348 bus_space_write_4( \ 349 ((struct ena_bus*)bus)->reg_bar_t, \ 350 ((struct ena_bus*)bus)->reg_bar_h, \ 351 (bus_size_t)(offset), (value)) 352 353#define ENA_REG_READ32(bus, offset) \ 354 ena_reg_read32((struct ena_bus*)(bus), (bus_size_t)(offset)) 355 356#define ENA_DB_SYNC_WRITE(mem_handle) bus_dmamap_sync( \ 357 (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREWRITE) 358#define ENA_DB_SYNC_PREREAD(mem_handle) bus_dmamap_sync( \ 359 (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREREAD) 360#define ENA_DB_SYNC_POSTREAD(mem_handle) bus_dmamap_sync( \ 361 (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_POSTREAD) 362#define ENA_DB_SYNC(mem_handle) ENA_DB_SYNC_WRITE(mem_handle) 363 364#define time_after(a,b) ((long)((unsigned long)(b) - (unsigned long)(a)) < 0) 365 366#define VLAN_HLEN sizeof(struct ether_vlan_header) 367#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 368 369#define prefetch(x) (void)(x) 370#define prefetchw(x) (void)(x) 371 372/* DMA buffers access */ 373#define dma_unmap_addr(p, name) ((p)->dma->name) 374#define dma_unmap_addr_set(p, name, v) (((p)->dma->name) = (v)) 375#define dma_unmap_len(p, name) ((p)->name) 376#define dma_unmap_len_set(p, name, v) (((p)->name) = (v)) 377 378#define memcpy_toio memcpy 379 380#define ATOMIC32_INC(I32_PTR) atomic_add_int(I32_PTR, 1) 381#define ATOMIC32_DEC(I32_PTR) atomic_add_int(I32_PTR, -1) 382#define ATOMIC32_READ(I32_PTR) atomic_load_acq_int(I32_PTR) 383#define ATOMIC32_SET(I32_PTR, VAL) atomic_store_rel_int(I32_PTR, VAL) 384 385#define barrier() __asm__ __volatile__("": : :"memory") 386#define dma_rmb() barrier() 387#define mmiowb() barrier() 388 389#define ACCESS_ONCE(x) (*(volatile __typeof(x) *)&(x)) 390#define READ_ONCE(x) ({ \ 391 __typeof(x) __var; \ 392 barrier(); \ 393 __var = ACCESS_ONCE(x); \ 394 barrier(); \ 395 __var; \ 396 }) 397#define READ_ONCE8(x) READ_ONCE(x) 398#define READ_ONCE16(x) READ_ONCE(x) 399#define READ_ONCE32(x) READ_ONCE(x) 400 401#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 402#define lower_32_bits(n) ((uint32_t)(n)) 403 404#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 405 406#define ENA_FFS(x) ffs(x) 407 408void ena_rss_key_fill(void *key, size_t size); 409 410#define ENA_RSS_FILL_KEY(key, size) ena_rss_key_fill(key, size) 411 412#include "ena_defs/ena_includes.h" 413 414#endif /* ENA_PLAT_H_ */ 415