ena_eth_com.h revision 343397 
1/*-
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef ENA_ETH_COM_H_
35#define ENA_ETH_COM_H_
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40#include "ena_com.h"
41
42/* head update threshold in units of (queue size / ENA_COMP_HEAD_THRESH) */
43#define ENA_COMP_HEAD_THRESH 4
44
45struct ena_com_tx_ctx {
46	struct ena_com_tx_meta ena_meta;
47	struct ena_com_buf *ena_bufs;
48	/* For LLQ, header buffer - pushed to the device mem space */
49	void *push_header;
50
51	enum ena_eth_io_l3_proto_index l3_proto;
52	enum ena_eth_io_l4_proto_index l4_proto;
53	u16 num_bufs;
54	u16 req_id;
55	/* For regular queue, indicate the size of the header
56	 * For LLQ, indicate the size of the pushed buffer
57	 */
58	u16 header_len;
59
60	u8 meta_valid;
61	u8 tso_enable;
62	u8 l3_csum_enable;
63	u8 l4_csum_enable;
64	u8 l4_csum_partial;
65	u8 df; /* Don't fragment */
66};
67
68struct ena_com_rx_ctx {
69	struct ena_com_rx_buf_info *ena_bufs;
70	enum ena_eth_io_l3_proto_index l3_proto;
71	enum ena_eth_io_l4_proto_index l4_proto;
72	bool l3_csum_err;
73	bool l4_csum_err;
74	/* fragmented packet */
75	bool frag;
76	u32 hash;
77	u16 descs;
78	int max_bufs;
79};
80
81int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
82		       struct ena_com_tx_ctx *ena_tx_ctx,
83		       int *nb_hw_desc);
84
85int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
86		   struct ena_com_io_sq *io_sq,
87		   struct ena_com_rx_ctx *ena_rx_ctx);
88
89int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
90			       struct ena_com_buf *ena_buf,
91			       u16 req_id);
92
93int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id);
94
95static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq,
96				       struct ena_eth_io_intr_reg *intr_reg)
97{
98	ENA_REG_WRITE32(io_cq->bus, intr_reg->intr_control, io_cq->unmask_reg);
99}
100
101static inline int ena_com_free_desc(struct ena_com_io_sq *io_sq)
102{
103	u16 tail, next_to_comp, cnt;
104
105	next_to_comp = io_sq->next_to_comp;
106	tail = io_sq->tail;
107	cnt = tail - next_to_comp;
108
109	return io_sq->q_depth - 1 - cnt;
110}
111
112/* Check if the submission queue has enough space to hold required_buffers */
113static inline bool ena_com_sq_have_enough_space(struct ena_com_io_sq *io_sq,
114						u16 required_buffers)
115{
116	int temp;
117
118	if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
119		return ena_com_free_desc(io_sq) >= required_buffers;
120
121	/* This calculation doesn't need to be 100% accurate. So to reduce
122	 * the calculation overhead just Subtract 2 lines from the free descs
123	 * (one for the header line and one to compensate the devision
124	 * down calculation.
125	 */
126	temp = required_buffers / io_sq->llq_info.descs_per_entry + 2;
127
128	return ena_com_free_desc(io_sq) > temp;
129}
130
131static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
132{
133	u16 tail;
134
135	tail = io_sq->tail;
136
137	ena_trc_dbg("write submission queue doorbell for queue: %d tail: %d\n",
138		    io_sq->qid, tail);
139
140	ENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr);
141
142	return 0;
143}
144
145static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq)
146{
147	u16 unreported_comp, head;
148	bool need_update;
149
150	head = io_cq->head;
151	unreported_comp = head - io_cq->last_head_update;
152	need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH);
153
154	if (io_cq->cq_head_db_reg && need_update) {
155		ena_trc_dbg("Write completion queue doorbell for queue %d: head: %d\n",
156			    io_cq->qid, head);
157		ENA_REG_WRITE32(io_cq->bus, head, io_cq->cq_head_db_reg);
158		io_cq->last_head_update = head;
159	}
160
161	return 0;
162}
163
164static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq,
165					    u8 numa_node)
166{
167	struct ena_eth_io_numa_node_cfg_reg numa_cfg;
168
169	if (!io_cq->numa_node_cfg_reg)
170		return;
171
172	numa_cfg.numa_cfg = (numa_node & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK)
173		| ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
174
175	ENA_REG_WRITE32(io_cq->bus, numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);
176}
177
178static inline void ena_com_comp_ack(struct ena_com_io_sq *io_sq, u16 elem)
179{
180	io_sq->next_to_comp += elem;
181}
182
183#if defined(__cplusplus)
184}
185#endif
186#endif /* ENA_ETH_COM_H_ */
187